Substrate processing system with in-SITU capacitive dividers for detection of plasma properties

Abstract

A substrate processing system is disclosed and includes a sensor and at least one controller. The sensor is disposed at least partially within at least one component of a process chamber of the substrate processing system. The sensor includes a capacitive divider. The capacitive divider includes a first capacitor and a second capacitor connected in series. The first capacitor and the second capacitor include a conductive base layer and a conductive middle layer. The at least one controller is configured to: detect a first voltage of the conductive base layer and a second voltage of the conductive middle layer; based on the first voltage and the second voltage, determine a first plasma property of plasma in the process chamber; and adjust a parameter of the substrate processing system based on the first plasma property.

Description

SUBSTRATE PROCESSING SYSTEM WITH IN-SITU CAPACITIVE DIVIDERS FOR DETECTION OF PLASMA PROPERTIESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 546,852, filed on November 1 , 2023. The entire disclosure of the application referenced above is incorporated herein by reference.FIELD

[0002] The present disclosure relates to substrate processing systems and more particularly to systems for controlling plasma properties in a process chamber.BACKGROUND

[0003] The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] A substrate processing system typically includes a plurality of process chambers (also called process modules) to perform deposition, etching, and other treatments of substrates such as semiconductor wafers. For example, deposition may be performed to deposit conductive film, dielectric film, or other types of film using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhance ALD (PEALD), and / or other deposition processes. As an example, etching may be performed to remove material from one or more layers and include atomic layer etching (ALE), high aspect ratio (HAR) etching, plasma etching, and / or other etch processes. During deposition, a substrate is arranged on a substrate support (e.g., a pedestal) and one or more precursor gases may be supplied to a process chamber using a gas distribution device (e.g., a showerhead) during one or more process steps. In a PECVD or PEALD process, plasma is used to activate chemical reactions within the process chamber during deposition. Additional examples of processes that may be performed on a substrate include, but are not limited to, dielectric etching, chemical etching, plasma etching, reactive ion etching, and cleaning processes. During thedeposition and etching processes, gas mixtures are introduced into the process chamber via showerheads, and plasma is struck to activate chemical reactions. During the cleaning processes, gases may also be introduced via the showerheads.SUMMARY

[0005] A substrate processing system is disclosed and includes a sensor and at least one controller. The sensor is disposed at least partially within at least one component of a process chamber of the substrate processing system. The sensor includes a capacitive divider. The capacitive divider includes a first capacitor and a second capacitor connected in series. The first capacitor and the second capacitor include a conductive base layer and a conductive middle layer. The at least one controller is configured to: detect a first voltage of the conductive base layer and a second voltage of the conductive middle layer; based on the first voltage and the second voltage, determine a first plasma property of plasma in the process chamber; and adjust a parameter of the substrate processing system based on the first plasma property.

[0006] In other features, the sensor is embedded in a substrate support of the process chamber. In other features, the sensor is embedded at least partially in a window of the process chamber.

[0007] In other features, the window is a transformer coupled plasma window, a capacitive coupled plasma window, or a remote plasma source window and is disposed above a substrate support of the process chamber.

[0008] In other features, the window is disposed in a sidewall of the process chamber. In other features, the sensor is embedded in a wall of the process chamber. In other features, the sensor is disposed at least partially in an opening exposed to the plasma and is connected to a feedthrough seal.

[0009] In other features, the sensor includes: the first capacitor includes the conductive base layer, the conductive middle layer and a first dielectric layer disposed between the conductive base layer and the conductive middle layer; and the second capacitor includes the conductive middle layer, a second dielectric layer, and an inner surface of the second dielectric layer. The second dielectric layer is disposed between the conductive middle layer and the plasma. In other features, the conductive base layer is a conductive layer of a wall of the process chamber.

[0010] In other features, the sensor includes: the first capacitor including the conductive base layer, the conductive middle layer and a first dielectric layer; the first dielectric layer is disposed between the conductive base layer and the conductive middle layer; the second capacitor includes the conductive middle layer, a second dielectric layer, and an inner surface of the second dielectric layer; the conductive middle layer is surrounded by the second dielectric layer; and a portion of the second dielectric layer is disposed between the plasma and the conductive middle layer. In other features, the portion of the second dielectric layer is a portion of an inner surface layer of a wall of the process chamber.

[0011] In other features, the substrate processing system further includes a window including a channel. The conductive middle layer is disposed within the channel. A first dielectric portion of the window is disposed between the conductive middle layer and the plasma. A second dielectric portion of the window is disposed between the conductive middle layer and the conductive base layer.

[0012] In other features, the at least one controller is configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine the first plasma property.

[0013] In other features, the at least one controller is configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine plasma properties including the first plasma property. The plasma properties include an impinging ion energy of positive ions, ion flux, a positive ion energy distribution function, and electron density.

[0014] In other features, the at least one controller is configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine whether the substrate processing system is operating in an active-glow phase or an after-glow phase.

[0015] In other features, the at least one controller includes a digital signal processor configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine a voltage at a surface of a substrate disposed on a substrate support of the process chamber and an amount of current passing through the substrate support.

[0016] In other features, the at least one controller includes a digital signal processor configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine a voltage at a surface of the sensor exposed to the plasma and an amount of current passing through the sensor.

[0017] In other features, the at least one controller includes a digital signal processor configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine a voltage at a surface of the at least one component and an amount of current passing through the sensor.

[0018] In other features, the at least one controller includes: a first scaling device configured to scale the first voltage; a second scaling device configured to scale the second voltage; and a differential amplifier configured to determine a third voltage based on a difference between the scaled first voltage and the scaled second voltage. The at least one controller is configured to determine the first plasma property based on the third voltage.

[0019] In other features, the at least one controller includes: a differential amplifier configured to generate a third voltage based on a difference between the first voltage and the second voltage; a differentiator configured to differentiate the third voltage to provide current; and a scaling device configured to scale the current. The at least one controller is configured to determine the first plasma property based on the current.

[0020] In other features, the conductive middle layer includes one or more electrostatic clamping electrodes. The conductive base layer includes one or more radio frequency electrodes.

[0021] In other features, the substrate processing system further includes: one or radio frequency electrodes; and one or more conductive traces electrically connecting the conductive base layer to the one or more radio frequency electrodes.

[0022] In other features, a method of operating a substrate processing system is disclosed and includes: setting system inputs of the substrate processing system; setting plasma parameters of the substrate processing system; operating the substrate processing system based on the system inputs and the plasma parameters to provide keys, where the keys include at least one plasma property; measuring voltages of layers of a sensor, where the sensor includes a capacitive divider; calculating the at least one plasma property based on the voltages of the layers of the sensor; and adjusting at leastone of the system inputs and the plasma parameters based on the at least one plasma property.

[0023] In other features, the sensor is implemented in a substrate support, a window or a wall of a process chamber. In other features, the layers are conductive elements of the capacitive divider. In other features, the at least one plasma property includes plasma properties.

[0024] In other features, the at least one plasma property includes at least one of an impinging ion energy of positive ions, ion flux, a positive ion energy distribution function, and an electron density.

[0025] In other features, the method further includes: determining whether the substrate processing system is operating in an active-glow phase or an after-glow phase based on the voltages of the layers; and adjusting the at least one of the system inputs and the plasma parameters based on whether the substrate processing system is operating in the active-glow phase or the after-glow phase.

[0026] In other features, a method of operating a substrate processing system is disclosed and includes: setting at least one target for at least one plasma property; measuring and / or calculating parameters of layers of a component in the substrate processing system, where the component includes at least partially a capacitive divider; determining the at least one plasma property based on the parameters; comparing the at least one target to the determined at least one plasma property; and adjusting at least one parameter of the substrate processing system based on results of comparing the at least one target to the determined at least one plasma property.

[0027] In other features, the method further includes: determining voltages of the layers, where the capacitive divider includes the layers; and determining the at least one plasma property based on the voltages.

[0028] In other features, the method further includes: determining current passing through the capacitive divider; and determining the at least one plasma property based on the current.

[0029] In other features, the at least one plasma property includes at least one of an impinging ion energy of positive ions, ion flux, a positive ion energy distribution function, and an electron density.

[0030] In other features, the method further includes: determining whether the substrate processing system is operating in an active-glow phase or an after-glow phase based on the parameters of the layers; and adjusting the at least one parameter of the substrate processing system based on whether the substrate processing system is operating in the active-glow phase or the after-glow phase.

[0031] Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0033] FIG. 1 is a functional block diagram and cross-sectional side view of an example substrate processing system including capacitive dividers in accordance with the present disclosure;

[0034] FIG. 2 is a functional block diagram of an example substrate processing system incorporating a capacitive divider in accordance with the present disclosure;

[0035] FIG. 3 is a schematic representative view of an example capacitive divider implemented in a component of a process chamber in accordance with the present disclosure;

[0036] FIG. 4 is a schematic representative view of another example capacitive divider implemented in a component of a process chamber in accordance with the present disclosure;

[0037] FIG. 5 is a functional block diagram of an example system controller illustrating some example input and determined parameters in accordance with the present disclosure;

[0038] FIG. 6 is a schematic diagram of an example analog circuit for detecting a surface voltage (e.g., top or inner surface voltage) of a component in accordance with the present disclosure;

[0039] FIG. 7 is a schematic diagram of an example analog circuit for detecting current through a surface (top or inner surface) of a component in accordance with the present disclosure;

[0040] FIG. 8 is an example plot of measured base layer voltage of a substrate support, measured substrate voltage, measured plasma voltage, and measured sidewall voltage versus time;

[0041] FIG. 9 is an example plot of measured base layer voltage, measured middle layer voltage, and measured substrate (or top layer) voltage versus time for a capacitive divider of a substrate support in accordance with the present disclosure;

[0042] FIG. 10 is an example plot comparing measured substrate (or top layer) voltage and calculated top layer voltage versus time of the substrate support in accordance with the present disclosure;

[0043] FIG. 1 1 is example plot of calculated current through the substrate in accordance with the present disclosure;

[0044] FIG. 12 is an example diagram including a plot of substrate current versus substrate voltage and a plot of corresponding intensity versus substrate voltage provided by integrating bin sections of the substrate current versus voltage plot in accordance with the present disclosure;

[0045] FIG. 13 is an example intensity versus ion energy plot (or ion energy distribution plot) provided by inverting the polarity of the intensity versus voltage plot of FIG. 12;

[0046] FIG. 14 is an example plot of intensity versus ion energy for a first bin size based on the substrate current versus voltage plot of FIG. 12;

[0047] FIG. 15 is an example plot of intensity versus ion energy for a second bin size based on the substrate current versus voltage plot of FIG. 12;

[0048] FIG. 16 is an example plot of intensity versus ion energy for a third bin size based on the substrate current versus voltage plot of FIG. 12;

[0049] FIG. 17 is an example diagram including a plot of measured base layer voltage, measured middle layer voltage, and measured surface voltage versus time, a plot of a slope of the measured surface voltage versus time, and a plot of calculated current versus time for a component in accordance with the present disclosure;

[0050] FIG. 18 is an example plot of electron density and positive ions versus time during a pulse of pulsed plasma;

[0051] FIG. 19 illustrates a method of operating a substrate processing system based on detected plasma properties in accordance with the present disclosure;

[0052] FIG. 20 illustrates a substrate processing method including adjustment of system parameters based on detected plasma properties in accordance with the present disclosure; and

[0053] FIG. 21 is a functional block diagram and cross-sectional side view of another example substrate processing system including capacitive dividers in accordance with the present disclosure.

[0054] In the drawings, reference numbers may be reused to identify similar and / or identical elements.DETAILED DESCRIPTION

[0055] Size requirements of features (e.g., vias, trenches, conductive elements, etc.) of microchips continue to decrease and can be below 10 nanometers (nm). Plasma properties (also referred to as charged plasma species properties) can affect accuracy of substrate processes used to form the features. Some example plasma properties are species density, species flux, electron energy and angular distribution (EEAD), ion energy and angular distribution (IEAD), impinging ion energy of positive ions, ion flux, a positive ion energy distribution function, electron density, and active-glow and after-glow phases. Others are referred to below.

[0056] Measurement tools such as a Langmuir probe and a retarding field energy analyzer (RFEA) can be used to detect plasma properties. The Langmuir probe can be used to detect electron properties. The RFEA can be used to detect ion properties. The Langmuir probe and RFEA are however intrusive. Both the Langmuir probe and RFEA require insertion of a measurement probe into a process chamber making each of them inappropriate for in-situ monitoring of fabrication processes. Electrical and mechanical properties of a measurement probe can change plasma properties leading to issues such as contamination, plasma non-uniformity, and manufacturing yield loss. The inserted measurement probes are exposed to the environment within a process chamber and as a result can, for example, be etched. This results in particles entering a plasma cloud, which can contaminate the substrate being processed. Also, voltages are typicallyapplied to measurement probes to measure parameters. The introduced voltages can change properties of plasma. Although measurement probes are capable of taking quantitative measurements, they have not been broadly adopted in sensitive manufacturing processes for at least the above-stated reasons.

[0057] An optical emission spectroscopy instrument can be used to detect electron density but can be difficult to calibrate and maintain for quantitative analysis. An optical emission spectroscopy instrument is used external to a process chamber for analysis of a substrate after processing and removal from a process chamber.

[0058] In-situ quantitative measurement of plasma properties in process chambers enables precise control of plasma during fabrication processing. The examples set forth herein include in-situ capacitive divider-based sensors, which provide voltages based on which plasma properties are detected (i.e., monitored, determined and / or calculated). The plasma properties include the above-stated plasma properties and others referred to and further described below. The sensors do not protrude into a process chamber and / or a process environment and thus are non-invasive. The sensors are rather embedded in and / or constructed as part of process chamber components (e.g., substrate supports, chamber walls, windows, feedthrough seals, etc.).

[0059] FIG. 1 shows an example substrate processing system 100 including a process chamber 102 having a substrate support 104 supporting a substrate 106 and a chamber body 108. The chamber body 108 includes an inner sidewall surface 109, a first window 1 10, and a feedthrough seal 1 12. Sensors 120, 122, 124, 126 are included and are examples of some capacitive divider-based sensors that may be included in the substrate processing system 100. Although a certain number of sensors are shown, any number of sensors may be included. In an embodiment, one or more sensors are included. The sensors are used to detect states of plasma in local areas in which the sensors are located. Each of the sensors 120, 122, 124, 126 is used to detect plasma properties and includes multiple capacitors connected in series to provide a capacitive divider. The capacitors are provided by i) corresponding conductive layers and dielectric layers of the components of the substrate processing system, and ii) plasma. The components include conductive and dielectric layers.

[0060] The substrate support 104 may include a body 130 formed of dielectric material, a first conductive layer 132, a first dielectric layer 134, a second conductive layer 136, and a second dielectric layer 138. The layers 132, 134, 136 perform as a first capacitorC1 . The layers 132, 136 may be referred to as conductive elements and are respectively a conductive base layer and a conductive middle layer. Layers 136, 138 and a top surface 139 of the substrate 106 perform as the second capacitor C2. The capacitors C1 , C2 are electrically coupled in series and perform as a capacitive divider. The conductive layers 132, 136 may be formed of aluminum, steel, copper, and / or other conductive material. The conductive layers 132, 136 may be circular shaped and have smaller diameters than a diameter of the substrate support 104. The conductive layers 132, 136 are embedded within the substrate support 104. The conductive layers 132, 136 may have the same dimensions or may be sized differently as shown. The dielectric layer 134 is disposed between the conductive layers 132, 136. The dielectric layer 138 is disposed between the conductive layer 136 and a top surface 144 of the substrate support 104. The conductive layer 132 may be radio frequency (RF) electrode receiving a RF voltage Vrf. In an embodiment, the conductive layer 136 is an electrostatic clamping electrode that receives an electrostatic clamping voltage Ve.

[0061] A sidewall 150 of the chamber body 108 includes a conductive outer layer 151 and a dielectric inner layer 152 having the inner sidewall surface 109. The conductive outer layer 151 may be referred to as a conductive base layer for each of the sensors 122, 124 and 126. The sensor 122 includes a conductive element (or conductive middle layer) 154. The conductive element 154 is surrounded by a dielectric insulative layer 156 that is disposed between the conductive element 154 and the conductive outer layer 151 . The layers 154, 156 and 151 perform as a first capacitor. The conductive element 154, the dielectric inner layer 152, and an inner surface 157 of the dielectric layer 156 adjacent the conductive element 154 perform as a second capacitor that is connected in series with the first capacitor to provide a capacitive divider of the sensor 122. The structure around conductive element 154 needs to be appropriately designed to minimize the impact of conductive element 154 to the potential of inner surface 157. A first voltage probe 158 is connected to the conductive element 154 via a conductive line 159 and detects a voltage at the conductive element 154. The first voltage probe 158 generates an attenuated voltage signal based on a signal received from the conductive line 159 and feeds back the attenuated voltage signal to the system controller 190.

[0062] The first window 110 may be a transformer coupled plasma (TCP) window, a capacitive coupled plasma window for dielectric chambers, a remote plasma source window for deposition chambers, etc. and has a dielectric body 160 including a channel 162. A conductive element (or conductive middle layer) 164 is disposed in the channel162. In an embodiment, the conductive element 164 is disposed i) near any portion of an inner surface 171 of the dielectric body 160, ii) anywhere in the channel 162, and / or iii) on a bottom surface of the channel 162. A second probe 166 is connected to the conductive element 164 via a conductive line 167 and detects a voltage at the conductive element 164. In an embodiment, the second voltage probe 166 generates an attenuated voltage signal based on a signal received from the conductive line 167 and feeds the attenuated voltage signal back to the system controller 190. A first portion 168 of the dielectric body 160 is disposed between the conductive element 164 and an inner surface 171 of the dielectric window 110. A second portion 169 of the dielectric body 160 is disposed between the conductive element 164 and the conductive outer layer 151 . The conductive element 164, the second portion 169, and the conductive outer layer 151 perform as a first capacitor. The conductive element 164, the first portion 168, and the inner surface 171 perform as a second capacitor that is connected in series with the first capacitor. The first and second capacitors provide the capacitive divider of the sensor 124.

[0063] The feedthrough seal 1 12 seals off an end of an opening 170 in the sidewall 150 near the third voltage probe 180. A dielectric layer 172 exists between i) the outer conductive layer 151 and ii) plasma 181 and the feedthrough seal 1 12. A portion of the plasma 181 is in the opening 170 between a dielectric layer 176 and the dielectric layer 172. The dielectric layer 172 is surrounded by the conductive outer layer 151. A conductive element (or conductive middle layer) 174 is surrounded by the dielectric layer 176. A first portion 178 of the dielectric layer 176 is disposed between the conductive element 174 and the inner surface 183. A second portion 179 of the dielectric layer 176 is disposed between the conductive element 174 and the conductive outer layer 151 . The conductive element 174, the second portion 179, and the conductive outer layer 151 perform as a first capacitor. The conductive element 174, the first portion 178, and an inner surface 183 of the first portion 178 perform as a second capacitor. The first and second capacitors provide the capacitive divider of the sensor 126. A third probe 180 is connected to the conductive element 174 via a conductive line 182 and detects a voltage at the conductive element 174. In an embodiment, the third voltage probe 180 generates an attenuated voltage signal based on a signal received from the conductive line 182 and feeds the attenuated voltage signal back to the system controller 190. A surface of the portion 179 that is exposed to the plasma 181 is located away from the sidewall 150. The voltage at the conductive element 174 is decoupled from a voltage potential of the innersidewall surface 109 and as a result the voltage of the conductive element 174 is floating and coupled to the voltage potential of the plasma 181 .

[0064] The substrate processing system 100 further includes a system control circuit 190 including an RF generator 192 that is configured to generate and / or provide a RF voltage Vrf to the conductive layer 132, and an electrostatic clamping voltage Ve via a DC voltage generator 194 of the system control circuit 190 to the conductive layer 136. The system control circuit 190 is also configured to monitor voltages Vb, Vm respectively at the conductive layers 132, 136 and voltages detected by the voltage probes 158, 166, 180. The conductive layer 132 may be referred to as a base layer and be at a voltage potential Vb. The voltage potential Vb may be the same as the voltage Vrf. The conductive layer 136 may be referred to as a conductive middle layer and be at a voltage potential Vm. The system controller 190, based on the voltages Vb, VM and the voltages detected by the voltage probes 158, 166, 180 determines plasma properties as described below. The system controller 190 then adjusts system parameters based on the determined plasma properties as described below.

[0065] The sensors 120, 122, 124, 126 measure voltages and are used to determine current at surfaces where plasma sheath is formed. Actual measurements are collected from sides of the surfaces of interest adjacent and opposing (or facing) the plasma. The measurements are taken internally to components for the substrate support 104, the window 1 10, and the sidewall 150 of the process chamber 102. The conductive element 174 is used for plasma potential measurement, has a dielectric layer 176, and is positioned along the inner sidewall surface 109. The sensors 120, 122, 124, 126 are thus non-invasive. Each of the sensors 120, 122, 124, 126 includes a capacitive divider with three distinct conductive layers and two distinct insulative (or dielectric) layers. The surfaces of interest are isolated from the measurement layers forming capacitive division with other surrounding materials such as a process chamber grounded material.

[0066] FIG. 2 a substrate processing system (or tool) 200 incorporating the substrate support 104, which includes the sensor 120. Although FIG. 2 is described having the substrate support 104 of FIG. 1 , the substrate processing system 200 may be modified to include the substrate support of FIG. 21 . Although FIG. 2 shows a capacitive coupled plasma (CCP) system, the embodiments disclosed herein are applicable to transformer coupled plasma (TCP) systems, electron cyclotron resonance (ECR) plasma systems, inductively coupled plasma (ICP) systems and / or other systems and plasma sources thatinclude a substrate support. The embodiments are applicable to PVD processes, PECVD processes, chemically enhanced plasma vapor deposition (CEPVD) processes, ion implantation processes, and / or other etch, deposition, and cleaning processes.

[0067] Although the substrate support 104 is shown as being mounted to a bottom of a process chamber 204, the substrate support 104 may be mounted to a bottom or a top of a process chamber. If mounted to a top of a process chamber, the substrate support 104 may have similar configurations to that disclosed herein, but flipped upside down and may include peripheral substrate holding, clamping, and / or clasping hardware.

[0068] The substrate processing system 200 includes the process chamber 204, which includes the substrate support 104 with the sensor 120 as shown and may further include one or more other sensors, such as one or more other capacitive divider-based sensors as disclosed herein. The sensor 120 has the capacitances C1 , C2. The substrate support 104 is enclosed within the process chamber 204. The process chamber 204 also encloses other components, such as an upper electrode 205, and contains RF plasma. During operation, a substrate 207 is arranged on and electrostatically clamped to the substrate support 104.

[0069] For example only, the upper electrode 205 may include a showerhead 209 that introduces and distributes gases. The showerhead 209 may include a stem portion 211 including one end connected to a top surface of the process chamber 204. The showerhead 209 is generally cylindrical and extends radially outward from an opposite end of the stem portion 21 1 at a location that is spaced from the top surface of the process chamber 204. A substrate-facing surface or the showerhead 209 includes holes through which process or purge gas flows. Alternately, the upper electrode 205 may include a conducting plate and the gases may be introduced in another manner. One or more plates of the substrate support 104 may perform as a lower electrode.

[0070] The substrate processing system 200 further includes a system control circuit 219 that includes an RF generating system 220. The RF generating system 220 generates and outputs RF voltages to the upper electrode 205 and one or more lower electrodes (e.g., the conductive layer 136). One of the upper electrode 205 and the substrate support 104 may be DC grounded, AC grounded or at a floating potential. For example only, the RF generating system 220 may include one or more power sources 222 that generate RF voltages. As an example, the power sources may be implemented as RF generators. Outputs of the power sources 223, 225 may be fed by one or morematching and distribution networks 224 to the upper electrode 205 and / or the substrate support 104 or may be provided directly to the upper electrode 205 and / or the substrate support 104. In an embodiment, the RF matching networks 227, 229 are not included. The RF generating system 220 is provided as an example, other types of power and / or voltage sources may be implemented. In an embodiment, the power sources 223, 225 are implemented as RF generators that along with the matching networks 227, 229 generate "sinusoidal" voltage waveforms. In another embodiment, the matching networks 227, 229 are not included and the power sources 223, 225 generate "non-sinusoidal" waveforms such as square waves and / or arbitrary waveforms. Fig 8 and 9 are examples when non-sinusoidal waveforms are generated.

[0071] As an example, a first RF generator 223, a second RF generator 225, a first RF matching network 227 and a second RF matching network 229 are shown. The first RF generator 223 may be a high-power RF generator producing, for example, 6-10 kilowatts (kW) of power or more. In an embodiment, the second RF matching network 229 supplies power to one or more RF electrodes embedded in the substrate support 104.

[0072] A gas delivery system 230 includes one or more gas sources 232-1 , 232-2,..., and 232-N (collectively gas sources 232), where N is an integer greater than zero. The gas sources 232 supply one or more precursors and gas mixtures thereof. The gas sources 232 may also supply etch gas, carrier gas and / or purge gas. Vaporized precursor may also be used. The gas sources 232 are connected by valves 234-1 , 234-2, ..., and 234-N (collectively valves 234) and mass flow controllers 236-1 , 236-2, ..., and 236-N (collectively mass flow controllers 236) to a manifold 240. An output of the manifold 240 is fed to the process chamber 204. For example only, the output of the manifold 240 is fed to the showerhead 209. Gas channels for passage of gases received from the gas delivery system 230 through the showerhead are not shown.

[0073] A valve 256 and pump 258 may be used to evacuate reactants from the process chamber 204. A system controller 260 of the system control circuit 219 controls components of the substrate processing system 200 including controlling supplied RF power levels, pressures and flow rates of supplied gases, RF matching, etc. The system controller 260 controls states of the valve 256 and the pump 258. A robot 270 may be used to deliver substrates onto, and remove substrates from, the substrate support 104. For example, the robot 270 may transfer substrates between the substrate support 104and a load lock 272. The robot 270 may be controlled by the system controller 260. The system controller 260 may control operation of the load lock 272.

[0074] The system controller 260 monitors voltages of the sensor 120, such as voltages at Vb and Vm and based on these voltages determines plasma properties as described below. The system controller 260 then adjusts system parameters based on the determined plasma properties as described below.

[0075] FIG. 3 shows an example capacitive divider 300 that is implemented in a component of a process chamber. In an embodiment, the capacitive divider 300 is shown as a representation of the capacitive divider of the sensor 120 of FIGs. 1 -2 and includes the capacitors C1 and C2 connected in series. Voltages Vb and Vm are shown at ends of the first capacitor C1 . Voltages Vx and Vm are shown at ends of the second capacitor C2. The voltage Vx, for this embodiment, refers to a voltage, for example, at a top surface of a substrate such as a top surface of the substrate 106 of FIG. 1 or the substrate 207 of FIG. 2.

[0076] FIG. 4 shows an example capacitive divider 400 that is implemented at least partially in and / or attached to a component of a process chamber. In an embodiment, the capacitive divider 400 is shown as a representation of each of the capacitive dividers of the sensors 122, 124, 126 of FIG. 1. The component being a chamber wall such as the sidewall 150 of a chamber body 108 of FIG. 1 or one of the window 1 10 and the feedthrough seal 1 12. The capacitive divider 400 include capacitors C1 , C2 connected in series. Voltage Vm is shown at a first end of the first capacitor C1 . In an embodiment, the other end of the capacitor C1 is grounded and is at 0V. The grounding of the capacitor C1 corresponds to the ground of the conductive outer layer 151 of FIG. 1. Voltages Vx and Vm are shown at ends of the second capacitor C2. Voltage Vm refers to a voltage at a middle conductive element, such as a voltage at one of the conductive elements 154, 164, 174 of FIG. 1 . The voltage Vx, for this embodiment, refers to a voltage, for example, at i) an inner side surface of a chamber wall or window such as portion 157 of the inner sidewall surface 109 of the sidewall 150, ii) the inner side surface 183 of the plasma exposed dielectric layer 176, or ii) at a bottom surface of a window such as a bottom surface of the window 1 10 of FIG 1 .

[0077] FIG. 5 shows a diagram of an example system controller 500, which may replace at least a portion of a system controller of the system control circuit 190 of FIG. 1 or the system controller 260 of FIG. 2. In an embodiment, the system controller 500 is a digitalsignal processor that receives the voltages Vb and Vm from a sensor, such as one of the sensors stated above. The system controller 500 may sample the voltages Vb, Vm, represented as Vb(n), and Vm(n), where n refers to the sample number. The system controller 500 calculates voltages Vx(n) and current lx(n) based on the measured voltages Vb(n) and Vm(n). The voltage Vx(n) refers to any of the surface voltages (or voltages of plasma exposed surfaces) referred to with regard to FIGs. 1 -4 such as surfaces 139, 157, 171 , and 183 of FIG. 1 . The current lx(n) refers to the current through the corresponding sensor and represents charged species flux. As an example, the voltage Vx(n) and the current lx(n) may be calculated using equations 1 -2. The voltages Vb and Vm are input parameters and the voltage Vx(n) and the current lx(n) are detected parameters.

[0078] The capacitances of capacitors C1 and C2 of the sensors described herein and thus capacitances of the layers of the sensors may be measured and used to calibrate attenuation using, for example, equation 1 . Vb(n) is 0V when the bottom layer of the sensor is grounded.

[0079] The system controller 500 may determine Vx(n) and lx(n) for each sensor. The system controller 500 also determines a ratio between the capacitances C1 and C2 of each sensor. Vx(n) and lx(n) may be calculated via a digital circuit, an analog circuit, or a combination of digital and analog circuitry. Example analog circuits are shown in FIGs. 6-7.

[0080] FIG. 6 shows an example analog circuit 600 for detecting a surface voltage (e.g., top or inner surface voltage) Vx of a component. The surface voltage Vx may be determined based on Vm and Vb as shown if referring to a component that has a conductive base layer and a conductive middle layer such as the substrate support 104 of FIGs. 1 -2. The surface voltage Vx may be determined based on Vm and a reference voltage, for example, 0V if referring to a component such as a window with a middle conductive element and a grounded element (e.g., grounded conductive outer layer). The reference voltage may be a voltage of an adjacent and / or surrounding conductive element.

[0081] The analog circuit 600 includes a first scaling device 602, a second scaling device 604 and a differential amplifier 606. The first scaling device 602 multiplies the voltage Vm by a first scaling value Km. The second scaling device 604 multiplies the voltage Vb by a second scaling value Kb. The resulting scaled voltages are provided to the differential amplifier 606, which determines the voltage Vx. This may be represented by equation 3.Vx = Km * Vm — Kb * Vb (3)

[0082] FIG. 7 shows an example analog circuit 700 for detecting current lx(n) through a surface (top or inner surface) of a component. The current lx(n) is determined based on the voltages Vm and either Vb as shown or the reference voltage. The analog circuit 700 includes a differential amplifier 702, a differentiator 704 and a scaling device 706. The differential amplifier 702 receives the voltages i) Vm, and ii) Vb or the reference voltage. The differentiator 704 differentiates an output Vd of the differential amplifier 702 to provide an output Id. The scaling device 706 scales the output Id by multiplying the output by a scaling value K to provide lx. This may be represented by equation 4, where t is time.Ix = K * d(Vm — Vb) / dt (4)

[0083] Each of the controllers 190, 260 of FIGs. 1 -2 may include the analog circuits of FIGs. 6-7.

[0084] FIG. 8 shows a plot of measured base layer voltage Vb of a substrate support, measured substrate voltage Vx, measured plasma voltage Vp, and measured sidewall voltage Vsidewall versus time. The plasma potential Vp remains positive while the substrate potential Vx goes negative. As a result, the corresponding sheath voltage is equal to the substrate voltage Vx when Vx is less than 0. The plasma potential Vp remains greater than or equal to 0V.

[0085] FIG. 9 shows a plot of measured base layer voltage Vb, measured middle layer voltage Vm, and measured substrate (or top layer) voltage Vx versus time for a capacitive divider of a substrate support. FIG. 10 shows a plot comparing measured substrate (or top layer) voltage Vxm and calculated top layer voltage Vxc versus time of the substrate support. FIG. 1 1 shows a plot of calculated current Ix through the substrate.

[0086] FIG. 12 shows a diagram including a plot 1200 of substrate current versus substrate voltage Vx and a plot 1202 of corresponding intensity versus substrate voltage Vx provided by integrating bin sections of the substrate current versus voltage plot 1200. Example bins 1204 are shown and have respective bin widths (or intervals). As an example, each bin may have a 10V, 50V, 200V or other voltage width. The bins are integrated such that points in each of the bins are summed to provide a point value in the plot 1202. Plot 1202 includes an intensity versus voltage curve 1206. FIG. 13 shows an intensity versus ion energy plot (or ion energy distribution plot) provided by inverting the voltage polarity of the intensity plot 1202 of FIG. 12. This provides intensity versus ion energy curve 1300.

[0087] FIG. 14 shows a plot of intensity versus ion energy for a first bin size (e.g., 200V) based on the substrate current versus voltage plot of FIG. 12. FIG. 15 shows a plot of intensity versus ion energy for a second bin size (e.g., 50V) based on the substrate current versus voltage plot of FIG. 12. FIG. 16 shows a plot of intensity versus ion energy for a third bin size (e.g., 10V) based on the substrate current versus voltage plot of FIG. 12. In an embodiment, the voltage width (or interval size) of each bin determines the resolution of an ion energy distribution function (IEDF). The determined IEDF may be compared to a target IEDF. System parameters may then be adjusted based on the difference between the determined IEDF and the target IEDF, such as described with respect to operation 2016 of FIG. 20.

[0088] FIG. 17 shows a diagram including a plot 1700 of measured base layer voltage Vb, measured middle layer voltage Vm, and measured surface voltage Vx, a plot 1702 of a slope of the measured voltage versus time, and a plot 1704 of calculated current lx versus time for a component. The slope of Vx noticeably bends due to high electron flux with positive Vx, as identified by arrow 1706. The slop of Vx rapidly decreases subsequent to the identified bend in Vx, as indicated by arrow 1708. Range A is associated with negative current driven by a voltage generator. Range B is associated with negative current that continues to decrease (or increase in magnitude) while Vx increases and change in Vb slows down. This additional boost in current lx is attributed to electron flux. Range C is associated with the current lx increasing (or decreasing in magnitude) due to depletion of electrons near the substrate.

[0089] FIG. 18 shows a plot 1800 of electron density and positive ion versus time during a pulse. The plot 1800 shows time evolution of species densities. The plot 1800 includesan electron density curve 1802 and a positive ion curve 1804. The positive curve 1804 may be of any positive ion introduced into a process chamber. In the example shown, a plasma source was pulsed with a duty cycle ratio of 50%. There is no substrate bias. Each pulse is separated into four time windows l-IV. The first time window I refers to an early active-glow phase (or region). The second time window II refers to a late activeglow phase (or region). The third time window III refers to an after-glow phase (or region). The fourth time window IV refers to a late after-glow phase (or region). Plot 1800 provides an example relationship between the density and the active-glow and after-glow phases.

[0090] FIG. 19 shows a method of operating a substrate processing system is shown. The operations may be iteratively performed. The following operations 1900, 1902, 1904, 1906 and 1910 may be performed by a system controller (e.g., one of the system controllers of FIGs. 1 -2). At 1900, the system controller sets, determines and / or adjusts system inputs (or states of elements of the corresponding substrate processing system) including source power, component geometries, bias power, RF frequencies, fluid pressures, fluid flow rates, fluid compositions, chamber and component materials, temperatures, etc. The inputs may be adjusted based on keys including plasma properties, which may be determined at 1906.

[0091] At 1902, the system controller sets, determines and / or adjusts plasma parameters including source power, bias power, synchronous pulsing parameters, RF pulsing frequencies, duty cycle ratios between RF signals, phases of RF power, etc. The synchronous pulsing parameters may include amplitudes (or magnitudes), frequencies, duty cycles, timing, etc. The plasma parameters may be adjusted based on the keys including plasma properties, which may be determined at 1906.

[0092] At 1904, the system controller operates the corresponding substrate processing system to provide the keys. The keys may include etching yields and plasma properties. The plasma properties may include species densities, fluxes, EEAD, IEAD ion energy IEDF, electron energy distribution function (EEDF), impinging ion energy of positive ions, ion flux (or current), electron density, active-glow phase, and after-glow phase.

[0093] At 1906, the system controller measures and / or calculates and thus determines keys including etching yields, plasma properties, and other keys. In an embodiment, certain plasma properties are determined including the impinging ion energy of positive ions, ion flux, positive IEDF, and electron density. In this embodiment, a determination may be made whether the system is in the active-glow phase or the after-glow phase.Determination of the active-glow phase and after-glow phase is a determination of whether the substrate processing system is operating in the active-glow phase or the after-glow phase, examples of which are described with respect to FIG. 18.

[0094] At 1908, operation of the substrate processing system to provide the stated keys results in certain outputs. The outputs may include a certain etch rate, deposition rate, etch uniformity across a substrate, deposition uniformity across a substrate, etch selectivity, deposition selectivity, an anisotropy effect, an isotropy effect, a certain amount of damage, etc.

[0095] At 1910, the system controller may receive results from analysis of the substrate. The analysis may be performed subsequent to processing and at a location remote from the process chamber. The results of the analysis are directly related to the keys provided by the operation of the substrate processing system based on the inputs and plasma parameters.

[0096] FIG. 20 shows a substrate processing method including adjustment of system parameters based on detected plasma properties. The operations may be iteratively performed. The operations may be performed by a system controller (e.g., one of the system controllers of FIGs. 1 -2). At 2000, the system controller may determine and / or obtain a recipe for subsequent processing of a substrate. Parameters of the recipe may be set based on operator inputs.

[0097] At 2002, the system controller sets fluid pressures, fluid flow rates, fluid timing, RF power levels, RF frequencies, RF timing, bias power, and timing, and / or other system parameters based on the recipe.

[0098] At 2004, the system controller sets targets for plasma properties such as targets for the impinging ion energy of positive ions, ion flux, positive IEDF, and electron density. This may be based on the recipe.

[0099] At 2006, the system controller may perform a processing operation on a substrate such as an etch, deposition, or clean operation. At 2008, the system controller may determine whether another operation is to be performed on the substrate. If yes, operation 2002 may be performed, otherwise the method may end.

[0100] The following operations 2010, 2012, 2014, 2016 may be performed prior to, during, and / or subsequent to operations 2006, 2008.

[0101] At 2010, the system controller measures and / or calculates layer voltages of components and current levels at the components. This may include measuring voltages Vb, Vm of each of the one or more sensors involved and / or calculating voltage Vx and current lx of each of the one or more sensors, as described above.

[0102] At 2012, the system controller determines plasma properties based on the voltages Vb, Vm, Vx and current lx of the one or more sensors. For example, the impinging ion energy of positive ions is determined from the sheath voltage, which is equal to the voltage Vx minus the plasma voltage Vp. The impinging ion energy of positive ions may be determined when the sheath voltage is less than 0. The plasma voltage Vp may be measured with an additional measurement device or may be assumed to be 0V since the plasma voltage Vp is at a few electronvolts (eV) while Vx is less than 0V, as can be seen in FIG. 8. The current lx is directly related to ion flux and represents the ion flux of positive ions when Vx is less than 0V. See FIGs. 9-1 1. The positive ion energy distribution function is obtained from the measurement of substrate voltage Vx and ion flux lx when the sheath voltage is less than 0V. See FIGs. 12-16. The electron density can be obtained with analysis of Vx(t) and lx(t) when Vx is greater than Vp. See FIG. 17.

[0103] A determination of whether the substrate processing system is in the active-glow or after-glow phase with pulsing plasma may be obtained from analysis of Vx, lx, and Vp. See FIG. 18. Electron density is high during the active-glow phases I and II and low during the after-glow phases III and IV. The determination may be made based on the determined electron density.

[0104] At 2014, the system controller compares the determined plasma properties to the targets. If the targets are satisfied then operations 2010 is performed, otherwise operation 2016 is performed. The targets may be satisfied when the determined plasma properties are within predetermined ranges (e.g., within ±5% or less of the target values).

[0105] At 2016, the system controller adjusts system input parameters such as fluid pressures, fluid flow rates, fluid timing, RF power levels, RF frequencies, RF timing, bias power levels, and timing, and / or other system parameters based on the differences between the target values and the determined values of the plasma properties. Operation 2010 may be performed subsequent to operation 2016.

[0106] FIG. 21 shows an example substrate processing system 2100 including the process chamber 102 having a substrate support 2104 supporting a substrate 2106 and the chamber body 108. The chamber body 108 includes the inner sidewall surface 109,the first window 1 10, and the feedthrough seal 112. The substrate processing system 2100 is similar to the substrate processing system 100 of FIG. 1 , except the substrate support 2104 replaces the substrate support 104.

[0107] Sensors 2120, 122, 124, 126 are included and are examples of some capacitive divider-based sensors that may be included in the substrate processing system 2100. Each of the sensors 2120, 122, 124, 126 is used to detect plasma properties and includes multiple capacitors connected in series to provide a capacitive divider. The capacitors are provided by corresponding conductive layers and dielectric layers of the components of the substrate processing system. The components include conductive and dielectric layers.

[0108] The substrate support 2104 may include a body 2130 formed of dielectric material, a first conductive layer 2132, a first dielectric layer 2134, one or more RF electrodes 2140, a second dielectric layer 2138, electrostatic clamping electrodes 2142, and a third dielectric layer 2143. The RF electrodes are electrically connected to the conductive layer 2132. This may be done via one or more conductive traces 2135.

[0109] The conductive layer 2132, the conductive traces 2135 and the RF electrodes 2140 are collectively a first conductive layer of a first capacitor C1. In an embodiment, conductive layer 2132 and conductive traces 2135 are not included and RF voltage Vrf is supplied directly to the RF electrodes 2140. The electrostatic clamping electrodes 2142 are the second conductive layer of the first capacitor C1 . The first conductive layer of C1 , the second conductive layer of C1 , and the dielectric layer 2138 perform as the first capacitor C1 . Electrostatic electrodes 2142, dielectric layer 2143 and a top surface 2139 of the substrate 106 perform as the second capacitor C2. The capacitors C1 , C2 are electrically coupled in series and perform as a capacitive divider. The electrodes 2140, 2142, and the conductive layer 2132 may be formed of aluminum, steel, copper, and / or other conductive material. The conductive layer 2132 may be circular shaped and have smaller diameters than a diameter of the substrate support 2104. The conductive layer 132 and the electrodes 2140, 2142 are embedded within the substrate support 2104. The conductive layer 2132 may receive a RF voltage Vrf, which is received at the electrodes 2140. The electrostatic clamping electrodes 2142 receive an electrostatic clamping voltage Ve.

[0110] The sidewall 150 of the chamber body 108 is shown and includes the conductive outer layer 151 and the dielectric inner layer 152 having the inner sidewall surface 109.The sensor 122 includes the conductive element 154, which is surrounded by the dielectric insulative layer 156 that is disposed between the conductive element 154 and the conductive outer layer 151. The conductive element 154, the dielectric inner layer 152, and the inner surface 157 of the dielectric layer 156 adjacent the conductive element 154 perform as a second capacitor that is connected in series with the first capacitor to provide a capacitive divider of the sensor 122. The first voltage probe 158 is connected to the conductive element 154 via a conductive line 159.

[0111] The first window 1 10 has the dielectric body 160 including the channel 162. The conductive element 164 is disposed in the channel 162. The second probe 166 is connected to the conductive element 164 via the conductive line 167. The first portion 168 of the dielectric body 160 is disposed between the conductive element 164 and the inner surface 171 of the dielectric body 160. The second portion 169 of the dielectric body 160 is disposed between the conductive element 164 and the conductive outer layer 151 .

[0112] The feedthrough seal 1 12 seals off the end of the opening 170 in the sidewall 150 near the third voltage probe 180. The dielectric layer 172 exists between i) the outer conductive layer 151 and ii) plasma 181 and the feedthrough seal 1 12. A portion of the plasma 181 is in the opening 170 between a dielectric layer 176 and the dielectric layer 172. The conductive element 174 is surrounded by the dielectric layer 176. The first portion 178 of the dielectric layer 176 is disposed between the conductive element 174 and the plasma 150. The second portion 179 of the dielectric layer 176 is disposed between the conductive element 174 and the conductive outer layer 151 . The conductive element 174, the second portion 179, and the conductive outer layer 151 perform as the first capacitor. The conductive element 174, the first portion 178, and the inner surface 183 of the first portion 178 perform as the second capacitor. The third probe 180 is connected to the conductive element 174 via the conductive line 182 and detects the voltage at the conductive element 174. The surface of the portion 179 is exposed to the plasma 181 and is located away from the sidewall 150.

[0113] The substrate processing system 100 further includes the system control circuit 190 including the RF generator 192 that is configured to generate and / or provide a RF voltage Vrf to the conductive layer 2132, and an electrostatic clamping voltage Ve to the electrodes 2142. The system control circuit 190 is also configured to monitor voltages Vb, Vm respectively at the conductive layer 2132 and the RF electrodes 2142 and voltages detected by the voltage probes 158, 166, 180. The conductive layer 132 andthe electrodes 2140 may be collectively referred to as a base conductive layer and be at a voltage potential Vb. The electrodes 2140 may be referred to as a conductive layer or a conductive base layer depending on whether the conductive layer 2132 is included. The voltage potential Vb may be the same as the voltage Vrf. The RF electrodes 2142 may be referred to as conductive middle layer and be at a voltage potential Vm, which may be equal to Ve, which is generated by the DC voltage generator 194. The system controller 190, based on the voltages Vb, VM and the voltages detected by the voltage probes 158, 166, 180 determines plasma properties as described below.

[0114] When troubleshooting process chamber matching issues, multiple blanket wafers with fingerprint recipes are typically used i) to measure etch rate, ii) to determine whether there is a plasma property deviation larger than a specification requirement, and iii) to determine where the property deviation is coming from. This is a slow process to troubleshoot since etch rate measurement of wafers is done separately using special measurement equipment. Non-invasive in-situ measurement as disclosed herein of key plasma properties such as IEDF, EEDF, and active-glow and after-glow phases enables rapid iteration of troubleshooting cycles of chamber matching.

[0115] The key plasma properties are outcomes resulted by inputs such as process gas mixtures, gas flows, gas pressure, RF powers, etc. Process optimization typically scans a matrix of the input parameters to find a trend for improving on-wafer performance. The examples described herein enable feedback control of the key plasma properties that are more directly related to on-wafer performance. This provides insight about the process results and accelerates process development cycles.

[0116] The examples described herein enable closed loop control of each key plasma property. Conventionally, key plasma properties were unknown and blended with system inputs and pulsed plasma parameters to obtain an understanding of system outputs (i.e., results) using remote or offsite substrate analysis. The examples disclosed herein provide a two-part development process that includes i) providing relationships between system inputs and key plasma properties, and ii) between key plasma properties and resulting outputs. In an embodiment, the disclosed control algorithm automatically tunes the system inputs to provide target key plasma properties, which provides a better understanding of how the key plasma properties impact the resulting outputs.

[0117] The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure canbe implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and / or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

[0118] Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”

[0119] In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequencysettings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0120] Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0121] The controller, in some implementations, may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from multiple fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller may be distributed, such as by comprising one or more discretecontrollers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0122] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0123] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

Claims

CLAIMSWhat is claimed is:1 . A substrate processing system comprising: a sensor disposed at least partially within at least one component of a process chamber of the substrate processing system, wherein the sensor comprises a capacitive divider, wherein the capacitive divider comprises a first capacitor and a second capacitor connected in series, and wherein the first capacitor and the second capacitor comprise a conductive base layer and a conductive middle layer; and at least one controller configured to detect a first voltage of the conductive base layer and a second voltage of the conductive middle layer, based on the first voltage and the second voltage, determine a first plasma property of plasma in the process chamber, and adjust a parameter of the substrate processing system based on the first plasma property.

2. The substrate processing system of claim 1 , wherein the sensor is embedded in a substrate support of the process chamber.

3. The substrate processing system of claim 1 , wherein the sensor is embedded at least partially in a window of the process chamber.

4. The substrate processing system of claim 3, wherein the window is a transformer coupled plasma window, a capacitive coupled plasma window, or a remote plasma source window and is disposed above a substrate support of the process chamber.

5. The substrate processing system of claim 3, wherein the window is disposed in a sidewall of the process chamber.

6. The substrate processing system of claim 1 , wherein the sensor is embedded in a wall of the process chamber.

7. The substrate processing system of claim 1 , wherein the sensor is disposed at least partially in an opening exposed to the plasma and is connected to a feedthrough seal.

8. The substrate processing system of claim 1 , wherein: the sensor comprises the first capacitor comprising the conductive base layer, the conductive middle layer and a first dielectric layer disposed between the conductive base layer and the conductive middle layer, and the second capacitor comprising the conductive middle layer, a second dielectric layer, and an inner surface of the second dielectric layer; and the second dielectric layer is disposed between the conductive middle layer and the plasma.

9. The substrate processing system of claim 1 , wherein the conductive base layer is a conductive layer of a wall of the process chamber.

10. The substrate processing system of claim 1 , wherein: the sensor comprises the first capacitor comprises the conductive base layer, the conductive middle layer and a first dielectric layer disposed between the conductive base layer and the conductive middle layer, and the second capacitor comprises the conductive middle layer, a second dielectric layer, and a top surface of a substrate; and the second dielectric layer is disposed between the conductive middle layer and the plasma.11 . The substrate processing system of claim 1 , wherein: the sensor comprises the first capacitor comprises the conductive base layer, the conductive middle layer and a first dielectric layer disposed between the conductive base layer and the conductive middle layer, and the second capacitor comprises the conductive middle layer, a second dielectric layer, and the plasma; andthe second dielectric layer is disposed between the conductive middle layer and the plasma.

12. The substrate processing system of claim 1 , wherein the sensor comprises: the first capacitor comprising the conductive base layer, the conductive middle layer and a first dielectric layer; the first dielectric layer is disposed between the conductive base layer and the conductive middle layer; the second capacitor comprises the conductive middle layer, a second dielectric layer, and an inner surface of the second dielectric layer; the conductive middle layer is surrounded by the second dielectric layer; and a portion of the second dielectric layer is disposed between the plasma and the conductive middle layer.

13. The substrate processing system of claim 12, the portion of the second dielectric layer is a portion of an inner surface layer of a wall of the process chamber.

14. The substrate processing system of claim 1 , further comprising a window comprising a channel, wherein: the conductive middle layer is disposed within the channel; a first dielectric portion of the window is disposed between the conductive middle layer and the plasma; and a second dielectric portion of the window is disposed between the conductive middle layer and the conductive base layer.

15. The substrate processing system of claim 1 , wherein the at least one controller is configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine the first plasma property.

16. The substrate processing system of claim 1 , wherein the at least one controller is configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine a plurality of plasma properties including the first plasma property; and the plurality of plasma properties including an impinging ion energy of positive ions, ion flux, a positive ion energy distribution function, and electron density.

17. The substrate processing system of claim 1 , wherein the at least one controller is configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine whether the substrate processing system is operating in an active-glow phase or an after-glow phase.

18. The substrate processing system of claim 1 , wherein the at least one controller comprises a digital signal processor configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine a voltage at a surface of a substrate disposed on a substrate support of the process chamber and an amount of current passing through the substrate support.

19. The substrate processing system of claim 1 , wherein the at least one controller comprises a digital signal processor configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine a voltage at a surface of the sensor exposed to the plasma and an amount of current passing through the sensor.

20. The substrate processing system of claim 1 , wherein the at least one controller comprises a digital signal processor configured to, based on the first voltage, the second voltage, a capacitance of the first capacitor and a capacitance of the second capacitor, determine a voltage at a surface of the at least one component and an amount of current passing through the sensor.21 . The substrate processing system of claim 1 , wherein: the at least one controller comprises a first scaling device configured to scale the first voltage, a second scaling device configured to scale the second voltage, and a differential amplifier configured to determine a third voltage based on a difference between the scaled first voltage and the scaled second voltage; and the at least one controller is configured to determine the first plasma property based on the third voltage.

22. The substrate processing system of claim 1 , wherein: the at least one controller comprisesa differential amplifier configured to generate a third voltage based on a difference between the first voltage and the second voltage, a differentiator configured to differentiate the third voltage to provide current, and a scaling device configured to scale the current; and the at least one controller is configured to determine the first plasma property based on the current.

23. The substrate processing system of claim 1 , wherein: the conductive middle layer comprises one or more electrostatic clamping electrodes; and the conductive base layer comprises one or more radio frequency electrodes.

24. The substrate processing system of claim 1 , further comprising: one or radio frequency electrodes; and one or more conductive traces electrically connecting the conductive base layer to the one or ore radio frequency electrodes.

25. A method of operating a substrate processing system, the method comprising: setting system inputs of the substrate processing system; setting plasma parameters of the substrate processing system; operating the substrate processing system based on the system inputs and the plasma parameters to provide keys, wherein the keys include at least one plasma property; measuring voltages of layers of a sensor, wherein the sensor comprises a capacitive divider; calculating the at least one plasma property based on the voltages of the layers of the sensor; and adjusting at least one of the system inputs and the plasma parameters based on the at least one plasma property.

26. The method of claim 25, wherein the sensor is implemented in a substrate support, a window or a wall of a process chamber.

27. The method of claim 25, wherein the layers are conductive elements of the capacitive divider.

28. The method of claim 25, wherein the at least one plasma property comprises a plurality of plasma properties.

29. The method of claim 25, wherein the at least one plasma property comprises at least one of an impinging ion energy of positive ions, ion flux, a positive ion energy distribution function, and an electron density.

30. The method of claim 25, further comprising: determining whether the substrate processing system is operating in an activeglow phase or an after-glow phase based on the voltages of the layers; and adjusting the at least one of the system inputs and the plasma parameters based on whether the substrate processing system is operating in the active-glow phase or the after-glow phase.31 . A method of operating a substrate processing system, the method comprising: setting at least one target for at least one plasma property; measuring and / or calculating parameters of layers of a component in the substrate processing system, wherein the component comprises at least partially a capacitive divider; determining the at least one plasma property based on the parameters; comparing the at least one target to the determined at least one plasma property; and adjusting at least one parameter of the substrate processing system based on results of comparing the at least one target to the determined at least one plasma property.

32. The method of claim 31 , further comprising: determining voltages of the layers, wherein the capacitive divider comprises the layers; and determining the at least one plasma property based on the voltages.

33. The method of claim 31 , further comprising: determining current passing through the capacitive divider; and determining the at least one plasma property based on the current.

34. The method of claim 31 , wherein the at least one plasma property comprises at least one of an impinging ion energy of positive ions, ion flux, a positive ion energy distribution function, and an electron density.

35. The method of claim 31 , further comprising: determining whether the substrate processing system is operating in an activeglow phase or an after-glow phase based on the parameters of the layers; and adjusting the at least one parameter of the substrate processing system based on whether the substrate processing system is operating in the active-glow phase or the after-glow phase.

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