CMOS imager with backside bias for broad band imaging

Abstract

In a CMOS image sensor, a bias connection is made of a first semiconductor material and arranged to be reversed biased by a voltage source opposite in polarity to a polarity of the first semiconductor material. A pixel can include a photosensitive element that includes a first well made of a second semiconductor material and a second well made of the first semiconductor material. The implanted or epitaxial growth buried layer is made of the second semiconductor material and extends continuously across a region making up the pixel array beneath the first and the second well of the pixels. The implanted buried layer made with the second semiconductor material is arranged to cooperate with the reverse bias applied to the bias connection to reduce a parasitic current path between the second well and a substrate.

Description

CMOS IMAGER WITH BACKSIDE BIAS FOR BROAD BAND IMAGINGRELATED APPLICATIONS

[0001] This application claims priority to and the benefit of under 35 USC 119 of U.S. provisional patent application titled “CMOS imager with backside bias for broad band imaging,” filed Nov. 02, 2023, serial number 63 / 595,586, which is incorporated herein in its entirety by reference.FIELD[2] Embodiments generally relate to an image sensor.BACKGROUND[3] CMOS imagers can have a bias applied to a substrate. For example, see US patent 8,592,245 where a single layer of EPI runs across a pixel and its associated support circuitry. (See Figure 1 illustrating Figure 5 of US patent 8,592,245 showing a CMOS imager with a PMOS pixel and a p-type photodiode. Also, in a previous US patent application publication US2015 / 0263058A describing an NMOS pixel an n-type photodiode, the process places pockets of N- doping buried under each Pwell isolation region. The N- doping is deep and the pockets are small which requires thick resist or hard masking with small openings such that the resist or hard mask thickness to the opening aspect ratio is difficult to achieve. A high aspect ratio makes it very difficult to pattern maintaining good critical dimension (CD) and alignment controls. For example, the pocket of N- doping depth can be in the range of 2 to 3 urn which requires resistthickness in the range of 3 to 4 um. An N- doping resist opening can be as small as 0.6 um such that the opening aspect ratio, resist thickness to the opening width, can be in the range of 5 to 6.7 Such a high aspect ratio is very difficult to pattern to produce a uniform critical dimension (CD) from the top to bottom of the resist opening and consistent across a large array. For a 4 um thick resist there is a 0.7 um CD difference between the top and bottom of the opening. Also, any misalignment of the pocket of the N- region can change the N- potential barrier height. So, the previous CMOS imagers’ structure as described in patent US2015 / 0263058A is highly susceptible to large pixel to pixel variability for full well saturation, blooming, sub threshold leakages even with a bias applied, and possibly high photo-response non-uniform ity (PRNU).SUMMARY[4] Provided herein are some embodiments of apparatus and methods associated with an image sensor. In an embodiment, a complementary metal-oxide- semiconductor (CMOS) image sensor has various components including a bias connection, a pixel array, a substrate, and an implanted or epitaxial grown buried layer which is continuous in the pixel array. The bias connection is made of a first semiconductor material type arranged to be reversed biased by a voltage source opposite in polarity to a polarity of the first semiconductor material type. A pixel can include a photosensitive element that includes a first well made of a second semiconductor material type and a second well made of the first semiconductor material type. The second well can be utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image signal captured by the photosensitive element. The buried layer is made of the second semiconductor material type and extends across a region making up the pixel array beneath the first and the second well of the pixel. The implanted / epi buried layer made with the second semiconductor material type is arranged to cooperate with the reversed bias applied by the voltage source to the active region to reduce a parasitic current path between the second well made of the first semiconductor material type utilized by the active CMOS elements and a substrate, which will result in low leakage current as bias is applied, improved charge collection with lower lateral signal charge spreading and more uniform pixel to pixel performances in an image sensor with two or more pixels.[5] In an embodiment, the CMOS image sensor has various components including a bias connection, a pixel array, a substrate, and two or more layers ofepitaxial films. The bias connection is made of a first semiconductor material type arranged to be reversed biased by a voltage source opposite in polarity to a polarity of the first semiconductor material type. A pixel can include a photosensitive element that includes a first well made of a second semiconductor material type and a second well made of the first semiconductor material type. The second well can be utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image signal captured by the photosensitive element. Two or more layers of epitaxial films are doped so that at least one of the epitaxial layers is doped to have an opposite polarity to the active region made of the first semiconductor material type. The two or more epitaxial layers are arranged to cooperate with the reversed bias applied by the voltage source to the active region to reduce a parasitic current path between the second well made of the first semiconductor material type utilized by the active CMOS elements and a substrate to increase the electric field to reduce photocharge lateral spreading and to cut off the parasitic current leakage path in an image sensor with two or more pixels.[6] These and other features of the design provided herein can be better understood with reference to the drawings, description, and claims, all of which form the disclosure of this patent application.BRIEF DESCRIPTION OF THE DRAWINGS[7] The drawing refers to example embodiments of the design.[8] Figure 1 illustrates Figure 5 of US patent 8,592,245 showing a CMOS imager.[9] Figure 2a illustrates an example embodiment of a cross-section block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., an NMOS pixel) with a backside bias.

[0010] Figure 2b illustrates an example embodiment of a cross-section block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., a PMOS pixel) with a backside bias.

[0011] Figure 3 illustrates an example embodiment of a cross-section block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., an NMOS pixel) with a backside bias.

[0012] Figure 4a illustrates an example embodiment of a cross-section block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., NMOS pixels) with a backside bias where the substrate comprises two or more epitaxial films.

[0013] Figure 4b illustrates an example embodiment of a cross-section block diagram of the CMOS image sensor, similar to Figure 4a, with two or more layers of EPI and an active region on the top side of the CMOS image sensor being reverse biased but with a PMOS pixel.

[0014] Figure 5a illustrates an example embodiment of a block diagram of the CMOS image sensor with one or more NMOS pixels with backside bias and two or more epitaxial films.

[0015] Figure 5b illustrates an example embodiment of a cross-section block diagram of the CMOS image sensor, similar to Figure 5a, with one or more PMOS pixels with backside bias and two or more epitaxial films.

[0016] Figure 6a illustrates an example embodiment of a cross section block diagram of the CMOS image sensor with one or more NMOS pixels with backside bias and three or more epitaxial films.

[0017] Figure 6b illustrates an example embodiment of a cross section block diagram of the CMOS image sensor, similar to Figure 6a, with one or more PMOS pixels with backside bias and three or more epitaxial films.

[0018] Figure 7a illustrates an example embodiment of a cross section block diagram of the CMOS image sensor with a single extra thick N- epi substrate, and an NMOS pixel, and a bias connection.

[0019] Figure 7b illustrates an example embodiment of a cross section block diagram of the CMOS image sensor with a backside bias employing the bias connection with a vertical channel front to back P- region.

[0020] Figure 8 illustrates an example embodiment of a block diagram of a complete CMOS image sensor showing support functions with two or more pixels in the pixel array that use the bias connection with reverse bias applied, and the implanted buried layer and / or epi film layer.

[0021] While the design is subject to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. The design should be understood to not be limited to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the design.

[0022] DETAILED DISCUSSION

[0023] In the following description, numerous specific details are set forth, such as examples of specific data signals, named components, etc., in order to provide a thorough understanding of the present design. It will be apparent, however, to one of ordinary skill in the art that the present design can be practiced without these specific details. In other instances, well-known components or methods have not been described in detail but rather in a block diagram in order to avoid unnecessarily obscuring the present design. Further, specific numeric references, such as a first pixel, can be made. However, the specific numeric reference should not be interpreted as a literal sequential order but rather interpreted that the first pixel is different than a second pixel. A first semi-conductor material type can be, for example, a P+ type semiconductor material and as such then a second semi-conductor material type would be the opposite, e.g., a N- type semiconductor material. Thus, the first semi-conductor material type can be, for example, a N- type semiconductor material and as such then a second semi-conductor material type would be the opposite, e.g., a P+ type semiconductor material. Thus, the specific details set forth are merely exemplary. Also, the features implemented in one embodiment may be implemented in another embodiment where logically possible. The specific details can be varied from and still be contemplated to be within the spirit and scope of the present design. The term coupled is defined as meaning connected either directly to the component or indirectly to the component through another component.

[0024] Figure 2a illustrates an example embodiment of a cross section block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., anNMOS pixel) with a backside bias. The CMOS image sensor is constructed with a biasconnection / region 13 made of a P+ type semiconductor material arranged to be reversed biased / backside biased by a voltage source opposite in polarity (e.g., V -) to a polarity of the P+ type semiconductor material type making up the bias connection / region 13. The pixel 1-6 can include a photosensitive element that includes a surface pinning implant 2, a photodiode well 3 made of an N- type semiconductor material, and a well 1 made of a P+ type semiconductor material; a transfer gate 4; a sense node 5 made of an N+ type semiconductor material, and its sense node well region 6 made of a P+ semiconductor material type. The readout circuit’s and reset FETs are in wells 1 and 6. The sense node 5 and transfer gate 4 can be utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image data captured by the photosensitive element 2, 3. The NMOS pixel structure also includes CMOS logic 15. The CMOS image sensor is constructed with an implanted buried layer 10 that is made of the N- semiconductor material type that extends across a region (e.g. real estate) making up the pixel 1 -6 beneath the wells 1 , 6 made of the P+ semiconductor material type as well as sometimes extends beneath the zone for the support circuitry - guard ring region 7, vertical N- Deep well region 11 , top N- well regions 12. The CMOS image sensor is also constructed with an epitaxial (EPI) substrate 8 and a backside layer 9. The implanted buried layer 10 made with the N- semiconductor material type is arranged to cooperate with the reversed bias applied by the voltage source to the bias connection / region 13 to reduce (e.g. pinch off / stop) a parasitic current path between the wells 1 , 6 made of the P+ semiconductor material type utilized by the active CMOS elements and the EPI substrate 8, which is doped to have a P polarity. Pinching off the parasitic current path between the wells 1 , 6 made ofthe P+ semiconductor material type and the EPI substrate 8 will result in a more uniform pixel to pixel performance in this CMOS image sensor with two or more pixels. The NMOS pixel has a n-type photodiode in p-type epi with an implanted (or epitaxially grown) buried continuous n-layer 10 under the pixel array 1 -6 on p-type epi substrate 8. The bias connection 13 can be a pocket of semiconductor material.

[0025] Figure 2b illustrates an example embodiment of a cross section block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., a PMOS pixel) with a backside bias. Similar to Figure 2a, the CMOS image sensor in Figure 2b is constructed with a bias connection / region 13, but is made of an N+ semiconductor material type, arranged to be reversed biased / backside biased by a voltage source opposite in polarity (e.g., V +) to a polarity of the N+ semiconductor material type making up the bias connection / region 13. The PMOS pixel 1 -6 can include a photosensitive element that includes a surface pinning implant 2, a photodiode well 3 made of an P+ type semiconductor material, and a well 1 made of an N- type semiconductor material; a transfer gate 4; a sense node 5 made of a P+ type semiconductor material and its sense node well region 6 made of an N- semiconductor material type. The sense node 5 and transfer gate 4 can be utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image data captured by the photosensitive element 2, 3. The CMOS image sensor is constructed with an implanted buried layer 10 made of the P+ semiconductor material type that extends across a region making up the pixel 1 -6 beneath the wells 1 , 6 made of the N- semiconductor material type as well as sometimes extends beneath the zone for the support circuitry - guard ring region 7 connected to VDD ground, the deep well P+ region 11 , and the topP+ region 12. The PMOS pixel structure also includes CMOS logic 15. The CMOS image sensor is also constructed with an EPI substrate 8 and a backside layer 9. The implanted buried layer 10 made with the P+ semiconductor material type is arranged to cooperate with the reversed bias applied by the voltage source to the bias connection / region 13 to reduce (e.g. pinch off / stop) a parasitic current path between the wells 1 , 6 made of the N- semiconductor material type utilized by the active CMOS elements and the EPI substrate 8 doped to have an N- polarity, which will result in a more uniform pixel to pixel performance in the CMOS image sensor with two or more pixels. Note, the extent of the pinch-off can be dependent on the bias applied and depth of the implanted buried layer 10 (or in another embodiment the epi layer 10). The pinch-off can be achieved under all operating conditions and is possible if the wells are deep and / or more highly doped than the photosensitive elements. The parasitic substrate current can be eliminated in the CMOS image sensor. The implanted buried layer 10 (or in another embodiment the epi layer 10) contacts or otherwise cooperates with the well of the support circuitry as well as the bias applied to the bias connection 13 to eliminate the parasitic substrate current in the CMOS image sensor. The pixel type is PMOS pixel with a p-type photodiode in a n-type epi with an implanted buried continuous p-layer 10 under the pixel array 1-6 on an n-type epi substrate 8.

[0026] Please note that what has been shown for NMOS pixels also applies when all semiconductor types are switched to the opposite polarity. Photo-holes in N-type are used and similarly photo-electrons are used in P-type. Thus, the CMOS image sensor with one or more NMOS pixels with backside bias in Figure 2a shown thus far is for a CMOS image sensor that captures an electron as the signal / photo carrier. The sameprinciple can be applied to image sensors with a PMOS pixel that captures a hole as the signal (e.g., Figure 2b). The doping type for each region will need to be flipped / reversed. A backside bias hole sensor structure equivalent to Figure 2a is shown in Figure 2b. For example, Pwell regions 1 and 6 now become Nwell regions 1 and 6, P- doped epi substrate 8 now becomes an N- doped epi substrate 8, P type material backside layer 9 now becomes N type material region 9, bias connection 13 which is made of P+ semiconductor material now becomes N- semiconductor material, implanted buried layer 10 made of N- semiconductor material is now made of P+ semiconductor material, etc.

[0027] Referring to Figures 2a and 2b, the implanted buried layer 10 made of the second semiconductor material type, (P+ semiconductor material type for a PMOS pixel and N- semiconductor material type for an NMOS pixel) is arranged to cooperate with the reversed bias applied by the voltage source to the bias connection 13 to extend an electric field all the way through the substrate 8 (and be as high as possible) to increase the electric field to reduce photocharge lateral spreading and to cut off the parasitic current leakage path. The implanted buried layer 10 is made by an implant process (or epitaxial growth process for Figures 4a through 6b). A region of a first polarity type (e.g., P+ type in Figure 2a) is continuous from the top down vertically from the bias connection 13 and then over laterally via the epi substrate 8 under all of the pixel 1 -6. The bias connection 13 is electrically connected to the epi substrate 8. However, the implanted buried layer 10 made of the second semiconductor material type isolates the bias connection region 13 with its reverse bias applied and the electrically connected substrate 8 from the pixel 1 -6. The reverse bias with low parasitic leakage currentreduces lateral photocharge spreading to improve image sensor resolution and permits thicker silicon for improved sensitivity particularly in the near infrared for image sensors with two or more pixels.

[0028] The CMOS image sensor with one or more pixels and a backside bias for broad band imaging is much simpler to manufacture and does not need state of the art lithography equipment. In Figure 2a, the implanted buried layer 10 is made of N-type semiconductor material so that it has an excess of electrons (e.g., n-) and is uniform across the array which results in more uniform pixel to pixel performances. The CMOS image sensor with one or more pixels and a backside bias places this blanket of implanted buried layer 10 made of N-type semiconductor material evenly in the array. The resist opening covers the whole array. The resist thickness to opening aspect ratio is much less than 1 , which should have no problem patterning. There is no need to maintain Critical Distance and alignment control.

[0029] Again, in Figure 2a, the CMOS image sensor has a pixel with a backside bias applied to bias connection 13 and buried N type of semiconductor material (N-) implant layer 10. The resist opening covers the array and the guard ring. This makes patterning significantly easier to manufacture which is a huge advantage. There is no need to maintain tight Critical Distance control of small resist openings. The doping is uniform evenly that eliminates the need to maintain precise alignment control of the N- edges in the previous CMOS sensor. Now, the implanted buried layer 10 made of N- material is depleted and forms a sub-threshold barrier to electrically isolate the top Pwell region 1 , 6 from the P- epi substrate 8.

[0030] In Figure 2a, the implanted buried layer 10 made of N- type material cooperates with the backside bias applied to the active region 13 to allow the use of a thicker epi substrate 8. The thicker epi substrate 8 increases the quantum efficiency of absorbing photons for the full wavelength range. The CMOS image sensor will have a higher performance uniformity in full well capacity, less blooming leakages, and a photo response uniformity, which will result in more uniform pixel to pixel performances.

[0031] Next, the implanted buried layer 10 made with the second semiconductor material type is constructed to extend uniformly across the region making up the pixel 1 - 6 but not under a second region making up the bias connection 13 made of the first semiconductor material type. The bias connection 13 made up of the first semiconductor material type is configured to work in relationship with the implanted buried layer 10 such that the bias connection 13 can be / ‘is capable of being’ located either 1 ) on a top side of a chip containing the layers of the CMOS image sensor or 2) on a bottom side of the chip containing the layers of the CMOS image sensor.

[0032] The implanted buried layer 10 made with the second semiconductor material type is constructed with semiconductor material type with a doping concentration in a range of about 1e16to 1e13(preferably 1e15to 1 e14) per cubic centimeter. In Figure 2a, the implanted buried layer 10 made of N-type semiconductor material (N-) has a doping concentration in the range of 1e14to 1 e15 / cm3for ion implantation. A larger pixel generally needs the buried n- epi concentration to be lower than 1e15 / cm3, which is below the implant limit.

[0033] The backside layer 9 can be constructed with at least one of 1 ) an epitaxial layer or 2) graded materials that are doped to match a polarity of the first semiconductormaterial type used in the bias connection 13 and the polarity of the substrate layer 8. The backside layer 9 is located below the substrate layer 8. FETs are located to the right of Pwell 1 .

[0034] In Figure 2a, the CMOS logic 15 cooperates with the Nwell 12 and deep Nwell 11 to implement image sensor control / signal processing circuits. The CMOS logic 15 cooperates with the Nwell 12 and deep Nwell 11 and is being isolated by the Nwell 12 and deep Nwell 11 from connecting to the implanted buried layer 10 made of N - type material. The well structure of the Nwell 12 and deep Nwell 11 are located between the pixel array 1-5 and the bias application to the bias connection / region 13.

[0035] The buried layer can be either the implanted buried layer 10 or provided by epitaxial grow as the epi layer 10 by the wafer starting material design and manufacture prior to foundry wafer fabrication. In an embodiment, the two or more layers of epitaxial films can be uniformly doped and formed prior to going through the foundry wafer fabrication process. The two or more layers of epitaxial films can be uniformly doped and formed so that at least one of the epitaxial layers is doped to have an opposite polarity to the active region made of the first semiconductor material type via epitaxial grow with a wafer’s starting material as a manufacturing step prior to a wafer fabrication in a foundry.

[0036] Operation

[0037] In the operation of the CMOS image sensor of Figure 2a, a photon strikes the silicon substrate 8 to generate an electron hole pair. Electrons are collected by the N- photodiode 3 region and then transferred into the N+ sense node 5 at the end of the integration to be sampled by the read out integrated circuit, (ROIC). Generated holes inthe silicon substrate 8 flow out to the ground electrode of the voltage source connected to the P+ sub region 7.

[0038] Broadband imaging with the CMOS image sensor uses a very thick epitaxial substrate 8 that results in a large field free region at the substrate bottom. The thick substrate is used to maximize photon collection efficiency for both short wavelengths and long wavelengths. However, photo carriers that generate at the bottom of the epi substrate 8 outside the photodiode depletion region need to first transit toward the photodiode by thermal diffusion. Thus, the photo carriers (e.g. holes or electrons) generated in the no field region need to first transit toward the photodiodes 3 by thermal diffusion. Once reaching the photodiode depletion edge, the electric field helps drive the photo carrier vertically toward the photodiode center. However, thermal diffusion is a random process and carriers transport both vertically and laterally. The photo carriers that transit laterally can end up being collected by a neighboring pixel on the image sensor. This results in a reduced collection efficiency for the illuminated pixel with a higher neighbor pixel crosstalk, which degrades the sensor sampling frequency or MTF. For this reason, the CMOS image sensor employs different front and back biases to form an electric field across the whole epi substrate 8. For this to be possible, the implanted buried layer 10 has an opposite polarity type material relative the wells 1 , 6 of the pixel and is placed below the image sensor well region 1 , 6 to disconnect the wellsl , 6 from the substrate 8 since the wells 1 , 6 and the substrate 8 are typically made of the same type of semiconductor material.

[0039] The implanted buried layer / epi 10 made of the second semiconductor material type is located above the substrate 8 made of the first semiconductor materialtype to separate / disconnect the substrate 8 from the second well 1 , 6 also made of the first semiconductor material type. The substrate 8 is up to 200 urn thick in order to efficiently absorb photons in a range of light optimized for UV wavelengths to infrared wavelengths. In an embodiment, the substrate 8 is about 20 urn thick. In an embodiment, the substrate 8 is about 200 urn thick.

[0040] The CMOS image sensor can be illuminated either from the frontside or the backside. A near infrared photon absorbs deeper in the silicon substrate 8, up to 200 urn thick, while an ultraviolet photon absorbs near the silicon surface, <0.1 urn. For broadband imaging, a thick substrate 8 is used to maximize photon collection efficiency for both short wavelengths and long wavelengths. However, as discussed, photo carriers that generate at the bottom of the epi substrate 8 outside the photodiode depletion region need to first transit toward the photodiode 3 by thermal diffusion. Once reaching the photodiode depletion edge, the photodiode electric field further assists carrier transport vertically toward the photodiode center. The problem with thermal diffusion is that carriers transport both vertically and laterally. Carriers that transit laterally may end up in the neighbor pixel before that carrier encounters the drift field. This is worse when there is narrower pixel spacing with a very thick substrate in the real estate making up the pixel 1-6 where the vertical transit distance is multiple times the pixel width. This results in reduced collection efficiency for the illuminated pixel 1-6 along with a higher neighbor pixel crosstalk, which degrades the CMOS image sensor sampling frequency or MTF. Thus, the bias connection / region 13 with its reverse bias and the implanted buried layer 10 allow for narrower pixel spacing in the real estatemaking up the pixel 1-6 with a very thick substrate to maximize photon collection of incoming light waves to the image sensor.

[0041] To assist photo carrier vertical transit time, the photodiode electric field needs to extend all the way through the epi substrate 8 and be as high as possible. This is done by either adding a long and low doping tail to the N- photodiode 3 or using a very high epi resistivity. However, the voltage source has a maximum CMOS VDD of only 3.3 Volts to be applied to the bias connection 13. This limits the maximum epi thickness of the epi substrate 8 to about 20 urn where a reasonable electric field can be formed across the epitaxial (epi) substrate 8. For an even thicker epi substrate 8, a negative bias can be applied to the substrate 8 to increase the voltage range, VDD minus backside voltage. Doing so requires the top Pwell active region 13 that is normally biased at 0 Volts to be electrically isolated from the P- epi substrate.

[0042] Again, the CMOS image sensor with one or more pixels with backside bias for broad band imaging is much simpler to manufacture and does not need state of the art lithography equipment. In the CMOS image sensor, a pocket of N- buried implant 10 may be added below the Pwell region 1 , 6. The N- region of the implanted buried layer 10 is depleted and forms a sub-threshold barrier to electrically isolate the top Pwell region 1 , 6 from the P- epi substrate 8. The CMOS image sensor with the implanted buried layer 10 has smaller pixel to pixel variability for full well saturation, less blooming, smaller sub threshold leakages, and better photodiode potential. Thus, an advantage is that the buried N- is uniform across the array, which should result in a more uniform pixel to pixel performance.

[0043] Figure 3 illustrates an example embodiment of a block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., an NMOS pixel) with a backside bias. The CMOS image sensor has similar components to the CMOS image sensor discussed in Figure 2a. Thus, the CMOS image sensor is constructed with a bias connection 13 made of a P+ type semiconductor material arranged to be reversed biased / backside biased by a voltage source opposite in polarity (e.g., V -) to a polarity of the semiconductor material type making up the bias connection 13. The pixel 1 -6 (NMOS pixel) can include a photosensitive element that includes a surface pinning implant 2, photodiode 3, and a well 1 made of a P+ type semiconductor material; a transfer gate 4; a sense node made of an N+ type semiconductor material, and its sense node well region 6 made of a P+ type semiconductor material type. The sense node 5 and the transfer gate 4 can be utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image data captured by the photosensitive element 2, 3. The CMOS image sensor is constructed with an implanted buried layer 10 made of the N- semiconductor material type that extends across a region making up the pixel 1 -6 beneath the wells 1 , 6 made of the P+ semiconductor material type as well as sometimes extends beneath the zone for the support circuitry guard ring region 7, vertical N- region 11 , top N+ region 12. The CMOS image sensor is also constructed with an EPI substrate 8 and a backside layer 9. The implanted buried layer 10 made with the N- semiconductor material type is arranged to cooperate with the reversed bias applied by the voltage source to the bias connection 13 to reduce (e.g. pinch off / stop) a parasitic current path between the wells 1 , 6 made of the P+ semiconductor material type utilized by the active CMOS elements and the EPI substrate 8 doped to have Ppolarity, which will result in more uniform pixel to pixel performances in an image sensor with two or more pixels. The main difference between Figure 3 and Figure 2a is the CMOS logic implemented in Figure 2a. Figure 3 includes the vertical N- region 11 connecting to the implanted buried layer 10 made of N- material to isolate the P+ guard ring region 7 from the P+ backside bias connection 13. The doping concentration for the implanted buried layer / epi 10 is made of N- material and is set in the range of 1e15to 1e14at / cm3. This is at the low doping limit that an implant engineer may have difficulty monitoring for process control. The pixel type is NMOS pixel with n-type photodiode in p-type epi with a buried n-layer 10 on p-type substrate 8.

[0044] Figure 4a illustrates an example embodiment of a block diagram of a CMOS image sensor with one or more photosensitive elements (e.g., NMOS pixels) with a backside bias where the substrate comprises two or more epitaxial films. The CMOS image sensor is constructed with a bias connection 13 made of a P+ type semiconductor material arranged to be reversed biased / backside biased by a voltage source opposite in polarity (e.g., V -) to a polarity of the semiconductor material type making up the bias connection 13. The pixel 1-6 can include a photosensitive element that includes a surface pinning implant 2, photodiode 3, and a well 1 made of a P+ type semiconductor material; a transfer gate 4; a sense node made of an N+ type semiconductor material, and its sense node well region 6 made of a P+ type semiconductor material type. The sense node 5 and transfer gate 4 can be utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image data captured by the photosensitive element 2, 3. The CMOS image sensor is constructed with two or more layers of epitaxial films 8, 10 that are doped so that at least one of theepitaxial layers is doped to have an opposite polarity to the active region 13 made of the first semiconductor material type as well as extends beneath the zone for the support circuitry guard ring region 7, and vertical P- region 12. The pixel type is NMOS pixel with n-type photodiode in n-type epi on p-type epi. The n- epi layer 10, formed under SXW pwell 1 and SN pwell 6, will serve as the implanted buried layer 10 in Figures 2a or 3, and be depleted to form an electrical barrier to cut off the electrical path for leakage current between the pixel 1 -6 to the substrate 8. The n- epi outside the array still serves as CMOS logic isolation nwell / deep nwell shown in Figure 2a.

[0045] The buried layer 10 can be done two ways, either by an implant process or by an epi doping process. For the implant method as shown in Figure 3, the implanted buried layer 10 can be patterned and placed selectively so it is NOT under the bias connection / region 13. For the epi method, the buried EPI region 10 will go across the whole structure. In Figure 4a, the CMOS image sensor with one or more pixels with backside bias includes other embodiments where the N- buried doping region is replaced with two (or three layers see Figures 5a-6b) of Epitaxial (epi) film stacks. In the epi method, another well 12 made of the same type of semiconductor material as the bias connection / region 13 is added to compensate for the added thickness of EPI region 10 made of the opposite polarity semiconductor material so that the bias connection / region 13 is electrically connected to the bottom epi substrate 8 region.Thus, all three of the bias connection 13, the extension well 12, and the epi substrate 8 region have the same polarity either through having a same type of semiconductor material or a doping of the epi to have the same polarity. The buried EPI layer 10 can be made by a doping process.

[0046] In Figure 4a, two doped epi layers 8, 10 go all the way across the pixel area and the bias connection 13 that has the reversed bias applied. The top epitaxial film layer 10 is made of an N-type dopant to replace the implanted buried layer 10 made of an N- material shown in Figure 3. The thickness of the N- epi layer of epitaxial film 10 extends deeper than the depth of the Pwell regions 1 , 6 so that the sub-threshold barrier can be formed under the Pwell regions 1 , 6. The bottom P- epitaxial film / substrate 8 is made of the P-type dopant like that of the P- epi substrate 8 in Figure 3. The backside bias is applied to the bias connection 13 made of P+ material from the top and then connects to P- region of Pwell 12 and then to P- epi layer substrate 8 and the P+ material in the backside layer 9. In an embodiment, the substrate 8 can be up to 200 urn thick. In an embodiment, the substrate 8 can be about 20 urn thick.

[0047] The two or more layers of epitaxial films 8, 10 are doped so that they will have opposite polarities with respect to another epitaxial in contact with each other. The two or more layers of epitaxial films 8, 10 that are doped so that they will have opposite polarities to another epitaxial in contact with each other and are constructed to extend uniformly across the region making up the pixel as well as a second region making up the bias connection 13 made of the first semiconductor material type. The two or more epitaxial layers are arranged to cooperate with the reversed bias applied by the voltage source to the bias connection 13 and a third well 12, made of the first semiconductor material type, in contact with the bias connection 13 to reduce (e.g. pinch off / stop) a parasitic current path between the wells 1 , 6 made of the P+ semiconductor material type utilized by the active CMOS elements and the EPI substrate 8 doped to have P polarity, which will result in an increased electric field to reduce photocharge lateralspreading and to cut off the parasitic current leakage path in an image sensor with two or more pixels. In addition, the bias connection 13 made up of the first semiconductor material type is configured to work in relationship with the two or more layers of epitaxial films 8, 10 that are doped so that they will have opposite polarities to another epitaxial layer in contact with each other such that the bias connection 13 is capable of being located either 1 ) on a top side of a chip containing the layers of the CMOS image sensor or 2) on a bottom side of the chip containing the layers of the CMOS image sensor. In addition, FETs are located to the right of Pwell 1 .

[0048] The buried epitaxial film 8, 10 layers can be grown during wafer starting material epi growth. The epi can be a deposited highly controlled silicon-based crystalline film. The doping placement can be optimized in depth. Precision during epi growth is high. Deep, difficult foundry implantation to achieve this layer is limited to implant energy; and thus, depth. Epi growth does not have this limitation. Epi deposition can be done at a much lower doping concentration, a few orders of magnitude lower than implanting method. The CMOS image sensor has two or more layers of epitaxial films 8, 10 that are thick enough so that the doping can be set as low as 1 e13 / cm3. A larger pixel needs the buried n- epi concentration to be lower than 1 e15 / cm3, below that the implant limit.

[0049] Figures 4b to 6b show additional examples of a CMOS image sensor with two or more layers of EPI 8, 10, and a bias connection 13 that operate and are constructed in a similar manner to the embodiment shown in Figure 4a.

[0050] Figure 4b illustrates an example embodiment of a block diagram of the CMOS image sensor, similar to Figure 4a, with two or more layers of EPI 8, 10 and an activeregion 13 on the top side of the CMOS image sensor being reverse biased but with a PMOS pixel. In Figure 4b, the bias connection 13 is in contact with a deep Nwell region 12 that penetrates into the bottom EPI substrate layer 8. Note, the EPI layers 8, 10 are doped to have opposite polarities. The pixel type is PMOS pixel with p-type photodiode in p-type epi on n-type epi.

[0051] Figure 5a illustrates an example embodiment of a block diagram of the CMOS image sensor with one or more NMOS pixels with backside bias and two or more epitaxial films. Figure 5b illustrates an example embodiment of a block diagram of the CMOS image sensor with one or more PMOS pixels with backside bias and two or more epitaxial films. In Figure 5a, the pixel type is NMOS pixel with n-type photodiode in p- type epi on n-type epi on top of p-type epi. The substrate bias is provided by the backside connection 13. Figure 5b illustrates an example embodiment of a block diagram of the CMOS image sensor with two or more layers of EPI and an active region that is capable of being located on the topside or bottom of the image sensor being reverse biased but is shown being located on the bottom of the CMOS image sensor. Thus, the backside bias is connected to the bias connection 13 of made of P+ type material (see Figure 5a) on the bottom of the structure. The pixel type is PMOS pixel with a p-type photodiode on a p-type epi layer 10 on top of an n-type epi substrate 8. The substrate bias is provided by the backside connection 13.

[0052] Figure 6a illustrates an example embodiment of a block diagram of the CMOS image sensor with one or more NMOS pixels with backside bias and three or more epitaxial films. Figure 6b illustrates an example embodiment of a block diagram of the CMOS image sensor with one or more PMOS pixels with backside bias and three ormore epitaxial films. Figure 6b illustrates an example embodiment of a block diagram of the CMOS image sensor with three or more layers of EPI and an active region on the top side of the image sensor being reverse biased and the bias connection 13 is surrounded by a deep Nwell region that penetrates into the three layers of EPI. The structure has three epitaxial films / layers. The EPI layers are doped to have opposite polarities. In Figure 6a, the top P- epi layer 11 and the bottom P- epi layer 8 can have the same dopant type and similar resistivity. The middle epi layer 10 is doped N- to serve a similar function to, the buried implant layer, located under the Pwell regions 1 and 6. The N- epi layer 10 resistivity and thickness are tuned appropriately to form a desired sub-threshold barrier. The top side connection for the backside bias of the bias connection 13 is made of P+ type material and Pwell 12 is added to complete the connection down to the bottom epi substrate layer 8 and the backside layer 9 which is made of P+ material. The pixel type is NMOS pixel with n-type photodiode in p-type epi on n-type epi on top of p-type epi. The substrate bias provided by front side connection 13. In Figure 6b, the pixel type is PMOS pixel with p-type photodiode in n-type epi on p- type epi on top of n-type epi. The substrate bias is provided by the front side connection 13.

[0053] Figure 7a illustrates an example embodiment of a cross section block diagram of the CMOS image sensor with a single extra thick N- epi substrate 8, and an NMOS pixel 1-6, and a bias connection 13 . The structure is much simpler than other embodiments because there is no implanted buried layer and no multiple epi film stacks are used. The backside layer 9 of the structure has a heavy and thick P+ region to form the bias connection 13 that has the backside bias applied to. The backside bias fromthe voltage source connects to the back of the structure at the P+ bias connection 13.The substrate bias is provided by the backside connection 13.

[0054] Figure 7b illustrates an example embodiment of a block diagram of the CMOS image sensor with a backside bias to the bias connection 13 with a vertical channel front to back P- region 14. When the backside bias to the bias connection 13 needs to be made from the top, then a vertical front to back P- region 14 is added to the structure to allow the voltage source to apply the bias from the top or the bottom. The vertical channel P- region 14 can be implanted but the maximum commercially available implanter range is about 5 to 6 urn. For a thicker epi structure than 6 urn, then deep trench isolation, DTI, with filled P type doped films or N type doped films will need to be used depending upon whether it is an NMOS pixel or a PMOS pixel.

[0055] It will be understood that the buried implant layer 10 may be implanted using an ion beam of sufficiently high energy. If a typical manufacturing process for CMOS image sensors is assumed, the new implant requires merely one additional step. In an implementation, the buried implant layer 10 is made using a same mask for alignment with the well of the pixel.

[0056] Figure 8 illustrates an example embodiment of a block diagram of a complete CMOS image sensor showing support functions with two or more pixels in the pixel array that use the bias connection with reverse bias applied, and the implanted buried layer 10 and / or epi film layer 10. The example array shows a 5 x 5 pixel array 102 but normally has millions to hundreds of millions of pixels in the array. The image sensor can have power supply, reading circuitry, and timing circuitry.

[0057] Again, the effects described in a CMOS image sensor with a p-type substrate will be understood to operate similarly in a CMOS image sensor with the opposite conductivity type layers and wells. The substrate biasing method described herein is useful for both front side and back side illuminated image sensors to reduce crosstalk and to improve modulation transfer function (MTF) performance.

[0058] It is to be understood that the exemplary embodiments are merely illustrative of the invention and that many variations of the above-described embodiments may be devised by one skilled in the art without departing from the scope of the invention. It is therefore intended that all such variations be included within the scope of the following claims and their equivalents.

[0059] References in the specification to “an embodiment,” “an example,” etc., indicate that the embodiment or example described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Such phrases can be not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed to be within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly indicated.

[0060] While the foregoing design and embodiments thereof have been provided in considerable detail, it is not the intention of the applicant(s) for the design and embodiments provided herein to be limiting. Additional adaptations and / or modifications are possible, and, in broader aspects, these adaptations and / or modifications are also encompassed. Accordingly, departures may be made from the foregoing design andembodiments without departing from the scope afforded by the following claims, which scope is only limited by the claims when appropriately construed.

Claims

CLAIMS1 . A complementary metal-oxide-sem iconductor (CMOS) image sensor, comprising: i) a bias connection that is made of a first semiconductor material type and is electrically coupled a voltage source to apply a reverse bias opposite in polarity to a polarity of the first semiconductor material type to the bias connection, ii) a pixel in a pixel array comprising: a photosensitive element that includes a first well made of a second semiconductor material type, and a second well made of the first semiconductor material type utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image data captured by the photosensitive element; and iii) an implanted buried layer that is made of the second semiconductor material type and that extends across a region making up the pixel array beneath the second well made of the first semiconductor material type; wherein the implanted buried layer made with the second semiconductor material type is arranged to cooperate with the reversed bias applied by the voltage source to the bias connection to reduce a parasitic current path between the second well made of the first semiconductor material type utilized by the active CMOS elements and a substrate, which will result in more uniform pixel to pixel performances in an image sensor with two or more pixels.

2. The CMOS image sensor as claimed in claim 1 , wherein the implanted buried layer made of the second semiconductor material type is located above the substrate made of the first semiconductor material type to disconnect the substrate from the second well also made of the first semiconductor material type.

3. The CMOS image sensor as claimed in claim 1 , wherein the implanted buried layer made of the second semiconductor material type is arranged to cooperate with the reversed bias applied by the voltage source to the bias connection to extend an electric field all the way through the substrate to increase the electric field to reduce photocharge lateral spreading and to cut off the parasitic current leakage path.

4. The CMOS image sensor as claimed in claim 1 , wherein the implanted buried layer made with the second semiconductor material type is constructed with a doping concentration in a range of about 1e16to 1e14per cubic centimeter and is in contact with a well utilized by CMOS logic.

5. The CMOS image sensor as claimed in claim 1 , further comprising: a backside layer that is constructed with at least one of 1 ) an epitaxial layer or 2) graded materials that are doped to match a polarity of the first semiconductor material type and is located below the substrate layer, andwherein the active region made up the first semiconductor material type is configured to cooperate with the implanted buried layer so that the active region is capable of being located either 1 ) on a top side of a chip containing the CMOS image sensor or 2) on a bottom side of the chip containing the CMOS image sensor.

6. The CMOS image sensor as claimed in claim 1 , wherein the substrate is up to 200 urn thick in order to efficiently absorb photons in a range of light optimized for UV wavelengths to infrared wavelengths.

7. A CMOS image sensor, comprising: i) a bias connection that is made of a first semiconductor material type and is electrically coupled a voltage source to apply a reverse biased opposite in polarity to a polarity of the first semiconductor material type to the bias connection, ii) a pixel in a pixel array comprising: a photosensitive element that includes a first well made of a second semiconductor material type, and a second well made of the first semiconductor material type utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image data captured by the photosensitive element; andiii) two or more layers of epitaxial films that are doped so that at least one of the epitaxial layers is doped to have an opposite polarity to the active region made of the first semiconductor material type, where the two or more epitaxial layers are arranged to cooperate with the reversed bias applied by the voltage source to the active region to reduce a parasitic current path between the second well made of the first semiconductor material type utilized by the active CMOS elements and a substrate to increase the electric field to reduce photocharge lateral spreading and to cut off the parasitic current leakage path in an image sensor with two or more pixels.

8. The CMOS image sensor as claimed in claim 7, where the two or more layers of epitaxial films are doped so that they will have opposite polarities with respect to another epitaxial in contact with each other.

9. The CMOS image sensor as claimed in claim 7, wherein the two or more layers of epitaxial films that are doped so that they will have opposite polarities to another epitaxial in contact with each other and are constructed to extend uniformly across the region making up the pixel as well as a second region making up the active region made of the first semiconductor material type; and where the active region made up the first semiconductor material type is configured to work in relationship with the two or more layers of epitaxial films that are doped so that they will have opposite polarities to another epitaxial layer in contact with each other such that the active region is capable of being located either 1 ) on atop side of a chip containing the layers of the CMOS image sensor or 2) on a bottom side of the chip containing the layers of the CMOS image sensor.

10. The CMOS image sensor as claimed in claim 7, wherein the two or more layers of epitaxial films that are doped so that they will have opposite polarities to another epitaxial in contact with each other and are constructed to extend uniformly across the region making up the pixel array as well as a second region making up the active region made of the first semiconductor material type so that the doping can be set as low as 1e13 / cm3.11 . A method for a complementary metal-oxide-sem iconductor (CMOS) image sensor, comprising: providing a bias connection made of a first semiconductor material type arranged to be reversed biased by a voltage source opposite in polarity to a polarity of the first semiconductor material type; providing a pixel that includes 1) a photosensitive element that includes a first well made of a second semiconductor material type and 2) a second well made of the first semiconductor material type utilized by active CMOS elements for at least one of I) reading and II) resetting image data captured by the photosensitive element;providing an implanted buried layer made of the second semiconductor material type that extends across a region making up the pixel beneath the second well made of the first semiconductor material type; and providing the implanted buried layer made with the second semiconductor material type to cooperate with the reversed bias applied by the voltage source to the bias connection to reduce a parasitic current path between the second well made of the first semiconductor material type utilized by the active CMOS elements and a substrate, which will result in more uniform pixel to pixel performances in an image sensor with two or more pixels.

12. The method for the CMOS image sensor as claimed in claim 11 , further comprising: providing the implanted buried layer made of the second semiconductor material type to be located above the substrate made of the first semiconductor material type to disconnect the substrate from the second well also made of the first semiconductor material type.

13. The method for the CMOS image sensor as claimed in claim 11 , further comprising: providing the implanted buried layer made of the second semiconductor material type to cooperate with the reversed bias applied by the voltage source to the active region to extend an electric field all the way through the substrate to increase theelectric field to reduce photocharge lateral spreading and to cut off the parasitic current leakage path.

14. The method for the CMOS image sensor as claimed in claim 11 , further comprising: providing the implanted buried layer made with the second semiconductor material type to be made with a doping concentration in a range of about 1e16to 1e14per cubic centimeter and be in contact with a well utilized by CMOS logic.

15. The method for the CMOS image sensor as claimed in claim 11 , further comprising: providing a backside layer that is constructed with at least one of 1 ) an epitaxial layer or 2) graded materials that are doped to match a polarity of the first semiconductor material type and is located below the substrate layer.

16. The method for the CMOS image sensor as claimed in claim 11 , further comprising: providing the substrate with up to a 200 urn thickness in order to efficiently absorb photons in a range of light optimized for UV wavelengths to infrared wavelengths.

17. A method for a CMOS image sensor, comprising:providing an active region of a first semiconductor material type to be reversed biased by a voltage source opposite in polarity to a polarity of the first semiconductor material type; providing a pixel in a pixel array that includes a photosensitive element that includes a first well made of a second semiconductor material type and a second well made of the first semiconductor material type utilized by active CMOS elements for at least one of 1 ) reading and 2) resetting image data captured by the photosensitive element; providing two or more layers of epitaxial films that are doped so that at least one of the epitaxial layers is doped to have an opposite polarity to the active region made of the first semiconductor material type; and providing the two or more epitaxial layers to cooperate with the reversed bias applied by the voltage source to the active region to reduce a parasitic current path between the second well made of the first semiconductor material type utilized by the active CMOS elements and a substrate to increase the electric field to reduce photocharge lateral spreading and to cut off the parasitic current leakage path in an image sensor with two or more pixels.

18. The method for the CMOS image sensor as claimed in claim 17, further comprising: providing the two or more layers of epitaxial films to be doped so that they will have opposite polarities with respect to another epitaxial in contact with each other.

19. The method for the CMOS image sensor as claimed in claim 17, further comprising: providing the two or more layers of epitaxial films that are doped so that they will have opposite polarities to another epitaxial in contact with each other and that are constructed to extend uniformly across the region making up the pixel array as well as a second region making up the active region made of the first semiconductor material type; and providing the active region made up the first semiconductor material type to work in relationship with the two or more layers of epitaxial films that are doped so that they will have opposite polarities to another epitaxial layer in contact with each other such that the active region is capable of being located either 1 ) on a top side of a chip containing the layers of the CMOS image sensor or 2) on a bottom side of the chip containing the layers of the CMOS image sensor.

20. The method for the CMOS image sensor as claimed in claim 17, further comprising: providing the two or more layers of epitaxial films that are doped so that they will have opposite polarities to another epitaxial in contact with each other and that are constructed to extend uniformly across the region making up the pixel array as well as a second region making up the active region made of the first semiconductor material type so that the doping can be set as low as 1 e13 / cm3.21 . The method for the CMOS image sensor as claimed in claim 17, further comprising: providing the two or more layers of epitaxial films that are uniformly doped so that at least one of the epitaxial layers is doped to have an opposite polarity to the active region made of the first semiconductor material type via epitaxial grow with a wafer’s starting material as a manufacturing step prior to a wafer fabrication in a foundry.

Images