Etching method for sc-containing layer, semiconductor device and manufacturing method therefor, and process device

Abstract

The present application relates to the technical field of semiconductors, and particularly relates to an etching method for a Sc-containing layer, a semiconductor device and a manufacturing method therefor, and a process device. The etching method comprises a primary etching process step and a secondary etching process step, which are cyclically performed, wherein the primary etching process step comprises introducing process gases into a process chamber, and exciting the process gasses to generate plasma, so as to etch a Sc-containing layer; and the secondary etching process step comprises at least one of a volatilization step and a cooling step. The manufacturing method comprises the etching method. The manufacturing method is used to form a trench gate structure in the semiconductor device. The process device uses the etching method or the manufacturing method. By means of the etching method, an etching rate of a Sc-containing layer can be increased.

Description

Etching method of Sc-containing layer, semiconductor device and manufacturing method and process equipment thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to an etching method of Sc-containing layer, a semiconductor device and a manufacturing method and process equipment thereof. BACKGROUND

[0002] Modern communication has entered the 5G era, and in the future development process to 6G, the working frequency of semiconductor devices is increasingly required. Among them, the working frequency of semiconductor devices can be improved by increasing the mobility of carriers in the channel. Specifically, high electron mobility semiconductor devices can be made based on high mobility two-dimensional electron gas. In this semiconductor device, the metal in the two-dimensional electron gas system material generally uses group IIIA elements (such as Al, Ga, In, etc.), or uses group IIIB metal elements with a positive trivalent valence (such as Sc).

[0003] The ionic radius of Sc is between Ga and In, which has the ability to form Sc-containing alloy with AlN, GaN and other group III-V compounds. The Sc-containing alloy formed has a high piezoelectric coefficient and spontaneous polarization rate. In the semiconductor device prepared by using the Sc-containing alloy, the channel has a higher surface charge density and electron mobility. However, in the dry etching process of Sc alloy, the by-product ScCl3 has a significantly higher boiling point than other metal halides, and is difficult to volatilize from the reaction system. Therefore, the content of Sc affects the etching rate, and the higher the content, the more difficult the dry etching. There is no effective rapid etching method for Sc-containing alloy layer in the prior art, which limits the application of Sc-containing alloy in semiconductor devices.

[0004] SUMMARY

[0005] The purpose of the present application is to provide an etching method of Sc-containing layer, a semiconductor device and a manufacturing method and process equipment thereof, to solve the technical problem of low etching rate when etching Sc-containing alloy layer.

[0006] The present application provides an etching method of Sc-containing layer, which comprises a main etching process step and an auxiliary etching process step which are cyclically executed; wherein,

[0007] The main etching process step comprises: introducing process gas into the process chamber and exciting to generate plasma, and etching the Sc-containing layer, wherein the process gas comprises chlorine-containing gas and inert gas;

[0008] The auxiliary etching process step comprises at least one of a volatilization step and a cooling step;

[0009] The volatilizing step comprises: reducing the power of the lower electrode to zero or close to zero, and reducing the flow rate of the process gas to zero or close to zero;

[0010] The cooling step comprises: reducing the power of the lower electrode to zero or close to zero, reducing the flow rate of the chlorine-containing gas to zero or close to zero, and continuing to supply the inert gas.

[0011] In some embodiments, the main etching process step comprises a first etching step and / or a second etching step, the process gas used in the first etching step is the same as that used in the second etching step, and the power of the lower electrode in the first etching step is greater than that in the second etching step.

[0012] In some embodiments, the power ratio of the lower electrode in the first etching step to that in the second etching step is (1.2-1.8):1.

[0013] In some embodiments, the process time ratio of the first etching step to the second etching step is 1:(4-6).

[0014] In some embodiments, the power of the lower electrode in the first etching step is 100-1000 W, and the power of the lower electrode in the second etching step is 100-1000 W.

[0015] In some embodiments, the process time of the first etching step is 1.2-3 s, and the process time of the second etching step is 8-12 s.

[0016] In some embodiments, in the main etching process step, the flow rate ratio of the chlorine-containing gas to the inert gas is (0.3-0.5):1.

[0017] In some embodiments, in the main etching process step, the flow rate of the chlorine-containing gas is 20-200 sccm, and the flow rate of the inert gas is 10-1000 sccm.

[0018] In some embodiments, the chlorine-containing gas comprises at least one of SiCl4, BCl3 and Cl2, and / or the inert gas comprises Ar.

[0019] In some embodiments, the chlorine-containing gas comprises BCl3 and Cl2, and the flow rate ratio of BCl3 to Cl2 is (0.9-1.1):1.

[0020] Alternatively, the chlorine-containing gas comprises SiCl4.

[0021] In some embodiments, the process time of the volatilizing step is 0.5-1.5 s, and / or the process time of the cooling step is 0.5-1.5 s.

[0022] Compared with the prior art, the etching method for the Sc-containing layer provided in the embodiments of the present application has the following beneficial effects:

[0023] In the embodiments of the present application, in the main etching process step, the process gas containing chlorine gas and inert gas is introduced into the process chamber and plasma is excited to effectively etch the Sc-containing layer; in the auxiliary etching process step, the power of the lower electrode is reduced to zero or close to zero, and when the process gas is reduced to zero or close to zero, the etching by-products can be quickly volatilized during vacuum pumping, and when the chlorine-containing gas is reduced to zero or close to zero and the inert gas is continuously introduced, not only the etching by-products can be quickly volatilized during vacuum pumping, but also the heat of the Sc-containing layer can be taken away, so that the uniformity of etching is achieved; the main etching process step and the auxiliary etching process step are executed in a cycle, the etching by-products generated in each cycle step can be volatilized in time, so that the etching depth and the etching quality of the subsequent cycle step are reduced or even avoided, so as to ensure the etching depth and the etching quality (such as etching uniformity) of each cycle step, and the etching rate of the Sc-containing layer is improved, that is, the rapid etching of the Sc-containing layer is achieved.

[0024] The embodiments of the present application also provide a manufacturing method of a semiconductor device, comprising the steps of:

[0025] providing a substrate;

[0026] forming a Sc-containing layer on the substrate;

[0027] applying the above-mentioned etching method to etch the Sc-containing layer to form a groove with a predetermined depth, and the predetermined depth is less than the thickness of the Sc-containing layer;

[0028] forming a gate electrode in the groove and forming source and drain electrodes on both sides of the groove.

[0029] The etching method for the Sc-containing layer provided in the embodiments of the present application can produce the same beneficial effects as the above-mentioned etching method, that is, the etching efficiency is improved, and details are not repeated here.

[0030] The embodiments of the present application also provide a semiconductor process equipment, comprising a process chamber, a gas inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, the controller comprises at least one processor and at least one memory, the memory stores a computer program, and the computer program is executed by the processor to realize the above-mentioned etching method or the above-mentioned manufacturing method.

[0031] The process equipment provided in the embodiments of the present application has the beneficial effects of the above-mentioned etching method and manufacturing method, and details are not repeated here.

[0032] The embodiments of the present application also provide a semiconductor device, comprising:

[0033] a substrate;

[0034] a Sc-containing layer disposed on the substrate, a groove being formed on a side of the Sc-containing layer away from the substrate, the groove having a depth less than a thickness of the Sc-containing layer;

[0035] a source electrode disposed on a first side of the groove;

[0036] a drain electrode disposed on a second side of the groove, the second side being opposite to the first side, a distance between the source electrode and an edge of the first side of the groove being less than a distance between the drain electrode and an edge of the second side of the groove;

[0037] a gate electrode disposed in the groove, and a distance between the gate electrode and the source electrode being less than a distance between the gate electrode and the drain electrode.

[0038] In some embodiments, the Sc-containing layer comprises Sc x Al 1-x N, wherein a value range of x is less than 43%; or,

[0039] a distance between a bottom of the groove and a side of the Sc-containing layer facing the substrate ranges from 1 nm to 100 nm; or,

[0040] a distance between the source electrode and the edge of the first side of the groove ranges from 0.1 μm to 0.5 μm; or,

[0041] a distance between the drain electrode and the edge of the second side of the groove ranges from 0.5 μm to 5 μm; or,

[0042] a length of the gate electrode ranges from 0.5 μm to 5 μm, and a width of the gate electrode ranges from 0.1 mm to 10 mm.

[0043] In the semiconductor device provided by the embodiments of the present application, the Sc-containing layer is a potential barrier layer, and the groove is formed to thin the potential barrier layer where the gate electrode is located. In this way, when the gate voltage is regulated, a potential well appears to form a two-dimensional electron gas, thereby achieving high electron mobility of the semiconductor device. When no gate voltage is applied, the potential well of the two-dimensional electron gas disappears, and the semiconductor device is in an off state, i.e., the semiconductor device is a normally-off semiconductor device, thereby achieving safety control performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0045] Figure 1 is a schematic diagram of a cross-sectional structure of a semiconductor device with a Sc-containing layer according to an embodiment of the present application;

[0046] Figures 2a-2n are schematic diagrams of a process flow of a method for manufacturing a semiconductor device with Sc according to an embodiment of the present application;

[0047] Figure 3a is a schematic diagram of a local enlarged view of etching Sc x Al 1-x N in Figure 3a;

[0048] Figure 3b is a schematic diagram of a local enlarged view of L in Figure 3a;

[0049] Figures 3c-3d are schematic diagrams of a local enlarged view of R in Figure 3a;

[0050] Figures 4a-4d are schematic diagrams of a local enlarged view of M in Figure 3a, with the difference being the etching thickness of Sc x Al 1-x N;

[0051] Figures 5a-5d are schematic diagrams of etching results of Sc x Al 1-x N in Comparative Example 1;

[0052] Figures 6a-6b are schematic diagrams of EDX of Sc x Al 1-x N by-products in Comparative Example 1;

[0053] Figure 7 is a statistical diagram of etching results of Comparative Example 2;

[0054] Figures 8a-8b are schematic diagrams of etching results of Comparative Example 3;

[0055] Figures 9a-9d are schematic diagrams of etching results of Comparative Example 4;

[0056] Figure 10 is a schematic diagram of a structure of a semiconductor process equipment according to an embodiment of the present application;

[0057] Figures 11a-11b are schematic diagrams of energy levels of the semiconductor device in Figure 1.

[0058] Explanation of reference signs: 100-epitaxial wafer; 110-epitaxial layer; 120-substrate; 130-buffer layer; 200-barrier layer; 210-source electrode; 220-gate electrode; 230-drain electrode; 240-recess; 310-first photoresist layer; 311-first through slot; 320-second photoresist layer; 321-second through slot; 322-third through slot; 330-third photoresist layer; 331-fourth through slot; 400-passivation layer; 500-process chamber; 510-upper electrode assembly; 520-lower electrode assembly; 511-radio frequency coil; 512-upper radio frequency power supply; 513-upper matching device; 521-wafer support device; 522-lower radio frequency power supply; 523-lower matching device. DETAILED DESCRIPTION

[0059] The technical solutions of the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0060] Sc is a group III-B metal element with a main valence of +3, and its ionic radius is between that of Ga and In, and it has the ability to form alloys with III-V compounds such as AlN, GaN, etc. For example, Sc x Al 1-x N, etc. The Sc-containing layer (Sc x Al 1-x N) has a high piezoelectric coefficient and spontaneous polarization rate, and the prepared semiconductor device can make the channel have a higher surface charge density (for example, the mobility of the HEMT using Sc x Al 1-x N as the barrier layer is about 5 times that of Al x Ga 1-x N), thereby improving the mobility of the semiconductor device. In the related etching process of the dry etching of the Sc-containing layer, Sc reacts with Cl to generate a by-product ScCl3, which adheres to the sidewall of the etching hole and is not easy to volatilize, thus affecting the etching rate of the Sc-containing layer, and the angle of the Sc-containing layer cannot be consistent with the angle of the photoresist, affecting the etching uniformity and etching quality.

[0061] The embodiments of the present application provide an etching method for a Sc-containing layer, a semiconductor device, a manufacturing method thereof, and a process equipment. In the etching process, the etching rate and etching quality can be improved, and the angle of the Sc-containing layer can be basically consistent with the angle of the photoresist. The present application will be described in further detail below through specific embodiments and in conjunction with the drawings.

[0062] Embodiment one

[0063] The embodiment of the present application provides a kind of Sc layer containing etching method, etching method includes the main etching process step and auxiliary etching process step of cyclic execution;Wherein,

[0064] Main etching process step includes: into process gas and excitation produce plasma in process chamber, Sc layer containing etching, process gas includes chlorine-containing gas and inert gas;

[0065] Auxiliary etching process step includes: at least one of volatilization step and cooling step;

[0066] Volatilization step includes: reduce the power of lower electrode to zero power or close to zero power, reduce process gas to zero flow or close to zero flow;

[0067] Cooling step includes: reduce the power of lower electrode to zero power or close to zero power, reduce chlorine-containing gas to zero flow or close to zero flow, continue to pass through inert gas.

[0068] In the embodiment of the present application, in main etching process step, chlorine-containing gas, inert gas and other process gases are introduced into the process chamber and plasma is excited to produce etching of Sc layer containing; In auxiliary etching process step, the power of lower electrode is reduced to zero or close to zero, and when the process gas is reduced to zero or close to zero, the by-products generated during etching process are quickly volatilized during vacuum pumping (no other gas is introduced, only the by-products can be pumped away), when the chlorine-containing gas is reduced to zero or close to zero and the inert gas is continuously introduced, not only the by-products generated during etching process are quickly volatilized during vacuum pumping, but also the heat of Sc layer containing is removed, ensuring the uniformity of etching; The main etching process step and the auxiliary etching process step are cyclically executed, the by-products generated in each cycle are volatilized in time, so as to reduce or even avoid the influence on the etching depth and etching quality of subsequent cycle, to ensure the etching depth and etching quality (such as etching uniformity) of each cycle, improve the etching rate and etching uniformity of Sc layer containing, that is, realize the rapid etching of Sc layer containing.

[0069] It should be noted that in the above volatilization step and cooling step, "reduce" means to close or set the power of lower electrode to a small value or close to zero value;"Reduce" means to stop passing process gas and chlorine-containing gas, or set the flow of process gas and chlorine-containing gas to a small value or close to zero value.

[0070] In the embodiment of the present application, the main etching process step includes at least one of the first etching step and the second etching step, wherein the process gas used in the first etching step and the second etching step is the same, and the lower electrode power of the first etching step is greater than that of the second etching step. In this way, the first etching step can break some chemical bonds during the process to facilitate the subsequent etching of the second etching step, and generate a large amount of heat, which is beneficial to the volatilization of by-products.

[0071] In the embodiment of the present application, the ratio of the lower electrode power of the first etching step to that of the second etching step can be selected as (1.2-1.8):1, preferably (1.3-1.7):1, further preferably (1.4-1.6):1, and more preferably 1.5:1. In this way, matching the lower electrode power can ensure the etching efficiency and quality during the corresponding etching process, which is beneficial to the timely volatilization of by-products.

[0072] Specifically, in the embodiment of the present application, the lower electrode power of the first etching step is 100W-1000W, preferably 300W-800W, further preferably 500W-700W, and more preferably 600W. The lower electrode power of the second etching step is 100W-1000W, preferably 200W-800W, further preferably 300W-500W, and more preferably 400W. In this way, matching the lower electrode power can ensure the etching efficiency and quality during the corresponding etching process, which is beneficial to the timely volatilization of by-products.

[0073] In the embodiment of the present application, the ratio of the process time of the first etching step to that of the second etching step is 1:(4-6), preferably 1:5. In this way, matching the process time can ensure the etching efficiency and quality during the corresponding etching process.

[0074] Specifically, in the embodiment of the present application, the process time of the first etching step is 1.2s-3s, preferably 1.5s-2.5s, and more preferably 2s. The process time of the second etching step is 8s-12s, preferably 9s-11s, and more preferably 10s. In this way, matching the process time can ensure the etching efficiency and quality during the corresponding etching process.

[0075] In the embodiment of the present application, in the main etching process step, the flow ratio of the chlorine-containing gas to the inert gas is (0.3-0.5):1, preferably (0.35-0.45):1, and more preferably 0.4:1. In this way, matching the chlorine-containing gas and the inert gas can ensure the etching efficiency and quality during the corresponding etching process.

[0076] Specifically, in the main etching process step, the flow rate of the chlorine-containing gas is 20-200sccm, preferably 25-150sccm, further preferably 30-100sccm, further preferably 35-70sccm, and more preferably 40sccm, and the flow rate of the inert gas is 10-1000sccm, preferably 30-800sccm, further preferably 50-500sccm, further preferably 80-200sccm, and more preferably 100sccm. In this way, the flow rates of the chlorine-containing gas and the inert gas are set, so that the etching efficiency and quality can be ensured in the corresponding etching process.

[0077] In the embodiment of the present application, in the main etching process step, the chlorine-containing gas includes at least one of SiCl4, BCl3 and Cl2, for example, the chlorine-containing gas includes BCl3 and Cl2, and the flow rate ratio of BCl3 to Cl2 is (0.9-1.1):1, preferably (0.99-1.05):1, and further preferably 1:1; or the chlorine-containing gas includes SiCl4. BCl3 and SiCl4 can not only play an etching role, but also play a side wall protection role, and Cl2 only has a pure etching role. Therefore, when the chlorine-containing gas with the side wall protection performance (such as BCl3 and SiCl4) is selected, the side wall can be protected in the etching process, so that anisotropic etching is realized, the consistency of the etching angle of the Sc-containing layer and the photoresist in the etching process is ensured, the selection of Cl2 can accelerate the etching rate, ensure the etching rate, and reduce the deposition amount of the side wall deposits, facilitate the subsequent cleaning process, and ensure the consistency of the etching angle of the Sc-containing layer and the photoresist in the etching process. Therefore, when the process gas is selected, the chlorine-containing gas with the side wall protection performance and Cl2 with high etching rate are preferably selected to simultaneously ensure the etching efficiency and the consistency of the etching angle, and thus the etching uniformity and etching quality are ensured.

[0078] In the embodiment of the present application, in the main etching process step, the inert gas includes Ar; the selection of Ar as the inert gas can ensure the etching efficiency and quality in the corresponding etching process.

[0079] In the embodiment of the present application, the process time of the volatilization step is 0.5-1.5s, further preferably 0.8-1.2s, and more preferably 1s. The purpose of setting the process time of the volatilization step to a relatively short time (for example, 1s, 2s, etc.) is to reduce the overall process time without affecting the etching quality, and thus to improve the etching rate.

[0080] In the embodiment of the present application, the process time of the cooling step is 0.5s-1.5s, further preferably 0.8s-1.2s, and more preferably 1s. By setting the process time of the cooling step to a relatively short time (for example, 1s, 2s, etc.), the purpose is to reduce the overall process time without affecting the etching quality, and to improve the etching rate. However, the process time cannot be too short, otherwise the effect of this step cannot be achieved. Although the process time of the volatilization step and the cooling step is longer, the effect is better, but it will affect the production capacity. In the example of the present application, the process time of the volatilization step and the cooling step is set to 1s.

[0081] In the volatilization step, the lower electrode power and all process gases can be turned off to facilitate the rapid volatilization of by-products under the action of vacuum; or the lower electrode power in the volatilization step is set to a small value, even to near zero, for example, 1W, and the process gas in the volatilization step is set to a small value, even to near zero, for example, the gas flow of chlorine-containing gas and Ar is set to 1sccm. In this way, on the one hand, the by-products can be volatilized in time, and on the other hand, the rapid switching of process steps does not require the opening / closing of the radio frequency, and the opening / closing of the gas pipeline valve, thereby avoiding the frequent opening / closing of the radio frequency and the frequent opening / closing of the gas pipeline valve.

[0082] In the cooling step, the lower electrode power and the chlorine-containing gas can be turned off, and a small flow of Ar is still introduced, so as to cool the wafer to be etched and volatilize at least part of the by-products in time under the action of vacuum; or the lower electrode power in the cooling step is set to a small value, even to near zero, for example, 1W, and the chlorine-containing gas in the cooling step is reduced to near zero, for example, 1sccm, and a small flow of Ar, for example, 10sccm, is continuously introduced. In this way, on the one hand, the wafer to be etched can be cooled in time, and at least part of the by-products can be volatilized in time, and on the other hand, the rapid switching of process steps does not require the opening / closing of the radio frequency, and the opening / closing of the gas pipeline valve, thereby avoiding the frequent opening / closing of the radio frequency and the frequent opening / closing of the gas pipeline valve.

[0083] In the embodiment of the present application, before the main etching process step and the auxiliary etching process step are cycled, a stabilization step and an ignition step can also be included, and after the main etching process step and the auxiliary etching process step are cycled, a desorption step can also be included. The process parameters in each step are shown in the following specific examples.

[0084] In the embodiments of the present application, the etching method mainly comprises a main etching process step and an auxiliary etching process step. The main etching process step comprises at least one of a first etching step and a second etching step, and the auxiliary etching process step comprises at least one of a volatilization step and a cooling step. The present application will be described in more detail below with the main etching process step comprising the first etching step and the second etching step and the auxiliary etching process step comprising the volatilization step and the cooling step.

[0085] In the specific examples of the present application, the etching method comprises the following steps:

[0086] S1100, a stabilization step;

[0087] In the process of the stabilization step, the cavity pressure is 1 mTorr to 30 mTorr, preferably 3 mTorr to 10 mTorr, and further preferably 5 mTorr; the upper electrode power is zero, the lower electrode power is zero, the argon (Ar) flow rate is 10 sccm to 1000 sccm, preferably 30 sccm to 800 sccm, further preferably 50 sccm to 500 sccm, further preferably 80 sccm to 200 sccm, and more preferably 100 sccm; the chlorine-containing gas flow rate is 20 sccm to 200 sccm, preferably 25 sccm to 150 sccm, further preferably 30 sccm to 100 sccm, further preferably 35 sccm to 70 sccm, and more preferably 40 sccm; and the process time is 2 s to 8 s, preferably 4 s to 6 s, and further preferably 5 s.

[0088] S1200, an ignition step;

[0089] In the process of the first etching step, the lower electrode power is 100-1000 W, further preferably 300-800 W, further preferably 500-700 W, and more preferably 600 W. This setting can ensure etching efficiency and quality. Because the lower electrode power is high, some chemical bonds can be broken during the process to facilitate subsequent etching, and a large amount of heat is generated, which is conducive to the volatilization of by-products.

[0090] S1310, the first etching step;

[0091] In the process of the first etching step, the lower electrode power is 100-1000 W, further preferably 300-800 W, further preferably 500-700 W, and more preferably 600 W. This setting can ensure etching efficiency and quality. Because the lower electrode power is high, some chemical bonds can be broken during the process to facilitate subsequent etching, and a large amount of heat is generated, which is conducive to the volatilization of by-products.

[0092] In the process of the first etching step, the argon (Ar) flow rate is 10-1000 sccm, preferably 30-800 sccm, further preferably 50-500 sccm, further preferably 80-200 sccm, and more preferably 100 sccm. The flow rate of the chlorine-containing gas is 20-200 sccm, preferably 25-150 sccm, further preferably 30-100 sccm, further preferably 35-70 sccm, and more preferably 40 sccm. This setting of the flow rates of the chlorine-containing gas and the inert gas can ensure etching efficiency and quality.

[0093] In the process of the first etching step, the process time is 1-5 s, preferably 1.5-3 s, and further preferably 2 s. This setting can ensure etching efficiency and quality.

[0094] In addition, in the first etching step, the chamber pressure is 1-30 mTorr, preferably 3-10 mTorr, and more preferably 5 mTorr; the center power of the upper electrode is 100-1000 W, preferably 300-800 W, and more preferably 600 W; and the edge power of the upper electrode is 500-3000 W, preferably 1000-2000 W, and more preferably 1500 W.

[0095] S1320, the second etching step;

[0096] In the second etching step, the power of the lower electrode is 100-1000 W, preferably 200-800 W, and more preferably 300-500 W, and more preferably 400 W. Such a setting can ensure the etching efficiency and quality.

[0097] In the second etching step, the flow rate of argon (Ar) is 10-1000 sccm, preferably 30-800 sccm, and more preferably 50-500 sccm, and more preferably 80-200 sccm, and more preferably 100 sccm; and the flow rate of chlorine-containing gas is 20-200 sccm, preferably 25-150 sccm, and more preferably 30-100 sccm, and more preferably 35-70 sccm, and more preferably 40 sccm. Such a setting of the flow rates of the chlorine-containing gas and the inert gas can ensure the etching efficiency and quality.

[0098] In the second etching step, the process time is 5-15 s, preferably 8-12 s, and more preferably 10 s. Such a setting can ensure the etching efficiency and quality.

[0099] In addition, in the second etching step, the chamber pressure is 1-30 mTorr, preferably 5 mTorr; the center power of the upper electrode is 100-1000 W, preferably 300-800 W, and more preferably 600 W; and the edge power of the upper electrode is 500-3000 W, preferably 1000-2000 W, and more preferably 1500 W.

[0100] S1330, the volatilization step;

[0101] In the process of the volatilization step, the lower electrode power is 0.5 W to 5 W, preferably 0.8 W to 2 W, and further preferably 1 W; the argon (Ar) flow rate is 0.5 sccm to 5 sccm, preferably 0.8 sccm to 2 sccm, and further preferably 1 sccm; and the chlorine-containing gas flow rate is 0.5 sccm to 5 sccm, preferably 0.8 sccm to 8 sccm, and further preferably 1 sccm. In this way, on the one hand, the by-products can be volatilized in time, and on the other hand, the radio frequency does not need to be turned on / off and the gas pipeline valve does not need to be turned on / off when the process steps are rapidly switched, thereby avoiding frequent turning on / off of the radio frequency and frequent turning on / off of the gas pipeline valve.

[0102] In the process of the volatilization step, the process time is 0.5 s to 1.5 s, preferably 0.8 s to 1.2 s, and further preferably 1 s. In this way, the overall process time is reduced without affecting the etching quality, thereby improving the etching rate.

[0103] In addition, in the process of the volatilization step, the cavity pressure is 1 mTorr to 30 mTorr, preferably 5 mTorr; the upper electrode center power is 100 W to 1000 W, preferably 300 W to 800 W, and further preferably 600 W; and the upper electrode edge power is 500 W to 3000 W, preferably 1000 W to 2000 W, and further preferably 1500 W.

[0104] S1340, cooling step;

[0105] In the process of the cooling step, the lower electrode power is 0.5 W to 5 W, further preferably 0.8 W to 2 W, and further preferably 1 W; the argon (Ar) flow rate is 1 sccm to 15 sccm, further preferably 8 sccm to 12 sccm, and further preferably 10 sccm; and the chlorine-containing gas flow rate is 0.5 sccm to 5 sccm, further preferably 0.8 sccm to 8 sccm, and further preferably 1 sccm. On the one hand, the wafer to be etched can be cooled in time and at least part of the by-products can be volatilized in time, and on the other hand, the radio frequency does not need to be turned on / off and the gas pipeline valve does not need to be turned on / off when the process steps are rapidly switched, thereby avoiding frequent turning on / off of the radio frequency and frequent turning on / off of the gas pipeline valve.

[0106] In the process of the cooling step, the process time is 0.5 s to 1.5 s, further preferably 0.8 s to 1.2 s, and more preferably 1 s. In this way, the overall process time is reduced without affecting the etching quality, thereby improving the etching rate.

[0107] In addition, in the process of the cooling step, the chamber pressure is 1 mTorr to 30 mTorr, preferably 3 mTorr to 10 mTorr, and more preferably 5 mTorr; the center power of the upper electrode is 100 W to 1000 W, preferably 300 W to 800 W, and more preferably 600 W; and the edge power of the upper electrode is 500 W to 3000 W, preferably 1000 W to 2000 W, and more preferably 1500 W.

[0108] S1400, a desorption step;

[0109] In the process of the desorption step, the chamber pressure is 10 mTorr to 100 mTorr, preferably 30 mTorr to 70 mTorr, and more preferably 50 mTorr; the center power of the upper electrode is 100 W to 1000 W, preferably 300 W to 700 W, and more preferably 400 W to 600 W, and more preferably 500 W; the edge power of the upper electrode is 100 W to 1000 W, preferably 300 W to 700 W, and more preferably 400 W to 600 W, and more preferably 500 W; the power of the lower electrode is zero; the chlorine-containing gas includes chlorine, and the flow rate of the chlorine is 10 sccm to 1000 sccm, more preferably 20 sccm to 500 sccm, more preferably 50 sccm to 200 sccm, and more preferably 100 sccm; the flow rate of argon (Ar) is 10 sccm to 1000 sccm, more preferably 50 sccm to 600 sccm, more preferably 100 sccm to 300 sccm, and more preferably 200 sccm; and the process time is 2 s to 8 s, preferably 4 s to 6 s, and more preferably 5 s.

[0110] In the examples of the present application, the chlorine-containing gas in the stabilization step, the ignition step, the first etching step, and the second etching step includes BCl3 and Cl2, wherein the flow rate of BCl3 is 10 sccm to 100 sccm, more preferably 15 sccm to 50 sccm, and more preferably 20 sccm; and the flow rate of Cl2 is 10 sccm to 100 sccm, more preferably 15 sccm to 50 sccm, and more preferably 20 sccm. In addition, the chlorine-containing gas SiCl4 can be used to replace the chlorine-containing gas BCl3 and Cl2, and the flow rate of SiCl4 is 10 sccm to 100 sccm, more preferably 15 sccm to 50 sccm, and more preferably 20 sccm.

[0111] In addition, in the examples of the present application, the temperature of the cooling liquid of the susceptor is -15℃ to 60℃, preferably 0℃ to 50℃, and more preferably 40℃.

[0112] To make the etching method in the above examples of the present application more clearly and in detail, the process parameters in each process step are explained by tables as follows, see Table 1 and Table 2 below.

[0113] Table 1, plasma etching process recipe in the examples of the present application

[0114] Table 2, process recipe of main etching process step and auxiliary etching process step in the examples of the present application

[0115] The above-mentioned main etching process step and auxiliary etching process step are cycled, at least one of the first etching step and the second etching step is selected, and at least one of the volatilization step and the cooling step is selected, for example, the first etching step + cooling step can be cycled, the second etching step + cooling step can be cycled, the first etching step + volatilization step can be cycled, the second etching step + volatilization step can be cycled, the first etching step + volatilization step + cooling step can be cycled, the second etching step + volatilization step + cooling step can be cycled, the first etching step + second etching step + cooling step can be cycled, the first etching step + second etching step + volatilization step can be cycled, and all of them can be selected, that is, the first etching step + second etching step + volatilization step + cooling step (as shown in Table 2, the main etching process step includes the first etching step and the second etching step, and the auxiliary etching process step includes the volatilization step and the cooling step) can be cycled, and BCl3 and Cl2 can also use SiCl4 and other chlorine-containing gases; wherein, BCl3 and SiCl4 can not only play an etching role, but also play a side wall protection role, and Cl2 only has a pure etching role, therefore, when a chlorine-containing gas with a side wall protection performance (such as BCl3 and SiCl4) is selected, the side wall can be protected during the etching process, thereby realizing anisotropic etching, ensuring the consistency of the etching angle of the Sc-containing layer and the photoresist during the etching process, selecting Cl2 can accelerate the etching rate, ensure the etching rate, and reduce the deposition amount of the side wall deposits, facilitate the subsequent cleaning process, and ensure the consistency of the etching angle of the Sc-containing layer and the photoresist during the etching process; therefore, when the process gas is selected, chlorine-containing gases with a side wall protection performance and Cl2 with a high etching rate are preferred to be selected to simultaneously ensure the etching efficiency and the consistency of the etching angle, thereby ensuring the etching uniformity and the etching quality.

[0116] Specifically, in the examples of the present application, the lower electrode power of the first etching step is significantly greater than that of the second etching step, and the lower electrode power in the volatilization step and the cooling step is as low as possible, the gas flow (chlorine-containing gas and inert gas) in the volatilization step is as small as possible, the chlorine-containing gas flow in the cooling step is as small as possible, and a little inert gas flow is appropriately reserved in the cooling step to better cool the etching wafer.

[0117] The purpose of setting the lower electrode power, the chlorine-containing gas flow rate and the Ar gas flow rate in the volatilization step to 1 is to avoid frequent opening and closing of the radio frequency and the valve of the gas pipeline during the rapid switching of the volatilization step. The purpose of setting the lower electrode power and the chlorine-containing gas flow rate in the cooling step to 1 and setting the Ar gas flow rate to 10 (i.e., continuing to introduce a small amount of inert gas such as Ar) is to avoid frequent opening and closing of the radio frequency and the valve of the gas pipeline during the rapid switching of the cooling step and to ensure the cooling effect of the wafer to be etched. The purpose of setting the process time to a relatively short time (for example, 1 s, 2 s, etc.) is to reduce the process time and improve the etching rate without affecting the etching quality. However, the process time cannot be too short, otherwise the effect of the step cannot be achieved. Although the process time of the volatilization step and the cooling step is longer, the effect is better, but the productivity will be affected. In the example of the present application, the process time of the volatilization step and the cooling step is set to 1 s.

[0118] The lower electrode power in the first etching step is greater than that in the second etching step, which serves to break some chemical bonds in the process of the first etching step to facilitate subsequent etching and generate a large amount of heat, which is beneficial to the volatilization of by-products. In the volatilization step, the lower electrode power is turned off and all the inlets are closed, and vacuum is applied to volatilize the by-products quickly (no other gas is introduced, only the by-products can be removed). In the cooling step, the lower electrode power is turned off and most of the inlets participating in the chemical reaction (only Ar inert gas is retained) are closed, and vacuum is applied to remove the heat generated on the wafer and ensure the uniformity of etching. In this process, part of the by-products will also be volatilized quickly.

[0119] It should be noted that in the present embodiment, the Sc-containing layer is etched by using Sc x Al 1-x N material as an example, Sc is a metal element that can react with chlorine to generate ScCl3 which has a certain volatility but not too good. The etching method provided in the present embodiment can volatilize the by-product ScCl3 well during the etching process, so other materials containing Sc can also be etched by using the method provided in the present embodiment. As can be seen from the etching Sc-containing layer result representation graph shown in FIGS. 3a-3b, using the etching method provided in the present embodiment, there is no obvious by-product on the side wall, which can make each cycle stage smoothly perform the etching process, and the angle (inclination) of the etched Sc-containing layer and the photoresist is basically consistent, and the etching is relatively uniform, which not only ensures the etching rate but also ensures the etching quality. The size in FIGS. 3a-3b is only a rough value of a specific example, which is only to present the angle relationship between the etched Sc layer and the photoresist, for example, the angle between the Sc layer and the photoresist in the figure is about 65°, in fact, the angle between the two can also reach 75°, that is, the size in the figure does not limit the present application.

[0120] As can be seen from Figure 3a-Figure 3d, Sc x Al 1-x The angle of the N barrier layer is consistent with that of the photoresist, indicating that the etching process was not affected by sidewall deposition byproducts. It should also be noted that Figures 3a-3d are only used to illustrate the etching results and do not represent the actual structure of the semiconductor device.

[0121] Using IEP (Interferometry End Point) or LEP (Laser-Interferometry End Point) method to indicate the etching end point, Sc with different thickness can be obtained. x Al 1-x N barrier layer, as shown in FIG4a-FIG4d, can be obtained by the etching method provided in the embodiment of the present application. x Al 1-x The thickness of the N barrier layer can be about 100 nm (103 nm in FIG. 4 a), 50 nm (46.3 nm in FIG. 4 b), 30 nm (26.4 nm in FIG. 4 c), etc., wherein Sc in FIG. 4 d x Al 1-x The thickness of the N barrier layer is about 10 nm. It is not marked because it is too thin. As shown in Figures 4a to 4d, the etching method provided in the embodiment of the present application can etch a wide range of thicknesses of the Sc-containing layer, and the etching thickness is easy to control. That is, not only can a thicker Sc-containing layer (such as 100 nm Sc) be etched, but also a thicker Sc-containing layer (such as 100 nm Sc) can be etched. x Al 1-x N barrier layer), and can also be etched to obtain a thinner Sc-containing layer (such as Sc below 10nm). x Al 1-x N barrier layer). By introducing a recessed gate structure into the manufacture of a semiconductor device containing a Sc layer, a normally-off semiconductor device, such as a normally-off transistor containing a Sc layer, can be manufactured.

[0122] It should be noted that this characterization diagram is not part of a real semiconductor device, but is only used to schematically present the etching results. It can simulate the processing effect diagram of the semiconductor device manufactured by Figures 2a to 2n (the manufacturing method of a semiconductor device containing a Sc layer, which will be described in detail in Example 2 below) and can be characterized by SEM without the need for a TEM (Transmission Electron Microscope).

[0123] It should be noted that Figures 3a-3d and 4a-4d in the examples of this application are all electron microscope photos. In order to facilitate the presentation of contrast, Sc x Al 1-xN is a metal layer, which is thin, about 100nm or less, and the metal layer is not etched by Sc x Al 1-x N layer will not etch to the bottom of the metal layer, so the metal layer does not affect the etching of Sc x Al 1-x N layer does not affect the etching result, that is, Sc x Al 1-x N layer below, whether it is a metal layer or GaN, will not affect the etching result, so in the manufacture of semiconductor devices containing Sc x Al 1-x N layer below, a GaN layer can be provided. In addition, the dimensions in Figures 4a-4d are only approximate values of specific examples, and are only for presenting that Sc x Al 1-x N barrier layer, that is, the dimensions in the figure do not have a limiting effect on the present application.

[0124] In addition, the first etching step in the embodiment of the present application can include a bombardment step and / or an etching step, and the second etching step can include a bombardment step and / or an etching step, and can also be configured as the first etching step being a bombardment step and the second etching step being an etching step, which is not limited by the present application.

[0125] The etching method of the embodiment of the present application will be further compared and described below in conjunction with the following comparative examples.

[0126] Comparative Example 1

[0127] In this comparative example, Sc x Al 1-x N x = 20%, that is, the molar ratio of Sc content is 20%, and the process recipe in Table 3 is used to etch Sc x Al 1-x N, wherein the ESC temperature is 40°C.

[0128] Table 3, plasma etching process recipe of comparative example 1

[0129] In this comparative example 1, the main etching step does not use the cyclic main etching process step and auxiliary etching process step in the embodiment of the present application, but only uses the etching step, and the process parameters are shown in Table 3. Referring to Figures 5a-5d, the SEM characterization result shows that the side wall in this comparative example has a relatively heavy by-product, which causes the angle to be skewed, wherein the photoresist has an angle of about 75° or so, and the Sc x Al 1-xThe angle of N is only about 47°, and the tilt angles of both are very different. It should be noted that Figures 5a-5d are only used to illustrate the etching results, and are not the semiconductor devices shown in Figures 2a-2n. The sidewall by-products were characterized by Energy Dispersive X-Ray, and it was found that they contained Sc, as shown in Figures 6a-6b, which indicates that the by-products are caused by the difficulty of volatilization of ScCl3, and cause the photoresist to be attached to Sc x Al 1-x The post-etching angles of the angles of N are obviously inconsistent.

[0130] Comparative Example Two

[0131] In this comparative example two, M.T. Hardy et al. published an article entitled A Novel Barrier Material for High Power GaN-Based RF Transistors, in which Sc x Al 1-x N was etched using an upper electrode power of 200 W and a lower electrode power of 30 W-70 W, and according to the result graph shown in Figure 7, it can be seen that the etching rate is low.

[0132] Comparative Example Three

[0133] In this comparative example three, P.M. Mayrhofer et al. published an article entitled FABRICATION AND CHARACTERISATION OF SCALN-BASED PIEZOELECTRIC MEMS CANTILEVERS, in which Sc x Al 1-x N was etched using an etching gas containing SiCl4, a chamber pressure of 15 mTorr, an upper electrode power of 150 W, and a lower electrode power of 225 W, and according to the etching result characterization graph shown in Figures 8a-8b, it can be seen that the etching rate is low, only 10 nm / min.

[0134] Comparative Example Four

[0135] In this comparative example four, Konsta Airola et al. published an article entitled High-fidelity patterning of AlN and ScAlN thin films with wet chemical etching, in which Sc x Al 1-xThe etching morphology of N is shown in Figs. 9a-9d. As can be seen from the figures, although the etching rate can reach more than 100 nm / min, when the size of the semiconductor device is small, it is difficult for the solution to enter the etching surface, and the acidic or alkaline solution used for etching will also affect other structures in the device.

[0136] From the comparative analysis of the above comparative examples, it can be seen that the etching method of the Sc-containing layer provided in the embodiments of the present application can achieve high etching rate and etching uniformity, thereby ensuring etching efficiency and quality, and can achieve angle consistency of the Sc-containing layer and the photoresist, can etch to obtain Sc-containing layers of different thicknesses, and can realize thinning design of the Sc-containing layer, thereby providing technical support for manufacturing normally-off semiconductor devices.

[0137] Embodiment Two

[0138] The embodiment of the present application provides a manufacturing method of a semiconductor device, comprising the steps of:

[0139] S210, providing a substrate;

[0140] S220, forming a Sc-containing layer on the substrate; wherein the Sc-containing layer can act as a barrier layer, and Sc x Al 1-x N barrier layer is taken as an example;

[0141] S230, etching the Sc-containing layer to form a groove with a predetermined depth by using the etching method in the above-mentioned embodiment one, and the predetermined depth is less than the thickness of the Sc-containing layer;

[0142] S240, forming a gate electrode in the groove, and forming a source electrode and a drain electrode on both sides of the groove.

[0143] The etching method of the Sc-containing layer provided in the embodiments of the present application can produce the same beneficial effects as the above-mentioned etching method, i.e., improving etching efficiency, which will not be described here.

[0144] In the embodiments of the present application, step S220 comprises the following sub-steps:

[0145] S2202, obtaining a Sc precursor by using an electron beam evaporation method;

[0146] S2204, obtaining an Al precursor by using a filamentous exuding chamber;

[0147] S2206, depositing and growing a Sc x Al 1-x N barrier layer on the substrate by using a molecular beam epitaxy method; wherein in the process parameters of the molecular beam epitaxy method, the temperature is 500-900℃, and the nitrogen flow rate is 0.1-10 sccm.

[0148] In the embodiment of the present application, step S210 comprises the following sub-steps:

[0149] S2102, taking the substrate which has been cleaned;

[0150] S2104, depositing a buffer layer on the substrate;

[0151] S2106, depositing an epitaxial layer on the buffer layer.

[0152] In step 2104, the buffer layer comprises a first buffer layer and a second buffer layer, and comprises the following sub-steps:

[0153] (1) introducing trimethylaluminum and ammonia into the reaction chamber to deposit a first buffer layer on the substrate; the thickness of the first buffer layer is 4-6 nm, preferably 5 nm, the temperature is 680-720 °C, preferably 700 °C, and the deposition growth rate is 0.8-1.2 nm / min, preferably 1 nm / min;

[0154] (2) continuing to introduce trimethylaluminum and ammonia into the reaction chamber to form a second buffer layer on the first buffer layer; the thickness of the second buffer layer is 4-96 nm, the temperature is 780-820 °C, preferably 800 °C, and the deposition growth rate is 4.5-5.5 nm / min, preferably 5 nm / min.

[0155] Step 2106 comprises the step of introducing trimethylgallium and ammonia into the reaction chamber to deposit an epitaxial layer on the second buffer layer; in this process step, the temperature is 1050-1150 °C, preferably 1100 °C.

[0156] The above step S2102 comprises the following sub-steps:

[0157] (1) selecting a substrate, the substrate being a sapphire substrate, a silicon carbide substrate or a silicon substrate;

[0158] (2) selecting a cleaning solvent, the cleaning solvent being a mixed solution of 98% concentrated sulfuric acid and 30% hydrogen peroxide, wherein the volume ratio of 98% concentrated sulfuric acid to 30% hydrogen peroxide is 6 / 4-8 / 2, preferably 7 / 3;

[0159] (3) placing the substrate in the cleaning solvent and heating to a preset cleaning temperature for at least 30 minutes or until the bubbles disappear; wherein the preset cleaning temperature is 105-115 °C, preferably 110 °C;

[0160] (4) taking the substrate out of the cleaning solvent and cleaning it with ultrapure water.

[0161] In the embodiment of the present application, step 230 comprises the following sub-steps:

[0162] S2302, spin-coating a first photoresist on the barrier layer, and performing exposure, development and fixation on the first photoresist to obtain a first mask plate with a first through slot, the position of the barrier layer exposed by the first through slot being the position of the groove;

[0163] The thickness of the first photoresist is 0.5-10 μm, preferably 3 μm; the exposure time is 3-20 s, preferably 6 s; the development time is 45-120 s, preferably 75 s; and the fixation time is 60-300 s, preferably 120 s.

[0164] S2304, etching the first mask plate and the barrier layer, wherein the region opposite to the first through slot is etched to form the groove;

[0165] The etching process step adopts the steps provided in the etching method of Embodiment One, including a stabilization step, an ignition step, a main etching process step, an auxiliary etching process step and a desorption step, wherein the main etching process step and the auxiliary etching process step are executed cyclically, the main etching process step includes at least one of a first etching step and a second etching step, the auxiliary etching process step includes at least one of a volatilization step and a cooling step, and each process step and its process parameters are as stated in Embodiment One, which will not be described herein again.

[0166] S2306, removing the first photoresist and by-products. This step includes the following sub-steps:

[0167] (1) If the first photoresist still remains, the first photoresist is soaked and washed with an organic liquid until the first photoresist completely falls off;

[0168] (2) removing the by-products of the first photoresist and the by-products generated in the etching process in step S2304.

[0169] In the embodiments of the present application, step S240 includes the following sub-steps:

[0170] S2402, spin-coating a second photoresist on the barrier layer with the groove, and performing exposure, development and fixation on the second photoresist to obtain a second mask plate with a second through slot and a third through slot, the position of the barrier layer exposed by the second through slot being the position of the source electrode, and the position of the barrier layer exposed by the third through slot being the position of the drain electrode;

[0171] The thickness of the second photoresist is 0.5-10 μm, preferably 1-5 μm, and more preferably 3 μm; the width of the second through slot is 5-500 μm, preferably 6-200 μm, more preferably 7-100 μm, and even more preferably 8-50 μm, and even more preferably 10 μm; the width of the third through slot is 5-500 μm, preferably 6-200 μm, more preferably 7-100 μm, and even more preferably 8-50 μm, and even more preferably 10 μm; the exposure time is 3-20 s, preferably 5-10 s, and more preferably 6 s; the developing time is 45-120 s, preferably 60-100 s, and more preferably 75 s; and the fixing time is 60-300 s, preferably 80-200 s, and more preferably 120 s.

[0172] S2404, depositing metal ions on the source and drain positions of the second photoresist and the barrier layer to form the source and the drain; or, thermally evaporating the barrier layer to form the source and the drain;

[0173] In the physical vapor deposition process, Ti ions and Al ions are sequentially deposited to obtain Ti layer and Al layer; the cavity pressure of the reaction chamber is 10-100 mTorr; the upper electrode power is 750-3000 W, the lower electrode power is 5-500 W, and the process gas includes argon with a flow rate of 50-500 sccm; or, in the thermal evaporation process, the cavity pressure of the reaction chamber is 5×10 -5 Pa-5×10 -4 Pa, preferably 1×10 -4 Pa, and the current is 1-20 mA, preferably 5 mA.

[0174] S2406, removing the second photoresist and by-products. This step includes the following sub-steps:

[0175] (1) If the second photoresist remains, the second photoresist is soaked and washed with organic liquid until the second photoresist is completely removed;

[0176] (2) removing by-products of the second photoresist and by-products generated in the deposition process of step S2404, or removing by-products of the second photoresist and by-products generated in the thermal evaporation process of step S2404;

[0177] S2408, spin-coating a third photoresist on the barrier layer with the groove, the source and the drain, and exposing, developing and fixing the third photoresist to obtain a third mask plate with a fourth through slot, the barrier layer exposed by the fourth through slot being the gate position, and the gate position being located in the groove.

[0178] The third photoresist has a thickness of 0.5-10 μm, preferably 1-5 μm, and more preferably 3 μm. The exposure time is 3-20 s, preferably 5-10 s, and more preferably 6 s. The developing time is 45-120 s, preferably 60-100 s, and more preferably 75 s. The fixing time is 60-300 s, preferably 80-200 s, and more preferably 120 s.

[0179] S2410. Metal ions are deposited on the third photoresist and the gate position in the groove to form a gate; or, the step is to form a gate by thermal evaporation at the gate position in the groove.

[0180] The physical vapor deposition is used to sequentially deposit Ni ions and Au ions to obtain the Ni layer and the Au layer. The cavity pressure of the reaction chamber is 10-100 mTorr. The upper electrode power is 750-3000 W, and the lower electrode power is 5-500 W. The process gas includes argon, and the argon flow rate is 50-500 sccm. Alternatively, during the thermal evaporation process, the cavity pressure of the reaction chamber is 5×10 -5 Pa-5×10 -4 Pa, preferably 1×10 -4 Pa, and the current is 1-20 mA, preferably 5 mA.

[0181] S2412. The third photoresist and by-products are removed. The step includes the following sub-steps:

[0182] (1) If the third photoresist remains, the second photoresist is soaked and washed with an organic liquid until the third photoresist is completely removed.

[0183] (2) The by-products of the third photoresist and the by-products generated in the deposition process of step S2410 are removed; or, the by-products of the third photoresist and the by-products generated in the thermal evaporation process of step S2410 are removed.

[0184] In the embodiments of the present application, step S240 is followed by the following steps:

[0185] S250. The barrier layer with the source electrode, the gate electrode, the drain electrode and the groove is deposited to form a passivation layer.

[0186] Specifically, in the deposition process of this step, a passivation layer is formed by plasma enhanced chemical vapor deposition or high-density plasma chemical vapor deposition; the passivation layer comprises a SiN layer and a SiO2 layer; the cavity pressure of the reaction chamber is 1 mTorr-1000 mTorr, if high-density plasma chemical vapor deposition is used, the cavity pressure is preferably 5 mTorr, if plasma enhanced chemical vapor deposition is used, the cavity pressure is preferably 500 mTorr; the upper electrode power is 500 W-15000 W, preferably 5000 W; the lower electrode power is 0-15000 W, preferably 5000 W; the process gas comprises SiH4 and O2, the flow rate of SiH4 is 10 sccm-1000 sccm, preferably 50 sccm, the flow rate of O2 is 10 sccm-1000 sccm, preferably 500 sccm, and the cooling liquid temperature of the susceptor is -15℃-100℃, preferably 40℃.

[0187] In the embodiment of the present application, after step S250, the following steps are further included:

[0188] S260, packaging and cutting to obtain a semiconductor device containing a Sc layer, for example, a transistor containing a Sc layer.

[0189] To further explain the manufacturing method of the semiconductor device provided by the embodiment of the present application, a specific example is listed as follows:

[0190] S301, cleaning of the substrate to obtain a substrate meeting the cleanliness requirement, as shown in FIG. 2a, wherein the substrate 120 can be selected from sapphire, silicon carbide, silicon, etc., taking silicon as an example, a RCA standard cleaning method is used, commercially available 98% sulfuric acid and commercially available 30% hydrogen peroxide are mixed in a volume ratio of 7:3, then the mixture is put into a silicon wafer and heated to 110℃ until the bubbles disappear (at least thirty minutes or more), then the silicon wafer is taken out and cleaned with ultrapure water;

[0191] S302, growing an AlN buffer layer by Metal-Organic Chemical Vapor Deposition (MOCVD), the thickness of the AlN buffer layer is 10 nm-100 nm, preferably 40 nm, as shown in FIG. 2b, specifically, trimethylaluminum and ammonia are introduced into the reaction chamber, the temperature is raised to 700℃, the growth rate is controlled at 1 nm / min, and a 5 nm-thick AlN nucleation layer is deposited on the substrate 120; then, the introduction of trimethylaluminum and ammonia is continued, the temperature in the chamber is raised to 800℃, and the growth rate is increased to 5 nm / min to form the AlN buffer layer 130;

[0192] S303, on the basis of step S302, stop the input of trimethylaluminum, continue to input trimethylgallium and ammonia into the reaction chamber, and raise the temperature to 1100°C, so as to continue the deposition of the GaN epitaxial layer 110 on the AlN buffer layer 130, as shown in FIG. 2c. The thickness of the GaN epitaxial layer 110 is 1 μm to 10 μm, and preferably 3 μm;

[0193] S304, using a molecular beam epitaxy (MBE) method to grow a Sc x Al 1-x N epitaxial layer 200, as shown in FIG. 2d, wherein the thickness of the epitaxial layer 200 is 0.01 μm to 1 μm, the temperature is 500°C to 900°C, the nitrogen flow rate is 0.1 sccm to 10 sccm, the Sc precursor can be obtained by an electron beam evaporation method, and the Al precursor can be obtained by a filament effusion cell;

[0194] S305, spin-coating photoresist, as shown in FIG. 2e, to obtain a first photoresist layer 310 having a first through slot 311, wherein the thickness of the first photoresist layer 310 is 0.5 μm to 10 μm, and preferably 3 μm, exposure, development, and a mask plate is designed and processed in advance, so that the distance between the first through slot 311, i.e., the groove portion (calculated from both ends of the groove), and the source electrode and the drain electrode is 0.3 μm and 1 μm, respectively, the exposure time is 3 s to 20 s, and preferably 6 s, the development time is 45 s to 120 s, and preferably 75 s, and the fixing time is 60 s to 300 s, and preferably 120 s, so as to pattern the photoresist;

[0195] It should be noted that for a voltage-resistant device, the distance between the gate electrode and the drain electrode can affect the voltage that the device can withstand, and for a radio frequency device, the distance between the gate electrode and the source electrode can affect the current density, on-resistance, and transconductance peak value of the device, and reducing the distance between the gate electrode and the source electrode can improve the above parameters, therefore, the distance between the gate electrode and the drain electrode is set to be 1 to 5 times the distance between the gate electrode and the source electrode, i.e., the ratio of the distance between the gate electrode and the drain electrode to the distance between the gate electrode and the source electrode is (1-5): 1.

[0196] S306, plasma etching the Sc x Al 1-xN, as shown in Figure 2f, the groove 240 is formed, the cavity pressure is 1 mTorr ~ 30 mTorr, preferably 5 mTorr, the upper electrode power is 500 W ~ 3000 W, the upper electrode center power is preferably 600 W, the upper electrode edge power is preferably 1500 W; the lower electrode power of the main etching process step is 100 W ~ 1000 W, the lower electrode power of the first etching step is preferably 600 W, the lower electrode power of the second etching step is preferably 400 W; the lower electrode power of the auxiliary etching process step is close to zero, preferably 1 W; the argon (Ar) flow rate of the main etching process step is 10 sccm ~ 1000 sccm, preferably 100 sccm, the BCl3 flow rate is 10 sccm ~ 100 sccm (other chlorine-containing gases such as SiCl4 can also be used), preferably 20 sccm, the Cl2 flow rate is 10 sccm ~ 100 sccm (other chlorine-containing gases such as SiCl4 can also be used); the process gas flow rate of the auxiliary etching process step is close to zero, wherein the chlorine-containing gas and Ar flow rates of the volatilization step are both preferably 1 sccm, the chlorine-containing gas flow rate of the cooling step is preferably 1 sccm, and the Ar flow rate is preferably 10 sccm; the base cooling liquid temperature is -15℃ ~ 60℃, preferably 40℃.

[0197] Specifically, the etching process steps adopt the steps provided in the etching method of the above-mentioned embodiment one, including: a stabilization step, an ignition step, a main etching process step, an auxiliary etching process step, and a desorption step, wherein the main etching process step and the auxiliary etching process step are executed cyclically, the main etching process step includes at least one of a first etching step and a second etching step, the auxiliary etching process step includes at least one of a volatilization step and a cooling step, and each process step and its process parameters are referred to the content stated in the above-mentioned embodiment one, which will not be repeated here.

[0198] S307, wet degumming, as shown in Figure 2g, the first photoresist layer 310 is removed, wherein an organic chemical solution such as acetone is used, the time is not limited, and the soaking is ended when most of the photoresist falls off the Sc-containing layer surface, and then the photoresist is completely removed from the Sc-containing layer surface by washing with flowing organic chemical solution;

[0199] S308, spin coating photoresist, as shown in Figure 2h, to obtain a second photoresist layer 320 with a second through groove 321 and a third through groove 322, the thickness of the second photoresist layer 320 is 0.5 μm ~ 10 μm, preferably 3 μm, exposure, development, the mask plate is designed and processed in advance, and the electrode width of the source and the drain is about 5 μm ~ 500 μm, preferably 10 μm, the exposure time is 3 s ~ 20 s, preferably 6 s, the development time is 45 s ~ 120 s, preferably 75 s, and the fixing time is 60 s ~ 300 s, preferably 120 s, so as to pattern the photoresist;

[0200] S309, metal Ti / Al of source 210 and drain 230 is made to form ohmic contact with conductive channel, as shown in FIG. 2i, specifically, Physical Vapor Deposition (PVD) method is adopted, wherein, Ti thickness is 0.05 μm-0.2 μm, preferably 0.1 μm, Al thickness is 0.1 μm-0.5 μm, preferably 0.3 μm, in terms of process conditions, cavity pressure is 10 mTorr-100 mTorr, upper electrode power is 750 W-3000 W, lower electrode power is 5 W-500 W, Ar flow is 50 sccm-500 sccm; in some embodiments, this step can also be prepared by thermal evaporation, cavity pressure is 5x10 -5 Pa-5x10 -4 Pa, preferably 1x10 -4 Pa, current is 1 mA-20 mA, preferably 5 mA;

[0201] S310, wet stripping, as shown in FIG. 2j, the second photoresist layer 320 is removed, specifically, this step is basically the same as step S307;

[0202] S311, spin coating photoresist, as shown in FIG. 2k, third photoresist 330 is obtained, which has fourth through slot 331, thickness is 0.5 μm-10 μm, preferably 3 μm, exposure, development, mask plate is designed and processed in advance, so that the distance between the metal of the gate of the device and the metal of the drain 230 is about 1 μm-10 μm, preferably 5 μm, the distance between the metal of the gate and the metal of the source 210 is about 0.5 μm-5 μm, preferably 1 μm, the length of the gate is about 0.5 μm-5 μm, preferably 1 μm, the width of the gate is about 0.1 mm-10 mm, preferably 3 mm, the effective area of the semiconductor device is about (1-10) x 10 -4 cm 2 (including source and drain), exposure time is 3 s-20 s, preferably 6 s, development time is 45 s-120 s, preferably 75 s, fixing time is 60 s-300 s, preferably 120 s, so that the photoresist is patterned;

[0203] S312, metal Ni / Au of gate 220 is made, as shown in FIG. 2l, specifically, Ni thickness is 1 nm-10 nm, preferably 5 nm, Au thickness is 10 nm-100 nm, preferably 50 nm, PVD or thermal evaporation can be adopted, similar to step S309;

[0204] S313, wet stripping, as shown in FIG. 2m, the third photoresist 330 is removed, this step is basically the same as step S307;

[0205] S314, a passivation layer 400 is deposited on the surface of the semiconductor device by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD) to protect the semiconductor device, as shown in FIG. 2n, for example, by depositing SiN with a thickness of 300 nm and SiO2 with a thickness of 600 nm, wherein the process parameters of this step are as follows: chamber pressure is 1 mTorr-1000 mTorr, preferably 5 mTorr for HDPCVD and 500 mTorr for PECVD, upper electrode power is 500 W-15000 W, preferably 5000 W, lower electrode power is 0-15000 W, preferably 5000 W, SiH4flow rate is 10 sccm-1000 sccm, preferably 50 sccm, O2flow rate is 10 sccm-1000 sccm, preferably 500 sccm, and base cooling liquid temperature is -15℃-100℃, preferably 40℃;

[0206] S315, packaging and cutting.

[0207] The embodiment of the present application further provides a semiconductor device, which comprises a substrate, a Sc-containing layer, a source electrode, a drain electrode and a gate electrode; wherein the Sc-containing layer is arranged on the substrate, a recess is formed on the side of the Sc-containing layer away from the substrate, and the depth of the recess is less than the thickness of the Sc-containing layer; the source electrode is arranged on the first side of the recess; the drain electrode is arranged on the second side of the recess, the second side being opposite to the first side, and the distance between the source electrode and the edge of the first side of the recess is less than the distance between the drain electrode and the edge of the second side of the recess; and the gate electrode is arranged in the recess, and the distance between the gate electrode and the source electrode is less than the distance between the gate electrode and the drain electrode. In this embodiment, the recess can be formed by the etching method of the Sc-containing layer described above. It is easily understood that the source electrode and the drain electrode are both arranged on the side of the Sc-containing layer away from the substrate and outside the recess, and the first side and the second side of the recess respectively refer to the outside of the two groove side surfaces of the recess.

[0208] The semiconductor device has a Sc-containing layer, the Sc-containing layer is a barrier layer, the Sc-containing layer is etched by using the etching method to form a groove with a predetermined depth, the groove is formed, and the gate electrode in the groove forms a groove gate structure. Compared with related technologies, the groove gate structure can thin the barrier layer where the gate electrode is located. When the gate voltage is regulated, a potential well appears to form a two-dimensional electron gas, thereby realizing high electron mobility of the semiconductor device. When no gate voltage is applied, the potential well of the two-dimensional electron gas disappears, and the semiconductor device is in an off state, that is, the semiconductor device is a normally-off semiconductor device, thereby realizing safety control performance of the semiconductor device.

[0209] In the embodiment of the present application, the Sc-containing layer includes Sc x Al 1-x N, wherein the value range of x is less than 43%, preferably 20% to 40%, further preferably 22% to 38%, further preferably 25% to 35%, further preferably 28% to 32%, and more preferably 30%; the distance between the bottom of the groove and the side of the Sc-containing layer facing the substrate is 1 nm to 100 nm, preferably 2 nm to 20 nm, further preferably 3 nm to 10 nm, and more preferably 5 nm; the distance between the source electrode and the edge of the first side of the groove is 0.1 μm to 0.5 μm; the distance between the drain electrode and the edge of the second side of the groove is 0.5 μm to 5 μm; the length of the gate electrode is 0.5 μm to 5 μm, further preferably 0.6 μm to 2 μm, and further preferably 1 μm; and the width of the gate electrode is 0.1 mm to 10 mm, further preferably 1 mm to 5 mm, and further preferably 3 mm.

[0210] The following takes the manufacture of a semiconductor device (for example, a transistor) with a Sc-containing layer as an example. As shown in FIG. 1, the semiconductor device includes a substrate 120, a Sc-containing layer (that is, a barrier layer 200), a source electrode 210, a drain electrode 230, and a gate electrode 220. The Sc-containing layer is arranged above the substrate 120. The side of the Sc-containing layer away from the substrate 120 is formed with a groove 240, the depth of the groove 240 is less than the thickness of the Sc-containing layer. The source electrode 210 is arranged at the first side of the groove 240. The drain electrode 230 is arranged at the second side of the groove 240, the second side is opposite to the first side, and the distance between the source electrode 210 and the edge of the first side of the groove 240 is less than the distance between the drain electrode 230 and the edge of the second side of the groove 240. The gate electrode 220 is arranged in the groove 240, and the distance between the gate electrode 220 and the source electrode 210 is less than the distance between the gate electrode 220 and the drain electrode 230.

[0211] Specifically, in the embodiment, the substrate 120 and the Sc-containing layer further have a buffer layer 130 and an epitaxial layer 110, wherein the epitaxial layer 110, the buffer layer 130 and the substrate 120 are sequentially arranged from top to bottom to form an epitaxial wafer 100. Please continue to refer to FIG. 1, the epitaxial layer 110 of the epitaxial wafer 100 is deposited with a barrier layer 200, the barrier layer 200 is formed with a groove 240 away from the side of the substrate 120, a source electrode 210 is arranged on a first side of the groove 240; a drain electrode 230 is arranged on a second side of the groove 240, and a gate electrode 220 is arranged in the groove 240. The source electrode 210, the gate electrode 220, the drain electrode 230 and the groove 240 are arranged at intervals, the opening of the groove 240 faces away from the epitaxial layer 110, and the bottom of the groove 240 does not pass through the epitaxial layer 110, that is, the depth of the groove 240 is less than the thickness of the barrier layer 200, and the gate electrode 220 is located in the groove 240; the barrier layer 200 is a Sc-containing layer. In the embodiment, the barrier layer 200 is still a Sc-containing layer x Al 1-x N barrier layer is taken as an example.

[0212] The distance h between the bottom of the groove 240 and the side of the Sc-containing layer facing the substrate is 1 nm to 100 nm, preferably 2 nm to 20 nm, further preferably 3 nm to 10 nm, and more preferably 5 nm. The groove 240 has oppositely arranged first and second edges, wherein the first edge is located between the gate electrode 220 and the source electrode 210, and the second edge is located between the gate electrode 220 and the drain electrode 230. The distance M between the first edge and the source electrode 210 is 0.1 μm to 0.5 μm, and the distance N between the second edge and the drain electrode 230 is 0.5 μm to 5 μm. The length G of the gate electrode 220 is 0.5 μm to 5 μm, further preferably 0.6 μm to 2 μm, and further preferably 1 μm. The width of the gate electrode 220 is 0.1 mm to 10 mm, further preferably 1 mm to 5 mm, and further preferably 3 mm. In this way, as shown in FIG. 11a, when the gate voltage is regulated, a potential well appears, thereby forming a two-dimensional electron gas, achieving high electron mobility of the semiconductor device; as shown in FIG. 11b, when no gate voltage is applied, the potential well of the formed two-dimensional electron gas disappears, and the semiconductor device is in an off state, that is, the semiconductor device is a normally-off semiconductor device, achieving safety control performance of the semiconductor device.

[0213] The thickness H of the barrier layer 200 is 0.01 μm to 1 μm, preferably 0.01 μm to 0.5 μm, further preferably 0.01 μm to 0.1 μm, further preferably 0.01 μm to 0.05 μm, and further preferably 0.03 μm. The thickness of the epitaxial layer 110 is taken as an example of a GaN epitaxial layer, which is 1 μm to 10 μm, preferably 2 μm to 5 μm, and further preferably 3 μm.

[0214] The length Y of the source electrode 210 is 5 μm to 500 μm, further preferably 6 μm to 100 μm, further preferably 7 μm to 50 μm, and further preferably 10 μm. The source electrode 210 includes a Ti layer and an Al layer, and the Ti layer is located between the barrier layer 200 and the Al layer. The thickness of the Ti layer is 0.05 μm to 0.2 μm, and is preferably 0.1 μm. The thickness of the Al layer is 0.1 μm to 0.5 μm, and is preferably 0.3 μm.

[0215] The length D of the drain electrode 230 is 5 μm to 500 μm, further preferably 6 μm to 100 μm, further preferably 7 μm to 50 μm, and further preferably 10 μm. The size of the drain electrode 230 can be the same as that of the source electrode 210. Specifically, the drain electrode 230 includes a Ti layer and an Al layer, and the Ti layer is located between the barrier layer 200 and the Al layer. The thickness of the Ti layer is 0.05 μm to 0.2 μm, and is preferably 0.1 μm. The thickness of the Al layer is 0.1 μm to 0.5 μm, and is preferably 0.3 μm.

[0216] The gate electrode 220 includes a Ni layer and an Au layer, and the Ni layer is located between the barrier layer 200 and the Au layer. The thickness of the Ni layer is 1 nm to 10 nm, and is preferably 5 nm. The thickness of the Au layer is 10 nm to 100 nm, and is preferably 50 nm.

[0217] The distance y between the gate electrode 220 and the source electrode 210 is 0.5 μm to 5 μm, and is preferably 1 μm. The distance d between the gate electrode 220 and the drain electrode 230 is 1 μm to 10 μm, and is preferably 5 μm. The distance d between the gate electrode 220 and the drain electrode 230 is set as a first distance, and the distance y between the gate electrode 220 and the source electrode 210 is set as a second distance. The ratio d / y of the first distance to the second distance is 1 to 5.

[0218] The distance m between the first edge of the recess 240 and the gate electrode 220 is 0.1 μm to 1 μm, further preferably 0.2 μm to 5 μm, and further preferably 0.3 μm. The distance n between the second edge of the recess 240 and the gate electrode 220 is 0.3 μm to 5 μm, further preferably 0.5 μm to 3 μm, and further preferably 1 μm.

[0219] In the embodiment of the present application, the buffer layer 130 is an AlN buffer layer. The thickness of the buffer layer 130 is 10 nm to 100 nm, further preferably 20 nm to 60 nm, and further preferably 40 nm.

[0220] In the embodiments of the present application, a passivation layer 400 is also deposited on the surface of the semiconductor device to protect the semiconductor device. The passivation layer 400 covers the surface of the barrier layer 200 away from the substrate 120 except the areas where the source 210, the drain 230 and the gate 220 are located (including the surface in the groove 240). The passivation layer 400 includes, for example, SiN with a thickness of 300 nm and SiO2 with a thickness of 600 nm.

[0221] The semiconductor device with the Sc-containing layer provided by the embodiments of the present application, for example, a transistor, can achieve both high electron mobility and normally-off.

[0222] Embodiment Three

[0223] The embodiments of the present application provide a process equipment, which is actually a semiconductor process equipment. As shown in FIG. 10, the semiconductor process equipment includes a process chamber 500, a gas inlet assembly (not shown in the figure), an upper electrode assembly 510 and a lower electrode assembly 520, and a controller (not shown in the figure). The controller includes at least one processor and at least one memory, and the memory stores a computer program which is executed by the processor to implement the etching method and the manufacturing method of any one of the above embodiments.

[0224] Exemplarily, the controller can be an upper computer or a lower computer. The controller can control the opening of the valve of the gas inlet assembly to introduce corresponding process gas into the inside of the process chamber 500, and can control the opening degree of the valve of the gas inlet assembly to control the flow of the process gas. The controller can also control the exhaust assembly to exhaust the inside of the process chamber 500 to control the pressure in the process chamber 500, discharge reaction byproducts, etc.

[0225] The upper electrode assembly 510 includes a radio frequency coil 511, an upper radio frequency power supply 512 and an upper matching device 513. The controller is further configured to control the upper radio frequency power supply 512 to provide upper electrode power to the radio frequency coil 511 through the upper matching device 513, so that the radio frequency coil 511 excites the process gas in the process chamber 500 to generate plasma.

[0226] The lower electrode assembly 520 includes a wafer supporting device 521, a lower radio frequency power supply 522 and a lower matching device 523. The controller is further configured to control the lower radio frequency power supply 522 to provide lower electrode power to the lower electrode of the wafer supporting device 521 through the lower matching device 523, so that the lower electrode of the wafer supporting device 521 provides radio frequency bias to adsorb the plasma above the object to be etched (not shown in the figure) to bombard the object to be etched.

[0227] The semiconductor process equipment of the embodiments of the present application can be an inductively coupled plasma (ICP) etching equipment, or can be a capacitively coupled plasma (CCP) etching equipment. The embodiments of the present application do not limit the type of semiconductor process equipment.

[0228] The process equipment provided by the embodiments of the present application has the beneficial effects of the etching method and the manufacturing method described above, which will not be repeated here.

[0229] In the description of the present application, it should be noted that the terms "upper", "lower", "front", "horizontal" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0230] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the term "mounting" should be understood broadly, for example, it can be fixedly connected, or can be detachably connected, or integrally connected; it can be mechanically connected, or can be electrically connected; it can be directly connected, or can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above-mentioned term in the present application can be understood according to the specific circumstances.

[0231] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for etching a Sc-containing layer, characterized in that: The etching method includes a main etching process step and an auxiliary etching process step which are performed cyclically; wherein, The main etching process step includes: introducing a process gas into a process chamber and exciting to generate plasma to etch the Sc-containing layer, wherein the process gas includes a chlorine-containing gas and an inert gas; The auxiliary etching process step includes: at least one of a volatilization step and a cooling step; The volatilization step includes: reducing the power of the lower electrode to zero power or close to zero power, and reducing the flow of the process gas to zero flow or close to zero flow; The cooling step includes: reducing the power of the lower electrode to zero power or close to zero power, reducing the flow of chlorine-containing gas to zero flow or close to zero flow, and continuing to introduce inert gas.

2. The etching method according to claim 1, wherein: The main etching process step includes a first etching step and / or a second etching step. The process gas used in the first etching step and the second etching step is the same. The lower electrode power of the first etching step is greater than the lower electrode power of the second etching step.

3. The etching method according to claim 2, wherein: The power ratio of the lower electrode in the first etching step to that in the second etching step is (1.2-1.8):1; And / or, the process duration ratio of the first etching step to the second etching step is 1:(4-6).

4. The etching method according to claim 3, wherein: The power of the lower electrode in the first etching step is 100W to 1000W; the power of the lower electrode in the second etching step is 100W to 1000W; And / or, the process time of the first etching step is 1.2s to 3s, and the process time of the second etching step is 8s to 12s.

5. The etching method according to any one of claims 1 to 4, characterized in that: In the main etching process step, the flow ratio of chlorine-containing gas to inert gas is (0.3-0.5):1; And / or, in the main etching process step, the flow rate of the chlorine-containing gas is 20 sccm to 200 sccm, and the flow rate of the inert gas is 10 sccm to 1000 sccm.

6. The etching method according to claim 5, characterized in that: The chlorine-containing gas includes at least one of SiCl 4 , BCl 3 and Cl 2 , and / or the inert gas includes Ar.

7. The etching method according to claim 6, characterized in that: The chlorine-containing gas includes BCl3 and Cl2, and the flow ratio of BCl3 to Cl2 is (0.9-1.1):1; Alternatively, the chlorine-containing gas comprises SiCl 4 .

8. The etching method according to any one of claims 1 to 4, characterized in that: The process duration of the volatilization step is 0.5s to 1.5s; and / or the process duration of the cooling step is 0.5s to 1.5s.

9. A method for manufacturing a semiconductor device, characterized in that: Including steps: providing a substrate; forming a Sc-containing layer on the substrate; Applying the etching method according to any one of claims 1 to 8 to etch the Sc-containing layer to form a groove of a predetermined depth, wherein the predetermined depth is less than the thickness of the Sc-containing layer; A gate is formed in the groove, and a source and a drain are formed on both sides of the groove.

10. A semiconductor process equipment comprising a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory. When the computer program is executed by the processor, the etching method according to any one of claims 1 to 8 is implemented, or the manufacturing method according to claim 9 is implemented.

11. A semiconductor device, characterized in that: include: substrate; a Sc-containing layer disposed on the substrate, wherein a groove is formed on a side of the Sc-containing layer away from the substrate, and a depth of the groove is less than a thickness of the Sc-containing layer; a source electrode, disposed on a first side of the groove; a drain electrode, disposed on a second side of the groove, the second side being opposite to the first side, wherein a distance between the source electrode and an edge of the first side of the groove is smaller than a distance between the drain electrode and an edge of the second side of the groove; A gate is disposed in the groove, and a distance between the gate and the source is smaller than a distance between the gate and the drain.

12. The semiconductor device according to claim 11, wherein The Sc-containing layer includes Sc x Al 1-x N, where the range of x is less than 43%; or, The distance between the bottom of the groove and the side of the Sc-containing layer facing the substrate is in the range of 1 nm to 100 nm; or, The distance between the source electrode and the edge of the first side of the groove is 0.1 μm to 0.5 μm; or, The distance between the drain electrode and the edge of the second side of the groove is 0.5 μm to 5 μm; or, The gate has a length of 0.5 μm to 5 μm and a width of 0.1 mm to 10 mm.

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