Current interruption protection for current source converters using gate current mirrors

Abstract

A control circuit for a current source converter, having a current generator comprising: an inductance having two or more half bridges, each half bridge having an upper leg provided with an upper switching device, and a lower leg provided with a lower switching device, said upper legs switching devices and said lower leg switching devices being controlled by a controller, to provide an overlap between an upper leg turning OFF and an upper leg turning ON switching device and to provide an overlap between a lower leg turning ON switching device and a lower leg turning OFF switching device through gate pull up and gate pull down pulse signals to gate driver buffers of said switching devices, where said gate driver circuit comprises: for each switching device: a gate current mirroring circuit on a sink branch of the gate driver buffer of such switching device to provide a gate pull down detection signal from a turning OFF switching device, a gate command connection path to provide a gate command signal, at least one logic circuit combining a gate command signal of a first upper or lower leg switching device and a gate pull down signal of a respective second upper or lower leg switching device, to provide a first protection trigger signal, when said gate command signal of said first upper or lower leg switching device, and said gate pull down detection signal of said respective second upper or lower leg switching device correspond to both said first and second upper leg switching devices or both said first and second lower leg switching devices being OFF.

Description

[DESCRIPTION][TITLE OF INVENTION]CURRENT INTERRUPTION PROTECTION FOR CURRENT SOURCECONVERTERS USING GATE CURRENT MIRRORS[Technical Field]

[0001] The present disclosure pertains to current source power converters comprising at least two half-bridges with upper and lower switching devices and more precisely concerns the reduction of the risk of current interruption when switching from one upper switching device to another upper switching device or switching from one lower switching device to another lower switching device. Priority is claimed on European Patent Application No. EP23306948.3, filed November 10, 2023, the contents of which are incorporated herein by reference.[Background Art]

[0002] Current source converters (CSC) are used for different applications, which includes HVDC, motor drive, or power factor correctors. The main limitation of such converters is the use of bulky input inductances and power modules, designed for conventional switching cells. However, the growing emergence of wide bandgap devices, e.g. Silicone Carbide and / or Gallium Nitride, with lower conductive and switching losses opened up new possibilities for current fed converter design by reducing a size and improving an efficiency thereof.[Summary of Invention][PROBLEM TO BE SOLVED BY THE INVENTION]

[0003] In a current fed power converter composed of at least two half bridges, the switches of the different half bridges are controlled in a complementary way (conducting to blocking and blocking to conducting). Between these transitions, overlapping (both switches ON) between upper switching devices and between lower switching devices is used. The main reason of the overlapping is due to the nature of the input source, which is an inductive source that resists current changes, and may cause overvoltage pulses in a case of abrupt current change. A cause of DC link current interruption can be due to multiple factors, including wrong control signal of a switching device, a faulty device, a failed in open circuit, or a failed gate driver. In consequence, an open current path for the DC current can lead to tremendous damages. A current interruption in a current fed converter induces a fast increase in the voltage across the semiconductor devices, higher than the breakdown voltage, causing the destruction of the power converter. In such a case, the power devices may enter in an avalanche mode, where the energy stored in the inductance is dissipated. Said devices are not capable of withstanding such high voltage and high current conditions for a prolonged period of time.While such overlapping is necessary to avoid voltage peaks, a reduction of the overlapping time is beneficial for the overall converter operation. In fact, too high of an overlapping time would lead to high Total Harmonic Distortion (THD) of the output current. Some software solutions can be implemented in the control loop to mitigate such side effects. In addition, the reduction of the overlapping time could reduce the losses in case of a CSC having a current bi-directionality feature, where control of two devices placed in series depends on the overlapping time. The longer the overlappingtime is, the longer is the conduction of one of the body diodes. Thus, the conduction losses increase because of the high forward voltage. The reduction of the overlapping time also creates a need to prevent an open circuit situation that could occur due to timing mismatches between the commands of the gate driver of the closing switching device, and the opening switching device.[MEANS TO SOLVE THE PROBLEM]

[0004] In view of the situation above, the method and device proposed in the present disclosure provides a way to prevent an open circuit situation downstream of an inductance of a current generator in a current fed converter, during commutation between upper switching devices of two or more half bridges of such converter, or between lower switching devices of said two or more half bridges of such converter, through detecting whether an upper or lower current conducting switching device is turned OFF, prior to turning ON another respective upper or lower switching device, and triggering a protection circuit that creates a conductive path at the poles of the current generator. This prevents overvoltage peaks due to a failures such as a false control signal, or a faulty gate driver.More precisely, the present disclosure proposes a control circuit for a current source converter, having a current generator including an inductance having two or more half bridges, each half bridge having an upper leg provided with an upper switching device and a lower leg provided with a lower switching device, said upper legs switching devices and said lower legs switching devices being controlled by a controller to provide an overlap between an upper leg turning OFF and an upper leg turning ON switching device, and to provide an overlap between a lower leg turning ON switchingdevice and a lower leg turning OFF switching device, through gate pull up and gate pull down pulse signals, to gate driver buffers of said switching devices, wherein said gate driver circuit includes: for each switching device: a gate current mirroring circuit on a sink branch of the gate driver buffer of such switching device, to provide a gate pull down detection signal from a turning OFF switching device, and a gate command connection path to provide a gate command signal, at least one logic circuit combining a gate command signal of a first upper or lower leg switching device, and a gate pull down signal of a respective second upper or lower leg switching device, to provide a first protection trigger signal, when said gate command signal of said first upper or lower leg switching device, and said gate pull down detection signal of said respective second upper or lower leg switching device correspond to both said first and second upper leg switching devices or both said first and second lower leg switching devices being OFF.The controller controls switching of the switching devices through gate pre-drivers, each having a gate buffer, said controller providing, through said gate pre-drivers, gate pull up and gate pull down pulse signals to the gates driver buffers. The controller is configured to create an overlapping time during switching transitions between switching devices of a first and a second half-bridge, wherein said gate buffers of said gate drivers are each provided with a current mirroring circuit on sink branches thereof, and a detection circuit configured for triggering a protection circuit, which includes a protection switch at poles of said current source converter. When a command signal or a driver buffer does not provide turning ON of a switch while a corresponding switch isturning OFF, the control circuit of the present disclosure creates a current path at the poles of the current generator to avoid overvoltage, such overvoltage being caused by energy stored in the inductance of the current generator.In a particular realization mode, said gate command signal of a first upper or lower leg switching device may be inverted and the inverted gate command signal combined with said gate pull down signal of said respective second upper or lower leg switching device in an AND gate to provide said protection trigger signal.Preferably, the control circuit may comprise OR gates to combine the protection trigger signals of the gate drivers of the upper switch devices and of the gate drivers of the lower switch devices of the current source converter.The gate command signal of each switching device may be taken after a pre driver providing galvanic isolation between the controller and the gate driver buffer of said switching device.Said gate current mirroring circuit of each switching device may provide said gate pull down detection signal from a turning OFF switching device through a galvanic isolation device.

[0005] The present disclosure also pertains to a current source converter that includes a control circuit according to any one of the aforementioned.

[0006] The use of gate mirroring circuits provides an accurate view of gate command signals without causing perturbations on the gate commands. The gate driver buffers provide a first galvanic isolation between said controller and said gate driver buffers.[EFFECTS OF THE INVENTION]

[0007] An object of the present disclosure is to provide a way to prevent an open circuit situation downstream of an inductance of a current generator in a current fed converter, during commutation between upper switching devices of two or more half bridges of such converter, or between lower switching devices of said two or more half bridges of such converter, through detecting whether an upper or lower current conducting switching device is turned OFF, prior to turning ON another respective upper or lower switching device, and triggering a protection circuit that creates a conductive path at the poles of the current generator.[Brief Description of Drawings]

[0008] A detailed description of exemplary embodiments disclosed will be discussed hereunder in reference to the attached drawings, where:FIG. 1 is a schematic view of a traditional single phase current source inverter.FIG. 2 is a schematic view of an example of detection circuit according to an embodiment of the present disclosure.FIG. 3 shows a complete control circuit of the present disclosure.FIG. 4 shows a schematic view of a traditional three phase current source inverter.[Description of the Embodiments]FIG. 1 is a schematic view of a DC / AC current source converter, also called an inverter. Such converter comprises a DC source 1 , an inductance 2, and two half bridges. A first half-bridge comprises first upper leg switch device 11 with IGBT QI and a diode 21, and first lower leg switch device 12 with IGBT Q2 and diode 22. A second half-bridge comprises second upper leg switch device 13 with IGBT Q3 and adiode 23, and second lower leg switch device 14 with IGBT Q4 and diode 24. The IGBT+ diode design shown may be replaced with serial opposite polarity IGBTs having reverse freewheeling diodes, or serial reverse polarity MOSFET having an inherent body diode, or with additional freewheeling diodes, as shown in circle A of FIG. 1.

[0009] The half-bridges of the current source converter are connected to an alternating voltage, and current load 4.The switches are controlled through gate drivers. A first gate driver 31 for the first half-bridge first upper leg switch device 11, a second gate driver 32 for the first halfbridge first lower switch device 12, and a third gate driver 33 for the second upper leg switch device 13 of the second half bridge and gate driver 34 for the second lower leg switch device 14 of the second half-bridge.

[0010] Starting from such basic schematics, the present disclosure concerns a driver circuit that aims at avoiding having open circuit situations, e.g. in case an overlap does not occur during switching transitions between the upper legs switching devices 11 and 13, or during switching transitions between lower leg switching devices 12 and 14, or in case a switch device does not turn ON due to a faulty gate driver. Such circuit shown in FIG. 2 uses a sink current mirror circuit 5 to sense the gate current on a sink side of a gate buffer 6, of a first upper or lower switching device. The detailed circuit of FIG. 2 shows a gate driver comprising a pre-driver 7 which provides galvanic isolation between the controller circuitry having a first supply VDD1, VS SI and a switch device circuitry comprising gate buffer 6 and having a second supply VDD2, VSS2. The gate buffer comprises push / pull transistors T1 and T2, and the sink current mirror circuit 5 isconnected between the collector of T2 and the negative voltage VSS2. In the sink current mirror circuit 5, the transistor T4 is in a diode configuration as its base and collector electrodes are shorted. The current flowing through the collector of T4, being the gate current during turn- OFF, generates a corresponding base-emitter voltage (VBE), which is the same VBE voltage for the transistor T6. Therefore, the current flowing through T6 will be the image of the gate current. The mirror resistor (RMOFF) should be less or equal to the overall gate resistance (Roiot) to obtain a current with the same amplitude. In the case of RMOFF > RGTOI, the maximal current is capped and is equal to ((VDD - Vss - [VcE]s t)) / RMOFF. The image imof the mirrored current after being conditioned and passed through galvanic isolation 8 is then transformed to a logic signal Im, which is as shown in FIG. 3 combined through an AND gate with the inverted gate command signal G of a second respective upper or lower switch device, with which a commutation with overlap is to be done.The logic signal Imis in the described example a logic ONE signal when the switching device passes from a current conducting state (ON state) to a current blocking state (OFF state).

[0011] Also shown on FIG. 2 is a detection line providing a signal representative of the command signal from the controller at the mixed output of the pre-driver 7, after resistors RON and ROFF. In the example, this signal, which is already a logic signal, goes through galvanic isolation 91, and is inverted in inverter 9 to provide the inverted gate command signal G~ of the corresponding switching device, which is a logic ONE when the gate command signal G is low, that corresponds to a switching device in an OFF state.

[0012] As shown on FIG. 3, the inverted gate command signal GAx of a first upper switch device X is added through an AND gate 10, with the gate current detection signal Imy of a second upper switch device Y. The inverted gate command signal G _y of the second upper switch device Y is added through an AND gate 10’, with the gate current detection signal Imx of the first upper switch device X. The aforementioned output signals of the two AND gates are input to an OR gate 20.

[0013] The same applies to the lower switches inverted gate command signal G^x and gate current detection signal which are combined in AND gates 10 and 10’, which have outputs thereof combined in a another OR gate 20. The signals that are output from the OR gate for the upper switches, and the signal output from the OR gate for the lower switches are in turn combined in a further OR gate 30 to turn ON a protection switch 100, which provides a short circuit at the poles of the current generator that include the source 1 and the inductor 2, when a switch which should turn ON remains OFF either in the upper legs or in the lower legs. Since this circuit concerns fault detection, a latch gate is positioned between the output of the OR gate 30 and the protection switch 100, to keep the protection active until a reset coming from the controller is sent to the latch gate.

[0014] The circuitry of FIG. 3 is used for the upper switch devices and lower switch devices, and may be used for the upper and lower switch devices of inverters having not only two half bridges, but also three half bridges, and a three-phase load 4’, as shown in FIG. 4, or more.

[0015] In FIG. 2, the transistors T4 and T6 are usually matched transistors, having the same gain (b) and sharing the same package. The transistors selected to design the current mirrors must have the same, or close characteristics as the ones in the buffer (current capability, gain-bandwidth product). The current mirror circuits are not limited to BJT components.

[0016] The mirrored current signal taken at the bottom of resistor RMOFF is injected into the detection circuit through the galvanic isolation device 8 and such insolation device may be, depending on the situation, a photo-coupler, a current transformer, a voltage transformer, or even a digital isolator. This is due to the fact that voltages VDD2XH, VSS2XH of the first upper leg of the first half-bridge switch element having gate XH, the voltages VoD2yH, Vss2yH of the first upper leg of the second half-bridge switch element having gate YI1, the voltages VDD2XL, VSS2XL of the first lower leg of the first half-bridge switch element having gate XL, and the voltages VoD2yL, Vss2yL of the second lower leg of the second half-bridge switch element having gate YL are not the same, and are also different from the logic voltages needed to control the protection device 100.

[0017] The signals Imtransferred through the isolation devices 8 and 8’ may be amplified or triggered in gate 81, having hysteresis to become a logic signal.

[0018] The invention of the present disclosure is not limited to the above description, and e.g. realization of logical circuits may be carried out using bipolar transistors, or MOS transistors. The positive logic described may be replaced by an inverted logic wherethe gate command signal G is combined with the inverted gate pull down detection signal, and as mentioned earlier, the control circuit may be adapted to a three phase output current source converter as per FIG. 4, with the use of adapted logic circuits such as three input AND gates and OR gates to combine the gate command signals, and gate pull down detection signals of three half-bridges.

[0019] Also, the present disclosure may be applied to DC / AC converters but also to AC / DC converters, the source and load being reversed.

[0020] In addition, the present invention may be combined with a circuit designed to reduce the overlap times in the transitions between the current source converter upper legs switches, or lower legs switches, such circuit using a source current mirror circuit similar to the sink current mirror depicted.[Reference Signs List]

[0021] 2... Inductance 5.. . Current Mirroring Circuit 6... Buffer 11, 13... UpperSwitching Device 12, 14...Lower Switching Device 20, 30...OR Gate40... Controller G ... Gate Command Signal G ... Inverted Gate Command Signal

Claims

[CLAIMS]

1. A control circuit for a current source converter, having a current generator comprising: an inductance having two or more half bridges, each half bridge having an upper leg provided with an upper switching device, and a lower leg provided with a lower switching device, said upper legs switching devices and said lower leg switching devices being controlled by a controller, to provide an overlap between an upper leg turning OFF and an upper leg turning ON switching device and to provide an overlap between a lower leg turning ON switching device and a lower leg turning OFF switching device through gate pull up and gate pull down pulse signals to gate driver buffers of said switching devices, characterized in that said gate driver circuit comprises: for each switching device: a gate current mirroring circuit on a sink branch of the gate driver buffer of such switching device to provide a gate pull down detection signal from a turning OFF switching device, a gate command connection path to provide a gate command signal, at least one logic circuit combining a gate command signal of a first upper or lower leg switching device and a gate pull down signal of a respective second upper or lower leg switching device, to provide a first protection trigger signal, when said gate command signal of said first upper or lower leg switching device, and said gate pull down detection signal of said respective second upper or lower leg switching device correspond to both said first and second upper leg switching devices or both said first and second lower leg switching devices being OFF.

2. The control circuit according to claim 1, wherein said gate command signal of a first upper or lower leg switching device is inverted, and the inverted gate command signal is combined with said gate pull down signal of said respective second upper, or lower leg switching device in an AND gate, to provide said protection trigger signal.

3. The control circuit according to claim 1 or 2 further comprising:OR gates to combine the protection trigger signals of the gate drivers of the upper switch devices, and of the gate drivers of the lower switch devices of the current source converter.

4. The control circuit according to any one of claims 1 to 3, wherein the gate command signal of each switching device is taken, after a pre-driver provides galvanic isolation between the controller and the gate driver buffer of said switching device.

5. The control circuit according to any one claims 1 to 4, wherein said gate current mirroring circuit of each switching device provides said gate pull down detection signal from a turning OFF switching device, through a galvanic isolation device.

6. The current source converter further comprising:a control circuit according to any one of claims 1 to 5.

7. A method for protecting a current source converter from open circuits in the current source path during switching transitions between upper legs half bridges each half bridge, having an upper leg provided with an upper switching device, and a lower leg provided with a lower switching device, said upper legs switching devices and said lower legs switching devices being controlled by a controller to provide an overlap between an upper leg turning off OFF and an upper leg turning ON switching device, and to provide an overlap between a lower leg turning ON switching device and a lower leg turning OFF switching device, through gate pull up and gate pull down pulse signals to gate driver buffers of said switching devices, characterized in that said gate driver circuit comprises: for each switching device: a gate current mirroring circuit on a sink branch of the gate driver buffer of such switching device to provide a gate pull down detection signal from a turning OFF switching device, a gate command connection path to provide a gate command signal, said method comprising: combining a gate command signal of a first upper or lower leg switching device and a gate pull down signal of a respective second upper or lower leg switching device to provide a first protection trigger signal, when said gate command signal of said first upper or lower leg switching device and said gate pull down detection signal of said respective second upper or lower leg switching device correspond to both said first and second upper leg switching devices, or both said first and second lower leg switching devices being OFF and,using said protection trigger signal to switch ON a load between the poles of the converter.

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