SPI system, SPI data writing method, and SPI data reading method

Abstract

The present invention provides an SPI system, comprising an SPI module, and at least one functional module. The SPI module is connected to an SPI master controller by means of an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line; and the functional module is connected to the SPI module. The present invention is suitable for application scenarios with long transmission links, and is also compatible with local applications with short transmission links, providing an ideal solution for SPI transmission.

Description

SPI interface system, SPI data writing method and SPI data reading method Technical Field

[0001] The present invention relates to the field of communication technology, in particular to encoding, decoding and transmission of physical layer data, and more particularly to an SPI interface system, an SPI data writing method and an SPI data reading method. Background Art

[0002] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus that only occupies four pins on the chip, saving chip pins and space on PCB layout. SPI typically has four signal lines: SPI_CSN, SPI_CK, SPI_MOSI, and SPI_MISO. The SPI master controller connects to the SPI interface module via these four signal lines. The SPI master controller is the SPI master device, and the SPI interface module is the SPI slave device. The SPI master controller drives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines, while the SPI interface module receives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines. The SPI interface module drives the SPI_MISO signal line, while the SPI master controller receives the SPI_MISO signal line. The SPI interface module receives and samples data on the SPI_MOSI line driven by the SPI master controller on the rising or falling edges of the SPI_CK line. The SPI master controller receives and samples data on the SPI_MISO line driven by the SPI interface module on the rising or falling edges of the SPI_CK line. In the SPI protocol, the SPI master controller drives the SPI_CK line and generates clock edges on the SPI_CK line. The SPI master controller and the SPI interface module sample data on the SPI_MISO and SPI_MOSI lines on the rising or falling edges of the SPI_CK line, enabling bidirectional data transmission between the SPI master controller and the SPI interface module. The SPI_CSN line is a select signal. In the SPI protocol, data transmission occurs only when the SPI_CSN line is low. An SPI master controller can connect to multiple SPI interface modules, meaning that an SPI master device can connect to multiple SPI slave devices. The SPI master controller and multiple SPI interface modules share the SPI_CK, SPI_MOSI, and SPI_MISO signal lines, but each SPI interface module has an independent SPI_CSN signal line input. When the SPI_CSN signal line of an SPI interface module is high, this SPI interface module does not drive the SPI_MISO signal line (the driver connected to the SPI_MISO signal line of this SPI interface module outputs a Hi-Z state). An SPI interface module only drives the SPI_MISO signal line when its SPI_CSN signal line is low. When an SPI master controller connects to multiple SPI interface modules, at any given time, only one SPI interface module's SPI_CSN signal line is low, thus preventing conflicts caused by multiple SPI interface modules driving the SPI_MISO signal line simultaneously.

[0003] When an SPI master controller is connected to only one SPI interface module, this SPI interface module can drive the SPI_MISO signal line at any time without causing conflict. In this case, there can be no SPI_CSN signal line between the SPI master controller and the SPI interface module. That is, when an SPI master controller is connected to only one SPI interface module, the SPI master controller and the SPI interface module can be connected only through the SPI_CK signal line, SPI_MOSI signal line and SPI_MISO signal line.

[0004] When transmitting data over long distances, the process typically involves sending a command packet and then receiving a feedback packet. The feedback packet contains information about the command's execution status and, in the case of a read command, may also contain the read data. The existing SPI protocol enables bidirectional data transmission between the SPI master controller and the SPI interface module by sampling the data on the SPI_MISO and SPI_MOSI lines at the rising or falling edges of the SPI_CK signal line. However, this type of data transmission can be considered a data stream and is unsuitable for long-distance data transmission. Currently, there is a lack of a solution for long-distance data transmission based on the existing SPI protocol and using SPI interface signals.

[0005] Summary of the Invention

[0006] In order to solve the problem that the SPI protocol in the prior art cannot perform long-distance transmission, an object of the present invention is to provide an SPI interface system, the SPI interface system comprising an SPI interface module and at least one functional module;

[0007] The SPI interface module is connected to the SPI main controller via the SPI_CK signal line, the SPI_MOSI signal line and the SPI_MISO signal line, and the functional module is connected to the SPI interface module.

[0008] Another object of the present invention is to provide an SPI data writing method, which uses an SPI interface system to write data, comprising:

[0009] The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module through the SPI_MOSI signal line, where the write command packet starts with a first identifier;

[0010] After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module sends the write command packet to the functional module;

[0011] The functional module receives the write command packet and executes the write command, and when the functional module completes the write command, returns a write status packet to the SPI interface module;

[0012] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0013] When the SPI interface module receives the write status packet, the SPI interface module sends the write feedback packet through the SPI_MISO signal line, where the write feedback packet starts with a second identifier and includes the status information included in the write status packet.

[0014] In a preferred embodiment, when the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet, the SPI interface module receives the write command packet.

[0015] In a preferred embodiment, the write command packet further includes a write command packet check code;

[0016] When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet and the write command packet check code is verified to be correct, the SPI interface module receives the write command packet.

[0017] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0018] When the SPI interface module does not receive the write status packet, the SPI interface module sends data that cannot be identified as the write feedback packet to the SPI master controller through the SPI_MISO signal line.

[0019] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0020] When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the write feedback packet is read through the SPI_MISO signal line.

[0021] The SPI interface module then sends a write feedback packet to the SPI master controller via the SPI_MISO signal line.

[0022] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line and sends the write command packet to the SPI interface module via the SPI_MOSI signal line.

[0023] The SPI master controller then generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. After the SPI interface module sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, which include write command packets and read command packets.

[0024] In a preferred embodiment, the write feedback packet is divided into a write success feedback packet and a write failure feedback packet;

[0025] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0026] When the SPI interface module receives the write status packet and the status information contained in the write status packet is success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, where the write success feedback packet starts with a third identifier;

[0027] When the SPI interface module receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, where the write failure feedback packet starts with a fourth identifier.

[0028] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0029] When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout and reads the write feedback packet through the SPI_MISO signal line, the SPI interface module sends the write failure feedback packet to the SPI master controller through the SPI_MISO signal line.

[0030] Another object of the present invention is to provide an SPI data reading method, which uses an SPI interface system to read data, comprising:

[0031] The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module through the SPI_MOSI signal line, where the read command packet starts with a fifth identifier;

[0032] After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module sends the read command packet to the functional module;

[0033] The functional module receives the read command packet and executes the read command, and when the functional module completes the read command, returns the read data packet to the SPI interface module;

[0034] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line.

[0035] When the SPI interface module receives the read data packet, the SPI interface module sends the read feedback packet through the SPI_MISO signal line, where the read feedback packet starts with a sixth identifier and includes the read data included in the read data packet.

[0036] In a preferred embodiment, when the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet, the SPI interface module receives the read command packet.

[0037] In a preferred embodiment, the read command packet further includes a read command packet check code;

[0038] When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet and the check code of the read command packet is verified to be correct, the SPI interface module receives the read command packet.

[0039] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line.

[0040] When the SPI interface module does not receive the read data packet, the SPI interface module sends data that cannot be identified as the read feedback packet to the SPI master controller through the SPI_MISO signal line.

[0041] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0042] When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the read feedback packet is read through the SPI_MISO signal line.

[0043] The SPI interface module then sends a read feedback packet to the SPI master controller via the SPI_MISO signal line.

[0044] In a preferred embodiment, the SPI master controller generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module via the SPI_MOSI signal line.

[0045] The SPI master controller then generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line. After the SPI interface module sends the read feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, which include read command packets and write command packets.

[0046] In a preferred embodiment, the read feedback packet is divided into a read success feedback packet and a read failure feedback packet;

[0047] The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line;

[0048] When the SPI interface module receives the read data packet and the status information contained in the read data packet is success, the SPI interface module sends the read success feedback packet through the SPI_MISO signal line, where the read success feedback packet starts with the seventh identifier;

[0049] When the SPI interface module receives the read data packet and the status information contained in the read data packet is failure, the SPI interface module sends the read failure feedback packet through the SPI_MISO signal line, where the read failure feedback packet starts with an eighth identifier.

[0050] In a preferred embodiment, the SPI interface module includes a timeout timer;

[0051] When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout and reads the read feedback packet through the SPI_MISO signal line, the SPI interface module sends the read failure feedback packet to the SPI master controller through the SPI_MISO signal line.

[0052] The present invention provides an SPI interface system, an SPI data writing method, and an SPI data reading method, which are suitable for application scenarios with long transmission links and are also compatible with local applications with short transmission links, providing an ideal solution for SPI transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] FIG1 schematically shows a structural block diagram of an SPI interface system of the present invention.

[0055] FIG2 is a schematic diagram of the data structure of a write command packet of the present invention.

[0056] FIG3 is a timing diagram of an SPI data writing method according to an embodiment of the present invention.

[0057] FIG4 is a timing diagram of an SPI data writing method in an embodiment of the present invention with an SPI_CSN signal line.

[0058] FIG5 is a timing diagram of an SPI data writing method in another embodiment of the present invention with an SPI_CSN signal line.

[0059] FIG6 is a timing diagram of an SPI data writing method according to a second embodiment of the present invention.

[0060] FIG7 is a timing diagram of an SPI data writing method in a third embodiment of the present invention.

[0061] FIG8 is a timing diagram of an SPI data writing method in a fourth embodiment of the present invention.

[0062] FIG9 is a timing diagram of an SPI data writing method in a fifth embodiment of the present invention.

[0063] FIG10 is a timing diagram of an SPI data writing method in a sixth embodiment of the present invention.

[0064] FIG11 is a timing diagram of an SPI data writing method in the seventh embodiment of the present invention.

[0065] FIG12 is a schematic diagram of the data structure of a read command packet of the present invention.

[0066] FIG13 is a timing diagram of an SPI data reading method in the eighth embodiment of the present invention.

[0067] FIG. 14 is a timing diagram of an SPI data reading method in a ninth embodiment of the present invention.

[0068] FIG15 is a timing diagram of an SPI data reading method in the tenth embodiment of the present invention.

[0069] FIG16 is a timing diagram of an SPI data reading method in the eleventh embodiment of the present invention.

[0070] FIG17 is a timing diagram of an SPI data reading method in the twelfth embodiment of the present invention.

[0071] FIG18 is a timing diagram of an SPI data reading method in the thirteenth embodiment of the present invention.

[0072] The meanings of the text symbols in the above drawings are as follows: 100: SPI master controller 100; 200: SPI interface module 200; SPI: functional module 300; SPI_CK: SPI_CK signal line; SPI_MOSI: SPI_MOSI signal line; SPI_MISO: SPI_MISO signal line; SPI_CSN: SPI_CSN signal line. DETAILED DESCRIPTION

[0073] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0074] As shown in FIG1 , according to an embodiment of the present invention, there is provided an SPI interface system including an SPI master controller 100 , an SPI interface module 200 , and at least one functional module 300 .

[0075] The SPI interface module 200 is connected to the SPI master controller 100 via the SPI_CK signal line, the SPI_MOSI signal line, and the SPI_MISO signal line. The functional module 300 is connected to the SPI interface module 200 .

[0076] The SPI interface module 200 can be connected to multiple functional modules 300 , such as functional module 1, . . . , functional module N. In this embodiment, the SPI interface module 200 is connected to one functional module 300 as an example for description.

[0077] The SPI master controller 100 is an SPI master device, and the SPI interface module 200 is an SPI slave device. The SPI master controller 100 drives the SPI_CK signal line and the SPI_MOSI signal line, and the SPI interface module 200 receives the SPI_CK signal line and the SPI_MOSI signal line. The SPI interface module 200 drives the SPI_MISO signal line, and the SPI master controller 100 receives the SPI_MISO signal line.

[0078] The present invention does not limit the connection method between the SPI interface module 200 and the functional module 300. The SPI interface module 200 can be connected to one or more functional modules 300 through one or more transmission lines. At the same time, the present invention does not limit the location of the SPI interface module 200 and the functional module 300. The SPI interface module 200 and the functional module 300 can be located in the same integrated circuit chip, or in different integrated circuit chips on a PCB board, or the SPI interface module 200 and the functional module 300 can also be located in different system devices.

[0079] SPI data writing method

[0080] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line, where the write command packet starts with a first identifier;

[0081] After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300;

[0082] The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200.

[0083] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line.

[0084] When the SPI interface module 200 receives the write status packet, the SPI interface module 200 sends the write feedback packet through the SPI_MISO signal line. The write feedback packet starts with a second identifier and includes the status information included in the write status packet.

[0085] As shown in FIG2 , four embodiments of write command packets are given:

[0086] The write command packet may include a first identifier and a write command data field, and start with the first identifier.

[0087] The write command packet may also include a first identifier, a write command length field, and a write command data field, and start with the first identifier.

[0088] The write command packet may also include a first identifier, a write command data field, and a write command check code, and start with the first identifier.

[0089] The write command packet may also include a first identifier, a write command length field, a write command data field, and a write command check code, and start with the first identifier.

[0090] The first identifier, write command length field (if any), write command data field, and write command check code (if any) contained in the write command packet are composed of a binary bit sequence. The present invention does not limit the length of the binary bit sequence of the first identifier, write command length field (if any), write command data field, and write command check code (if any).

[0091] It should be noted that the present invention does not limit the format of the write command packet, that is, the write command packet format in the present invention is not limited to the four write command packet embodiments shown in Figure 2. The SPI master controller 100 and the SPI interface module 200 can agree on other write command packet formats.

[0092] In the present invention, the SPI interface module 200 receiving the write command packet means that the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the write command packet. In the present invention, the data received by the SPI interface module 200 from the SPI_MOSI signal line reaching the length of the write command packet means that the SPI interface module 200 has received a complete write command packet. As shown in FIG2 , the write command packet may include a write command length field. The SPI interface module 200 may determine whether the received data reaches the length of the write command packet based on the write command length field (or partially based on the write command length field) according to an agreement between the SPI interface module 200 and the SPI master controller 100, that is, whether a complete write command packet has been received. As shown in FIG2 , the write command packet may not include the write command length field. In this case, the SPI interface module 200 determines whether the received data reaches the length of the write command packet based on the agreement between the SPI interface module 200 and the SPI master controller 100 (this agreement is not based on the write command length field), that is, whether a complete write command packet has been received.

[0093] When a write command packet includes a write command packet check code, the SPI interface module 200 receives the write command packet when the data received from the SPI_MOSI signal line reaches the length of the write command packet and the write command packet check code is verified to be correct. The present invention does not limit the type of write command packet check code. The SPI interface module 200 can agree on a write command packet check code with the SPI master controller 100, such as using a common CRC code as the write command packet check code. In the present invention, the write command packet check code can be an error detection code and an error correction code. The error detection code only has error detection capabilities, such as a CRC code, while the error correction code can both correct and detect errors.

[0094] The SPI master controller 100 drives the SPI_CK signal line, generates a clock edge on the SPI_CK signal line, and samples the data on the SPI_MISO signal line at the rising or falling edge of the clock on the SPI_CK signal line. The SPI interface module 200 samples the data on the SPI_MOSI signal line at the rising or falling edge of the clock on the SPI_CK signal line, thereby realizing bidirectional data transmission between the SPI master controller 100 and the SPI interface module 200.

[0095] The present invention is not limited to sampling data on the SPI_MISO and SPI_MOSI signal lines at the rising or falling edge of the SPI_CK signal line. In the embodiments of the present invention described below, data on the SPI_MISO and SPI_MOSI signal lines are sampled at the rising edge of the SPI_CK signal line. That is, in the embodiments of the present invention described below, the rising edge of the SPI_CK signal line serves as the sampling clock edge. In other embodiments of the present invention, data on the SPI_MISO and SPI_MOSI signal lines may also be sampled at the falling edge of the SPI_CK signal line. That is, in these embodiments, the falling edge of the SPI_CK signal line serves as the sampling clock edge.

[0096] As shown in FIG3 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time, and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. The write command packet contains N bytes, each byte is 8-bit binary data, the first byte is the first identifier, and the 8-bit binary data of the first byte is C 10 、C 11 …C 17 Indicates that the Nth byte of the write command packet is the last byte of the write command packet, and the 8-bit binary data of the Nth byte of the write command packet is in C N0 、C N1 …C N7 express.

[0097] The SPI interface module 200 samples the data on the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line, receives the write command packet from the SPI_MOSI signal line, and N7 After the SPI_MOSI signal line receives the data, the data received from the SPI_MOSI signal line reaches the length of the write command packet, and the SPI interface module 200 receives the write command packet.

[0098] After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. In the present invention, when the SPI interface module 200 sends the write command packet to the functional module 300, the content in the write command packet may be modified, added, or deleted, and the present invention does not impose any restrictions or regulations on this.

[0099] The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200.

[0100] At moment ①, the SPI interface module 200 receives a write status packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 drives the SPI_MISO signal line, and sends a write feedback packet through the SPI_MISO signal line. The SPI master controller 100 samples the data on the SPI_MISO signal line at the rising edge of the clock on the SPI_CK signal line and reads the write feedback packet. The write feedback packet starts with a second identifier and includes status information included in the write status packet. The status information included in the write status packet may be write success, write failure, or other status information.

[0101] The write feedback packet contains M bytes, each byte is 8-bit binary data, the first byte is the second identifier, and the 8-bit binary data of the first byte is A 10 、A 11 …A 17 Indicates that the Mth byte of the write feedback packet is the last byte of the write feedback packet, and the 8-bit binary data of the Mth byte of the write feedback packet is in A M0 、A M1 …A M7 express.

[0102] For ease of understanding, in the embodiment shown in FIG. 3 and in the following description of the present invention, each byte is described as 8-bit binary data. However, the present invention does not limit the number of bits of each byte, and each byte may also have other numbers of bits.

[0103] In the embodiment shown in FIG3 , the length of the first identifier and the second identifier is one byte, and the length of the write command packet and the write feedback packet is an integer multiple of a byte. For ease of understanding, in the following description of the present invention, the length of the first to eighth identifiers is one byte, and the length of the write command packet, the read command packet, the write feedback packet (including a write success feedback packet and a write failure feedback packet), and the read feedback packet (including a read success feedback packet and a read failure feedback packet) is an integer multiple of a byte. However, the present invention does not limit the length of the first to eighth identifiers to one byte, nor does it limit the length of the first to eighth identifiers to an integer multiple of a byte. The present invention also does not limit the length of the write command packet, the read command packet, the write feedback packet (including a write success feedback packet and a write failure feedback packet), and the read feedback packet (including a read success feedback packet and a read failure feedback packet) to an integer multiple of a byte.

[0104] During the interval marked as "no clock edge," the SPI master controller 100 does not generate a sampling clock edge on the SPI_CK signal line. In FIG. 3 and the subsequent embodiments of the present invention, the levels of the SPI_MOSI and SPI_MISO signal lines remain unchanged during the "no clock edge" interval. The present invention is not limited to the levels of the SPI_MOSI and SPI_MISO signal lines during the "no clock edge" interval. The levels of the SPI_MOSI and SPI_MISO signal lines may also change during the "no clock edge" interval. However, because data on the SPI_MOSI and SPI_MISO signal lines is sampled only on the sampling clock edge of the SPI_CK signal line (the sub-sampling clock edge in the embodiment shown in FIG. 3 is the rising clock edge), level changes on the SPI_MOSI and SPI_MISO signal lines during the "no clock edge" interval will not be sampled and received.

[0105] In the embodiment shown in FIG3 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and simultaneously drives the SPI_MOSI signal line. When sending a write command packet via the SPI_MOSI signal line, the SPI interface module 200 does not have a write feedback packet to send. At this time, the SPI interface module 200 drives the SPI_MISO signal line high. During this period, the SPI interface module 200 of the present invention may also drive the SPI_MISO signal line low or a varying level. However, the SPI interface module 200 must ensure that the level value or varying level value driven on the SPI_MISO signal line is not recognized as a second identifier if sampled by the SPI master controller 100 on the sampling clock edge of the SPI_CK signal line (in the embodiment shown in FIG3 , the sub-sampling clock edge is the rising clock edge). Taking the embodiment shown in FIG3 as an example, since the SPI interface module 200 drives the SPI_MISO signal line high (sampled as continuous binary bits 1) during this period, in order to avoid being recognized as a second identifier, the value of the second identifier should not be 0xFF.

[0106] In the embodiment shown in FIG3 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and the SPI interface module 200 drives the SPI_MISO signal line. When sending a write feedback packet via the SPI_MISO signal line, the SPI master controller 100 does not have a write command packet to send. During this period, the SPI master controller 100 of the present invention may also drive the SPI_MOSI signal line to a low level or a varying level. However, the SPI master controller 100 must ensure that the level value or varying level value driven on the SPI_MOSI signal line is not recognized as a first identifier if sampled by the SPI interface module 200 on the sampling clock edge of the SPI_CK signal line (in the embodiment shown in FIG3 , the sub-sampling clock edge is the rising clock edge). Taking the embodiment shown in FIG3 as an example, since the SPI master controller 100 drives the SPI_MOSI signal line to a high level (sampling continuous binary bits 1) during this period, in order to avoid being recognized as a first identifier, the value of the first identifier should not be 0xFF.

[0107] In addition to the SPI_CK, SPI_MOSI, and SPI_MISO signal lines, the SPI interface module 200 can also connect to the SPI master controller 100 via the SPI_CSN signal line. The SPI master controller 100 drives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines, while the SPI interface module 200 receives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines. The SPI interface module 200 drives the SPI_MISO signal line, while the SPI master controller 100 receives the SPI_MISO signal line. The SPI_CSN signal line is a select signal. In the SPI protocol, data transmission occurs only when the SPI_CSN signal line is low. An SPI master controller 100 can be connected to multiple SPI interface modules 200. The SPI master controller 100 and multiple SPI interface modules 200 share the SPI_CK, SPI_MOSI, and SPI_MISO signal lines. However, each SPI interface module 200 has an independent SPI_CSN signal line input. When the SPI_CSN signal line of an SPI interface module 200 is high, this SPI interface module 200 does not drive the SPI_MISO signal line (the driver connected to the SPI_MISO signal line of this SPI interface module 200 outputs a Hi-Z state). An SPI interface module 200 only drives the SPI_MISO signal line when its SPI_CSN signal line is low. When an SPI master controller 100 is connected to multiple SPI interface modules 200, at any given time, only one SPI interface module 200 has its SPI_CSN signal line low, thereby preventing conflicts caused by multiple SPI interface modules 200 driving the SPI_MISO signal line simultaneously.

[0108] When an SPI master controller 100 is connected to only one SPI interface module 200, the SPI interface module 200 can drive the SPI_MISO signal line at any time without causing any conflict. In this case, there may be no SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200. That is, when an SPI master controller 100 is connected to only one SPI interface module 200, the SPI master controller 100 and the SPI interface module 200 may be connected only through the SPI_CK signal line, the SPI_MOSI signal line, and the SPI_MISO signal line. This is the case in the above description of the embodiment shown in FIG. 3 .

[0109] As shown in FIG4 , an embodiment in which an SPI_CSN signal line exists between the SPI master controller 100 and the SPI interface module 200 is provided. The embodiment shown in FIG4 describes the same process as the embodiment shown in FIG3 , that is, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After the SPI interface module 200 receives the write command packet from the SPI_MOSI signal line, it sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it sends a write command packet to the SPI interface module 200. Block 200 returns a write status packet. At time ①, the SPI interface module 200 receives the write status packet. The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 via the SPI_MISO signal line. The SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_CSN signal line low before sending a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After reading the write feedback packet sent by the SPI interface module 200 via the SPI_MISO signal line, the SPI_CSN signal line is driven high. During the "no clock edge" period, the SPI_CSN signal line remains low.

[0110] As shown in FIG5 , another embodiment is provided in which an SPI_CSN signal line exists between the SPI master controller 100 and the SPI interface module 200. The embodiment shown in FIG5 describes the same process as the embodiment shown in FIG3 , namely, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After the SPI interface module 200 receives the write command packet from the SPI_MOSI signal line, it sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. After completing the write command, the functional module 300 returns a write status packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the write status packet and the SPI master controller 100 generates a clock edge on the SPI_CK signal line. The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet from the SPI interface module 200 through the SPI_MISO signal line. The SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_CSN signal line low before sending the write command packet to the SPI interface module 200 through the SPI_MOSI signal line. During the "no clock edge" period after sending the write command packet, the SPI master controller 100 drives the SPI_CSN signal line high. The SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_CSN signal line low before reading the write feedback packet sent by the SPI interface module 200 through the SPI_MISO signal line. After reading the write feedback packet sent by the SPI interface module 200 through the SPI_MISO signal line, the SPI_CSN signal line is driven high.

[0111] When an SPI master controller 100 is connected to only one SPI interface module 200, there may not be an SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200. This is the case described above with respect to the embodiment shown in FIG3 . FIG4 and FIG5 describe an embodiment, based on the embodiment shown in FIG3 , in which an SPI_CSN signal line is also present between the SPI master controller 100 and the SPI interface module 200. The following description of the present invention only describes the case in which there is no SPI_CSN signal line between the SPI master controller 100 and the SPI interface module 200. Based on the embodiments shown in FIG4 and FIG5 , the present invention can be easily expanded to the case in which an SPI_CSN signal line is present between the SPI master controller 100 and the SPI interface module 200. The following description of the present invention does not further describe the case in which an SPI_CSN signal line is present between the SPI master controller 100 and the SPI interface module 200. Whether or not an SPI_CSN signal line is present between the SPI master controller 100 and the SPI interface module 200 falls within the scope of protection of the present invention.

[0112] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module 200 does not receive the write status packet, the SPI interface module 200 sends data that cannot be identified as the write feedback packet to the SPI master controller 100 through the SPI_MISO signal line.

[0113] Taking FIG6 as an example, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. After the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At time ③, the SPI interface module 200 receives the write status packet. Before time ③ when the SPI interface module 200 receives the write status packet, between time ① and time ②, the SPI master controller 100 generates a clock edge on the SPI_CK signal line. In the embodiment shown in FIG6 , the SPI interface module 200 drives The SPI_MISO signal line is driven high. During this period, the SPI interface module 200 may also drive the SPI_MISO signal line to a low level or a varying level. However, the SPI interface module 200 should ensure that the level value driven or the varying level value on the SPI_MISO signal line is not recognized as the second identifier if it is sampled by the SPI master controller 100 on the sampling clock edge on the SPI_CK signal line (the sampling clock edge is the rising clock edge in the embodiment shown in FIG3 ). That is, when the SPI interface module 200 does not receive the write status packet, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 sends data that cannot be recognized as the write feedback packet to the SPI master controller 100 via the SPI_MISO signal line. At time ③, after the SPI interface module 200 receives the write status packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet from the SPI interface module 200 via the SPI_MISO signal line.

[0114] In the embodiment shown in FIG7 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. After completing the write command, the functional module 300 returns a write status packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the write status packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and reads a write feedback packet from the SPI interface module 200 via the SPI_MISO signal line. At moment ②, the SPI master controller 100 completes reading the write feedback packet, and the SPI interface module 200 completes sending the write feedback packet. The SPI master controller 100 continues to generate a clock edge on the SPI_CK signal line. At this time, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 may also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200 should ensure that the level value driven or the changing level value on the SPI_MISO signal line is not recognized as the second identifier if it is sampled by the SPI master controller 100 on the sampling clock edge on the SPI_CK signal line (the sampling clock edge is the rising clock edge in the embodiment shown in FIG. 3 ).

[0115] The SPI interface module 200 may further include a timeout timer; the timeout timer starts timing when a write command packet is received or sent to the functional module 300, or starts timing at a preset time after receiving the write command packet. If the SPI interface module 200 does not receive the write status packet before the timeout, after the timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line, the SPI interface module 200 sends a write feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The write feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include write command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0116] In the present invention, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends the write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. Then, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. Before the SPI master controller 100 reads the write feedback packet, if the SPI master controller 100 drives the SPI_MOSI signal line to send a command packet (including a write command packet and a read command packet described below in the present invention), the SPI interface module 200 does not receive the command packet sent before the SPI master controller 100 reads the write feedback packet. After the SPI master controller 100 reads the write feedback packet, that is, after the SPI interface module 200 sends the write feedback packet through the SPI_MISO signal line, the SPI interface module 200 can continue to receive subsequent command packets, which include a write command packet and a read command packet described below in the present invention.

[0117] In the present invention, the write feedback packet can be divided into a write success feedback packet and a write failure feedback packet. The SPI master controller 100 generates a clock edge on the SPI_CK signal line. When reading the write feedback packet through the SPI_MISO signal line, if the SPI interface module 200 receives the write status packet and the status information contained in the write status packet is success, the SPI interface module 200 sends the write success feedback packet through the SPI_MISO signal line, and the write success feedback packet starts with a third identifier. If the SPI interface module 200 receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module 200 sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet starts with a fourth identifier.

[0118] As shown in Figure 8, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 through the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. When the functional module 300 completes the write command, it returns a write status packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is success. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 through the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write success feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The write success feedback packet begins with a third identifier.

[0119] As shown in Figure 10, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. After completing the write command, the functional module 300 returns a write status packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is failure. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 via the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write failure feedback packet to the SPI master controller 100 via the SPI_MISO signal line. The write failure feedback packet begins with the fourth identifier.

[0120] In the present invention, the third identifier is different from the fourth identifier. When the SPI master controller 100 reads a write feedback packet, it can determine whether the read write success feedback packet or the write failure feedback packet is a write success feedback packet or a write failure feedback packet based on whether the write feedback packet starts with the third identifier or the fourth identifier. Therefore, the write success feedback packet can only include the third identifier, and the write failure feedback packet can only include the fourth identifier, so that the SPI master controller 100 can distinguish whether the read write feedback packet is a write success feedback packet or a write failure feedback packet.

[0121] As shown in FIG9 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. After completing the write command, the functional module 300 returns a write status packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is success. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 via the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write success feedback packet to the SPI master controller 100 via the SPI_MISO signal line. The write success feedback packet only includes the third identifier.

[0122] As shown in Figure 11, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a write command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the write command packet to the functional module 300. The functional module 300 receives the write command packet and executes the write command. After completing the write command, the functional module 300 returns a write status packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the write status packet, and the status information included in the write status packet is failure. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a write feedback packet from the SPI interface module 200 via the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a write failure feedback packet to the SPI master controller 100 via the SPI_MISO signal line. The write failure feedback packet only includes the fourth identifier.

[0123] The SPI interface module 200 may further include a timeout timer, which starts timing when a write command packet is received or sent to the functional module 300, or starts timing at a preset time after receiving the write command packet. When the SPI interface module 200 does not receive the write status packet before the timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line after the timeout, the write feedback packet is read through the SPI_MISO signal line, and the SPI interface module 200 sends a write failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The write feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include write command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0124] SPI data reading method

[0125] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module 200 via the SPI_MOSI signal line, where the read command packet starts with a fifth identifier;

[0126] After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300;

[0127] The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200.

[0128] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line.

[0129] When the SPI interface module 200 receives the read data packet, the SPI interface module 200 sends the read feedback packet through the SPI_MISO signal line. The read feedback packet starts with the sixth identifier and includes the read data included in the read data packet.

[0130] As shown in FIG12 , four embodiments of read command packets are given:

[0131] The read command packet may include a fifth identifier and a read command data field, and start with the fifth identifier.

[0132] The read command packet may also include a fifth identifier, a read command length field, and a read command data field, and start with the fifth identifier.

[0133] The read command packet may also include a fifth identifier, a read command data field, and a read command check code, and start with the fifth identifier.

[0134] The read command packet may also include a fifth identifier, a read command length field, a read command data field, and a read command check code, and start with the fifth identifier.

[0135] The fifth identifier, read command length field (if any), read command data field, and read command check code (if any) contained in the read command packet are composed of a binary bit sequence. The present invention does not limit the length of the binary bit sequence of the fifth identifier, read command length field (if any), read command data field, and read command check code (if any).

[0136] It should be noted that the present invention does not limit the format of the read command packet, that is, the read command packet format in the present invention is not limited to the four read command packet embodiments shown in Figure 12. The SPI master controller 100 and the SPI interface module 200 can agree on other read command packet formats.

[0137] In the present invention, the SPI interface module 200 receiving the read command packet means that the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the read command packet. In the present invention, the data received by the SPI interface module 200 from the SPI_MOSI signal line reaching the length of the read command packet means that the SPI interface module 200 has received a complete read command packet. As shown in FIG12 , the read command packet may include a read command length field. The SPI interface module 200 may determine whether the received data reaches the length of the read command packet based on the read command length field (or partially based on the read command length field) according to an agreement between the SPI interface module 200 and the SPI master controller 100, that is, whether a complete read command packet has been received. As shown in FIG12 , the read command packet may also not include the read command length field. In this case, the SPI interface module 200 determines whether the received data reaches the length of the read command packet based on the agreement between the SPI interface module 200 and the SPI master controller 100 (this agreement is not based on the read command length field), that is, whether a complete read command packet has been received.

[0138] When the read command packet includes a read command packet check code, when the data received by the SPI interface module 200 from the SPI_MOSI signal line reaches the length of the read command packet and the read command packet check code is verified to be correct, the SPI interface module 200 receives the read command packet. The present invention does not limit the type of read command packet check code. The SPI interface module 200 can agree on a read command packet check code with the SPI master controller 100, such as using a common CRC code as the read command packet check code. In the present invention, the read command packet check code can be an error detection code and an error correction code. The error detection code only has error detection capabilities, such as a CRC code, while the error correction code can both correct and detect errors.

[0139] As shown in FIG13 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and drives the SPI_MOSI signal line at the same time, and sends a read command packet to the SPI interface module 200 via the SPI_MOSI signal line. The read command packet contains N bytes, each byte is 8-bit binary data, the first byte is the fifth identifier, and the 8-bit binary data of the first byte is C 10 、C 11 …C 17 Indicates that the Nth byte of the read command packet is the last byte of the read command packet, and the 8-bit binary data of the Nth byte of the read command packet is in C N0 、C N1 …C N7 express.

[0140] The SPI interface module 200 samples the data on the SPI_MOSI signal line at the rising edge of the clock on the SPI_CK signal line, and receives a read command packet from the SPI_MOSI signal line. N7 bits later, the data received from the SPI_MOSI signal line reaches the length of the read command packet, and the SPI interface module 200 receives the read command packet.

[0141] After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. In the present invention, when the SPI interface module 200 sends the read command packet to the functional module 300, the content in the read command packet may be modified, added, or deleted, and the present invention does not impose any restrictions or regulations on this.

[0142] The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200.

[0143] At moment ①, the SPI interface module 200 receives a read data packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 drives the SPI_MISO signal line, and sends a read feedback packet through the SPI_MISO signal line. The SPI master controller 100 samples the data on the SPI_MISO signal line at the rising edge of the clock on the SPI_CK signal line and reads the read feedback packet, which starts with the sixth identifier and contains the read data contained in the read data packet.

[0144] The read data includes data read from the functional module 300, or read status information generated by the functional module 300 executing a read command, or both data read from the functional module 300 and read status information generated by the functional module 300 executing a read command. The read status information can be read success, read failure, or other status information.

[0145] The read feedback packet contains M bytes, each byte is 8-bit binary data, the first byte is the sixth identifier, and the 8-bit binary data of the first byte is A 10 、A 11 …A 17 Indicates that the Mth byte of the read feedback packet is the last byte of the read feedback packet, and the 8-bit binary data of the Mth byte of the read feedback packet is in A M0 、A M1 …A M7 express.

[0146] In the embodiment shown in FIG13 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and simultaneously drives the SPI_MOSI signal line. When sending a read command packet via the SPI_MOSI signal line, the SPI interface module 200 does not need to send a read feedback packet. During this period, the SPI interface module 200 of the present invention may also drive the SPI_MISO signal line to a low level or a varying level. However, the SPI interface module 200 must ensure that the level or varying level it drives on the SPI_MISO signal line is not recognized as the sixth identifier if sampled by the SPI master controller 100 on the sampling clock edge of the SPI_CK signal line (in the embodiment shown in FIG13 , the sub-sampling clock edge is the rising clock edge). Taking the embodiment shown in FIG13 as an example, since the SPI interface module 200 drives the SPI_MISO signal line high (sampling continuous binary bits 1) during this period, in order to avoid being recognized as the sixth identifier, the value of the sixth identifier should not be 0xFF.

[0147] In the embodiment shown in FIG13 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and the SPI interface module 200 drives the SPI_MISO signal line. When sending a read feedback packet via the SPI_MISO signal line, the SPI master controller 100 does not have a read command packet to send. During this period, the SPI master controller 100 of the present invention may also drive the SPI_MOSI signal line to a low level or a varying level. However, the SPI master controller 100 must ensure that the level or varying level it drives on the SPI_MOSI signal line is not recognized as the fifth identifier if it is sampled by the SPI interface module 200 on the sampling clock edge of the SPI_CK signal line (in the embodiment shown in FIG13 , the sub-sampling clock edge is the rising clock edge). Taking the embodiment shown in FIG13 as an example, since the SPI master controller 100 drives the SPI_MOSI signal line high (sampling continuous binary bits 1) during this period, in order to avoid being recognized as the fifth identifier, the value of the fifth identifier should not be 0xFF.

[0148] The SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line. When the SPI interface module 200 does not receive the read data packet, the SPI interface module 200 sends data that cannot be identified as the read feedback packet to the SPI master controller 100 through the SPI_MISO signal line.

[0149] Taking FIG. 14 as an example, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. After the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200. At time ③, the SPI interface module 200 receives the read data packet. Before time ③ when the SPI interface module 200 receives the read data packet, between time ① and time ②, the SPI master controller 100 generates a clock edge on the SPI_CK signal line. In the embodiment shown in FIG14 , the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 may also drive the SPI_MISO signal line to a low level or a varying level. However, the SPI interface module 200 must ensure that the level value or varying level value driven on the SPI_MISO signal line is not recognized as the sixth identifier if sampled by the SPI master controller 100 on the sampling clock edge on the SPI_CK signal line (the sampling clock edge is the rising clock edge in the embodiment shown in FIG14 ). That is, when the SPI interface module 200 does not receive the read data packet, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line, the SPI interface module 200 transmits data that cannot be recognized as the read feedback packet to the SPI master controller 100 via the SPI_MISO signal line. At time ③, after the SPI interface module 200 receives the read data packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet from the SPI interface module 200 via the SPI_MISO signal line.

[0150] In the embodiment shown in FIG15 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. After the functional module 300 completes the read command, it returns a read data packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the read data packet, the SPI master controller 100 generates a clock edge on the SPI_CK signal line, and reads a read feedback packet from the SPI interface module 200 via the SPI_MISO signal line. At moment ②, the SPI master controller 100 completes reading the read feedback packet, and the SPI interface module 200 completes sending the read feedback packet. The SPI master controller 100 continues to generate a clock edge on the SPI_CK signal line. At this time, the SPI interface module 200 drives the SPI_MISO signal line to a high level. During this period, the SPI interface module 200 may also drive the SPI_MISO signal line to a low level or a changing level. However, the SPI interface module 200 should ensure that the level value driven or the changing level value on the SPI_MISO signal line is not recognized as the sixth identifier if it is sampled by the SPI master controller 100 on the sampling clock edge on the SPI_CK signal line (the sampling clock edge is the rising clock edge in the embodiment shown in FIG. 15 ).

[0151] The SPI interface module 200 may further include a timeout timer; the timeout timer starts timing when a read command packet is received or sent to the functional module 300, or starts timing at a preset time after receiving the read command packet. If the SPI interface module 200 does not receive the read data packet before the timeout, after the timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line, the SPI interface module 200 sends the read feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The read feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include read command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0152] In the present invention, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends the read command packet to the SPI interface module 200 through the SPI_MOSI signal line. After the SPI interface module 200 receives the read command packet from the SPI_MOSI signal line, it sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns the read data packet to the SPI interface module 200. Then, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends the read command packet to the SPI interface module 200 through the SPI_MISO signal line. Read the read feedback packet. Before the SPI master controller 100 reads the read feedback packet, if the SPI master controller 100 drives the SPI_MOSI signal line to send a command packet (including a read command packet and a write command packet), the SPI interface module 200 does not receive the command packet sent before the SPI master controller 100 reads the read feedback packet. After the SPI master controller 100 reads the read feedback packet, that is, after the SPI interface module 200 sends the read feedback packet through the SPI_MISO signal line, the SPI interface module 200 can continue to receive subsequent command packets, which include a read command packet and a write command packet.

[0153] In the present invention, the read feedback packet can be divided into a read success feedback packet and a read failure feedback packet. The SPI master controller 100 generates a clock edge on the SPI_CK signal line. When reading the read feedback packet through the SPI_MISO signal line, if the SPI interface module 200 receives the read data packet and the status information contained in the read data packet is success, the SPI interface module 200 sends the read success feedback packet through the SPI_MISO signal line, and the read success feedback packet starts with the seventh identifier. If the SPI interface module 200 receives the read data packet and the status information contained in the read data packet is failure, the SPI interface module 200 sends the read failure feedback packet through the SPI_MISO signal line, and the read failure feedback packet starts with the eighth identifier.

[0154] As shown in FIG16 , the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. After the functional module 300 completes the read command, it returns a read data packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the read data packet, and the status information included in the read data packet is success. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a read feedback packet from the SPI interface module 200 via the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line and sends a read success feedback packet to the SPI master controller 100 via the SPI_MISO signal line. The read success feedback packet begins with the seventh identifier.

[0155] As shown in Figure 17, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. After the functional module 300 completes the read command, it returns a read data packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the read data packet containing the status information "failure". When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a read feedback packet from the SPI interface module 200 via the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line and sends a read failure feedback packet to the SPI master controller 100 via the SPI_MISO signal line. The read failure feedback packet begins with the eighth identifier.

[0156] In the present invention, the seventh identifier is different from the eighth identifier. When the SPI master controller 100 reads a read feedback packet, it can determine whether the read feedback packet is a read success feedback packet or a read failure feedback packet based on whether the read feedback packet starts with the seventh identifier or the eighth identifier. The read success feedback packet starts with the seventh identifier and includes data read from the functional module 300, while the read failure feedback packet may only include the eighth identifier.

[0157] As shown in Figure 18, the SPI master controller 100 generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module 200 via the SPI_MOSI signal line. After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module 200 sends the read command packet to the functional module 300. The functional module 300 receives the read command packet and executes the read command. When the functional module 300 completes the read command, it returns a read data packet to the SPI interface module 200. At time ①, the SPI interface module 200 receives the read data packet, and the status information included in the read data packet is failure. When the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads a read feedback packet from the SPI interface module 200 via the SPI_MISO signal line, the SPI interface module 200 drives the SPI_MISO signal line to send a read failure feedback packet to the SPI master controller 100 via the SPI_MISO signal line. The read failure feedback packet only includes the eighth identifier.

[0158] The SPI interface module 200 may further include a timeout timer, which starts timing when a read command packet is received or sent to the functional module 300, or starts timing at a preset time after receiving the read command packet. If the SPI interface module 200 does not receive the read data packet before the timeout, after the timeout, if the SPI master controller 100 generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line, the SPI interface module 200 sends a read failure feedback packet to the SPI master controller 100 through the SPI_MISO signal line. The read feedback packet includes status information, which is agreed upon by the SPI master controller 100 and the SPI interface module 200. The status information may include read command packet timeout information, or may be other status information agreed upon by the SPI master controller 100 and the SPI interface module 200.

[0159] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. Any changes, modifications, substitutions and variations of the above embodiments made by a person skilled in the art within the scope of the present invention shall fall within the scope of protection of the present invention.

Claims

1. An SPI interface system, characterized in that: The SPI interface system includes an SPI interface module and at least one functional module; The SPI interface module is connected to the SPI main controller via a SPI_CK signal line, a SPI_MOSI signal line and a SPI_MISO signal line, and the functional module is connected to the SPI interface module.

2. A SPI data writing method, characterized in that: Using the SPI interface system of claim 1 to write data comprises: The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a write command packet to the SPI interface module through the SPI_MOSI signal line, wherein the write command packet starts with a first identifier; After receiving the write command packet from the SPI_MOSI signal line, the SPI interface module sends the write command packet to the functional module; The functional module receives the write command packet and executes the write command, and when the functional module completes the write command, returns a write status packet to the SPI interface module; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module receives the write status packet, the SPI interface module sends the write feedback packet through the SPI_MISO signal line, the write feedback packet starts with a second identifier, and the write feedback packet includes the status information included in the write status packet.

3. SPI data writing method according to claim 2, characterized in that, When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet, the SPI interface module receives the write command packet.

4. The SPI data writing method according to claim 2, wherein: The write command packet also includes a write command packet verification code; When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet, and the write command packet verification code is verified to be correct, the SPI interface module receives The write command packet.

5. The SPI data writing method according to claim 2, wherein: The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module does not receive the write status packet, the SPI interface module sends data that cannot be identified as the write feedback packet to the SPI master controller through the SPI_MISO signal line.

6. The SPI data writing method according to claim 2, wherein: The SPI interface module includes a timeout timer; When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the write feedback packet is read through the SPI_MISO signal line, The SPI interface module then sends a write feedback packet to the SPI master controller via the SPI_MISO signal line.

7. The SPI data writing method according to claim 2, wherein: The SPI master controller generates a clock edge on the SPI_CK signal line, and sends the write command packet to the SPI interface module via the SPI_MOSI signal line. Then the SPI master controller generates a clock edge on the SPI_CK signal line, reads the write feedback packet through the SPI_MISO signal line, and after the SPI interface module sends the write feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, which include write command packets and read command packets.

8. The SPI data writing method according to claim 2, wherein: The write feedback packet is divided into a write success feedback packet and a write failure feedback packet; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line. When the SPI interface module receives the write status packet and the status information contained in the write status packet is success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, where the write success feedback packet starts with a third identifier; When the SPI interface module receives the write status packet and the status information contained in the write status packet is failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet starts with a fourth identifier.

9. The SPI data writing method according to claim 8, wherein: The SPI interface module includes a timeout timer; When the SPI interface module does not receive the write status packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, and reads the write feedback packet through the SPI_MISO signal line, the SPI interface module sends the write failure feedback packet to the SPI master controller through the SPI_MISO signal line.

10. A SPI data reading method, characterized in that: Using the SPI interface system of claim 1 to read data includes: The SPI master controller generates a clock edge on the SPI_CK signal line, and sends a read command packet to the SPI interface module through the SPI_MOSI signal line, wherein the read command packet starts with a fifth identifier; After receiving the read command packet from the SPI_MOSI signal line, the SPI interface module sends the read command packet to the functional module; The functional module receives the read command packet and executes the read command, and when the functional module completes the read command, returns the read data packet to the SPI interface module; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line. When the SPI interface module receives the read data packet, the SPI interface module sends the read feedback packet through the SPI_MISO signal line, the read feedback packet starts with the sixth identifier, and the read feedback packet includes the read data included in the read data packet.

11. The SPI data reading method according to claim 10, characterized in that: When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet, the SPI interface module receives the read command packet.

12. The SPI data reading method according to claim 10, characterized in that: The read command packet also includes a read command packet check code; When the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet, and the check code of the read command packet is verified to be correct, the SPI interface module receives the read command packet.

13. The SPI data reading method according to claim 10, characterized in that: The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line. When the SPI interface module does not receive the read data packet, the SPI interface module sends data that cannot be identified as the read feedback packet to the SPI master controller through the SPI_MISO signal line.

14. The SPI data reading method according to claim 10, characterized in that: The SPI interface module includes a timeout timer; When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, the read feedback packet is read through the SPI_MISO signal line, The SPI interface module then sends a read feedback packet to the SPI master controller via the SPI_MISO signal line.

15. The SPI data reading method according to claim 10, characterized in that: The SPI master controller generates a clock edge on the SPI_CK signal line and sends a read command packet to the SPI interface module via the SPI_MOSI signal line. The SPI master controller then generates a clock edge on the SPI_CK signal line, through SPI_MISO The signal line reads the read feedback packet, and after the SPI interface module sends the read feedback packet through the SPI_MISO signal line, it can continue to receive subsequent command packets, and the subsequent command packets include a read command packet and a write command packet.

16. The SPI data reading method according to claim 10, characterized in that: The read feedback packet is divided into a read success feedback packet and a read failure feedback packet; The SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet through the SPI_MISO signal line; When the SPI interface module receives the read data packet and the status information contained in the read data packet is success, the SPI interface module sends the read success feedback packet through the SPI_MISO signal line, and the read success feedback packet starts with the seventh identifier; When the SPI interface module receives the read data packet and the status information contained in the read data packet is failure, the SPI interface module sends the read failure feedback packet through the SPI_MISO signal line, and the read failure feedback packet starts with the eighth identifier.

17. The SPI data reading method according to claim 16, characterized in that: The SPI interface module includes a timeout timer; When the SPI interface module does not receive the read data packet before the timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after the timeout, and reads the read feedback packet through the SPI_MISO signal line, the SPI interface module sends the read failure feedback packet to the SPI master controller through the SPI_MISO signal line.

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