Double-sided packaged chip and electronic device

Abstract

A double-sided packaged chip (10) and an electronic device (100). The double-sided packaged chip (10) comprises a substrate (11), a first electronic component (12), and second electronic components (13). A first flip chip (12a) is arranged on the side of the substrate (11) provided with conductive bumps (14); the first flip chip (12a) comprises a first substrate layer (121) and first pins (122), wherein the thickness of the first substrate layer (121) ranges from 60 microns to 80 microns, and the thickness of the first pins (122) ranges from 20 microns to 30 microns; and under the condition that the first flip chip (12a) has a small thickness, the thickness of the first substrate layer (121) is made greater than that of the first pins (122). In the process of grinding and thinning the side of the substrate (11) provided with the conductive bumps (14), the stress borne by the double-sided packaged chip (10) is low, and cracking and damage are not prone to occur between the first flip chip (12a) and the substrate (11) or within the first flip chip (12a), such that the yield of devices is improved, and the production efficiency is high. The electronic device (100) comprises a circuit structure (20) and the double-sided packaged chip (10), wherein a plurality of conductive bumps (14) in the double-sided packaged chip (10) are connected to the circuit structure (20), and the circuit structure (20) is a circuit board (20a) or a first package structure (20a).

Description

Double-sided packaging chip and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 17, 2023, with application number 202323141455.9 and application name “A double-sided packaged chip and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a double-sided packaged chip and electronic device. Background Art

[0003] Double-sided chip packaging allows electronic components to be placed on opposite sides of a substrate, resulting in high integration and a small package thickness. A flip chip (FC) can be placed on the conductive bump side of the substrate. During the grinding and thinning process on the side of the substrate with the conductive bumps, there is a significant risk of cracking and damage between the flip chip and the substrate, as well as within the flip chip itself. Reducing the grinding feed rate can reduce the occurrence of cracking between the flip chip and the substrate, as well as within the flip chip itself, which can reduce production efficiency.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a double-sided packaged chip and an electronic device, which solves the problem in the related art that during the grinding and thinning process of the substrate of the double-sided packaged chip having the conductive bump on one side, there is a great risk of cracking and damage between the flip chip and the substrate, as well as the flip chip itself.

[0006] The embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a double-sided packaged chip, comprising: a substrate, a first electronic component, and a second electronic component. The substrate has a first surface and a second surface disposed opposite to each other, and a plurality of conductive bumps are provided on the first surface. The first electronic component is disposed on the first surface, the first electronic component comprising a first flip chip, the first flip chip comprising a first substrate layer and a plurality of first pins connected to each other, the plurality of first pins being soldered to the first surface, the plurality of first pins being electrically connected to the substrate, the thickness of the first substrate layer being in a range of 60 microns to 80 microns, and the thickness of a single first pin being in a range of 20 microns to 30 microns. The second electronic component is soldered to the second surface, and the second electronic component is electrically connected to the substrate.

[0008] The thickness of the first base material layer and the thickness of the first pin refer to the size of the first base material layer and the size of the first pin in the thickness direction of the double-sided packaged chip, respectively.

[0009] The double-sided packaged chip provided in the embodiment of the present application has a first flip chip disposed on the conductive bump side of the substrate. The first flip chip includes a first substrate layer and a first pin. The thickness of the first substrate layer ranges from 60 microns to 80 microns, and the thickness of the first pin ranges from 20 microns to 30 microns. When the first flip chip has a relatively small thickness, the thickness of the first substrate layer is made thicker than the thickness of the first pin. During the grinding and thinning process of the substrate side having the conductive bump, the double-sided packaged chip is subjected to lower stress, and cracking and damage between the first flip chip and the substrate, as well as the first flip chip itself, are less likely to occur. This improves device yield and increases production efficiency. There is no need to reduce the grinding feed speed to reduce the pressure transmitted to the double-sided packaged chip by the grinding tool.

[0010] In one optional implementation, the ratio of the thickness of the first substrate layer to the thickness of the single first pin is in the range of [2, 4]. Setting the thickness of the first substrate layer to the first pin within this ratio reduces stress on the double-sided packaged chip during the grinding and thinning process on the side of the substrate with the conductive bumps, and reduces cracking and damage between the first flip chip and the substrate, as well as the first flip chip itself, thereby improving device yield.

[0011] In one optional implementation, the thickness of the first substrate layer is 70 microns, and the thickness of the first pin is 30 microns. Alternatively, the thickness of the first substrate layer is 80 microns, and the thickness of the first pin is 20 microns. Alternatively, the thickness of the first substrate layer is 60 microns, and the thickness of the first pin is 20 microns.

[0012] In an optional implementation, a first packaging layer is further included, the first packaging layer at least partially wraps the first electronic component and the first surface, and the plurality of conductive bumps are exposed from the first packaging layer.

[0013] Coating the first electronic component and the first surface with the first packaging layer can enhance the connection strength between the first electronic component and the substrate, protect the first electronic component and the first surface from corrosion and damage, and enhance the stability of the first electronic component. Exposing the conductive bumps from the first packaging layer facilitates soldering and connection between the conductive bumps and a predetermined circuit structure (such as a circuit board), enabling assembly of a double-sided packaged chip and the predetermined circuit structure.

[0014] In an optional implementation, the first packaging layer can be exposed on a side of the first base material layer away from the substrate. This can reduce the overall thickness of the double-sided packaged chip to a certain extent, making it easier to use the double-sided packaged chip in compact environments.

[0015] In one optional implementation, after the first electronic component is disposed on the first surface of the substrate, a first encapsulation layer is disposed outside the first electronic component. During the grinding and thinning process on the side of the substrate having the conductive bump, the first encapsulation layer is exposed on the side of the first base material layer facing away from the substrate, and the first encapsulation layer is exposed on the end of the conductive bump facing away from the substrate.

[0016] In an optional implementation, the side of the first base material layer away from the substrate may not expose the first encapsulation layer, that is, the first encapsulation layer covers the side of the first base material layer away from the substrate.

[0017] In an optional implementation, the first packaging layer includes a filling glue. The first surface of the substrate and the first electronic component are coated with liquid filling glue, and the filling glue is cured to form the first packaging layer, thereby forming a protective structure for the first electronic component.

[0018] In one optional implementation, liquid filler is applied to the periphery of the first electronic component and the conductive bumps, partially filling the space between the first base material layer and the substrate, and then the filler is cured. The side of the substrate with the conductive bumps is then ground and thinned to expose the cured filler above the conductive bumps, thereby forming a first encapsulation layer.

[0019] In one optional implementation, the first packaging layer includes a filler and filler particles, with the filler particles disposed within the filler. The liquid filler containing the filler particles is coated around the first electronic component and the conductive bumps, and after the filler is cured, the structural strength of the first packaging layer is enhanced, thereby improving the reliability of the packaging structure.

[0020] In an optional implementation, the filling glue may include epoxy resin glue, which can easily wrap the first electronic component and the periphery of the conductive bump and can easily solidify to form a stable and reliable first packaging layer.

[0021] In an optional implementation, the filler particles may include one or more of silicon dioxide particles and aluminum oxide particles. The filler particles are easily mixed in the liquid filler and can effectively enhance the structural strength of the first encapsulation layer after the filler is cured.

[0022] In one optional implementation, the filler particles have a particle size of 15 microns or less. The thickness of the first pin ranges from 20 microns to 30 microns. The distance between the substrate and the first base material layer in the first flip chip is relatively small. Mixing the aforementioned small-sized filler particles in the liquid filler facilitates sufficient filling of the filler between the substrate and the first base material layer, improving the filling quality of the filler and thereby enhancing the structural strength of the first packaging layer.

[0023] In an optional implementation, the material of the conductive bump may be copper, copper alloy, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, etc.

[0024] In one optional implementation, the plurality of conductive bumps are solder balls, with a spherical portion formed at one end of the solder ball away from the substrate, the spherical portion protruding from the first packaging layer. The spherical portion protruding from the first packaging layer facilitates solder connection to a predetermined circuit structure (such as a circuit board), enabling assembly of a double-sided packaged chip and the predetermined circuit structure.

[0025] In an optional implementation, the solder balls may be disposed on the first surface of the substrate by evaporation, electroplating, printing, ball placement, or the like.

[0026] In an optional implementation, when the conductive bump is a solder ball, a first electronic component and a solder ball are arranged on the first surface of the substrate, and then a filling glue is wrapped around the first electronic component and the solder ball, and the filling glue is cured; then, one side of the filling glue is ground and thinned to form a final first packaging layer, so that the end of the solder ball away from the substrate is exposed; finally, a laser groove is formed around the exposed side of the solder ball, and solder filler is added to the exposed side of the solder ball, and a complete solder ball is formed by reflow.

[0027] In an optional implementation, the plurality of conductive bumps are solder pillars protruding from the first packaging layer. The solder pillars protruding from the first packaging layer are easily soldered to a predetermined circuit structure (such as a circuit board), thereby achieving assembly of a double-sided packaged chip and the predetermined circuit structure.

[0028] In an optional implementation, the solder pillars may be disposed on the first surface of the substrate by assembling, electroplating, or the like.

[0029] In an optional implementation, multiple first pins can be solder columns, which are in the form of copper columns and tin caps. One end of the copper column is connected to the first substrate layer, and the tin cap is arranged at the end of the copper column away from the first substrate layer. The connection between the tin cap and the substrate is convenient and reliable, so that the first flip chip is flipped on the substrate.

[0030] In an optional implementation, the plurality of first pins may be solder balls, such as tin balls, which are easily disposed on the first substrate layer, and the solder balls are easily and reliably connected to the substrate, thereby enabling the first flip chip to be flip-chip disposed on the substrate.

[0031] In one optional implementation, a second encapsulation layer is further included, at least partially encapsulating the second electronic component and the second surface. Coating the second electronic component on the second surface with the second encapsulation layer can enhance the connection strength between the second electronic component and the substrate, protect the second electronic component from corrosion and damage, and improve the stability of the second electronic component.

[0032] In one optional implementation, a first surface of the substrate is provided with a conductive bump and a first electronic component, which are encapsulated by a first encapsulation layer, with the conductive bump exposed outside the first encapsulation layer. A second surface of the substrate is provided with a second electronic component, which is encapsulated by a second encapsulation layer. This double-sided packaged chip forms a double-sided molded ball grid array package, which has a high degree of integration and a small package thickness.

[0033] In an optional implementation, the first flip chip may include one or more of a low noise amplifier, a radio frequency switch, and a power amplifier.

[0034] In an optional implementation, the second electronic component includes one or more of a chip capacitor, a filter, and a power amplifier.

[0035] In an optional implementation, the filter may be a surface acoustic wave filter or a bulk acoustic wave filter.

[0036] In an optional implementation, the filter and the power amplifier are chips and can be flip-chip mounted on the second surface of the substrate.

[0037] In an optional implementation, a second electronic component such as a low-noise amplifier and / or a radio frequency switch is provided on the first surface of the substrate, and a second electronic component such as a chip capacitor, a filter, a power amplifier is provided on the second surface of the substrate. Multiple electronic components are connected through lines on the substrate to form a predetermined radio frequency front-end circuit.

[0038] In an optional implementation, the substrate includes a redistribution layer, wherein a portion of the conductive bumps are interconnected and conductively connected to the first electronic component via the redistribution layer, and another portion of the conductive bumps are interconnected and conductively connected to the second electronic component via the redistribution layer.

[0039] The redistribution layer has a predetermined circuit. The conductive bumps and the first electronic component are soldered to the predetermined circuit on the first surface of the substrate, and the second electronic component is soldered to the predetermined circuit on the second surface of the substrate. This allows the conductive bumps to be interconnected with the first and second electronic components, respectively. When the double-sided packaged chip and the predetermined circuit structure are assembled, electrical continuity is achieved between the double-sided packaged chip and the predetermined circuit structure.

[0040] In a second aspect, an embodiment of the present application provides an electronic device, including a circuit structure and the above-mentioned double-sided packaging chip, wherein multiple conductive bumps in the double-sided packaging chip are connected to the circuit structure, and the circuit structure includes one or more of a circuit board and a first packaging structure.

[0041] In the electronic device provided by the embodiment of the present application, multiple conductive bumps of the double-sided packaged chip are connected to the circuit structure to achieve conduction between the double-sided packaged chip and the circuit structure.

[0042] In an optional implementation, when the circuit structure is a circuit board, the double-sided packaged chip and the circuit board can be assembled to form a circuit board assembly, thereby achieving electrical connection between the double-sided packaged chip and the circuit board.

[0043] In an optional implementation, when the circuit structure is a first packaging structure, the double-sided packaging chip and the first packaging structure can be assembled to form a stacked packaging structure to achieve conduction between the double-sided packaging chip and the first packaging structure.

[0044] In one optional implementation, the first package structure includes a first substrate and a first chip connected to the first substrate. Multiple conductive bumps in the double-sided packaged chip are soldered to the first substrate of the first package structure. Connecting the first package structure and the double-sided packaged chip to form a stacked package structure can improve the integration of electronic components, resulting in high performance and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] FIG1 is a schematic structural diagram of a double-sided packaged chip provided in an embodiment of the present application;

[0046] FIG2 is a schematic structural diagram of a double-sided packaged chip provided in another embodiment of the present application;

[0047] FIG3 is a simulation model diagram of a double-sided packaged chip provided in an embodiment of the present application;

[0048] FIG4 (a) and (b) are respectively stress finite element simulation diagrams of double-sided packaged chips of different embodiments of the present application;

[0049] FIG5 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0050] Description of reference numerals:

[0051] 1-Double-sided packaged chip; 2-Substrate; 3-Second electronic component; 4-Conductive bump; 5-Flip chip; 5a-Base material layer; 5b-Pin;

[0052] 10-Double-sided package chip;

[0053] 11-substrate; 11a-first surface; 11b-second surface; 111-rewiring layer; 111a-circuit;

[0054] 12-first electronic component; 12a-first flip chip; 121-first substrate layer; 122-first pin; 1221-copper pillar; 1222-tin cap; 12b-low noise amplifier; 12c-RF switch;

[0055] 13-second electronic component; 13a-chip capacitor; 13b-filter; 13c-power amplifier;

[0056] 14-conductive bump; 15-first packaging layer; 16-second packaging layer;

[0057] 20-circuit structure; 20a-circuit board, first packaging structure;

[0058] 100-Electronic equipment. DETAILED DESCRIPTION

[0059] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application. Although the description of this application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to this embodiment. On the contrary, the purpose of introducing the application in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of this application. In order to provide an in-depth understanding of the application, the following description will contain many specific details. This application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of this application, some specific details will be omitted in the description. It should be noted that the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict.

[0060] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0061] It should be understood that in the description of the embodiments of the present application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. The orientation or positional relationship indicated by the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present application.

[0062] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0063] In the embodiments of this application, "and / or" is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0064] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0065] Referring to FIG1 , an embodiment of the present application provides a double-sided packaged chip 1, wherein electronic components 3 are provided on opposite sides of a substrate 2. A flip chip 5 can be provided on one side of the conductive bump 4 of the substrate 2. The flip chip 5 includes a substrate layer 5a and pins 5b connected to each other, and the pins 5b are soldered to the substrate 2. The diameter of the pins 5b can range from 60 microns (μm) to 70 μm, and the thickness A2 of the pins 5b can range from 40 μm to 50 μm. When the thickness of the flip chip 5 is 100 μm, the thickness A1 of the substrate layer 5a of the flip chip 5 is approximately 50 μm, the thickness A2 of the pins 5b is approximately 50 μm, and the ratio of the thickness of the substrate layer 5a to the thickness of the single pin 5b is approximately 1. The thickness A1 of the substrate layer 5a and the thickness A2 of the pins 5b refer to the size of the substrate layer 5a and the size of the pins 5b in the thickness direction of the double-sided packaged chip 1, respectively.

[0066] During the production of double-sided packaged chips 1, the side of substrate 2 with conductive bumps 4 must be ground and thinned, creating a significant risk of cracking and damage between the flip chip 5 and substrate 2, as well as within the flip chip 5 itself. Reducing the grinding feed speed and the pressure imparted by the grinding tool to the double-sided packaged chips 1 can reduce the risk of cracking between the flip chip 5 and substrate 2, as well as within the flip chip 5 itself. However, this can result in reduced production efficiency.

[0067] Referring to FIG. 2 , an embodiment of the present application provides a double-sided packaged chip 10, comprising a substrate 11, a first electronic component 12, and a second electronic component 13. The substrate 11 has a first surface 11a and a second surface 11b disposed opposite each other. A plurality of conductive bumps 14 are provided on the first surface 11a. The first electronic component 12 is disposed on the first surface 11a and includes a first flip chip 12a. The first flip chip 12a includes a first substrate layer 121 and a plurality of first pins 122 connected to each other. The plurality of first pins 122 are soldered to the first surface 11a and electrically connected to the substrate 11. The thickness B1 of the first substrate layer 121 ranges from 60 microns to 80 microns, and the thickness B2 of each first pin 122 ranges from 20 microns to 30 microns. The second electronic component 13 is soldered to the second surface 11b and electrically connected to the substrate 11.

[0068] Among them, the substrate 11 serves as a carrier for the first electronic component 12 and the second electronic component 13. The conductive bump 14 is connected to the circuit 111a of the substrate 11, and the circuit 111a of the substrate 11 is connected to the first electronic component 12 and the second electronic component 13, so that the conductive bump 14 is electrically connected and interconnected with the first flip chip 12a and the second electronic component 13 respectively. The double-sided packaged chip 10 can be assembled and used with a predetermined circuit structure (such as a circuit board), and the conductive bump 14 is used for welding and conducting with the predetermined circuit structure. The thickness B1 of the first base material layer 121 and the thickness B2 of the first pin 122 refer to the size of the first base material layer 121 and the size of the first pin 122 in the thickness direction of the double-sided packaged chip 10, respectively. The thickness direction of the double-sided packaged chip 10 is perpendicular to the first surface 11a and the second surface 11b of the substrate 11.

[0069] The double-sided packaged chip 10 provided in the embodiment of the present application has a first flip chip 12a disposed on the side of the substrate 11 with the conductive bumps 14. The first flip chip 12a includes a first base material layer 121 and first leads 122. The thickness of the first base material layer 121 ranges from 60 to 80 microns, and the thickness of the first leads 122 ranges from 20 to 30 microns. If the first flip chip 12a is relatively thin, the thickness of the first base material layer 121 is made thicker than the thickness of the first leads 122. During the grinding and thinning process of the side of the substrate 11 with the conductive bumps 14, the double-sided packaged chip 10 is subjected to low stress. The gap between the first flip chip 12a and the substrate 11, as well as the first flip chip 12a itself, are less likely to crack or damage, thereby improving device yield and increasing production efficiency. There is no need to reduce the grinding feed speed to reduce the pressure transmitted to the double-sided packaged chip 10 by the grinding tool.

[0070] When setting the thickness of the first substrate layer 121 and the first pins 122, refer to 2. The ratio of the thickness B1 of the first substrate layer 121 to the thickness B2 of a single first pin 122 is in the range [2, 4]. Setting the thickness of the first substrate layer 121 and the first pin 122 within this ratio range reduces stress on the double-sided packaged chip 10 during the grinding and thinning process on the side of the substrate 11 with the conductive bumps 14. This reduces the risk of cracking and damage between the first flip chip 12a and the substrate 11, as well as the first flip chip 12a itself, thereby improving device yield.

[0071] The specific thicknesses of the first substrate layer 121 and the first pins 122 are set as needed. For example, the thickness B1 of the first substrate layer 121 is 70 microns, and the thickness B2 of the first pins 122 is 30 microns. Alternatively, the thickness B1 of the first substrate layer 121 is 80 microns, and the thickness B2 of the first pins 122 is 20 microns. Alternatively, the thickness B1 of the first substrate layer 121 is 60 microns, and the thickness B2 of the first pins 122 is 20 microns.

[0072] To verify the advantage of the double-sided packaged chip 10 of this embodiment in reducing stress during the grinding and thinning process, stress finite element simulations were performed on the double-sided packaged chip 1 and the double-sided packaged chip 10 of this embodiment. As shown in FIG1 , double-sided packaged chip 1 is used as a comparative example. A flip chip 5 is provided on one side of substrate 2. The flip chip 5 includes a connected base material layer 5a and leads 5b. The base material layer 5a has a thickness A1 of 50 microns, and the leads 5b have a thickness A2 of 45 microns. As shown in FIG2 , a first flip chip 12a is provided on one side of substrate 11. The first flip chip 12a includes a connected first base material layer 121 and first leads 122. The first base material layer 121 has a thickness B1 of 70 microns, and the first leads 122 have a thickness B2 of 25 microns.

[0073] 3 , a uniform pressure of 1 Newton per square meter (N / m 2 ) is applied to a surface of the substrate layer 5 a (the first substrate layer 121 ) away from the substrate. 2 ) pressure F, simulating the pressure on the double-sided packaged chip during the grinding process. After stress finite element simulation, as shown in Figure 4 (a), the first principal stress borne by the comparative double-sided packaged chip 1 on the flip chip is 89.6N / m 2 The stress at and near the connection position between the substrate layer 5a and the pin 5b is relatively large. As shown in FIG4(b), the first principal stress on the first flip chip 12a of the double-sided package chip 10 in this embodiment is 75.9N / m 2Compared to the double-sided packaged chip 1 in the comparative example, the first principal stress experienced by the double-sided packaged chip 10 in this embodiment is reduced by 15.3%. The stress experienced by the double-sided packaged chip 10 during the grinding and thinning process in this embodiment is relatively low, making cracking and damage between the first flip chip 12a and the substrate 11, as well as the first flip chip 12a itself, less likely to occur.

[0074] To improve the stability of the first electronic component 12 , in some embodiments, referring to FIG. 2 , a first packaging layer 15 is further included. The first packaging layer 15 at least partially wraps the first electronic component 12 and the first surface 11 a , and the plurality of conductive bumps 14 are exposed from the first packaging layer 15 .

[0075] Coating the first packaging layer 15 on the first electronic component 12 and the first surface 11a can enhance the connection strength between the first electronic component 12 and the substrate 11, protect the first electronic component 12 and the first surface 11a from corrosion and damage, and enhance the stability of the first electronic component 12. Referring to FIG5 , exposing the conductive bumps 14 from the first packaging layer 15 facilitates soldering and connection between the conductive bumps 14 and the predetermined circuit structure 20 (e.g., circuit board 20a), thereby achieving assembly of the double-sided packaged chip 10 and the predetermined circuit structure 20.

[0076] To reduce the overall thickness of the double-sided packaged chip 10, in some embodiments, referring to FIG2 , the first packaging layer 15 can be exposed on a side of the first base material layer 121 away from the substrate 11. This can reduce the overall thickness of the double-sided packaged chip 10 to a certain extent, facilitating its application in compact environments.

[0077] For example, after the first electronic component 12 is disposed on the first surface 11a of the substrate 11, a first encapsulation layer 15 is disposed outside the first electronic component 12. During the grinding and thinning process of the side of the substrate 11 having the conductive bump 14, the first encapsulation layer 15 is exposed on the side of the first base material layer 121 away from the substrate 11, and the first encapsulation layer 15 is exposed on the end of the conductive bump 14 away from the substrate 11.

[0078] In some other embodiments, the side of the first base material layer 121 away from the substrate 11 may not expose the first encapsulation layer 15 , that is, the first encapsulation layer 15 covers the side of the first base material layer 121 away from the substrate 11 .

[0079] When the first packaging layer 15 is provided, the first packaging layer 15 includes a filling glue. The liquid filling glue is used to cover the first surface 11a of the substrate 11 and the first electronic component 12, and the filling glue is cured to form the first packaging layer 15, forming a protective structure for the first electronic component 12.

[0080] For example, a liquid filler is applied to the periphery of the first electronic component 12 and the conductive bumps 14. A portion of the filler is then applied between the first base material layer 121 and the substrate 11. The filler is then cured. The side of the substrate 11 with the conductive bumps 14 is ground and thinned to expose the cured filler from the conductive bumps 14, thereby forming the first encapsulation layer 15.

[0081] To enhance the structural strength of the first packaging layer 15, in some embodiments, the first packaging layer 15 includes a filler and filler particles, with the filler particles disposed within the filler. Applying the liquid filler containing the filler particles around the first electronic component 12 and the conductive bumps 14 and curing the filler enhances the structural strength of the first packaging layer 15 and improves the reliability of the packaging structure.

[0082] When providing the filling glue, the filling glue may include epoxy resin glue, which can easily wrap the first electronic component 12 and the outer periphery of the conductive bump 14 and can easily solidify to form a stable and reliable first packaging layer 15 .

[0083] When setting the material of the filler particles, the filler particles may include one or more of silicon dioxide particles and aluminum oxide particles. The above filler particles are easily mixed in the liquid filler, and after the filler is cured, the filler particles can effectively improve the structural strength of the first encapsulation layer 15.

[0084] When setting the filler particle size, the filler particle size is less than or equal to 15 microns. The thickness of the first lead 122 ranges from 20 microns to 30 microns. The distance between the substrate 11 and the first base material layer 121 of the first flip chip 12a is relatively small. Using the above-mentioned small-sized filler particles mixed in the liquid filler facilitates the filler to fully fill the gap between the substrate 11 and the first base material layer 121, improving the filling quality of the filler and thereby enhancing the structural strength of the first encapsulation layer 15.

[0085] When setting the material of the conductive bump 14 , the material of the conductive bump 14 can be copper, copper alloy, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, etc.

[0086] There are multiple optional implementations for setting the shape of the conductive bump 14 , and two implementations are exemplified below.

[0087] The first implementation of conductive bumps 14: Referring to Figures 2 and 5 , multiple conductive bumps 14 are solder balls. The ends of the solder balls facing away from the substrate 11 form a spherical portion that protrudes from the first packaging layer 15. This spherical portion protruding from the first packaging layer 15 facilitates solder connection to a predetermined circuit structure 20 (e.g., a circuit board 20a), enabling assembly of the double-sided packaged chip 10 and the predetermined circuit structure 20. The solder balls can be deposited on the first surface 11a of the substrate 11 by vapor deposition, electroplating, printing, or placement.

[0088] In the case where the conductive bumps 14 are solder balls, the preparation process of the double-sided packaged chip 10 may include: arranging a first electronic component 12 and a solder ball on the first surface 11a of the substrate 11, then wrapping the first electronic component 12 and the solder ball with a filling glue, and curing the filling glue; then, grinding and thinning one side of the filling glue to form a final first packaging layer 15, so that the end of the solder ball away from the substrate 11 is exposed; finally, laser grooving around the exposed side of the solder ball, supplementing the exposed side of the solder ball with solder filler, and forming a complete solder ball through reflow.

[0089] Second implementation of conductive bumps 14: Multiple conductive bumps 14 are solder pillars protruding from first packaging layer 15. Solder pillars protruding from first packaging layer 15 facilitate soldering connection to a predetermined circuit structure 20 (e.g., circuit board 20a), enabling assembly of a double-sided packaged chip 10 and predetermined circuit structure 20. The solder pillars can be disposed on first surface 11a of substrate 11 by assembly, electroplating, or other methods.

[0090] There are multiple optional implementations for setting the first pins 122 of the first flip chip 12 a , and two implementations are exemplified below.

[0091] The first implementation method of the first pin 122 is: referring to Figure 2, multiple first pins 122 can be solder columns, for example, the solder column adopts the form of a copper column 1221 and a tin cap 1222, one end of the copper column 1221 is connected to the first substrate layer 121, and the tin cap 1222 is arranged at the end of the copper column 1221 away from the first substrate layer 121, and the connection between the tin cap 1222 and the substrate 11 is convenient and reliable, so that the first flip chip 12a is flipped and set on the substrate 11.

[0092] A second implementation of the first pins 122 is that the plurality of first pins 122 can be solder balls, such as tin balls. The solder balls are easily disposed on the first base material layer 121, and the solder balls are easily and reliably connected to the substrate 11, thereby enabling the first flip chip 12a to be flip-chip disposed on the substrate 11.

[0093] To enhance the stability of second electronic component 13 on second surface 11b of substrate 11, in some embodiments, referring to FIG2 , a second encapsulation layer 16 is further included. Second encapsulation layer 16 at least partially encapsulates second electronic component 13 and second surface 11b. Coating second encapsulation layer 16 on second electronic component 13 on second surface 11b enhances the connection strength between second electronic component 13 and substrate 11, protects second electronic component 13 from corrosion and damage, and enhances the stability of second electronic component 13.

[0094] In some embodiments, referring to FIG. 2 , a first surface 11a of a substrate 11 is provided with conductive bumps 14 and a first electronic component 12. A first encapsulation layer 15 surrounds the conductive bumps 14 and the first electronic component 12, with the conductive bumps 14 exposed from the first encapsulation layer 15. A second electronic component 13 is disposed on a second surface 11b of the substrate 11, which is surrounded by a second encapsulation layer 16. The double-sided packaged chip 10 forms a double-sided molded ball grid array (DSMBGA) package, which features a high level of integration and a compact package thickness.

[0095] When the first flip chip 12 a is provided, referring to FIG. 2 , the first flip chip 12 a may include one or more of a low noise amplifier (LNA) 12 b , a radio frequency switch (SW) 12 c , and a power amplifier (PA).

[0096] The radio frequency low noise amplifier 12b is a chip of the radio frequency front end, which is used to amplify the signal received from the antenna so as to facilitate processing by subsequent electronic equipment.

[0097] The RF switch 12c is a chip in the RF front end, used to switch signals of different frequencies or different communication formats on the signal transmission path.

[0098] The power amplifier is a chip in the RF front end that can amplify the RF signal power generated by the modulation circuit and output it to the antenna for radiation.

[0099] When the second electronic component 13 is provided, the second electronic component 13 includes one or more of a chip capacitor 13 a , a filter 13 b , and a power amplifier 13 c .

[0100] Chip capacitor 13a is a multilayer ceramic capacitor (MLCC). Chip capacitors are made by stacking ceramic dielectric diaphragms with printed inner electrodes in an offset pattern. They are then sintered at high temperature to form a ceramic chip, with outer electrodes sealed at both ends. Chip capacitors in 01005 or other sizes are available.

[0101] Filter 13b is a chip in the RF front end that filters out frequency components within a predetermined frequency range and outputs a signal with a predetermined frequency from among the multiple input RF signals. Filter 13b can be a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter.

[0102] The filter 13 b and the power amplifier 13 c are chips and can be flip-chip mounted on the second surface 11 b of the substrate 11 .

[0103] In some embodiments, referring to Figure 2, a second electronic component 13 such as a low-noise amplifier 12b and / or a radio frequency switch 12c is provided on the first surface 11a of the substrate 11, and a second electronic component 13 such as a chip capacitor 13a, a filter 13b, and a power amplifier 13c is provided on the second surface 11b of the substrate 11. The multiple electronic components are connected through the line 111a on the substrate 11 to form a predetermined radio frequency front-end circuit.

[0104] To achieve interconnection and electrical connection between the conductive bumps 14 and the first electronic component 12 and the second electronic component 13, in some embodiments, referring to FIG2 , the substrate 11 includes a redistribution layer 111. The substrate 11 includes the redistribution layer 111, wherein a portion of the conductive bumps 14 are interconnected and electrically connected to the first electronic component 12 via the redistribution layer 111, and another portion of the conductive bumps 14 are interconnected and electrically connected to the second electronic component 13 via the redistribution layer 111.

[0105] The redistribution layer 111 has a predetermined circuit 111a. The conductive bumps 14 and the first electronic component 12 are soldered to the predetermined circuit 111a on the first surface 11a of the substrate 11. The second electronic component 13 is soldered to the predetermined circuit 111a on the second surface 11b of the substrate 11. This achieves interconnection and electrical connection between the conductive bumps 14 and the first and second electronic components 12 and 13, respectively. With reference to FIG5 , when the double-sided packaged chip 10 is assembled with a predetermined circuit structure 20 (e.g., a circuit board 20a), electrical connection between the double-sided packaged chip 10 and the predetermined circuit structure 20 is achieved.

[0106] When confirming the double-sided packaged chip 10 of the embodiment of the present application, referring to Figure 2, the double-sided packaged chip 10 can be disassembled for analysis and longitudinally cut at the first pin 122 of the first flip chip 12a. A focused ion beam (FIB) microscope or a transmission electron microscope (TEM) is used to observe the thickness B1 of the first substrate layer 121 and the thickness B2 of the first pin 122 in the first flip chip 12a.

[0107] Referring to Figure 5, an embodiment of the present application provides an electronic device 100, including a circuit structure 20 and the above-mentioned double-sided packaging chip 10, multiple conductive bumps 14 in the double-sided packaging chip 10 are connected to the circuit structure 20, and the circuit structure 20 includes one or more of a circuit board 20a and a first packaging structure 20a.

[0108] In the electronic device 100 provided in the embodiment of the present application, the multiple conductive bumps 14 of the double-sided packaged chip 10 are connected to the circuit structure 20 to achieve conduction between the double-sided packaged chip 10 and the circuit structure 20 .

[0109] 5 , in the case where the circuit structure 20 is a circuit board 20 a , the double-sided packaged chip 10 and the circuit board 20 a are assembled to form a circuit board assembly, thereby achieving electrical connection between the double-sided packaged chip 10 and the circuit board 20 a .

[0110] 5 , when the circuit structure 20 is a first package structure 20 a , the double-sided package chip 10 and the first package structure 20 a are assembled to form a stacked package structure, thereby achieving electrical connection between the double-sided package chip 10 and the first package structure 20 a .

[0111] The first package structure 20a can employ various packaging structures. For example, the first package structure 20a includes a first substrate and a first chip connected to the first substrate. Multiple conductive bumps 14 in the double-sided packaged chip 10 are soldered to the first substrate of the first package structure 20a. The conductive connection between the first package structure 20a and the double-sided packaged chip 10 forms a stacked package structure, which can improve the integration of electronic components, achieve high performance, and reduce power consumption.

[0112] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A double-sided packaged chip, characterized in that: include: a substrate, a first electronic component, and a second electronic component; The substrate has a first surface and a second surface that are arranged opposite to each other, and a plurality of conductive bumps are arranged on the first surface; The first electronic component is disposed on the first surface, the first electronic component comprises a first flip chip, the first flip chip comprises a first substrate layer and a plurality of first pins connected to each other, the plurality of first pins are soldered to the first surface, the plurality of first pins are electrically connected to the substrate, the thickness of the first substrate layer is in a range of 60 microns to 80 microns, and the thickness of a single first pin is in a range of 20 microns to 30 microns; The second electronic component is soldered on the second surface, and the second electronic component is electrically connected to the substrate.

2. The double-sided packaged chip according to claim 1, characterized in that: It also includes a first packaging layer, wherein the first packaging layer at least partially wraps the first electronic component and the first surface, and the plurality of conductive bumps expose the first packaging layer.

3. The double-sided packaged chip according to claim 2, characterized in that: A side of the first base material layer away from the substrate exposes the first packaging layer.

4. The double-sided packaged chip according to claim 2 or 3, characterized in that: The first encapsulation layer includes a filling glue; Alternatively, the first encapsulation layer includes a filling glue and filling particles, and the filling particles are disposed in the filling glue.

5. The double-sided packaged chip according to claim 4, characterized in that: The filling glue includes epoxy resin glue; Or, in the case where the first encapsulation layer includes filler particles, the filler particles include one or more of silicon dioxide particles and aluminum oxide particles; Alternatively, when the first encapsulation layer includes filler particles, the particle size of the filler particles is less than or equal to 15 micrometers.

6. The double-sided packaged chip according to any one of claims 2 to 5, characterized in that: The plurality of conductive bumps are solder balls, one end of the solder ball away from the substrate forms a spherical portion, and the spherical portion protrudes from the first packaging layer; Alternatively, the plurality of conductive bumps are solder pillars, and the solder pillars protrude from the first packaging layer.

7. The double-sided packaged chip according to any one of claims 1 to 6, characterized in that: The ratio of the thickness of the first substrate layer to the thickness of a single first pin is in the range of [2,4].

8. The double-sided packaged chip according to any one of claims 1 to 7, characterized in that: The first plurality of pins are solder posts; Alternatively, the first plurality of pins are solder balls.

9. The double-sided packaged chip according to any one of claims 1 to 8, characterized in that: A second packaging layer is also included, and the second packaging layer at least partially wraps the second electronic component and the second surface.

10. The double-sided packaged chip according to any one of claims 1 to 9, characterized in that: The first flip chip includes one or more of a low noise amplifier, a radio frequency switch, and a power amplifier; And / or, the second electronic component includes one or more of a chip capacitor, a filter, and a power amplifier.

11. The double-sided packaged chip according to any one of claims 1 to 10, characterized in that: The substrate comprises a redistribution layer, wherein a portion of the conductive bumps and the first electronic component are interconnected and conducted through the redistribution layer, and another portion of the conductive bumps and the second electronic component are interconnected and conducted through the redistribution layer.

12. An electronic device, characterized in that: It comprises a circuit structure and a double-sided packaging chip as described in any one of claims 1 to 11, wherein a plurality of the conductive bumps in the double-sided packaging chip are connected to the circuit structure, and the circuit structure comprises one or more of a circuit board and a first packaging structure.

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