Display panel and display apparatus

Abstract

Provided in the present disclosure are a display panel and a display apparatus. The display panel comprises a base substrate and a plurality of pixel units (10) arranged in an array on the base substrate. Each column of pixel units (10) at least comprises a first sub-column (L1), a second sub-column (L2) and a third sub-column (L3). In the same column of pixel units (10), some of first sub-pixels (11) and some of third sub-pixels (13) are located in the first sub-column (L1), the other first sub-pixels (11) and the other third sub-pixels (13) are located in the third sub-column (L3), and second sub-pixels (12) are located in the second sub-column (L2). In the same column of pixel units (10), the first sub-pixels (11) are electrically connected to a first data line (DL1), the second sub-pixels (12) are electrically connected to a second data line (DL2), and the third sub-pixels (13) are electrically connected to a third data line (DL3).

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to the Chinese patent application filed on November 15, 2023, with application number "202311522887.6" and named "Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display panel and a display device. Background Art

[0004] With the development of display technology, the demand for low power consumption in display products has become increasingly strong. Taking the active-matrix organic light-emitting diode (AMOLED) in OLED (Organic Light-Emitting Diode) display panels as an example, its display power consumption can be divided into backplane (BP) circuit power consumption and OLED light-emitting device power consumption. Among them, with the update of light-emitting device materials, device power consumption has been decreasing year by year, while the proportion of BP circuit power consumption in total power consumption has been increasing. Therefore, it is necessary to reduce the overall display power consumption by focusing on the BP circuit power consumption.

[0005] Summary of the Invention

[0006] The problem of reducing the source driving power consumption of a display panel is solved by utilizing one or more embodiments of the present disclosure.

[0007] In a first aspect of the present disclosure, a display panel is provided, comprising: a substrate and a plurality of pixel units arranged in an array on the substrate. Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and each column of pixel units includes at least a first sub-column, a second sub-column, and a third sub-column arranged in sequence along a first direction, wherein, in the same column of pixel units, a portion of the first sub-pixels and a portion of the third sub-pixels are located in the first sub-column, another portion of the first sub-pixels and another portion of the third sub-pixels are located in the third sub-column, and the second sub-pixels are located in the second sub-column; each column of pixel units corresponds to a first data line, a second data line, and a third data line; and in the same column of pixel units, the first sub-pixel is electrically connected to the first data line, the second sub-pixel is electrically connected to the second data line, and the third sub-pixel is electrically connected to the third data line.

[0008] In a second aspect of the present disclosure, a display device is provided, comprising the display panel provided in the first aspect.

[0009] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1A shows an SPR pixel arrangement of an AMOLED;

[0011] FIG1B shows a schematic diagram of source drive timing for the SPR pixel arrangement of FIG1 ;

[0012] FIG2A is a schematic diagram showing an alternate arrangement of first sub-pixels and third sub-pixels according to some embodiments of the present disclosure;

[0013] FIG2B is a schematic diagram showing a first sub-pixel and a third sub-pixel arranged in pairs according to some embodiments of the present disclosure;

[0014] FIG2C shows a schematic diagram of a source driving timing sequence of a sub-pixel according to some embodiments of the present disclosure;

[0015] FIG3 shows a schematic diagram of a pixel arrangement when a pixel unit includes two second sub-pixels according to some embodiments of the present disclosure;

[0016] FIG4A shows a schematic diagram of pixel arrangement and winding compensation according to Solution 1 of some embodiments of the present disclosure;

[0017] FIG4B shows a schematic diagram of the circuit layout of Scheme 1;

[0018] FIG4C shows a schematic diagram of first electrode routing of the red sub-pixel R1 in the first row in FIG4B ;

[0019] FIG4D shows a schematic diagram of the first electrode routing of the red sub-pixel R2 in the second row in FIG4B ;

[0020] FIG4E shows a schematic diagram of the third electrode wiring of the blue sub-pixel B1 in the first row in FIG4B ;

[0021] FIG4F shows a schematic diagram of the third electrode routing of the blue sub-pixel B2 in the first row in FIG4B ;

[0022] FIG5A shows a schematic diagram of pixel arrangement and winding compensation according to Solution 2 of some embodiments of the present disclosure;

[0023] FIG5B shows a schematic diagram of the circuit layout of Scheme 2;

[0024] FIG6A shows a schematic diagram of pixel arrangement and winding compensation according to Solution 3 of some embodiments of the present disclosure;

[0025] FIG6B shows a schematic diagram of the circuit layout of Scheme 3;

[0026] FIG7A shows a schematic diagram of pixel arrangement and winding compensation according to Solution 4 of some embodiments of the present disclosure; and

[0027] FIG7B shows a schematic diagram of the circuit layout of Scheme 4.

[0028] Description of reference numerals:

[0029] 10. Pixel unit; 11. First sub-pixel; 12. Second sub-pixel; 13. Third sub-pixel; L1. First sub-column; L2. Second sub-column; L3. Third sub-column; L4. Fourth sub-column; A1. First area; A2. Second area; SD, Source / Drain metal layer; DL1, First data line; DL2, Second data line; DL3, Third data line; VDD, Power signal line; Block, Pad; 20, First electrode; 21. Main body; 22. Conductive block; 23A, First electrode trace; 23B, Second electrode trace; 23C, Third electrode trace; R, Red sub-pixel; G, Green sub-pixel; B, Blue sub-pixel. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0031] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0033] In the context of this disclosure, unless otherwise specified, the light-emitting side of a display panel is referred to as the "top side" or "upper side," and the opposite side is referred to as the "bottom side" or "lower side" to facilitate description of relative directions. Accordingly, the direction from the bottom side to the top side is the thickness direction of the display panel, and the direction perpendicular to the thickness direction is the "planar direction" or "extension direction" of the display panel. It should be understood that these directions are relative, not absolute, directions.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0035] To improve the lifespan of display panels and ensure the aperture ratio, current display panels, especially OLED display panels, are increasingly adopting sub-pixel rendering (SPR) technology. This technology utilizes the principle of sub-pixel borrowing, whereby two sub-pixels of different colors in each pixel unit of the display panel are shared by sub-pixels of another color. Taking the arrangement of RGB (red, green, and blue) sub-pixels as an example, two green sub-pixels often share one red sub-pixel and one blue sub-pixel, forming two pixel units. This not only ensures resolution while reducing the number of pixels in the pixel array, but also appropriately increases the area of ​​the sub-pixels to increase the aperture ratio, effectively compensating for the partial image loss caused by the lack of sub-pixels, which is beneficial to improving display quality and service life.

[0036] For example, an SPR pixel arrangement for an AMOLED display panel can be seen in Figure 1A , which employs an RGBG pixel array arrangement, whereby a pixel unit includes a red subpixel R, two green subpixels G, and a blue subpixel B. A green subpixel G can form a luminous center by utilizing the surrounding red subpixels R and blue subpixels B. In some embodiments, each column of pixel units includes four columns of subpixels, with red subpixels R and blue subpixels B alternately arranged in the first and third columns, and green subpixels G arranged in the second and fourth columns. The source drive of all column sub-pixels adopts the principle of proximity. For example, for the first column of pixel units, all red sub-pixels R and blue sub-pixels B in the first column of sub-pixels are connected to the adjacent data line R1 (Source Line), and all red sub-pixels R and blue sub-pixels B in the third column of sub-pixels are connected to the adjacent data line B1; and all green sub-pixels G in the second column of sub-pixels are connected to the adjacent data line G11, and all green sub-pixels G in the fourth column of sub-pixels are connected to the adjacent data line G12; and so on, for the Nth column of pixel units, all red sub-pixels R and blue sub-pixels B in the first column of sub-pixels are connected to the adjacent data line Rn1, and all red sub-pixels R and blue sub-pixels B in the third column of sub-pixels are connected to the adjacent data line Bn1; and all green sub-pixels G in the second column of sub-pixels are connected to the adjacent data line Gn1, and all green sub-pixels G in the fourth column of sub-pixels are connected to the adjacent data line Gn2.

[0037] However, this SPR pixel arrangement also brings about the problem of increased BP circuit driving power consumption, specifically the source driving power consumption. Since the first column of sub-pixels and the second column of sub-pixels contain both red sub-pixels R and blue sub-pixels B, and each column of sub-pixels shares the same data line and is driven by the same column of pixel circuits. Therefore, when emitting light, especially when displaying a pure red or pure blue picture, due to the principle of OLED's inherent row-by-row turn-on, the driving voltage in the data lines R1 and B1 needs to jump continuously, as shown in Figure 1B. The driving voltage is driven by the source driving circuit S-IC, and the continuous jumping will greatly increase the source driving power consumption, reducing the battery life of the display panel.

[0038] Therefore, in order to solve the problem of increased source driver power consumption, firstly, in an optional embodiment, a display panel is provided, and its pixel arrangement is shown in FIG2A . The display panel includes: a base substrate (not shown in the figure) and a plurality of pixel units 10 arranged in an array on the base substrate.

[0039] Each pixel unit 10 includes a first sub-pixel 11, a second sub-pixel 12 and a third sub-pixel 13, and each column of pixel units 10 includes at least: a first sub-column L1, a second sub-column L2 and a third sub-column L3 arranged in sequence along the first direction X1. In the same column of pixel units 10, a portion of the first sub-pixels 11 and a portion of the third sub-pixels 13 are located in the first sub-column L1, another portion of the first sub-pixels 11 and another portion of the third sub-pixels 13 are located in the third sub-column L3, and the second sub-pixels 12 are located in the second sub-column L2; each column of pixel units 10 corresponds to a first data line DL1, a second data line DL2 and a third data line DL3; in the same column of pixel units 10, the first sub-pixel 11 is electrically connected to the first data line DL1, the second sub-pixel 12 is electrically connected to the second data line DL2, and the third sub-pixel 13 is electrically connected to the third data line DL3.

[0040] In some embodiments, a plurality of pixel units 10 arranged in an array form a pixel array, with each column comprising a plurality of pixel units 10. The first direction X1 in the present disclosure may be the row direction or the column direction of the pixel array, and the second direction X2 intersects the first direction X1 and may be the other of the row direction and the column direction. Unless otherwise specified, the present disclosure uses the first direction X1 as the row direction of the pixel array and the second direction X2 as the column direction of the pixel array as an example for description. The first sub-column L1, the second sub-column L2, and the third sub-column L3 are arranged sequentially in the first direction X1, i.e., the row direction of the pixel array, and the sub-pixels contained in each sub-column are arranged in the second direction X2, i.e., the column direction of the pixel array. The first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are sub-pixels of three different colors, such as the currently commonly used RGB sub-pixels. Unless otherwise specified, the present disclosure uses the first sub-pixel 11 as a red sub-pixel R, the second sub-pixel 12 as a green sub-pixel G, and the third sub-pixel 13 as a blue sub-pixel B as an example for description.

[0041] Therefore, in the same column of pixel units 10, the first sub-column L1 and the third sub-column L3 are both arranged with the first sub-pixel 11 and the third sub-pixel 13, and only the second sub-pixel 12 is arranged in the second sub-column L2. In this way, an SPR pixel structure can be formed. Each second sub-pixel 12 in the second sub-column L2 can use the adjacent first sub-pixel 11 and third sub-pixel 13 to form a light-emitting center, which is beneficial to reducing the number of sub-pixels and improving the aperture ratio and service life while ensuring the total pixel density.

[0042] In either the first sub-column L1 or the third sub-column L3, the first sub-pixels 11 and the third sub-pixels 13 can be arranged alternately or in sequence. For example, taking the first sub-pixel 11 as a red sub-pixel R and the third sub-pixel 13 as a blue sub-pixel B, FIG2A employs an alternating arrangement in the second direction X2. That is, the first sub-column L1 in each column of pixel units 10 employs an RBRBRB arrangement, while the corresponding third sub-column L3 employs a BRBRBR arrangement, thereby ensuring the integrity of the pixel units 10 in the first direction X1. Alternatively, a two-by-two arrangement can be employed as shown in FIG2B , where the first sub-column L1 employs an RRBBRRBB arrangement of sub-pixels and the third sub-column L3 employs a BBRRBBRR arrangement of sub-pixels, which can also form a pixel borrowing structure.

[0043] At the same time, the substrate is provided with a first data line DL1, a second data line DL2, and a third data line DL3, arranged along the first direction X1 and extending in the second direction X2. A column of pixel units 10 includes at least one first data line DL1, one second data line DL2, and one third data line DL3. Unlike conventional methods in which sub-pixels of different colors in the same column are driven by the same adjacent data line, in this embodiment, the first sub-pixel 11 in the first sub-column L1 and the third sub-column L3 are connected to the first data line DL1, and the third sub-pixel 13 is connected to the third data line DL3. In other words, sub-pixels of the same color in different sub-columns are driven by the same data line. This adjusts the drive signals of the first data line DL1 and the third data line DL3 to stable DC voltages, as shown in FIG. 2C , thereby reducing power consumption losses in the source driver caused by voltage jumps.

[0044] Through simulation of the driving circuit, the results show that this design is expected to reduce the power consumption of the first sub-pixel 11 / the third sub-pixel 13 by about 25% under pure color images, and can also reduce the power consumption for conventional color images.

[0045] For an OLED display panel, four sub-pixels may be used to form a light-emitting center to form a pixel unit 10 . In some embodiments, referring to FIG. 3 , a pixel unit 10 includes a first sub-pixel 11, two second sub-pixels 12, and a third sub-pixel 13. Each column of pixel units 10 corresponds to a first data line DL1, two second data lines DL2, and a third data line DL3. Each column of pixel units 10 also includes a fourth sub-column L4, and the third sub-column L3 is located between the second sub-column L2 and the fourth sub-column L4. Within the same column of pixel units 10, the second sub-pixels 12 are located in the second sub-column L2 and the fourth sub-column L4. The second sub-pixels 12 in the second sub-column L2 are electrically connected to one second data line DL2, and the second sub-pixels 12 in the fourth sub-column L4 are electrically connected to another second data line DL2. In the first sub-column L1 and the third sub-column L3, the first sub-pixels 11 and the third sub-pixels 13 are alternately arranged. That is, the first sub-pixels 11 and the third sub-pixels 13 are alternately arranged. In the first sub-column L1 and the third sub-column L3, the first sub-pixels 11 are flanked by the third sub-pixels 13 on both sides, and the third sub-pixel 13 is flanked by the first sub-pixels 11 on both sides.

[0046] For OLEDs, the first subpixel 11 can be a red subpixel R, the second subpixel 12 can be a green subpixel G, and the third subpixel 13 can be a blue subpixel B, forming an RGBG SPR pixel arrangement. It is understood that the second subpixel 12 can be a subpixel of another color, and can effectively form pixel borrowing with the first subpixel 11 and the third subpixel 13 to produce white light.

[0047] For OLED, in some embodiments, please refer to Figures 4B, 5B, 6B and 7B, each sub-pixel includes a first electrode 20 stacked on the base substrate; the first electrode 20 includes a main body 21 and a conductive block 22. For the first sub-pixel 11, the main body 21 is connected to the conductive block 22 through the first electrode trace 23A, and the conductive block 22 is connected to the first data line DL1; for the second sub-pixel 12, the main body 21 is connected to the conductive block 22 through the second electrode trace 23B, and the conductive block 22 is connected to the second data line DL2; for the third sub-pixel 13, the main body 21 is connected to the conductive block 22 through the third electrode trace 23C, and the conductive block 22 is connected to the third data line DL3.

[0048] In some embodiments, the stacked structure of the display panel may include a source / drain metal layer SD, a planarization layer (PLN), a pixel definition layer (PDL), and an electroluminescent device layer stacked in sequence. These stacked structures are described in detail below.

[0049] The source / drain metal layer SD is stacked on the base substrate. The first data line DL1, the second data line DL2, and the third data line DL3 are arranged on the source / drain metal layer SD and extend along the second direction X2. The source / drain metal layer SD can be a multi-layer structure, such as a 2SD or 3SD structure. Taking the 3SD structure as an example, the source / drain metal layer SD includes, from closest to the base substrate, a first routing layer (SD1), a second routing layer (SD2), and a third routing layer (SD3). The SD1 layer mainly serves as the source and drain of each transistor in the pixel drive circuit, as well as other connecting lines; the SD2 layer mainly functions as the switching and connection of signal lines. The SD3 layer is used to set the first data line DL1, the second data line DL2, and the third data line DL3. In addition, the SD3 layer can also set the power signal line VDD for transmitting the VDD signal. If it is a 2SD structure, the first data line DL1, the second data line DL2, and the third data line DL3 can be set on the SD2 layer.

[0050] The planarization layer is stacked on the source / drain metal layer SD and plays the role of planarization and insulation.

[0051] The pixel definition layer (PDL) is arranged on the side of the planar layer away from the base substrate, and the pixel definition layer includes: pixel openings for defining the light-emitting area of ​​the first sub-pixel 11, the light-emitting area of ​​the second sub-pixel 12, and the light-emitting area of ​​the third sub-pixel 13.

[0052] Each subpixel in the electroluminescent device layer corresponds to an electroluminescent device, comprising at least a first electrode 20, a light-emitting layer, and a second electrode. The first electrode 20 is closer to the substrate than the second electrode, meaning it is located on the side of the light-emitting layer closer to the substrate. The first electrode 20 can be either the anode or cathode of the electroluminescent device, while the second electrode is the other of the two. Unless otherwise specified, this disclosure assumes that the first electrode 20 is the anode.

[0053] The main body 21 of the first electrode 20 is the main electrode portion of the electroluminescent device, and the conductive block 22 is a connection structure for the corresponding data line. In some embodiments, the planar layer is provided with a PLN hole, and the conductive block 22 can be transferred to the SD2 layer through the PLN hole, and then transferred to the corresponding data line through the SD1 layer.

[0054] The pixel opening of the pixel defining layer exposes at least a portion of the main body 21. For example, a portion of the main body 21 overlaps with the orthographic projection of the pixel opening on the substrate, while the other portion does not overlap. For another example, the orthographic projection of the main body 21 on the substrate is located within the orthographic projection of the pixel opening on the substrate. Optionally, the main body 21 is consistent with the shape of the pixel opening corresponding to it, and the edge of the main body 21 is expanded outward by a circle for the corresponding pixel opening. The first electrode trace 23A connects the main body 21 and the conductive block 22 corresponding to the first sub-pixel 11, the second electrode trace 23B connects the main body 21 and the conductive block 22 corresponding to the second sub-pixel 12, and the third electrode trace 23C connects the main body 21 and the conductive block 22 corresponding to the third sub-pixel 13. When the first electrode 20 is an anode, the first electrode trace 23A, the second electrode trace 23B, and the third electrode trace 23C can also be referred to as anode traces.

[0055] In some embodiments, within the same column of pixel units 10, for a first sub-pixel 11 near the first data line DL1, the first electrode trace 23A connects the conductive block 22 and the end of the main portion 21 away from the first data line DL1. For a first sub-pixel 11 away from the first data line DL1, the first electrode trace 23A connects the conductive block 22 and the end of the main portion 21 near the first data line DL1. Similarly, for a third sub-pixel 13 near the third data line DL3, the third electrode trace 23C connects to the end of the main portion 21 away from the first data line DL1. For a third sub-pixel 13 away from the third data line DL3, the third electrode trace 23C connects to the end of the main portion 21 near the first data line DL1.

[0056] In some embodiments, because the first sub-pixels 11 are distributed in both the first sub-column L1 and the third sub-column L3, and the first data line DL1 is typically located near either the first sub-column L1 or the third sub-column L3, one of the sub-pixels in the first sub-column L1 or the third sub-column L3 is inevitably located further away from the first data line DL1. This results in the first sub-pixels 11 located further away from the first data line DL1 having longer first electrode traces 23A. Longer first electrode traces 23A increase resistance and capacitance (RC loading), resulting in uneven brightness of the first sub-pixels 11 in the first sub-column L1 and the third sub-column L3. Therefore, the above solution implements winding compensation for the first electrode traces 23A of the first sub-pixels 11 located near the first data line DL1. By connecting the first electrode traces 23A corresponding to the first sub-pixels 11 located near the first data line DL1 to the end of the main body 21 away from the first data line DL1, the length of the first electrode traces 23A is increased to balance the RC loading in the first sub-column L1 and the third sub-column L3.

[0057] To balance RC loading, the dimensional deviation between the first electrode trace 23A of the first sub-pixel 11 near the first data line DL1 and the first electrode trace 23A of the first sub-pixel 11 far from the first data line DL1 can be no more than 10%. This dimensional deviation includes the length deviation of the first electrode trace 23A or the area deviation of the orthographic projection of the first electrode trace 23A on the substrate. The same applies to the third electrode trace 23C. That is, the anode traces with and without routing in odd and even rows have similar lengths or areas to ensure consistency in resistance and capacitance. Ideally, the lengths or areas of the two are as close or equal as possible.

[0058] In some embodiments, an optional winding compensation method is as follows: in the same column of pixel units 10, for the first sub-pixel 11 near the first data line DL1, the first electrode trace 23A at least partially surrounds the main portion 21 and is connected to the conductive block 22. Similarly, for the third sub-pixel 13 near the third data line DL3, the corresponding third electrode trace 23C at least partially surrounds the main portion 21 and is connected to the conductive block 22.

[0059] Partially surrounding means that the first electrode trace 23A or the third electrode trace 23C is routed around a portion of the edge of the main body 21, rather than around the entire circumference of the main body 21. For example, in some embodiments, the main body 21 is a rectangular square or a rounded square, and the square main body 21 includes a first side, a second side, a third side, and a fourth side, the first side and the third side form a set of opposing sides, and the second side and the fourth side form a set of opposing sides; the first electrode trace 23A includes a first connecting portion, a first connecting line, a second connecting line, and a second connecting portion that are connected to each other, the first connecting portion connecting to the main body 21, the first connecting line is parallel or nearly parallel to the first side, the second connecting line is parallel or nearly parallel to the second side, and the second connecting portion is connected to the conductive block 22. In some embodiments, the main body 21 may also be circular or elliptical, and the first electrode trace 23A or the second electrode trace 23B may be routed around 1 / 4 or 1 / 2 of the circumference.

[0060] In some embodiments, referring to Figures 4B, 5B, 6B and 7B, the source-drain metal layer SD further includes a plurality of power signal lines VDD extending along the second direction X2 and pads Block connected to the power signal lines VDD; the pads are formed by making large-area Blocks on the source-drain metal layer SD, which can flatten the sub-pixels and improve the uniformity of light emission.

[0061] In order to more intuitively illustrate the SPR sub-pixel arrangement and corresponding winding design of the present invention, in the following embodiments, the first electrode 20 is used as the anode, the first sub-pixel 11 is the red sub-pixel R, the second sub-pixel 12 is the green sub-pixel G, and the third sub-pixel 13 is the blue sub-pixel B as an example for explanation, and for the convenience of description, the orthographic projection of the first electrode 20 of the red sub-pixel R and the blue sub-pixel B on the source-drain metal layer SD is referred to as the first orthographic projection, and the orthographic projection of the first electrode 20 of the green sub-pixel G on the source-drain metal layer SD is referred to as the second orthographic projection.

[0062] Option 1: Please refer to Figure 4A and Figure 4B. The red sub-pixel R and the blue sub-pixel B are set at the data lines, and the green sub-pixel G is set at the pad block Block. At this time, at least two of the first data line DL1, the second data line DL2 and the third data line DL3 pass through the first orthographic projection, and the second orthographic projection at least partially overlaps with the pad block Block.

[0063] In some embodiments, in the pixel arrangement of FIG4A , in the first row, the red subpixels R in the first subcolumn L1 are close to the first data line DL1 connected thereto, while the red subpixels R in the third subcolumn L3 are close to the first data line DL1 connected thereto. In the second row, the red subpixels R in the first subcolumn L1 are far from the first data line DL1 connected thereto, while the red subpixels R in the third subcolumn L3 are far from the first data line DL1 connected thereto. Therefore, for the first subcolumn L1, the first electrode trace 23A corresponding to the red subpixels R in the first row is routed, while the first electrode trace 23A corresponding to the red subpixels R in the second row is connected normally, and the cycle repeats. Similarly, for the blue subpixels B, the third electrode trace 23C corresponding to the blue subpixels B in the first row is routed, while the third electrode trace 23C corresponding to the blue subpixels B in the second row is connected normally, and the cycle repeats.

[0064] In the circuit layout of Figure 4B, the red subpixel R and blue subpixel B are located above the data lines, and the green subpixel G is located above the pad Block. The red subpixel R1 in the first row is close to the first data line DL1, and the blue subpixel B1 is close to the third data line DL3. The red subpixel R2 in the second row is away from the first data line DL1, and the blue subpixel B2 is away from the third data line DL3. Therefore, during winding compensation, the first electrode trace 23A of the red subpixel R1 in the first row partially surrounds the main body 21 of the red subpixel R1 and then connects to the conductive block 22. The third electrode trace 23C of the blue subpixel B1 in the first row partially surrounds the main body 21 of the blue subpixel B1 and then connects to the conductive block 22. The red subpixel R2 in the second row is directly connected to the conductive block 22 via the first electrode trace 23A, and the blue subpixel B2 is directly connected to the conductive block 22 via the third electrode trace 23C. No winding compensation is performed.

[0065] Optionally, referring to Figure 4B , the first data line DL1 and the second data line DL2 pass through the first orthographic projection of the first sub-column L1, and the portions within the first orthographic projection are symmetrically distributed. The third data line DL3 and the second data line DL2 pass through the first orthographic projection of the third sub-column L3, and the portions within the first orthographic projection are symmetrically distributed. Symmetrical distribution can be point symmetry or line symmetry; point symmetry means the data lines are point symmetric about the center point of the first orthographic projection, while line symmetry means the data lines are symmetrical about the axis of the first orthographic projection. This symmetrical distribution, combined with the planarization layer, further improves the flatness of the first sub-pixel 11 and the third sub-pixel 13, enhancing luminous uniformity.

[0066] To balance the anode RC loading, this solution is to keep the lengths of the wound anode traces and the unwound anode traces as consistent as possible.

[0067] Figure 4C shows the length of the first electrode trace 23A, i.e., the anode trace, corresponding to the red sub-pixel R1 in the first row, with measurements of D11 = 20.8 μm and D12 = 11.9 μm. Figure 4D shows the length of the first electrode trace 23A corresponding to the red sub-pixel R2 in the second row, with measurements of D21 = 19.2 μm and D22 = 14 μm. Figure 4E shows the length of the third electrode trace 23C corresponding to the blue sub-pixel B1 in the first row, with measurements of D31 = 73.3 μm and D32 = 18.7 μm. Figure 4F shows the length of the third electrode trace 23C corresponding to the blue sub-pixel B2 in the second row, with measurements of D41 = 72.4 μm and D42 = 18.7 μm. It can be seen that the blue sub-pixel B has a longer anode trace than the red sub-pixel R.

[0068] The RC loading of the red sub-pixels R and blue sub-pixels B was tested, and the results are shown in Table 1. It can be seen that the deviation of the RC loading between the red sub-pixels R and blue sub-pixels B in two adjacent rows is within 2%, showing good consistency.

[0069] Table 1: RC Loading values ​​for red sub-pixel R and blue sub-pixel B

[0070] Through the above-mentioned anode winding design, the anode RC loading of the red sub-pixel R and the blue sub-pixel B in odd and even rows is balanced while ensuring process capability, so that the brightness remains consistent when emitting light.

[0071] It should be noted that the pixel design in Figures 4C to 4F is based on 460PPI and a pixel pitch of 55.2μm. The above data is only for exemplary purposes. For products with different PPI, the line width, line spacing and line length of the anode trace may be different. This disclosure does not limit its specific parameters. It only aims at keeping the line length of the anode trace and the underlying circuit overlap trace consistent as much as possible when the process capability can be ensured for pixels in odd and even rows of the same color.

[0072] Solution 2: Please refer to Figures 5A and 5B. Similar to Solution 1, the red sub-pixels R and blue sub-pixels B are positioned on the data lines, and the green sub-pixels G are positioned on the pads. The difference is that the positions of the red sub-pixels R and blue sub-pixels B in each row are swapped, and the red sub-pixels R have longer first electrode traces 23A than the blue sub-pixels B, i.e., anode winding compensation. It can be understood that after the red sub-pixels R in odd and even rows have the same or similar lengths of first electrode traces 23A and the blue sub-pixels B have the same or similar lengths of third electrode traces 23C, swapping their positions does not affect the RC loading balance.

[0073] Solution 3: Please refer to Figures 6A and 6B. This solution differs from Solutions 1 and 2 in that the red and blue subpixels R and B are arranged at the spacer block, while the green subpixel G is arranged at the data line. Specifically, the first orthographic projections of the first electrodes 20 of the red and blue subpixels R and B on the source / drain metal layer SD at least partially overlap with the spacer block, and at least one of the first, second, and third data lines DL1, DL2, and DL3 passes through the second orthographic projection of the first electrode 20 of the green subpixel G on the source / drain metal layer SD. Furthermore, the red subpixel R has a longer first electrode trace 23A than the blue subpixel B, meaning that the anode winding compensation is longer.

[0074] Optionally, referring to FIG6B , the second data line DL2 and the third data line DL3 pass through the second orthographic projection of the second sub-column L2, and the portions within the second orthographic projection are symmetrically distributed. This symmetrical distribution can be point-symmetrical or line-symmetrical, and the planarization layer is used to further improve the flatness of the second sub-pixel 12, ensuring uniform light emission.

[0075] Solution 4: Please refer to Figures 7A and 7B. The same as Solution 3 is that the red sub-pixel R and the blue sub-pixel B are arranged at the pad block Block, and the green sub-pixel G is arranged at the data line. The difference from Solution 3 is that the positions of the red sub-pixel R and the blue sub-pixel B in each row are swapped, and the blue sub-pixel B has a longer anode winding compensation relative to the red sub-pixel R.

[0076] On the other hand, referring to Figures 4B and 6B, if the area where the first data line DL1, the second data line DL2, and the third data line DL3 are located on the source-drain metal layer SD is considered the first area A1, and the area where the power signal line VDD and the pad block Block are located is considered the second area A2, then the first area A1 and the second area A2 are arranged alternately in the first direction X1. Another description of anode winding compensation can be:

[0077] For solutions 1 and 2, when at least one of the first data line DL1, the second data line DL2, and the third data line DL3 passes through the first orthographic projection, that is, the red subpixel R and the blue subpixel B are located in the first area A1, for the first subpixel 11 away from the first data line DL1, the first electrode trace 23A crosses the adjacent second area A2 and is connected to the conductive block 22; for the first subpixel 11 close to the first data line DL1, the first electrode trace 23A at least partially surrounds the main body 21 and is connected to the conductive block 22;

[0078] For Scheme 3 and Scheme 4, when the first orthographic projection at least partially overlaps with the pad Block, that is, the red sub-pixel R and the blue sub-pixel B are located in the second area A2, for the first sub-pixel 11 away from the first data line DL1, the first electrode trace 23A crosses the adjacent first area A1 and is connected to the conductive block 22; for the first sub-pixel 11 close to the first data line DL1, the first electrode trace 23A at least partially surrounds the main body 21 and is connected to the conductive block 22.

[0079] In summary, the above-mentioned SPR pixel arrangement combined with the anode compensation winding design not only reduces the source driver IC's power consumption for data signals (Source), but also balances the RC loading differences between sub-pixels of the same color in odd and even rows, reducing the risk of display unevenness.

[0080] In the second aspect, based on the same inventive concept, in another optional embodiment, a display device is provided, comprising the display panel provided in the embodiment of the first aspect. The display device may be a display module comprising a display panel, or a display device comprising a display panel. The display panel may be a conventional OLED display panel, or a QD-OLED (Quantum Dot Light Emitting Diodes) display panel, an MLED display panel (including Micro-LED micro-light-emitting diodes and Mini-LED sub-millimeter light-emitting diodes), etc. The display device may be a mobile phone, a tablet computer, a monitor, a car display, a digital photo frame, a wearable display device such as a VR device, an AR device, etc., and this embodiment does not limit this.

[0081] Through one or more technical solutions of the present disclosure, the present disclosure has the following beneficial effects or advantages:

[0082] The present disclosure provides a display panel and a display device. By mixing first and third subpixels to form a column of subpixels, i.e., a portion of the first and third subpixels are arranged in the first subpixel, and a portion of the first and third subpixels are arranged in the third subpixel, a pixel-borrowing arrangement can be formed with second subpixels arranged in the second subpixel. A second subpixel can borrow the surrounding first and third subpixels to form a light-emitting center, thereby reducing the number of pixels and improving the service life of the display panel. Based on this pixel-borrowing arrangement, a conventional driving scheme is to source-drive a column of subpixels using the same adjacent data line. Because subpixels of different colors require different drive voltages, drive voltage jumps occur for different pixels on a single data line. In contrast, the present scheme uses the same data line to drive subpixels of the same type, i.e., the first subpixel is connected to the first data line, the second subpixel is connected to the second data line, and the third subpixel is connected to the third data line. The drive signals for the first and third data lines can be adjusted to stable DC voltages, thereby reducing power consumption losses in the source drive caused by voltage jumps.

[0083] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0084] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display panel, comprising: substrate substrate; as well as A plurality of pixel units arranged in an array on the substrate; Each of the pixel units includes a first sub-pixel, a second sub-pixel and a third sub-pixel, and each column of pixel units includes at least: a first sub-column, a second sub-column and a third sub-column arranged in sequence along a first direction, and in the same column of pixel units, a part of the first sub-pixels and a part of the third sub-pixels are located in the first sub-column, another part of the first sub-pixels and another part of the third sub-pixels are located in the third sub-column, and the second sub-pixels are located in the second sub-column; Each column of pixel units corresponds to a first data line, a second data line and a third data line; in the same column of pixel units, the first sub-pixel is electrically connected to the first data line, the second sub-pixel is electrically connected to the second data line, and the third sub-pixel is electrically connected to the third data line.

2. The display panel according to claim 1, wherein: One of the pixel units includes one of the first sub-pixels, two of the second sub-pixels and one of the third sub-pixels, and each column of the pixel units corresponds to one of the first data lines, two of the second data lines and one of the third data line; Each column of pixel units further includes a fourth sub-column, and the third sub-column is located between the second sub-column and the fourth sub-column; In the same column of pixel units, the second sub-pixels are located in the second sub-column and the fourth sub-column, the second sub-pixels in the second sub-column are electrically connected to one second data line, and the second sub-pixels in the fourth sub-column are electrically connected to another second data line; in the first sub-column and the third sub-column, the first sub-pixels and the third sub-pixels are alternately arranged.

3. The display panel according to claim 2, wherein: Each of the sub-pixels includes a first electrode stacked on the base substrate; The first electrode includes a main body and a conductive block. For the first sub-pixel, the main body is connected to the conductive block through a first electrode wiring, and the conductive block is connected to the first data line. For the second sub-pixel, the main body is connected to the conductive block through a second electrode wiring, and the conductive block is connected to the second data line; For the third sub-pixel, the main body is connected to the conductive block through a third electrode wiring, and the conductive block is connected to the third data line.

4. The display panel according to claim 3, wherein: In the same column of pixel units, for the first sub-pixel close to the first data line, one end of the first electrode wiring is connected to the conductive block, and the other end is connected to an end of the main body away from the first data line; For the first sub-pixel far away from the first data line, one end of the first electrode wiring is connected to the conductive block, and the other end is connected to an end of the main body close to the first data line.

5. The display panel according to claim 3, wherein: In the same column of pixel units, for the first sub-pixel close to the first data line, the first electrode wiring at least partially surrounds the main body and is connected to the conductive block.

6. The display panel according to claim 5, wherein: The main body is square, and includes a first side, a second side, a third side and a fourth side, wherein the first side and the third side form a set of opposite sides, and the second side and the fourth side form a set of opposite sides; The first electrode wiring includes a first connecting portion, a first connecting line, a second connecting line, and a second connecting portion connected to each other. The connecting portion is connected to the main body, the first connecting line is parallel to the first side, the second connecting line is parallel to the second side, and the second connecting portion is connected to the conductive block.

7. The display panel according to claim 3, wherein: The scale deviation between the first electrode routing of the first sub-pixel close to the first data line and the first electrode routing of the first sub-pixel far from the first data line does not exceed 10%; the scale deviation includes the length deviation of the first electrode routing or the area deviation of the positive projection of the first electrode routing on the substrate.

8. The display panel according to claim 3, wherein: It also includes a source-drain metal layer, the first data line, the second data line and the third data line are arranged on the source-drain metal layer and extend along a second direction; the source-drain metal layer also includes a plurality of power signal lines extending along the second direction and a pad connected to the power signal lines; the first direction intersects with the second direction; At least one of the first data line, the second data line and the third data line passes through the first orthographic projection, and the second orthographic projection at least partially overlaps with the pad; or, the first orthographic projection at least partially overlaps with the pad, and at least one of the first data line, the second data line and the third data line passes through the second orthographic projection; The first orthographic projection is the orthographic projection of the first electrodes of the first subpixel and the third subpixel on the source-drain metal layer, and the second orthographic projection is the orthographic projection of the first electrode of the second subpixel on the source-drain metal layer.

9. The display panel according to claim 8, wherein: At least two of the first data lines, the second data lines, and the third data lines are symmetrically distributed in their portions within the first orthographic projection, or are symmetrically distributed in their portions within the second orthographic projection.

10. The display panel according to claim 8, wherein: The source-drain metal layer includes a first region and a second region, the first region and the second region are arranged alternately in the first direction, the first data line, the second data line and the third data line are located in the first region, and the power signal line and the pad are located in the second region; In each column of pixel units, when at least one of the first data line, the second data line, and the third data line passes through the first orthographic projection, for the first sub-pixel far from the first data line, the first electrode routing crosses the adjacent second region and is connected to the conductive block; for the first sub-pixel close to the first data line, the first electrode routing at least partially surrounds the main body and is connected to the conductive block; When the first orthographic projection at least partially overlaps with the pad, for the first sub-pixel far away from the first data line, the first electrode routing crosses the adjacent first area and is connected to the conductive block; for the first sub-pixel close to the first data line, the first electrode routing at least partially surrounds the main body and is connected to the conductive block.

11. The display panel according to any one of claims 1 to 10, wherein: The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

12. A display device comprising the display panel according to any one of claims 1 to 11.

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