Power electronics component with vertical structure and manufacturing method

Abstract

One aspect of the invention relates to a power electronics component comprising: - a substrate (31) made from an electrically conductive material; - a stack (32) of semiconductor layers comprising: - a first semiconductor layer (321) disposed on the substrate (31) and formed from an n-type doped semiconductor material, the first semiconductor layer (321) forming a voltage withstand layer and having an n-type dopant impurity concentration of between 1014 cm-3 and 1017 cm-3; and - a second semiconductor layer (322) disposed on the first semiconductor layer (321) and formed from a p-type doped semiconductor material; the stack (32) having side walls (W) inclined by an angle (α) strictly greater than 90° relative to a surface (S) of the substrate (31) covered by the stack (32).

Description

DESCRIPTION TITLE: POWER ELECTRONIC COMPONENT WITH VERTICAL STRUCTURE AND MANUFACTURING METHOD TECHNICAL FIELD

[0001] The technical field of the invention is that of power electronics. The present invention relates to a power electronic component with a vertical structure and a method for manufacturing this component. The component may be a diode or a transistor, for example of the MOSFET (for "metal-oxide-semiconductor field-effect transistor" in English) trench type. STATE OF THE ART

[0002] A high electron mobility transistor (HEMT) is a field-effect transistor that benefits from the conduction properties of a two-dimensional electron gas (2DEG). It comprises a vertical stack of lll-N semiconductor layers on a substrate, typically silicon, silicon carbide, or sapphire. The two-dimensional electron gas is formed by a heterojunction between a channel layer, typically gallium nitride (GaN), and a barrier layer, typically aluminum gallium nitride (AIGaN).

[0003] This heterojunction transistor is called a lateral structure transistor, because the source electrode, the drain electrode and the gate electrode of the transistor are arranged on the same side of the substrate, the source electrode and the drain electrode being located on either side of the gate electrode.

[0004] The HEMT supports high on-state current densities due to the high charge carrier density and high carrier mobility in the two-dimensional electron gas. It can also exhibit high switching speed.

[0005] On the other hand, to obtain good voltage resistance in the blocked state, in other words a high breakdown voltage, a large spacing between the gate electrode and the drain electrode is necessary, which increases the size of the transistor.

[0006] A vertically structured GaN transistor, on the other hand, can have a high breakdown voltage without increasing the surface area of ​​the component, by varying the thickness of an active layer called a drift layer. This type of transistor is generally formed from a self-supporting GaN substrate.

[0007] The document [“1.8 mO.cm 2vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation”, Tohru Oka et al., Appl. Phys. Express 8, 054101, 2015] describes an example of a vertical GaN transistor, of the trench MOSFET type.

[0008] With reference to Figure 1, this transistor 10 comprises a substrate 11 made of heavily n-doped GaN (n + -GaN), a 12 drift layer of lightly n-doped GaN (n _ - GaN) arranged on a first face 11 a of the substrate 11, a channel layer 13 of p-doped GaN (p-GaN) arranged on the drift layer 12 and a source contact layer 14 of heavily n-doped GaN (n +-GaN) disposed on the channel layer 13. A source electrode 15 is disposed on the source contact layer 14, while a drain electrode 16 is disposed on a second opposite face 11b of the substrate 11. Finally, a gate dielectric layer 17a and a gate electrode 17b are disposed at the bottom and against the side walls of a trench 18. The trench 18 extends to the drift layer 12 through the channel layer 13 and the source contact layer 14.

[0009] Transistor 10 in Figure 1 has a high breakdown voltage, of the order of 1.2 kV, and a small footprint. On the other hand, it is expensive to manufacture mainly due to the use of a self-supporting GaN substrate.

[0010] The use of low-cost substrates known as foreign (to the III-N semiconductor family), such as silicon substrates, would make it possible to manufacture high-performance power electronic components on large diameter wafers (200 mm, or even 300 mm) and therefore considerably reduce the manufacturing cost of these components.

[0011] The article [“Gallium nitride vertical power devices on foreign substrates: a review and outlook”, Yuhao Zhang et al., J. Phys. D: Appl. Phys., Vol. 51, 273001, 2018] describes several power devices formed from silicon or sapphire (AI2O3) substrates, in particular a GaN diode with a vertical structure and GaN transistors with quasi-vertical structure, of the trench MOSFET type and of the FinFET type (“fin field-effect transistor” in English).

[0012] Figure 2 illustrates the main steps of the manufacturing process of the vertical structure GaN diode 20, described in detail in the article [“High-Performance 500 V Quasi- and Fully-Vertical GaN-on-Si pn Diodes”, Yuhao Zhang et al., IEEE Electron Device Letters, Vol. 38, No. 2, pp. 248-251, 2016]. The manufacturing process comprises in particular the following steps: the growth, from a silicon substrate 21, of a stack successively comprising buffer layers 22, a semi-insulating GaN layer 23, a heavily n-doped GaN layer (n + -GaN) 24, a layer of lightly n-doped GaN (n _-GaN) 25 and a p-doped GaN (p-GaN) layer 26; etching the stack down to the substrate 21 to form an island called a mesa; forming an anode 27 (Ni / Au ohmic contact) on the p-GaN layer 26; flipping and bonding the anode-side stack 27 to a transfer substrate 31 (made of silicon) covered with metal layers 32; and removing the growth substrate 21, the buffer layers 22 and the semi-insulating GaN layer 23; and forming a cathode 28 (Ti / Al ohmic contact) on the n-GaN layer + - GaN 24.

[0013] This GaN on silicon diode, however, has a much lower breakdown voltage than its equivalent formed from a GaN substrate, of the order of 520 V. SUMMARY OF THE INVENTION

[0014] There is therefore a need to provide a power electronic component that is inexpensive to manufacture and has better voltage resistance than the components of the prior art.

[0015] According to a first aspect of the invention, this need is met by providing a power electronic component comprising: a substrate made of an electrically conductive material; a stack of semiconductor layers comprising: a first semiconductor layer arranged on the substrate and formed of an n-type doped semiconductor material, the first semiconductor layer forming a voltage-withstanding layer and having a concentration of n-type doping impurities of between 10 14 cm -3 and 10 17 cm -3 ; and a second semiconductor layer disposed on the first semiconductor layer and formed of a p-type doped semiconductor material.

[0016] This power electronic component is remarkable in that the stack has side walls inclined at an angle strictly greater than 90° relative to a surface of the substrate covered by the stack.

[0017] The inclination of the side walls gives the stack a flared shape. This geometry is advantageous for component voltage resistance, as it reduces the electric field at the surface of the side walls and moves the breakdown location of the component inside the stack.

[0018] In a first embodiment, the component further comprises: a source electrode disposed on the second semiconductor layer; a gate structure extending to the first semiconductor layer through the second semiconductor layer, the gate structure comprising a gate electrode and a gate dielectric layer; and the substrate forms a drain electrode.

[0019] According to a development of this first embodiment, the stack further comprises a source contact layer arranged between the source electrode and the second semiconductor layer.

[0020] According to another development compatible with the previous one, the stack further comprises a drain contact layer arranged between the substrate and the first semiconductor layer.

[0021] In a second embodiment: the second semiconductor layer is structured in patterns; the source electrode comprises several portions, each source electrode portion being arranged on a pattern; and the gate structure comprises several portions intermingled with the patterns.

[0022] In a third embodiment, the component further comprises patterns of semiconductor material arranged on the first semiconductor layer and wherein the second semiconductor layer comprises portions intermingled with the patterns, the component further comprising: a source electrode comprising several portions, each source electrode portion being arranged on a pattern; a gate electrode comprising several portions, each gate electrode portion being arranged on a portion of the second semiconductor layer; and wherein the substrate forms a drain electrode.

[0023] In a fourth embodiment, the component comprises an anode disposed on the second semiconductor layer and the substrate forms a cathode.

[0024] In a fifth embodiment, the component comprises an anode extending to the first semiconductor layer through the second semiconductor layer and the substrate forms a cathode, the anode being in Schottky contact with the first semiconductor layer.

[0025] According to a development of the fourth or fifth embodiment, the stack further comprises a layer of heavily doped n-type semiconductor material disposed between the substrate and the first semiconductor layer.

[0026] The component according to the first aspect of the invention may also have one or more of the following characteristics, considered individually or in all technically possible combinations: the angle of inclination of the side walls is between 110° and 160°. the first semiconductor layer has a thickness greater than or equal to 3 pm, preferably greater than or equal to 10 pm; the component further comprises a metal layer arranged between the substrate and the stack; the substrate is made of metal; the component further comprises a passivation layer covering the side walls of the stack; the component further comprises a dielectric layer arranged on the substrate and coating the stack; and the component forms a transistor, a PN junction diode or a Schottky diode.

[0027] A second aspect of the invention relates to a method for manufacturing a power electronic component, comprising the following steps: forming a stack of semiconductor layers on a growth substrate, by successively growing by selective epitaxy a first semiconductor layer made of a p-type doped semiconductor material and a second voltage-withstanding semiconductor layer made of an n-type doped semiconductor material, such that the stack has side walls inclined at an angle strictly less than 90° relative to a surface of the growth substrate covered by the stack, the second voltage-withstanding semiconductor layer having a concentration of n-type doping impurities of between 10 14 cm -3 and 10 17 cm -3 ; depositing a metal layer on the stack; bonding the metal layer to a transfer substrate made of a conductive material; and remove the growth substrate.

[0028] In a preferred embodiment, the method further comprises, between the step of forming the stack and the step of depositing the metal layer, the following steps: forming a passivation layer on the side walls of the stack; and coating the stack with a dielectric layer.

[0029] The transfer substrate is preferably made of metal, for example copper.

[0030] The growth substrate is advantageously made of silicon, silicon carbide or sapphire.

[0031] Preferably, the growth substrate and the transfer substrate are wafers and the bonding between the metal layer and the transfer substrate is accomplished at the wafer scale.

[0032] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0033] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the following figures:

[0034] Figure 1, previously described, is a sectional view of a vertically structured field effect transistor according to the prior art;

[0035] Figure 2, previously described, illustrates the main steps of manufacturing a diode with a vertical structure according to the prior art;

[0036] Figure 3 is a schematic sectional view of a power electronic component according to a first embodiment of the invention;

[0037] Figure 4 is a schematic sectional view of a power electronic component according to a second embodiment of the invention;

[0038] Figure 5 is a schematic sectional view of a power electronic component according to a third embodiment of the invention;

[0039] Figure 6 is a schematic sectional view of a power electronic component according to a fourth embodiment of the invention; and

[0040] Figures 7A to 7G represent steps of a method of manufacturing the power electronic component of Figure 3.

[0041] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0042] Figures 3 to 6 show in schematic sectional view different embodiments of a power electronic component 30. The component 30 can be a transistor (see Figs. 3-5) or a PN junction diode (see Fig. 6). It can switch reversibly between a first state called “on state” (or “ON state”) and a second state called “off state” (or “OFF state”). It can be used in many electronic devices, such as a power electronic module to produce an energy conversion circuit (e.g., a step-down or step-up converter or a direct current - alternating current converter).

[0043] In a manner common to all these embodiments, the component 30 comprises: a substrate 31 made of an electrically conductive material; a stack 32 of semiconductor layers comprising at least: a first semiconductor layer 321 arranged on the substrate 31; a second semiconductor layer 322 arranged on the first semiconductor layer 321.

[0044] The substrate 31 may be made of metal, for example copper, or a degenerate semiconductor material, for example degenerate silicon. It may also comprise a layer of metal on a layer of degenerate semiconductor material (e.g. titanium on degenerate silicon).

[0045] The first semiconductor layer 321, called drift layer or voltage withstand layer, is made of a material n-type doped semiconductor, and preferably an n-doped III-N semiconductor material such as n-doped gallium nitride (n-GaN). The concentration of n-type doping impurities in the first semiconductor layer 321 is advantageously between 10 14 cm' 3 and 10 17 cm' 3 , for example equal to 10 16 cm' 3 .

[0046] The thickness of the first semiconductor layer 321 is advantageously greater than or equal to 3 μm, preferably greater than or equal to 10 μm, in order to give the component 30 good voltage resistance (drain-source voltage VDS in the case of a transistor), for example of at least 1000 V.

[0047] The second semiconductor layer 322, also called the channel layer in the case of a transistor (i.e. the layer in which the conduction channel of the transistor is formed), is made of a p-type doped semiconductor material, and preferably a p-doped III-N semiconductor material such as p-doped gallium nitride (p-GaN). The thickness of the second semiconductor layer 322 may be between 200 nm and 1000 nm.

[0048] The second semiconductor layer 322 is preferably in direct contact with the first semiconductor layer 321. In other words, the stack 32 comprises a PN junction.

[0049] The semiconductor material of the second semiconductor layer 322 is preferably identical to the semiconductor material of the first semiconductor layer 321. Thus, the PN junction is a homojunction.

[0050] The component 30 comprises at least two electrodes: a first electrode formed by the substrate 31 made of electrically conductive material and a second electrode 33 arranged on the second semiconductor layer 322, opposite the substrate 31. The component 30 thus has a vertical structure, more advantageous in terms of size and / or conductivity in the on state than the horizontal and quasi-vertical structures.

[0051] The second electrode 33 is preferably made of metal, for example TiN or TiN on Ti (bilayer).

[0052] For a component 30 of the PN junction transistor or diode type, the first electrode (substrate 31) is in ohmic contact with the first semiconductor layer 321 (n-type), while the second electrode 33 is in ohmic contact with the second semiconductor layer 322 (p-type)

[0053] The component 30 may also comprise a metal layer 34 arranged between the substrate 31 and the stack 32. This metal layer 34, for example made of titanium (Ti) or formed from a titanium on aluminum bilayer (Ti / AI) improves the quality of the electrical contact between the substrate 31 (first electrode) and the first semiconductor layer 321.

[0054] To obtain a low-resistive (ohmic) contact with the first electrode (substrate 31) and / or with the second electrode 33, the stack 32 of semiconductor layers may further comprise: a third semiconductor layer 323 made of a heavily doped n-type semiconductor material and arranged between the substrate 31 and the first semiconductor layer 321, (the third semiconductor layer 323 thus becoming the first layer of the stack 32, starting from the substrate 31; cf. Figs. 3-6); and / or a fourth semiconductor layer 324 made of a heavily doped n-type semiconductor material and arranged between the second electrode 33 and the second semiconductor layer 322 (as the last layer of the stack 32; cf. Figs. 3-4).

[0055] A heavily doped n-type semiconductor material herein refers to a material having an n-type doping impurity concentration of between 10 17 cm' 3 and 10 20cm' 3 , for example equal to 10 18 cm' 3 .

[0056] The third and fourth semiconductor layers 323-324 are preferably made of a heavily n-doped III-N semiconductor material, for example heavily n-doped gallium nitride (n + -GaN).

[0057] The second electrode 33 is then, at least in part, separated from the second semiconductor layer 322 by the fourth semiconductor layer 324. Although this is not shown in the figures, the second electrode 33 may extend partly through the fourth semiconductor layer 324 to the second semiconductor layer 322, in order to be able to polarize the latter (instead of leaving it floating).

[0058] As illustrated in Figures 3 to 6, the stack 32 has side walls (or flanks) W inclined relative to a surface S of the substrate 31 covered by the stack 32. The surface S of the substrate 31 covered by the stack 32 is the portion of the surface of the substrate 31 located on the inner side of the side walls W. The angle of inclination a of the side walls W, that is to say the angle formed between the surface S of the substrate 31 and each of the side walls W of the stack 32 (measured in the trigonometric direction), is strictly greater than 90°.

[0059] Thus, the stack 32 has a flared shape. Inclined side walls W have the effect of reducing the amplitude of the electric field at the surface of these walls, at the level of the depletion zone (also called space charge zone) of the PN junction. This results in a displacement of the breakdown location of the component, from the surface to the volume of the stack 32, and therefore an increase in the breakdown voltage, as explained in the reference work [“Fundamentals of Power Semiconductor Devices”, B. Jayant Baliga, Springer 2019, Chap.3. Breakedown Voltage, pp.139-140],

[0060] The angle of inclination a of the side walls W is preferably strictly greater than 95° and more preferably still between 110° and 160°, in order to significantly reduce the electric field at the walls at the location of the PN junction.

[0061] Furthermore, the component 30 comprises a passivation layer 35 covering the side walls W of the stack 32. The passivation layer 35 reduces the parasitic conduction paths (and therefore the leakage currents) and further improves the breakdown voltage of the component 30. It can be formed of a dielectric layer, for example made of alumina (AI2O3), a stack of dielectric sub-layers or a depleted PN junction (therefore a stack comprising an n-doped semiconductor layer and a p-doped semiconductor layer).

[0062] Finally, the component 30 may comprise a dielectric layer 36 arranged on the substrate 31 and which coats the stack 32 and the passivation layer 35, if applicable. The dielectric layer 36 is for example made of silicon dioxide (SiO 2 ).

[0063] In the first embodiment shown in Figure 3, the component 30 is a trench MOSFET type transistor. The first electrode, formed by the substrate 31, is a drain electrode and the second electrode 33 is a source electrode. In addition to the drain and source electrodes, the transistor comprises a gate structure 37, of the MOS (Metal-Oxide-Semiconductor) type.

[0064] The gate structure 37 comprises a gate dielectric layer and a gate electrode separated, at least laterally, from the semiconductor layers of the stack 32 by the gate dielectric layer. The gate dielectric layer is for example made of silicon dioxide (SiC>2), aluminum oxide (AI2O3), aluminum nitride (AIN) or silicon nitride (SiN). It may comprise several sub-layers formed from these dielectric materials. The gate electrode is preferably made of metal, for example titanium nitride (TiN).

[0065] Preferably, the stack successively comprises (starting from the substrate 31) the third semiconductor layer 323 (e.g. n + -GaN), the first semiconductor layer 321 (e.g. n-GaN), the second semiconductor layer 322 (e.g. p-GaN) and the fourth semiconductor layer 324 (e.g. n + -GaN). The third semiconductor layer 323 forms a drain contact layer and the fourth semiconductor layer 324 forms a source contact layer.

[0066] The gate structure 37 is arranged in a trench 38, which extends to the first semiconductor layer 321 through the second semiconductor layer 322 and, here, the source contact layer 324.

[0067] The source electrode 33 and the gate electrode may each comprise several portions. The portions of the same electrode are electrically connected to each other in order to be subjected to the same electrical potential. For the sake of clarity, only one portion of the gate electrode and two portions of the source electrode 31, arranged on either side of the portion of the gate electrode, have been shown in FIG. 3. The portions of the source electrode 33 are advantageously intermingled (or nested) with the portions of the gate electrode in order to reduce the resistance of the transistor in the on state. Several arrangements (“layout” in English) are possible for the source electrode and the gate electrode: interdigitated combs, hexagonal cell structures as described in the document [“1.8 mO.cm 2vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation”, Tohru Oka et al., Appl. Phys. Express 8, 054101, 2015]...

[0068] In the second embodiment shown in Figure 4, the component 30 is also a transistor, but of the FinFET type. The FinFET transistor of Figure 4 differs from the trench MOSFET transistor of Figure 3 essentially in that the second semiconductor layer 322 (i.e. the channel layer) and the source contact layer 324 are structured in patterns commonly called fins. These patterns may have different shapes in top view, for example a rectangular, hexagonal, circular, annular shape, etc. The source electrode 33 comprises several portions (electrically connected to each other), each source electrode portion being arranged on a fin. The gate structure 37 also comprises several portions (electrically connected to each other) intermingled with the patterns of the second semiconductor layer 322 (depending on the arrangement chosen: interdigitated combs, hexagonal cell structures, etc.).In the sectional view of Figure 4, each portion of the gate structure 37 is disposed (in a trench 38) between two fins (and includes a gate electrode portion separated from said fins by a portion of the gate dielectric layer).

[0069] The second p-doped 322 semiconductor layer, although optional in a FinFET, gives the transistor a higher threshold voltage VTH.

[0070] In the third embodiment represented by FIG. 5, the component 30 is a JFET type transistor (junction field-effect transistor). The component 30 comprises patterns 325 made of semiconductor material arranged on the first semiconductor layer 321. Each pattern 325 is advantageously surmounted by a portion 326 of a source contact layer (made of highly n-doped semiconductor material, for example n +-GaN) and by a portion of the source electrode 33. The patterns 325 are advantageously formed in the second semiconductor layer 322 by passivating (locally) the p-type doping impurities, thus giving the semiconductor material an intrinsic behavior.

[0071] The second semiconductor layer 322 comprises several distinct portions. The portions of the second semiconductor layer 322 are intermingled with the patterns 325. In the sectional view of FIG. 5, the portions of the second semiconductor layer 322 are separated two by two by a pattern 325 and each surmounted by a gate electrode portion 37'.

[0072] In the fourth embodiment shown in Figure 6, the component 30 is a PN junction diode. The first electrode, formed by the substrate 31, is a cathode and the second electrode 33 is an anode.

[0073] Unlike the Zener diode or the avalanche diode, the PN junction diode only conducts under forward bias ("ON" state). It is blocked under reverse bias ("OFF" state). This type of diode operates in switching mode and can be used to create a current rectifier circuit.

[0074] Finally, in a fifth embodiment not shown, the component 30 is a Schottky diode. The first electrode (cathode) is formed by the substrate 31 and the second electrode (the anode) passes through the second semiconductor layer 322 to reach the first semiconductor layer 321 (in the manner of the gate structure 37 of FIG. 3), rather than being disposed on the second semiconductor layer 322. The second electrode is in Schottky contact with the first semiconductor layer 321 (and not ohmic with the second semiconductor layer 322).

[0075] Preferably, the stack 32 of the PN junction diode (Fig. 6) or of the Schottky diode successively comprises (starting from the substrate 31) the third semiconductor layer 323 (e.g. n + -GaN), the first semiconductor layer 321 (eg n-GaN) and the second semiconductor layer 322 (eg p-GaN).

[0076] A preferred embodiment of a method for manufacturing the component 30 will now be described with reference to FIGS. 7A to 7G, taking as an example the trench MOSFET transistor of FIG. 3. In this method, it is considered that the component 30 comprises the third and fourth semiconductor layers 323-324 (drain and source contact layers). However, one or both of these layers could be omitted.

[0077] Figures 7A to 7G schematically represent steps S1 to S7 of the manufacturing process.

[0078] Step S1 illustrated by FIG. 7A consists of forming the stack 32 of semiconductor layers on a growth substrate 70. The growth substrate 70 is advantageously a low-cost substrate, for example made of silicon, silicon carbide or sapphire. It is preferably covered with one or more buffer layers 71, making it possible to adapt the mesh mismatch between the growth substrate 70 and the semiconductor layers of the stack 32 and thus minimize the number of growth defects.

[0079] A first particularity of this step S1 is that the stack 32 is formed by growing the semiconductor layers by epitaxy in the reverse order to that described with reference to FIGS. 3 to 6 (which is also the conventional growth order). Thus, in this preferred mode of implementation of the manufacturing method, the fourth highly n-doped semiconductor layer 324 (e.g. n +-GaN), the second p-doped semiconductor layer 322 (e.g. p-GaN), the first n-doped semiconductor layer 321 (e.g. n-GaN) and, finally, the third heavily n-doped semiconductor layer 323 (e.g. n + -GaN).

[0080] A second particularity of this step S1 is the use of a selective epitaxy technique commonly called SAE (for “selective area epitaxy” in English). According to this technique, the growth of the semiconductor layers of the stack 32 is localized in one or more predefined regions of the growth substrate 70, and not on its entire surface. This technique may comprise the formation of a mask (not shown) on the surface of the growth substrate 70, before or after the growth of the buffer layer(s) 71, and the growth of the semiconductor layers of the stack 32 in the recess(es) of this mask. The number of stacks 32 obtained on the growth substrate 70 is equal to the number of recesses of the mask. Thus, it is possible to form several stacks 32 called “islands” simultaneously, these stacks 32 belonging to different components or to the same component.The mask is formed from a material capable of withstanding growth temperatures, generally above 1000°C. This is typically a dielectric material, for example aluminum oxide (AIOx).

[0081] It is also possible, after the growth of the buffer layer(s) 71, to etch (through a mask) the buffer layer 71 down to the growth substrate 70 to form the islands, before resuming the growth of the other semiconductor layers only on these islands. This option releases the stress in the islands, and gives the possibility of making wider islands without cracks.

[0082] A selective epitaxy technique is notably described in the article [“Selective-area growth study of GaN micropillars for quasi-vertical Schottky diodes”, A. Debald et al., Semicond. Sci. Technol., Vol. 36, 034005, 2021] for the fabrication of a Schottky diode with a quasi-vertical structure.

[0083] Epitaxial growth gives each stack 32 or island a truncated cone shape, with inclined side walls W (also called facets). The side walls W are inclined relative to a surface S' of the growth substrate 70 covered by the stack 32 by an angle a' strictly less than 90°, preferably strictly less than 85° and even more preferably between 20° and 70°. The angle a' of inclination of the side walls W of the stack 32 on the growth substrate 70 satisfies the following relationship:

[0084] [Math 1] a' = 180 — a

[0085] where a is the angle of inclination of the side walls W of the stack 32 on the substrate 31 made of electrically conductive material (Figs.3-6).

[0086] The formation in island(s) also makes it possible to reduce the stresses of the epitaxial layers induced by growth and then cooling and consequently to increase the thickness of the epitaxial layers compared to conventional epitaxy (“full wafer”). This is particularly interesting for the first semiconductor layer 321, or drift layer, which ensures the voltage resistance of the component. Thus, a drift layer 321 with a thickness greater than 3 pm, preferably greater than or equal to 10 pm, and with low stress can be obtained.

[0087] Finally, the formation of island(s) makes it easier to activate the second semiconductor layer 322 (for example in p-GaN) after the growth step S1, by allowing the hydrogen contained in this layer to escape from the sides.

[0088] Step S2 of Figure 7B is an optional step consisting of forming the passivation layer 35 on the side walls W of the stack 32.

[0089] In step S3 of FIG. 7C, the stack 32 is coated with the dielectric layer 36. The coating of the stack 32 may comprise a step of depositing a dielectric material until the stack 32 is completely covered, then a planarization step (for example by chemical-mechanical polishing) so that the dielectric layer 36 forms a flat surface with the upper face of the stack 32. The upper face of the stack 32 is formed by the semi-conductor layer epitaxied last, here the third semi-conductor layer 323.

[0090] Then, in S4 (see Fig. 7D), the metal layer 34 is formed on the stack 32. The metal layer 34 is here in contact with the third semiconductor layer 323. The metal layer 34 can cover both the stack 32 and the dielectric layer 36 or only the stack 32, as shown in FIG. 7D.

[0091] It is also possible to deposit the metal layer 34 on the passivation layer 35 and the upper face of the stack 32, before the step of coating with the dielectric layer 36. A planarization step is then carried out so that the dielectric layer 36 forms a flat surface with the portion of the metal layer 34 arranged on the upper face of the stack 32.

[0092] With reference to Figure 7E, the method for manufacturing the component 30 then comprises a step S5 of bonding the stack 32, via the metal layer 34, to the substrate 31 made of conductive material. This substrate 31, called the transfer substrate, is advantageously made of metal, for example copper, in order to improve the heat dissipation of the component 30 and the electrical conductivity of the first electrode (drain electrode in the example of the transistor). The bonding is then of the direct metal-metal type (without adding material). As shown, the bonding can be carried out after turning over the stack 32 (and the growth substrate 70 which supports it).

[0093] Then, in step S6 of FIG. 7F, the growth substrate 70 and the buffer layer 71 are removed so as to expose the stack 32, and more particularly the semiconducting layer epitaxied first, here the fourth semiconducting layer 324. The majority of the growth substrate 70 can be removed by grinding, by laser liftoff or by a technique called spalling and described in the document [“Kerf-less removal of Si, Ge, and 111—V layers by controlled spalling to enable low-cost PV technologies”, Stephen W. Bedell et al., IEEE Journal of Photovoltaics, Vol. 2, No. 2, pp. 141-147, 2012], Then, the remaining portion of the growth substrate 70 and the buffer layer 71 are removed by dry etching, to avoid damaging the electrically active layers.

[0094] Step S7 shown in Figure 7G relates to the formation of the second electrode 33 (source electrode) on the exposed surface of the stack (here the fourth semiconductor layer 324) and a gate structure 37 in the case of a transistor.

[0095] In the example of the MOSFET transistor, the gate structure 37 is a MOS gate structure comprising a gate dielectric layer and a gate electrode (separated at least laterally from the semiconductor layers by the gate dielectric layer). Its formation preferably comprises the following steps: the formation of a trench 38 extending to the first semiconductor layer 321, preferably by etching the fourth semiconductor layer 324, the second semiconductor layer 322 and possibly a surface portion of the first semiconductor layer 32T; the formation of the gate dielectric layer at least against the side walls of the trench 38, the bottom of the trench 38 being able to be covered by a so-called passivation layer made of an electrically insulating material; the filling of the trench 38 with an electrically conductive material, preferably a metal, to form the gate electrode.

[0096] To manufacture the FinFET type transistor of FIG. 4, step S7 comprises etching several trenches 38 through the fourth semiconductor layer 324 and the second semiconductor layer 322, so as to structure these layers in the form of fins, then forming the different portions of the source electrode 33 on the fins. The gate dielectric layer and the gate electrode are then formed in the different trenches 38 as described previously.

[0097] The method for manufacturing the JFET type transistor of Figure 5 comprises steps S1-S6 of Figures 7A-7H, with the difference that the stack 32 of epitaxial layers in step S1 is devoid of the fourth semiconductor layer 324. The manufacturing method then comprises a step of passivating the p-type doping impurities (e.g., magnesium ions) in regions of the second semiconductor layer 322, to form the patterns 325 made of semiconductor material (with intrinsic behavior), and preferably a step of implanting n-type doping impurities to form the portions 326 of the source contact layer located on the patterns 325. The doping impurities of p-type are preferably passivated (i.e., made inactive) by implantation of hydrogen ions. The source electrode 33 and gate electrode 37' portions are then formed, respectively, on the portions 326 of the source contact layer and on the portions of the second semiconductor layer 322.

[0098] In the case of the PN junction diode (see Fig. 6), the stack 32 of epitaxial layers in step S1 is also devoid of the fourth semiconductor layer 324 and only the second electrode 33 (anode) is formed on the stack 32 during step S7.

[0099] In the case of the Schottky junction diode, a trench extending to the first semiconductor layer 321 is formed, preferably by etching the second semiconductor layer 322 and possibly a surface portion of the first semiconductor layer 321, then the trench is filled with a metal making it possible to form a Schottky contact with the first semiconductor layer 321.

[0100] Whatever the component, the manufacturing method may also include a step of forming a contact pad on the rear face of the transfer substrate 31, to facilitate the subsequent connection of the component after it has been packaged.

[0101] When several islands or stacks 32 have been formed simultaneously in the selective epitaxy step S1, the passivation layer 35 is advantageously formed (in step S2) so as to cover the side walls of each stack 32. The dielectric layer 36 (step S3) also coats each stack 32. Finally, the metal layer 34 is formed on all the stacks 32. The metal layer 34 is preferably a solid layer which also covers the dielectric layer 36. The transfer substrate 31 forms a (first) electrode common to the different stacks 32.

[0102] The method for manufacturing the component 30 may further comprise a step of electrically connecting the stacks 32 in parallel. The step of electrically connecting the stacks 32 takes place after the step S7 of forming the second electrode 33 on each stack 32, by electrically connecting the second electrodes 33 together. In the case of a transistor, the gate electrodes are also electrically connected together.

[0103] The growth substrate 70 and the transfer substrate 31 are advantageously wafers which allow the manufacturing of several components 30 simultaneously. These wafers preferably have a disc shape. The bonding of FIG. 7E is advantageously carried out at the scale of these wafers (so-called “wafer-to-wafer” bonding), and not at the scale of a component (so-called “chip-to-wafer” bonding).

Claims

CLAIMS

1. Power electronic component (30) comprising: - a substrate (31) made of an electrically conductive material; - a stack (32) of semiconductor layers comprising: o a first semiconductor layer (321) arranged on the substrate (31) and formed of an n-type doped semiconductor material, the first semiconductor layer (321) forming a voltage-withstanding layer and having a concentration of n-type doping impurities of between 10 14 cm' 3 and 10 17 cm' 3 ; and o a second semiconductor layer (322) arranged on the first semiconductor layer (321) and formed from a p-type doped semiconductor material; characterized in that the stack (32) has side walls (W) inclined at an angle (a) strictly greater than 90° relative to a surface (S) of the substrate (31) covered by the stack (32).

2. Component (30) according to claim 1, wherein the angle (a) of inclination of the side walls (W) is between 110° and 160°.

3. Component (30) according to one of claims 1 and 2, in which the first semiconductor layer (321) has a thickness greater than or equal to 3 pm, preferably greater than or equal to 10 pm.

4. Component (30) according to any one of claims 1 to 3, further comprising a metal layer (34) disposed between the substrate (31) and the stack (32).

5. Component (30) according to any one of claims 1 to 4, wherein the substrate (31) is made of metal.

6. A component (30) according to any one of claims 1 to 5, further comprising: - a source electrode (33) arranged on the second semiconductor layer (322); a gate structure (37) extending to the first semiconductor layer (321) through the second semiconductor layer (322); and wherein the substrate (31) forms a drain electrode.

7. The component (30) of claim 6, wherein the stack (32) further comprises a source contact layer (324) disposed between the source electrode (33) and the second semiconductor layer (322).

8. Component (30) according to one of claims 6 and 7, wherein the stack (32) further comprises a drain contact layer (323) disposed between the substrate (31) and the first semiconductor layer (321).

9. Component (30) according to any one of claims 6 to 8, wherein: - the second semiconductor layer (322) is structured in patterns; - the source electrode (33) comprises several portions, each source electrode portion being arranged on a pattern; and - the grid structure (37) comprises several portions intermingled with the patterns.

10. A component (30) according to any one of claims 1 to 5, further comprising patterns (325) of semiconductor material arranged on the first semiconductor layer (321) and wherein the second semiconductor layer (322) comprises portions intermingled with the patterns (325), the component further comprising: - a source electrode (33) comprising several portions, each source electrode portion being arranged on a pattern (325); - a gate electrode (37') comprising several portions, each gate electrode portion being arranged on a portion of the second semiconductor layer (322); and wherein the substrate (31) forms a drain electrode.

11. A component (30) according to any one of claims 1 to 5, further comprising an anode (33) disposed on the second semiconductor layer (322) and wherein the substrate (31) forms a cathode.

12. A component (30) according to any one of claims 1 to 5, further comprising an anode (33) extending to the first semiconductor layer (321) through the second semiconductor layer (322), the anode being in Schottky contact with the first semiconductor layer (321), and wherein the substrate (31) forms a cathode.

13. Component (30) according to one of claims 11 and 12, wherein the stack further comprises a layer of heavily doped n-type semiconductor material (323) disposed between the substrate (31) and the first semiconductor layer (321).

14. Component (30) according to any one of claims 1 to 14. 13, further comprising a passivation layer (35) covering the side walls (W) of the stack (32).

15. Component (30) according to any one of claims 1 to 15. 14, further comprising a dielectric layer (36) disposed on the substrate (31) and coating the stack (32).

16. Component (30) according to any one of claims 1 to 16. 15, forming a transistor, a PN junction diode or a Schottky diode.

17. A method of manufacturing a power electronic component (30), comprising the following steps: - forming (S1) a stack (32) of semiconductor layers on a growth substrate (70), by successively growing by selective epitaxy a semiconductor layer (322) in a p-type doped semiconductor material and a voltage-withstanding semiconductor layer (321) in an n-type doped semiconductor material, so that the stack (32) has side walls (W) inclined at an angle (a') strictly less than 90° relative to a surface (S') of the growth substrate (70) covered by the stack (32), the voltage-withstanding semiconductor layer (321) having a concentration of n-type doping impurities of between 10 14 cm -3 and 10 17 cm -3 ; - depositing (S4) a metal layer (34) on the stack (32); - bonding (S5) the metal layer (34) to a transfer substrate (31) made of a conductive material; and - remove (S6) the growth substrate (70).

18. Method according to claim 17, further comprising, between the step (S1) of forming the stack (32) and the step (S4) of depositing the metal layer (34), the following steps: - forming (S2) a passivation layer (35) on the side walls (W) of the stack (32); and - coating (S3) the stack (32) with a dielectric layer (36).

19. Method according to one of claims 17 and 18, in which the transfer substrate (31) is made of metal.

20. A method according to any one of claims 17 to 19, wherein the growth substrate (70) is silicon, silicon carbide or sapphire.

21. A method according to any one of claims 17 to 20, wherein the growth substrate (70) and the transfer substrate (31) are wafers and wherein the bonding between the metal layer (34) and the transfer substrate (31) is accomplished at the wafer scale.

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