Vapor deposition mask and method for manufacturing electronic device

Abstract

The objective of the present invention is to provide a vapor deposition mask of which occurrence of breakage is suppressed, and a method for manufacturing an electronic device using the vapor deposition mask. A vapor deposition mask according to the present invention is disposed between a substrate to be vapor-deposited and a vapor deposition source and allows deposition of a vapor deposition material from the vapor deposition source on the surface of the substrate to be vapor-deposited through openings. The vapor deposition mask is characterized by comprising a membrane having an opening region provided with a plurality of openings and a peripheral region positioned around the opening region, and a support substrate for supporting the membrane in the peripheral region, in which the side surface of the support substrate includes a tapered surface in which the taper angle between the side surface of the support substrate and the opposing surface of the membrane facing the support substrate is less than 80°.

Description

Evaporation mask and method for manufacturing electronic device

[0001] The present invention relates to a deposition mask and a method for manufacturing an electronic device.

[0002] For example, a deposition mask is known that is used to paint three colors, RGB, in the production of organic EL displays.

[0003] Patent Documents 1 and 2 disclose deposition masks having a first layer (outer frame substrate) and a second layer (mask substrate). A plurality of openings are formed in the second layer (mask substrate). The first layer (outer frame substrate) is a substrate that supports the second layer (mask substrate).

[0004] International Publication No. 2023 / 145955 Japanese Patent Application Laid-Open No. 2022-175723

[0005] In order to increase the definition of deposition masks, it is necessary to make the masks thinner and process them with high precision. However, this has led to the problem that the deposition masks are prone to breakage during handling, cleaning, etc. during the manufacturing process.

[0006] Patent Documents 1 and 2 do not solve the above-mentioned problems by improving the shape of the first layer (outer frame substrate).

[0007] An object of the present invention is to provide a deposition mask that is less susceptible to breakage, and a method for manufacturing an electronic device using the deposition mask.

[0008] The deposition mask of the present embodiment is a deposition mask that is disposed between a substrate to be deposited and a deposition source, and that deposits a deposition material from the deposition source onto a surface of the substrate to be deposited through openings, and that includes a membrane having an opening region with a plurality of the openings and a peripheral region located around the opening region, and a support substrate that supports the membrane in the peripheral region, and is characterized in that a side surface of the support substrate includes a tapered surface having a taper angle of less than 80° between the surface that supports the membrane and a surface parallel to the surface.

[0009] According to the present invention, damage due to handling, cleaning, etc. in the manufacturing process of the deposition mask can be suppressed, and the yield can be increased.

[0010] 1 is a cross-sectional view showing an example of a deposition mask according to the present embodiment; FIG. 2 is a cross-sectional view showing an example of a deposition mask different from that shown in FIG. 1; FIG. 3 is a partially enlarged cross-sectional view showing a support substrate of the deposition mask; FIG. 4 is a cross-sectional view showing a manufacturing method of an electronic device using the deposition mask according to the present embodiment; FIG. 5 is a process diagram showing an example of a manufacturing method of the deposition mask according to the present embodiment; FIG. 6 is a process diagram showing an example of a manufacturing method of the deposition mask according to the present embodiment; FIG. 7 is a cross-sectional view showing an example of a deposition mask according to another embodiment; FIG. 8 is a cross-sectional view showing an example of a deposition mask according to another embodiment; FIG. 9 is a cross-sectional view showing an example of a deposition mask according to another embodiment; FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment; FIG. 11 is a plan view of a mask according to an experimental example; (a) is an SEM photograph showing a support substrate used in the experiment, and (b) is a schematic view of (a); (a) is an SEM photograph showing a support substrate used in the experiment, and (b) is a schematic view of (a); (a) is a partially enlarged plan view of the deposition mask used in the experiment, (b) is a partial cross-sectional view of the deposition mask, and (c) is a perspective schematic view showing an enlarged view of the vicinity of the support substrate of the membrane.

[0011] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. Furthermore, even when the same parts are shown between the drawings, the dimensional relationships and ratios between them may be different. In particular, the embodiments shown below are merely examples of structures for embodying the technical idea of ​​the present invention, and do not specify the technical idea of ​​the present invention. In the following description, elements having the same function and configuration are designated by the same reference numerals, and redundant description will be omitted. Furthermore, the lower and upper limits of numerical ranges include error ranges.

[0012] <Background to the Invention> Virtual reality / augmented reality (VR / AR) technology and the VR / AR-related market are growing rapidly. Along with this growth, display panels suitable for the VR / AR field are becoming smaller, with higher pixel counts (PPI: Pixels Per Inch), faster response times, and wider color gamuts. To advance this technology, silicon-based organic light-emitting diode (OLED) microdisplay panels are becoming increasingly popular.

[0013] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and higher PPI. Furthermore, to effectively prepare for the high-value-added industries of AR and VR, it is expected to realize ultra-high resolution displays, for example, 1000 ppi or higher. This has led to a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.

[0014] To achieve high-definition deposition masks, it was necessary to thin the membrane having multiple openings and process it with high precision. However, when the membrane becomes thin, it is prone to breakage due to cracks occurring at weak points caused by bending or vibration. For example, breakage occurs easily during handling or cleaning during the deposition mask manufacturing process, which leads to problems such as reduced yield.

[0015] Therefore, the present inventors have conducted extensive research and have developed a deposition mask that can suppress breakage by optimizing the shape of the support substrate that supports the membrane.

[0016] <Overview of Vapor Deposition Mask 1 in the Present Embodiment> FIG. 1 is a cross-sectional view of a vapor deposition mask 1 in the present embodiment. The vapor deposition mask 1 has a laminated structure of a membrane 2 and a support substrate 4. In the vapor deposition mask 1 shown in FIG. 1, the support substrate 4 is preferably configured as an SOI (Silicon-on-Insulator) substrate 9 including an insulating layer 3 and a silicon substrate 30. Alternatively, the vapor deposition mask 1 shown in FIG. 1 is configured as an SOI substrate 9 including a membrane 1, an insulating layer 3, and a support substrate 4 (in this case, the support substrate 4 does not include the insulating layer 3). The support substrate 4 is, for example, a silicon substrate, but is not limited thereto. In the embodiments of FIGS. 8 to 10 described later, a configuration of support substrate 4 / insulating layer 3 / membrane 2 is illustrated. The membrane 2 is preferably a silicon single crystal layer, also referred to as a semiconductor layer or active layer.

[0017] 1, the deposition mask 1 has a plurality of opening regions 15 and a peripheral region 16 located around the opening regions 15. The peripheral region 16 has a structure in which a membrane 2 and a support substrate 4 are laminated. On the other hand, only the membrane 2 is disposed in the opening regions 15, that is, the support substrate 4 is removed, and a plurality of minute openings 5 ​​are formed in each opening region 15.

[0018] 1, the membrane 2 has a front surface 2a and a back surface 2b that face each other in the thickness direction. A support substrate 4 is provided on the back surface 2b side. As shown in Fig. 4, the front surface 2a faces a deposition substrate 10, and the back surface 2b faces a deposition source 11.

[0019] As shown in FIG. 4 , the membrane 2 has a plurality of openings 5 ​​formed therein, penetrating between the front surface 2 a and the back surface 2 b. As shown in FIG. 4 , the opening width of each opening 5 gradually narrows from the back surface 2 b to the front surface 2 a. Therefore, the side wall surface 5 a of the opening 5 is inclined. Also, in FIG. 4 , the opening width W1 is defined as the width dimension in the planar direction along the front surface 2 a. As such, in FIG. 4 , the opening width W1 is illustrated at the location where the width dimension is narrowest. Note that in FIG. 4 , the reference symbols for the opening width W1 and the side wall surface 5 a are illustrated for only one opening 5, but they also apply to the other openings 5 ​​in the same manner. The spacing between adjacent openings 5 ​​is defined as the opening spacing dimension W2. Note that the opening spacing dimension W2 is defined as the dimension along the front surface 2 a.

[0020] Although not limited thereto, the opening width W1 is about 1 μm to 20 μm, preferably 3 μm to 15 μm, and more preferably 5 μm to 10 μm.

[0021] Although not limited thereto, the dimension W2 between the openings is about 1 μm to 20 μm, preferably 1 μm or more and 15 μm or less, and more preferably 3 μm or more and 10 μm or less.

[0022] The planar pattern of the openings 5 ​​(the shape seen from directly above the membrane 2 toward the surface 2a) is not limited, but examples include rectangles (including squares), polygons other than rectangles, circles, and ellipses. All the openings 5 ​​may have the same planar pattern, or some may have different patterns. The openings 5 ​​may be arranged regularly, irregularly, or a mixture of regular and irregular patterns.

[0023] The outer peripheral shape of the membrane 2 is preferably a rectangular or disk-shaped wafer, and although there are no limitations on the diameter (the length of one side in the case of a rectangle), it is preferable that it be approximately 100 mm to 500 mm. In this way, even if the diameter of the membrane 2 is large, the openings 5 ​​can be formed uniformly.

[0024] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, silicon oxide (SiO ２The insulating layer 3 is preferably a BOX (Buried Oxide Layer) layer. The thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 μm.

[0025] 1 is not provided in the opening region facing the opening 5 of the membrane 2, but has been removed, and is left only in the surrounding region of the opening region on the back surface 2b of the membrane 2. The insulating layer 3 serves as an etching stopper for the membrane 2, and the presence of the insulating layer 3 enables stable processing.

[0026] As shown in FIG. 1 , the support substrate 4 including the insulating layer 3 and the silicon substrate 30 can function as the columnar portions 16 a and the peripheral frame 16 b that constitute the peripheral region 16 of the opening region 15 on the back surface 2 b of the membrane 2. Therefore, the membrane 2 can be maintained in a taut state by the support substrate 4, eliminating the need for a tensioning process. The deposition mask 1 of this embodiment can also be closely attached to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force. As shown in FIG. 1 , the columnar portions 16 a are located inside the peripheral frame 16 b, and all of them have the same height. However, for example, the height of the columnar portions 16 a may be lower than the peripheral frame 16 b. However, by making the heights uniform, greater strength can be maintained.

[0027] 1, an alignment mark for positioning can be formed in the peripheral region on the surface 2a side of the membrane 2. The alignment mark can be formed, for example, in a recessed shape on the surface 2a, and can be formed to a depth that reaches the insulating layer 3.

[0028] 1, the support substrate 4 has a first surface 4a facing the membrane 2 and a second surface 4b opposite to the first surface 4a. The first surface 4a is the surface closer to the deposition target substrate 10 shown in Fig. 4, and the second surface 4b is the surface closer to the deposition source 11 shown in Fig. 4.

[0029] 1, the support substrate 4 is provided with a side surface 4e that connects an edge portion 4c of the first surface 4a and an edge portion 4d of the second surface 4b. An opening region 15 of the membrane 2 is provided inside the area surrounded by this side surface 4e.

[0030] As shown in FIG. 1, the side surface 4e is inclined so that the width of the support substrate 4 gradually increases from the second surface 4b toward the first surface 4a of the support substrate 4.

[0031] In this embodiment, the taper angle θ of the side surface 4e is defined as the angle between the surface supporting the membrane 2 and a parallel surface. The "surface supporting the membrane 2" is the back surface 2b of the membrane 2 and the first surface 4a of the support substrate 4. In FIG. 1, the "parallel surface" is the boundary surface between the silicon substrate 30 and the insulating layer 3 (referred to as the "third surface 4f"). The "parallel surface" may be a surface other than the third surface 4f, such as the first surface 4a. However, it is preferable to use a surface that is easy to measure the taper angle θ. Here, because the insulating layer 3 constituting the support substrate 4 is extremely thin compared to the silicon substrate 30, it is desirable to measure the taper angle θ using the side surface 4e of the silicon substrate 30, which can be clearly identified in an SEM photograph or the like. Therefore, defining the taper angle θ as the angle between the third surface 4f of the silicon substrate 30 and the side surface 4e of the silicon substrate 30, as shown in FIG. 1, can lead to a more accurate angle.

[0032] In this embodiment, the taper angle θ of the side surface 4e is less than 80°. If the taper angle θ of the side surface 4e is 80° or more, the area subjected to water pressure during the oscillation (three up and down movements) in the cleaning process described below is smaller than when the taper angle θ of the side surface 4e is less than 80°, resulting in a larger load per unit area. As a result, the load applied to the edge portion 4c of the first surface 4a of the support substrate 4 increases, making the membrane 2 more likely to be damaged. The taper angle θ is preferably 70° or less, more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less. Although the lower limit of the taper angle θ is not limited, it is preferably, for example, 5° or more or 10° or more.

[0033] 1, it is preferable that the entire side surface 4e has a taper angle θ of less than 80°, but a part of the side surface 4e may have a different angle. For example, in the part of the insulating layer 3, the side surface may be a vertical surface or may be an inversely tapered surface.

[0034] By inclining the side surface 4e of the support substrate 4 that supports the membrane 2, it is possible to reduce (disperse) the concentration of force applied to the membrane 2 when handling the support substrate 4 as a frame or during a cleaning process. As a result, damage such as cracks between the openings 5 ​​of the membrane 2 can be suppressed, and the yield can be increased.

[0035] Fig. 2 is a cross-sectional view showing an example of a deposition mask different from that shown in Fig. 1. Fig. 3 is a partially enlarged cross-sectional view showing a support substrate of the deposition mask.

[0036] In FIG. 1 , the side surface 4 e of the support substrate 4 is inclined at a generally constant taper angle θ from the second surface 4 b to the first surface 4 a. However, in FIG. 2 , the side surface 4 e is formed by a first tapered surface 6 and a second tapered surface 7. As shown in FIG. 2 , the first tapered surface 6 and the second tapered surface 7 have different taper angles from the first surface 4 a. In FIG. 2 , the first taper angle of the first tapered surface 6 is indicated by θ1, and the second taper angle of the second tapered surface 7 is indicated by θ2. As shown in FIG. 2 , the taper angle θ1 is greater than the taper angle θ2. The second tapered surface 7, which has a smaller taper angle θ2, is formed closer to the membrane 2 (the side in contact with the insulating layer 3) than the first tapered surface 6.

[0037] As shown in Figure 2, the first taper angle θ1 is approximately 90°, and therefore the first taper surface 6 is an approximately vertical surface. Hereinafter, the first taper surface 6 may be referred to as a "vertical surface 6." The term "approximately" includes an error of 5% or less. The first taper angle θ1 does not have to be approximately 90°, but it is preferably approximately 90° or close to it.

[0038] On the other hand, the second taper angle θ2, like the taper angle θ shown in FIG. 1, is preferably less than 80°, more preferably 70° or less, even more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less.

[0039] In this way, by forming the taper angle of the side surface 4e of the support substrate 4 in two or more steps and by making the taper angle smaller as it approaches the membrane 2, the width between cells can be narrowed, thereby improving the imposition efficiency within the mask. FIG. 14(a) shows a partially enlarged plan view of the deposition mask 1 used in the experiment described below, and FIG. 14(a) shows cells 8 arranged in a matrix. A large number of openings 5 ​​are formed in each cell 8 in the vertical and horizontal directions (X and Y directions). Note that FIG. 14(a) representatively marks only one cell 8 and one opening 5. A columnar portion 16a (see also FIGS. 1 and 2) of the support substrate 4 is arranged on the back side between the cells 8. FIG. 14(b) is a partial cross-sectional view showing one cell 8 extracted from FIG. 14(a).

[0040] Narrowing the spacing between cells 8 means narrowing the width of the columnar portion 16a of the support substrate 4. Here, to further improve the breakage suppression effect, it is desirable to make the second taper angle θ2 of the second tapered surface 7 on the membrane 2 side as gentle as possible. However, if a single-stage tapered surface (FIG. 1) is used, it is not possible to form a very gentle slope. Therefore, by forming the first tapered surface on the side away from the membrane 2 as a vertical surface 6 or a tapered surface with a high taper angle close to that, and by making the second taper angle θ2 of the second tapered surface 7 on the side closer to the membrane 2 smaller, it is possible to narrow the spacing between cells 8 while enhancing the breakage suppression effect.

[0041] 3A is a partially enlarged schematic diagram showing a portion of the support substrate 4 in this embodiment. In Fig. 3A, similar to that shown in Fig. 2, the side surface 4e of the support substrate 4 is composed of a first tapered surface 6 and a second tapered surface 7 with different taper angles, with the first tapered surface (vertical surface) 6 with a high taper angle being located on the side away from the membrane 2 and the second tapered surface 7 with a low taper angle being formed on the side closer to the membrane 2. The vertical surface 6 and the second tapered surface 7 are formed continuously.

[0042] 3A, the height dimension (=height dimension of the support substrate 4) from the second surface 4b to the first surface 4a, as drawn perpendicularly from the second surface 4b toward the first surface 4a, is defined as t1. The height dimension of the second tapered surface 7 is defined as the height dimension t2 of a vertical plane v drawn perpendicularly from the inflection point p between the first tapered surface 6 and the second tapered surface 7 to the first surface 4a. Furthermore, the protruding width of the second tapered surface from the vertical plane v is defined as w.

[0043] In this embodiment, t2 / t1 is preferably 0.3 or more and less than 0.85. Furthermore, w / t2 is preferably 0.4 or more and 1.4 or less. This increases the strength of the support substrate 4, regardless of the height dimension t1 of the support substrate 4, while also ensuring a contact area with the membrane 2, thereby enhancing the breakage suppression effect. Here, when the side surface 4e is composed of three or more tapered surfaces, the tapered surface that is the subject of t2 / t1 and w / t2 is the tapered surface closest to the membrane 2.

[0044] 3(a), the side surface 4e of the support substrate 4 shown in Fig. 3(b) is also formed by a first tapered surface (vertical surface) 6 and a second tapered surface 17. However, unlike Fig. 3(b), the second tapered surface 17 is formed in a concave shape rather than a linear shape. By forming the second tapered surface 17 in this concave shape, the second taper angle θ2 can be made smaller, that is, the second tapered surface 7 can be formed in a gentler shape.

[0045] 3(b), the second taper angle θ2 of the second tapered surface 17 can be determined by drawing a tangent line L that contacts the second tapered surface 17 from the edge 4c of the first surface 4a, and defining the second taper angle θ2 as the angle between the first surface 4a and the tangent line L. In this case, the second taper angle θ2 of the second tapered surface 17 formed by a concave surface is 50° or less, preferably 30° or less, and more preferably 10° or less.

[0046] In Fig. 3, the first surface 4a is used as the reference plane for the height dimensions t1, t2 and the protrusion width w, but the height dimensions t1, t2 and the protrusion width w can be measured using the third surface 4f (see Fig. 2, etc.) of the silicon substrate 30 as the reference plane. In particular, in the configuration of Fig. 3(b), the second taper angle θ2 is preferably measured excluding the insulating layer 3, since it may be clearer and easier to measure it on the side surface of the silicon substrate 30. Because the thickness of the insulating layer 3 is extremely thin, the above-mentioned numerical ranges do not change even if t2 / t1 and w / t2 are measured only on the silicon substrate 30 excluding the insulating layer 3.

[0047] 2, the distance D between the edge 4c of the first surface 4a of the support substrate 4 on the membrane 2 side and the opening 5 of the membrane 2 that is closest to the edge 4c is preferably 30 μm or more and 100 μm or less. This distance D is the distance in the horizontal direction (the direction of the surface parallel to the first surface 4a).

[0048] If the distance D is too small, breakage may occur easily, particularly during the process of forming the multiple openings 5 ​​in the membrane 2, due to cleaning and other factors during the manufacturing process. On the other hand, if the distance D is too large, the width dimensions of the columnar portions 16a and the peripheral frame 16b constituting the support substrate 4 become smaller and thinner, resulting in a loss of strength. Therefore, from the viewpoints of breakage prevention effect and strength, the distance D is set to 30 μm or more and 100 μm or less. In this configuration, it is sufficient for the side surface 4e of the support substrate 4 to have an inclined tapered surface. The taper angle is not limited, but as described with reference to FIGS. 1 and 2 , it is preferably less than 80°, more preferably 70° or less, even more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less.

[0049] According to the deposition mask 1 of the present embodiment described above in detail, the following inventions can exist independently: (1) The side surface 4 e of the support substrate 4 includes a tapered surface in which the taper angle θ between the surface supporting the membrane 2 and a surface parallel to the surface is less than 80° (see FIG. 1 ).

[0050] (2) The side surface 4e of the support substrate 4 has at least a first tapered surface 6 and a second tapered surface 7, which have different taper angles between the surface supporting the membrane 2 and a surface parallel to it, and the second tapered surface 7 has a smaller taper angle than the first tapered surface 6 and is formed on the side closer to the membrane 2, and the taper angle θ2 of the second tapered surface is less than 80° (see Figures 2 and 3).

[0051] (3) The side surface 4e of the support substrate 4 has at least a first tapered surface 6 and a second tapered surface 7, which have different taper angles between the surface supporting the membrane 2 and a surface parallel to it, and the second tapered surface 7 is formed closer to the membrane 2 than the first tapered surface 6, and when the height dimension of the support substrate 4 is t1, the height dimension of the second tapered surface 7 is t2, and the protruding width of the second tapered surface 7 is w, t2 / t1 is 0.3 or more and less than 0.85, and w / t2 is 0.4 or more and 1.4 or less (see Figure 3).

[0052] (4) An invention in which the side surface 4e of the support substrate 4 includes a tapered surface, and the distance D between the edge 4c of the surface of the support substrate 4 facing the membrane 2 and the opening 5 closest to the support substrate 4 is 30 μm or more and 100 μm or less (see Figures 2 and 14).

[0053] In this embodiment, the above inventions (1) to (4) may be combined in plural. For example, invention (2) may be combined with invention (3), or invention (1) may be combined with invention (4).

[0054] <Relationship Between Membrane 2 and Support Substrate 4> As shown in Fig. 1, sidewall surfaces 5a of the multiple openings 5 ​​formed in the membrane 2 are inclined, and the taper angle of these sidewall surfaces 5a is defined as θ3. As shown in Fig. 1, the taper angle θ3 of the openings 5 ​​is defined as the angle between the surface 2a of the opening 5 (the surface facing the substrate to be deposited) and the sidewall surface 5a. This taper angle θ3 is different from the taper angle θ of the side surface 4e of the support substrate 4. Note that, when the side surface 4e is formed of multiple tapered surfaces as shown in Figs. 2 and 3, the taper angle of the support substrate 4 to be compared with the taper angle θ3 is compared with the taper angle θ2 of the tapered surface closest to the membrane 2 (the second tapered surface 7, 17 in Figs. 2 and 3).

[0055] The taper angle θ 3 of the opening 5 of the membrane 2 is preferably larger than the taper angles θ and θ 2 of the side surface 4 e of the support substrate 4 .

[0056] In an ultra-high resolution display, the opening pitch is narrow, which restricts the taper angle θ3 from being small. Although not limited thereto, the taper angle θ3 of the opening 5 is in the range of 80° or more and less than 90°. On the other hand, the taper angles θ and θ2 of the side surface 4e of the support substrate 4 are preferably small to enhance the breakage suppression effect, and it is desirable to control the taper angles θ and θ2 so that they are smaller than the taper angle θ3.

[0057] In this embodiment, the membrane 2 and the support substrate 4 have different thicknesses. Specifically, the membrane 2 is thinner than the support substrate 4. There is no upper limit to the thickness of the membrane 2, but it is 10 μm or less, and preferably 5 μm or less. A thin thickness increases deposition efficiency and facilitates high definition. There is no lower limit to the thickness of the membrane 2, but it is preferably 1 μm or more from the viewpoints of processability and durability.

[0058] On the other hand, the thickness of the support substrate 4 (corresponding to the height dimension t1 shown in FIG. 3A) is, for example, about 100 μm to 1000 μm. The silicon substrate 30 accounts for the majority of the support substrate 4, and the silicon substrate 30 accounts for approximately 80% or more of the height dimension t1, preferably approximately 90% or more, more preferably approximately 95% or more, and even more preferably 99% or more.

[0059] Considering the pattern accuracy (rectangularity) of the vapor deposition film 13 formed on the deposition target substrate 10 through the vapor deposition mask 1 and vapor deposition efficiency, it is preferable that the thickness of the membrane 2 is thin. On the other hand, it is preferable that the thickness of the support substrate 4 is thick, considering the mask strength and the stability of support to the membrane 2. Therefore, it is preferable to control the thickness of the support substrate 4 so that it is greater than the thickness of the membrane 2.

[0060] As described above, a thinner membrane 2 is preferable, but the thinner it is, the more susceptible it is to breakage. If the thickness of the membrane 2 is 5 μm or less, the impact of breakage becomes particularly large, so it is preferable to increase the breakage prevention effect by making the taper angle θ of the side surface 4 e of the support substrate 4 as small as possible, or by forming the side surface 4 e shown in Figure 3( a) with multiple tapered surfaces with different taper angles, or by forming the tapered surface as a concave surface as shown in Figure 3( b).

[0061] <Regarding the Manufacturing Method of the Vapor Deposition Mask 1 in the Present Embodiment> FIG. 5 is a process chart showing a first manufacturing method of the vapor deposition mask 1 in the present embodiment. Here, the vapor deposition mask 1 in the manufacturing process shown in FIG. 5 and FIG. 6 described later only shows the vicinity of one opening region 15, but in reality, the multiple opening regions 15 shown in FIG. 1 are formed simultaneously. In FIG. 5( a), an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a membrane 2, an insulating layer 3, and a silicon substrate 30 (the insulating layer 3 and the silicon substrate 30 together constitute the support substrate 4). The materials and thicknesses of each layer have been explained with reference to FIG. 1, so please refer to that description.

[0062] In the case of the SOI substrate 9, the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.

[0063] 5(b), a mask layer 14 is patterned on the surface of the membrane 2. The mask layer 14 is preferably a resist, and can be patterned by exposure and development. A plurality of through holes 14a are formed in the mask layer 14. The through holes 14a are an opening pattern for forming openings 5 ​​in the membrane 2.

[0064] 5C, the membrane 2 exposed from the through-holes 14a of the mask layer 14 is dry-etched. For example, in this embodiment, the membrane 2 is deep-etched. ６ Etching of Si by C ４ F ８ It is preferable to use a method in which the formation of a polymer film by the method is repeated to dig deep into the silicon, and sidewall protection and bottom etching are alternately performed.

[0065] At this time, the composition and flow rate of the etching gas, the pressure inside the etching chamber, the power of the high frequency power source, etc. are adjusted appropriately so as to form an inversely tapered surface as shown in FIG. 5(c).

[0066] For example, in a dry etching device, SF ６ Gas and C ４ F ８ The Bosch process was carried out using alternating gases. ６Anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as that used to perform isotropic dry etching using fluorine radicals. For example, the processing conditions were SF ６ Gas: 0 to 500 sccm, C ４ F ８ The gas was set to 0 to 300 sccm, the platen LF to 0 to 1500 W, the coil RF to 300 to 1500 W, and the chamber pressure to 1 to 10 Pa, and various conditions were adjusted.

[0067] By using the Bosch process described above, a plurality of openings 5 ​​can be deeply formed in the membrane 2, and the taper angle θ3 of the sidewall surface 5a of the opening 5 can be adjusted appropriately. Next, in the step shown in Figure 5(d), the mask layer 14 is removed. This completes the SOI substrate 9 with a plurality of openings 5 ​​formed in the membrane 2.

[0068] 5( e), a protective layer 20 is formed on the surface of the membrane 2. This makes it possible to appropriately protect the entire surface of the membrane 2. The protective layer 20 is, for example, a resist film, although it is not limited thereto.

[0069] Next, in the step shown in Figure 5(f), a mask layer 21 is formed on the surface of the silicon substrate 30, which corresponds to the back surface of the SOI substrate 9. Although not limited to this, the mask layer 21 is a resist pattern. As shown in Figure 5(f), the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the membrane 2 in the thickness direction, but is provided only in the peripheral region 16 (see also Figure 1). Note that the mask layer 21 may be formed together with the mask layer 14 in the step shown in Figure 5(b).

[0070] 5( g), the silicon substrate 30 not covered with the mask layer 21 is removed by, for example, dry etching, and in the step shown in Fig. 5( h), the insulating layer 3 that is revealed by removing the silicon substrate 30 is removed by wet etching. At this time, the membrane 2 is not affected by the wet etching and maintains its shape with the plurality of openings 5.

[0071] 5(i), the protective layer 20 and the mask layer 21 are removed, thereby completing the deposition mask 1.

[0072] 6A to 6C are process diagrams showing a second manufacturing method of the deposition mask 1 according to the present embodiment. In Fig. 6A, an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a membrane 2, an insulating layer 3, and a silicon substrate 30. The materials and thicknesses of each layer have been explained in Fig. 1, so please refer to that explanation.

[0073] Although there is no limitation on the diameter of the SOI substrate 9, in this embodiment, it can accommodate a diameter up to about 500 mm.

[0074] 6( b), a mask layer 21 is formed on the surface of the silicon substrate 30, which corresponds to the back surface of the SOI substrate 9. The mask layer 21 is, but is not limited to, a resist pattern. As in FIG. 6( f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0075] Next, in the step shown in FIG. 6( c), the silicon substrate 30 that is not covered by the mask layer 21 is removed by, for example, dry etching, and in the step shown in FIG. 6( d), the insulating layer 3 that is revealed by removing the silicon substrate 30 is removed by wet etching.

[0076] 6(e), a mask layer 22 is formed on the rear surface of the membrane 2. Although not limited to this, the mask layer 22 can be formed using a resist pattern. As shown in FIG. 6(e), a plurality of openings 22a are patterned in the mask layer 22 by exposure and development.

[0077] 6(f), the membrane 2 exposed from the opening 22a is etched. This etching is dry etching, and preferably, an etching gas containing a fluorine compound and oxygen, and optionally a rare gas, is used, although this is not limited thereto.

[0078] The fluorine compound is, for example, CF ４ , S.F. ６ , N.F. ３ , B.F. ３ , P.F. ５ and F２ The rare gas may be selected from one or more of helium and argon.

[0079] For example, in a dry etching device, ４ Gas, O ２ Etching was performed using CF gas and Ar gas. ４ Gas: 10 to 100 sccm, O ２ The gas was set to 0-100 sccm, Ar gas to 0-200 sccm, IPC power to 200-1000 W, RIE power to 0-1000 W, and chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0080] 6(f), an opening 5 whose width gradually decreases with increasing distance from the mask layer 22 (toward the surface 2a of the membrane 2) can be formed in the membrane 2. This allows the sidewall surface 5a of the opening 5 to be formed as a tapered surface. Then, in the step of FIG. 6(g), the mask layer 22 is removed. This completes the deposition mask 1.

[0081] In the steps shown in FIG. 5( g) and FIG. 6( c), the method for forming the side surface 4 e of the silicon substrate 30 constituting the support substrate 4 into a tapered surface is not limited. For example, a dry etching apparatus may be used. ４ Gas, O ２ Etching was performed using fluorine compounds such as CF4 and Ar gas. ４ , S.F. ６ , N.F. ３ , B.F. ３ , P.F. ５ and F ２ The rare gas may be selected from one or more of helium and argon.

[0082] The treatment conditions were: ４ Gas: 10 to 100 sccm, O ２ Various conditions were adjusted to a gas flow rate of 0 to 100 sccm, Ar gas flow rate of 0 to 200 sccm, IPC power of 200 to 1000 W, RIE power of 0 to 1000 W, and chamber pressure of 1 to 10 Pa. This allows the side surface 4 e of the silicon substrate 30 to be formed as a tapered surface.

[0083] Furthermore, as shown in Figures 3(a) and (b), when the side surface 4e of the support substrate 4 is formed by combining the first tapered surface (vertical surface) 6 and the second tapered surfaces 7 and 17, this can be achieved, for example, by combining the vertical process with the above-mentioned dry etching process.

[0084] As a vertical process, for example, a dry etching device is used. ６ Gas and C ４ F ８ The Bosch process was carried out using alternating gases. ６ Anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as that used to perform isotropic dry etching using fluorine radicals. For example, the processing conditions were SF ６ Gas: 0 to 500 sccm, C ４ F ８ Various conditions were adjusted to a gas of 0 to 300 sccm, a platen LF of 0 to 1500 W, a coil RF of 300 to 1500 W, and a chamber pressure of 1 to 10 Pa. Alternatively, the vertical process and the wet etching process may be combined.

[0085] As the wet etching process, for example, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, electrolytic etching using hydrofluoric acid, or anisotropic etching using potassium hydroxide and TMAH was selected and processed to obtain the desired angle. As an example, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid was used for the processing, and the processing temperature was set to 20°C to 40°C.

[0086] Alternatively, by combining the above-mentioned dry etching process with a wet etching process, or by changing the etching conditions during the dry etching process, the side surface 4e of the support substrate 4 can be formed with multiple tapered surfaces having different taper angles.

[0087] 5(h) and 6(d), in the step of removing the insulating layer 3 constituting the support substrate 4, the side surface of the remaining insulating layer 3 is also likely to be formed following the taper angle of the silicon substrate 30. However, depending on the conditions, the side surface of the insulating layer 3 may be formed as a substantially vertical surface or an inversely tapered surface. Furthermore, since the insulating layer 3 is extremely thin compared to the silicon substrate 30, it may be difficult to determine the side surface of the insulating layer 3. Therefore, it is preferable to measure the taper angles θ and θ2 of the side surface 4e of the support substrate 4 using the angle of the side surface 4e of the silicon substrate 30, as shown in FIGS. 1 and 2.

[0088] According to the manufacturing method of this embodiment, the taper angles θ and θ2 of the side surface 4e of the support substrate 4 can be adjusted to less than 80°.

[0089] Furthermore, in this embodiment, when the height dimension perpendicularly drawn from the second surface 4 b of the support substrate 4 toward the first surface 4 a is defined as t1, the height dimension of the second tapered surface 7 is defined as t2, and the protruding width of the second tapered surface 7 is defined as w, it is preferable to control the above-mentioned etching conditions so that t2 / t1 is equal to or greater than 0.3 and less than 0.85, and w / t2 is equal to or greater than 0.4 and less than 1.4.

[0090] In addition, in this embodiment, as shown in FIG. 2, it is preferable to adjust the above-mentioned etching conditions so that the distance D between the edge 4 c of the first surface 4 a of the support substrate 4 and the opening 5 closest to the support substrate 4 is 30 μm or more and 100 μm or less.

[0091] <Method for manufacturing an electronic device according to this embodiment> In this embodiment, as shown in Fig. 4, the deposition mask 1 is placed between a substrate 10 to be deposited and a deposition source 11. At this time, the front surface 2a of the membrane 2 of the deposition mask 1 faces the substrate 10 to be deposited, and the back surface 2b of the membrane 2 faces the deposition source 11. A plurality of openings 5 ​​are formed in the membrane 2, and the opening width is narrower on the substrate 10 side than on the deposition source 11 side.

[0092] The deposition mask 1 is placed on a holder (not shown) of a deposition device, and an electrostatic chuck can be used to fix the deposition mask 1 and the deposition substrate 10. The deposition mask 1 and the deposition substrate 10 are rotated around the axis of the holder.

[0093] The deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 ​​of the deposition mask 1 and reaches the surface 10 a of the deposition substrate 10 , forming a deposition film 13 .

[0094] In this embodiment, examples of electronic devices include OLED microdisplay panels, liquid crystal panels, solar cells, etc., and the present invention is particularly suited to a method for manufacturing an OLED microdisplay panel as an organic electronic device.

[0095] Although the embodiments and modifications have been described above, other embodiments may be obtained by combining the above embodiments and modifications in whole or in part.

[0096] Furthermore, the present invention is not limited to the above-described embodiments and modifications, and may be variously changed, substituted, or modified within the scope of the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.

[0097] An embodiment of a layer structure different from that of the deposition mask 1 shown in Fig. 1 will be described. The deposition mask 1 shown in Fig. 1 is formed of an SOI substrate. For example, as shown in Fig. 7, the deposition mask 1 may be formed by depositing SiN or SiO ２ The membrane 31 may be formed in a central region where the silicon substrate 30 has been removed, and a plurality of openings 32 may be formed in the membrane 31. The membrane is formed by CVD, but it is preferable to use SiN in view of ease of stress control.

[0098] 7 constitutes the support substrate of this embodiment and preferably has at least one of the above-described inventions (1) to (4), thereby enhancing the effect of suppressing damage.

[0099] 8 to 10 use an SOI substrate 9 similarly to Fig. 1 , but in Fig. 8 , a SiN layer 33 is formed on the back side (support substrate 4 side, the side facing the deposition source 11) of the SOI substrate 9, in Fig. 9 , a SiN layer 33 is formed on the front side (semiconductor layer 2 side, the side facing the deposition substrate 10) of the SOI substrate 9, and in Fig. 10 , a SiN layer 33 is formed on both the back side and the front side of the SOI substrate 9. In the configuration in which the SiN layer 33 is formed on the front side (semiconductor layer 2 side) of the SOI substrate 9, an opening 5 is formed continuous with the semiconductor layer 2, as shown in Figs. 9 and 10 .

[0100] By providing the SiN layer 33, stress control of the deposition mask is facilitated, and distortion, etc. can be suppressed. Furthermore, the SiN layer 33 formed on the front side of the SOI substrate 9 is preferably thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited thereto, the thickness of the SiN layer 33 formed on the front side of the SOI substrate 9 is approximately 0.05 μm to 0.5 μm, and the thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is approximately 0.05 μm to 3 μm. Because the semiconductor layer 2 is thinner than the support substrate 4 and also has numerous openings 5 ​​formed in the semiconductor layer 2, the SiN layer 33 formed on the front side of the SOI substrate 9 is made thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 to achieve balanced stress control between the front side and the back side.

[0101] At least one of the support substrate 4 and the membrane 2 may have a polycrystalline silicon structure. Since polycrystalline silicon does not have a clear cleavage plane, it is less likely to break in the cleavage direction than single-crystal silicon, which has a cleavage plane. Although it is technically difficult to produce a large substrate from a single-crystal silicon material, using a polycrystalline silicon structure for the deposition mask 1 makes it easier to form a silicon substrate larger than a single-crystal silicon substrate. Furthermore, by making the planar shape of the deposition mask 1 polygonal (e.g., rectangular), the chamfering efficiency can be improved compared to a round deposition mask 1, and the number of surfaces can also be increased. A large-sized silicon substrate is preferably 500 mm x 500 mm or larger.

[0102] The effects of the present invention will be explained below with reference to examples and comparative examples. Note that the present invention is not limited to the following examples. As shown in FIG. 11, 30 cells were formed in a deposition mask, and damage due to cleaning was confirmed.

[0103] The deposition mask used was an SOI substrate, which consisted of a silicon substrate (675 μm) / insulating layer (0.5 μm) / membrane (4 μm). The thicknesses in parentheses indicate the thicknesses. The membrane was a Si layer, and the insulating layer was a SiO ２ The silicon substrate and the insulating layer were combined to form a support substrate that supported the membrane. The outer diameter of the SOI substrate was 200 mm.

[0104] A plurality of openings with a width of 5 to 10 μm were formed in each cell of the membrane. The side surface 4e of the support substrate 4 was formed with a single taper as shown in FIG. 1 or a double taper as shown in FIG. 3(a) or 3(b). The taper angle was measured by SEM observation. The device used for the measurement was an SU3500 manufactured by Hitachi High-Technologies.

[0105] In the experiment, cleaning was repeatedly carried out using Experimental Examples 1 to 10, which had different taper angles, and the damage status of 30 cells in the mask was confirmed.

[0106] FIG. 12( a) is an SEM photograph of the support substrate in Experimental Example 5, and FIG. 12( b) is a schematic diagram thereof. As shown in FIG. 12( b), in Experimental Example 5, the support substrate was formed with a two-stage inclination of a vertical surface and a tapered surface, and the tapered surface was concave. The taper angle θ2 of the tapered surface was 10°. FIG. 13( a) is an SEM photograph of the support substrate in Experimental Example 8, and FIG. 13( b) is a schematic diagram thereof. As shown in FIG. 13( b), in Experimental Example 8, the support substrate was formed with a two-stage inclination of a vertical surface and a tapered surface, and the tapered surface was approximately linear. The taper angle θ2 of the tapered surface was 60°. In this experiment, the taper angle θ2 of the side surface of the silicon substrate was measured as shown in FIG. 2.

[0107] The cleaning was performed by placing the deposition mask vertically (the direction perpendicular to the mask thickness direction was the up-down direction). One cycle consisted of immersion in sulfuric acid, immersion in pure water, and swinging the mask (moving up and down three times), and this cycle was repeated five times.

[0108] A state in which the mask could no longer function as a deposition mask, such as falling off or cracking, was deemed to be "damage," and the presence or absence of damage was evaluated by visually inspecting the appearance and by visually and microscopically observing for cracks. The experimental results of Experimental Examples 1 to 10 are shown in Table 1 below.

[0109]

[0110] As shown in Table 1, Experimental Examples 1 to 3 had a single-step inclined shape as shown in Figure 1. In Experimental Example 4, the entire side surface of the support substrate was a vertical surface. Experimental Examples 5 to 10 had a two-step inclined shape as shown in Figures 3(a) and 3(b). All of these were a combination of a vertical surface and a tapered surface.

[0111] The "judgment" shown in Table 1 was as follows: ⊚ if the breakage incidence rate was 2% or less, ○ if it was more than 2% and 5% or less, △ if it was more than 5% and 10% or less, and × if it was more than 10%.

[0112] As shown in Table 1, in the experimental examples where the taper angle was 80° to 90°, the breakage rate was very high and the result was rated as ×. Therefore, based on these experimental results, the preferred taper angle was set to less than 80°, and the more preferred taper angle was set to 70° or less.

[0113] Furthermore, by forming the surface with a two-stage incline, the rate of breakage was effectively reduced. In particular, by providing a portion of the surface that is vertical, it is easy to reduce the taper angle θ2 as shown in Figure 12, and by using a very gentle taper angle of 10° to 30°, the rate of breakage was reduced to approximately 0%.

[0114] Next, as shown in Table 2, the distance D, the opening width W1, and the opening interval W2 were adjusted appropriately, and the rate of breakage occurrence was measured.

[0115] The experimental examples in Table 2 with a taper angle of 30° were fabricated by combining a dry etching process and a wet etching process so as to form a two-step shape with a second taper angle θ2 of 30° as shown in FIG. 2 , and the experimental examples in Table 2 with a taper angle of 60° were fabricated by using only a dry etching process so as to form the inclined shape as shown in FIG. 1 .

[0116] 14, distance D refers to the distance from edge 4c of first surface 4a of support substrate 4 on the membrane 2 side to the opening 5 of membrane 2 that is closest to edge 4c. Opening width W1 refers to the width dimension of opening 5 along surface 2a of membrane 2 as shown in FIG. 14(b). Furthermore, opening spacing W2 refers to the distance between openings on surface 2a of membrane 2.

[0117] The cleaning method was the same as in the experiment in Table 1, and the cleaning evaluation was carried out by observing cracks and damage occurring between the openings near the support substrate at 40 locations after cleaning under a microscope and calculating the damage occurrence rate. The experimental results are shown in Table 2 below.

[0118]

[0119] As shown in Table 2, in Experimental Examples 11 to 14, the distance D was 10 μm, and the breakage incidence rate was higher than 10%, resulting in an evaluation of ×. In other words, if the distance D is too close, breakage or cracks are more likely to occur due to the effects of cleaning and the like in the manufacturing process.

[0120] Therefore, in this embodiment, the distance D is set to 30 μm or more and 100 μm or less. It has also been found that the opening width is preferably about 5 to 10 μm, and the distance between the openings is preferably about 3 to 10 μm.

[0121] This application is based on Japanese Patent Application No. 2023-195185, filed November 16, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A deposition mask for being placed between a substrate and a deposition source, for depositing a deposition material from the deposition source through openings onto a surface of the substrate, comprising: a membrane having an opening region with a plurality of the openings and a peripheral region located around the opening region; and a support substrate supporting the membrane at the peripheral region, wherein a side surface of the support substrate includes a tapered surface having a taper angle of less than 80° between the surface supporting the membrane and a surface parallel thereto.

2. The deposition mask according to claim 1, wherein the taper angle is 70° or less.

3. The deposition mask according to claim 1, wherein the taper angle is 60° or less.

4. The deposition mask according to claim 1, wherein the tapered surface is formed as a concave surface.

5. A deposition mask arranged between a substrate to be deposited and a deposition source for depositing a deposition material from the deposition source through openings onto a surface of the substrate to be deposited, comprising: a membrane having an opening region with a plurality of the openings and a peripheral region located around the opening region; and a support substrate supporting the membrane at the peripheral region, wherein a side surface of the support substrate has at least a first tapered surface and a second tapered surface having different taper angles between a surface supporting the membrane and a parallel surface, the second tapered surface having a smaller taper angle than the first tapered surface and being formed on a side closer to the membrane, and the taper angle of the second tapered surface being less than 80°.

6. The deposition mask according to claim 5, wherein the first tapered surface is a substantially vertical surface.

7. The deposition mask according to claim 5, wherein the taper angle of the second taper surface is 70° or less.

8. A deposition mask arranged between a substrate and a deposition source for depositing a deposition material from the deposition source onto a surface of the substrate through openings, comprising: a membrane having an opening region having a plurality of the openings and a peripheral region located around the opening region; and a support substrate supporting the membrane at the peripheral region, wherein a side surface of the support substrate has at least a first tapered surface and a second tapered surface having different taper angles between a surface supporting the membrane and a parallel surface, the second tapered surface being formed closer to the membrane than the first tapered surface, wherein t1 is a height dimension of the support substrate, t2 is a height dimension of the second tapered surface, and w is a protruding width of the second tapered surface, t2 / t1 is 0.3 or more and less than 0.85, and w / t2 is 0.4 or more and 1.4 or less.

9. A deposition mask arranged between a substrate to be deposited and a deposition source for depositing a deposition material from the deposition source onto a surface of the substrate to be deposited through openings, comprising: a membrane having an opening region with a plurality of the openings and a peripheral region located around the opening region; and a support substrate supporting the membrane at the peripheral region, wherein a side surface of the support substrate has an inclined portion, and the distance between an edge of the support substrate facing the membrane and the opening closest to the support substrate is 30 μm or more and 100 μm or less.

10. A deposition mask according to claim 1, claim 5, claim 8, or claim 9, characterized in that the side wall surface of the opening in the membrane has a tapered surface in which the opening width narrows from the deposition source side to the deposition substrate side, and the taper angle between the membrane surface on the deposition substrate side and the side wall surface is larger than the taper angle of the support substrate.

11. The deposition mask according to claim 1, claim 5, claim 8 or claim 9, wherein the supporting substrate is thicker than the membrane.

12. The deposition mask according to claim 1, claim 5, claim 8, or claim 9, characterized in that the deposition mask has a configuration in which a membrane having the opening is supported on a silicon substrate configured as the support substrate, or the support substrate is configured with an insulating layer and a silicon substrate, and is configured as an SOI substrate with the insulating layer between the silicon substrate and the membrane.

13. The deposition mask according to claim 12, wherein the membrane is made of SiN.

14. The deposition mask according to claim 1, claim 5, claim 8, or claim 9, characterized in that the deposition mask is made of an SOI substrate, and a SiN layer is formed on the front side on which the opening is formed, or on the back side, or on both the front side and the back side.

15. The deposition mask according to claim 1, claim 5, claim 8 or claim 9, wherein the thickness of the membrane is 5 μm or less.

16. The deposition mask according to claim 1, claim 5, claim 8 or claim 9, wherein at least one of the membrane and the supporting substrate has a polycrystalline silicon structure.

17. A method for manufacturing an electronic device, comprising: disposing a deposition mask according to claim 1, claim 5, claim 8 or claim 9 between a substrate to be deposited and a deposition source such that the membrane faces the substrate to be deposited; and depositing a deposition material onto the surface of the substrate through the opening.

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