Neural network analog operation system for implementing convolutional neural network

Abstract

A neural network analog operation system for implementing a convolutional neural network (CNN) according to an embodiment of the present invention includes: a DAC unit for receiving a digital signal for image or voice data, converting the digital signal into an analog signal, and outputting the analog signal; an analog operation unit which receives the analog signal, performs a parallel operation, and outputs analog data; and an ADC unit which receives the analog data, converts the analog data into a digital signal, and outputs the digital signal.

Description

A neural network analog computation system for implementing convolutional neural networks.

[0001] The present invention relates to electronic systems, and more particularly, to analog circuits that implement high-speed parallel processing.

[0002] With the introduction of neural networks and teaching concepts into recognition algorithms, high recognition rates are being achieved by applying neural networks and teaching concepts to areas that were previously considered difficult to implement using conventional algorithmic approaches.

[0003] Image recognition performs image segmentation, which identifies the characteristics of objects in a specific area of ​​an image to determine what the object is, the function of specifying the type of multiple objects through this, and dividing the area occupied by a specific object, etc. The common structure is an image input buffer, a kernel matrix, which is a matrix operation for feature extraction, activation, which removes the background, which is an uninteresting area, from the values ​​​​that passed through the kernel, and a max-pooling process that repeatedly goes through the process of reducing the size while preserving the characteristics of the image, and a structure that linearly arranges the representative values ​​of multiple blocks that have been reduced in this process, and connects the data with a fully-connected network (FC-Net) and connects it to an output value that determines the type of object. This structure is collectively called a convolutional neural network (CNN), and is applied to various fields such as character recognition, face recognition, object recognition, and medical image recognition.

[0004] In the convolutional neural network for image recognition, the learning process involves comparing the image to be distinguished (original) with the reference image that has been processed to the target image, and modifying the weight values ​​of the FC-Net.

[0005] Typically, object recognition requires approximately 1,000 original and processed reference images or object labels. Therefore, recognizing a wide range of objects and environments requires processing a large number of images, requiring significant computational time. Therefore, approaches are shifting to using ASICs, FPGAs, or multiple GPUs capable of parallel processing. However, these processes are difficult to apply to small systems due to their long learning times, high system specifications, high power consumption, and high-speed processing elements.

[0006] For example, in the case of ImageNet, when recognizing cases where 15 million high-quality labeled images have 22,000 categories, it is impossible to apply the above process to a small-scale system, or even if it is processed, the processing time is unmeasurable. Therefore, it is implemented in the form of transplanting the parameters obtained through a learning stage on a network-connected supercomputer to a small-scale system and using them for inference, which is a relatively simple calculation. Even in this case, if the number of parameters increases according to the complexity of the problem, expensive parallel GPUs, FPGAs, or ASICs must be used.

[0007] The unit for measuring the computational speed of a system is FLOPS (Floating point operations per second) for high-precision calculations, but IPS (Instructions per second) is used for calculations that do not require high precision, such as image signals. GPUs support parallel processing of multiple data, providing IPS that is difficult to achieve with CPUs, and thus are being applied to various applications. However, many applications require multiple GPUs to generate a lot of heat, consume a lot of power, and improve performance, and most of them are expensive. To avoid problems that occur in GPUs, FPGAs are sometimes used, and ASICs can be used, but they are applied in special cases and are not universal. In other words, if the network structure changes or the image format changes, the program must be rewritten or a different ASIC must be designed and manufactured.

[0008] In addition, in order to recognize a single object in various environments, hundreds of images are required, and as the number of objects to be recognized increases, the number of images to be processed increases proportionally. Therefore, a method of reducing the image or extracting a portion to learn is usually used. However, even in this case, learning requires a lot of time, a high-level system, and a lot of power consumption. Therefore, except for simple models, the development and implementation of small-scale artificial intelligence systems, such as using supercomputers connected to the cloud, is restricted.

[0009] Also, for example, when interpreting images input from a stereo camera mounted on a car to identify the type of object and extract the distance, it must be able to respond to high-speed movement, so an image processing speed of at least 100 fps (frames per second) is required, and high-resolution processing is required because even small objects must be distinguished. In this application, for two or more high-pixel (~ megapixel or more) images, inference to distinguish the type of individual objects and stereo matching to recognize the distance must be completed within 10 msec (100 fps). In order to implement such a system with the current level of technology, it must be composed of multiple parallel-arranged GPUs or multiple FPGAs, making it impractical for commercial application in individual cars.

[0010] The present invention is intended to solve the aforementioned problems, and aims to provide a neural network analog system that can handle a large-scale system and a recognition system that requires a lot of time and power consumption as described above as a small-scale system.

[0011] However, these tasks are exemplary and the scope of the present invention is not limited thereby.

[0012] According to one aspect of the present invention for solving the above technical problem, a neural network analog operation system may include a DAC (Digital to Analog converter) unit that receives a digital signal for image or voice data, converts it into an analog signal, and outputs it; an analog operation unit that receives the analog signal, performs parallel operations, and outputs analog data; and an ADC (Analog to digital converter) unit that receives the analog data, converts it into a digital signal, and outputs it.

[0013] According to one embodiment of the present invention, the analog operation unit includes a convolution unit for performing sum and multiplication operations, and the convolution unit can perform the sum and multiplication operations using at least one BPGA (Bipolar Programmable Gain Amplifier) ​​or at least one BVGA (Bipolar Variable gain amplifier) ​​circuit.

[0014] According to one embodiment of the present invention, the convolution unit may further include at least one adder connected to the at least one PGA (Programmable Gain Amplifier) ​​or the at least one VGA (Variable gain amplifier).

[0015] According to one embodiment of the present invention, the analog operation unit may further include an activation / pooling unit that receives an output of the convolution unit and performs activation and pooling operations.

[0016] According to one embodiment of the present invention, the analog operation unit further includes a kernel buffer unit connected to the convolution unit to output a kernel value to the convolution unit, and the kernel value may include a sine value specifying a positive signal or a negative signal and a multiplier value for adjusting the gain so that both positive and negative gains can be applied.

[0017] According to one embodiment of the present invention, the analog operation unit may further include a bipolar DAC unit connected between the kernel buffer unit and the convolution unit to change the kernel value into an analog value.

[0018] According to one embodiment of the present invention, in order to optimize the kernel value input to the convolution unit, at least one AC power supply unit connected between the kernel buffer unit and the convolution unit and applying an AC voltage to an output terminal of the kernel buffer unit may be further included.

[0019] According to one embodiment of the present invention, the activation / pooling unit can perform a ReLU operation and a Max-pooling operation to obtain a maximum value and output 0 if the maximum value is less than 0.

[0020] According to another aspect of the present invention for solving the above technical problem, a neural network analog operation unit may include a convolution unit for receiving an analog signal for image or voice data, performing a parallel operation to output analog data, and performing a sum operation and a multiplication operation; and a kernel buffer unit connected to the convolution unit to output a kernel value to the convolution unit, and the convolution unit may perform the sum operation and the multiplication operation using at least one BPGA (Bipolar Programmable Gain Amplifier) ​​or at least one BVGA (Bipolar Variable gain amplifier) ​​circuit.

[0021] According to another aspect of the present invention for solving the above technical problem, a neural network analog operation unit may include a convolution unit for receiving an analog signal for image or voice data, performing a parallel operation to output analog data, and performing a sum operation and a multiplication operation; and a kernel buffer unit connected to the convolution unit to output a kernel value to the convolution unit, and the convolution unit may perform the sum operation and the multiplication operation using at least one BPGA (Bipolar Programmable Gain Amplifier) ​​or at least one BVGA (Bipolar Variable gain amplifier) ​​circuit.

[0022] According to another aspect of the present invention for solving the above technical problem, a neural network analog operation unit may include a convolution unit for receiving an analog signal for image or voice data, performing a parallel operation to output analog data, and performing a sum operation and a multiplication operation; and a kernel buffer unit connected to the convolution unit to output a kernel value to the convolution unit, and the convolution unit may perform the sum operation and the multiplication operation using at least one BPGA (Bipolar Programmable Gain Amplifier) ​​or at least one BVGA (Bipolar Variable gain amplifier) ​​circuit.

[0023] According to one embodiment of the present invention as described above, if matrix operation and activation, and max pooling are configured as analog circuits and the operation is performed by forming them into a hierarchical structure, the time required for the operation depends on the speed at which data input is completed or changed, so that a faster operation speed than a digital operation can be implemented.

[0024] In addition, since analog amplifier circuits have fewer bus lines than digital circuits, analog multiplier adder circuits are simpler than digital multipliers and adders, making it easy to construct highly integrated parallel circuits, enabling multiple parallel processing. In addition, if a multi-layer configuration is used, no matter how many layers are used, once the input of the input stage is completed, the output of the final stage is calculated almost simultaneously depending on the response time of the circuit.

[0025] Therefore, the analog operation system according to one embodiment of the present invention is advantageous in terms of performance and power consumption compared to conventional systems.

[0026] Of course, the scope of the present invention is not limited by these effects.

[0027] FIG. 1 is a diagram showing the configuration of a neural network analog operation system (1000) for implementing a convolutional neural network (CNN) according to one embodiment of the present invention.

[0028] FIG. 2 is a drawing illustrating an analog operation unit using a bipolar PGA according to one embodiment of the present invention.

[0029] Fig. 3 is a drawing showing the configuration of the PGA circuit of Fig. 2.

[0030] FIG. 4 is a drawing illustrating an analog operation unit using a bipolar VGA according to another embodiment of the present invention.

[0031] Fig. 5 is a drawing showing the configuration of the VGA circuit of Fig. 4.

[0032] Fig. 6 is a diagram exemplarily showing the configuration of an activation / pooling unit (420) in the neural network analog operation system of Fig. 1.

[0033] FIG. 7 is a diagram illustrating a neural network analog operation system that implements kernel operation and activation and max pooling using a BPGA circuit according to one embodiment of the present invention.

[0034] FIG. 8 is a diagram illustrating a neural network analog operation system that implements kernel operation and activation and max pooling using a BVGA circuit according to another embodiment of the present invention.

[0035] FIG. 9 is a diagram exemplarily showing a process of optimizing a kernel in a neural network analog operation system according to another embodiment of the present invention.

[0036] Fig. 10 is a diagram illustrating an ADC structure in the neural network analog operation system of Fig. 1.

[0037] Hereinafter, various preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0038] The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. The following embodiments may be modified in various ways, and the scope of the present invention is not limited to the embodiments described below. Rather, these embodiments are provided to more faithfully and completely explain the present disclosure and to fully convey the spirit of the present invention to those skilled in the art.

[0039] In the drawings, variations in the shapes depicted may be expected, for example, depending on manufacturing techniques and / or tolerances. Furthermore, the thickness and size of each layer in the drawings are exaggerated for convenience and clarity of explanation. Therefore, embodiments of the present invention should not be construed as limited to the specific shapes of the regions depicted herein, and should include, for example, variations in shapes resulting from manufacturing processes.

[0040] According to embodiments of the present invention, a matrix operation block that takes a lot of time in a digital image recognition algorithm is configured to convert digital data input to an image buffer into analog using a digital to analog converter (DAC), and to operate with an analog matrix operation circuit composed of a PGA (Programmable Gain Amplifier) ​​array or a VGA (Variable Gain Amplifier) ​​array modified to allow positive and negative values ​​of a kernel to be applied as positive and negative gains, and an analog circuit that provides an analog activation circuit and an analog max-pooling circuit so that a recognition algorithm can be implemented with an analog neural network.

[0041] According to embodiments of the present invention, the time delay and excessive system requirements of the current digital-based neural network are implemented with a plurality of parallel-processable analog signal-based computational circuits. Digital signal processing is performed based on the system clock, and the time for processing one operation (instruction processing time, IPT) proceeds steadily. Parallel processing systems such as GPUs use a method of reducing processing time by performing operations on multiple variables simultaneously within one IPT. In contrast, analog operations are connected through physical signal lines and have the characteristic of immediately determining the output value when the input signal is stable.

[0042] FIG. 1 is a diagram showing the configuration of a neural network analog operation system (1000) for implementing a convolutional neural network (CNN) according to one embodiment of the present invention.

[0043] Referring to FIG. 1, the neural network analog operation system (1000) of the present invention includes a DAC unit (300), an analog operation unit (400), and an ADC unit (500). According to the neural network analog operation system (1000), a digital signal for image or voice data can be converted into an analog signal and processed in parallel.

[0044] Furthermore, the neural network analog operation system (1000) may further include a data buffer unit (100) for data input. The data buffer unit (100) applies a digital signal of data for convolution operation, and the data may be image or voice data.

[0045] Digital image data is composed of three RGB values ​​in 1-byte units for color, and when a digital image is input to a network, it is input by separating it into three images for each color, and is treated as a value between 0 and 1, which is a value normalized to 225 from 0 to 255.

[0046] The above data is applied to the DAC unit (300) as an 8-bit digital signal, and the DAC unit (200) is a circuit that receives the digital signal for image or voice data, converts it into an analog signal, and outputs it, and may include at least one amplifier and at least one resistor.

[0047] The above analog operation unit (400) can receive an analog signal, perform parallel operations, and output analog data. For example, the analog operation unit (400) can include a convolution unit (410) for performing sum and multiplication operations.

[0048] For example, the convolution unit (410) may perform sum and multiplication operations using at least one BPGA (Bipolar Programmable Gain Amplifier) ​​or at least one BVGA (Bipolar Variable gain amplifier) ​​circuit. Furthermore, the convolution unit (410) may further include at least one adder connected to at least one PGA or at least one VGA.

[0049] In some embodiments, the analog operation unit (400) may further include a kernel buffer unit (200) for outputting a kernel value.

[0050] The kernel buffer unit (200) applies the kernel value to the convolution unit (410). The kernel value can be used to obtain an optimal kernel through an optimization process described below.

[0051] For example, the convolution unit (410) may include at least one amplifier, at least one resistor, and at least one adder, and may perform a matrix operation on the kernel value by performing an operation using the gain of the amplifier. The kernel matrix performs an operation to extract an image pattern, and must be computable by including both negative and positive numbers.

[0052] For example, when extracting an edge of an image, the kernel operation requires a different operation from the PGA (Programmable Gain Amplifier) ​​or VGA (Variable gain amplifier) ​​that are commonly used when the gain is a positive value, because an operation that subtracts adjacent pixel data is required.

[0053] Furthermore, the analog operation unit (400) may further include an activation / pooling unit (420) that receives the output of the convolution unit (410) and performs activation and pooling operations.

[0054] Meanwhile, the kernel buffer unit (200) may be connected to the convolution unit (410) to output a kernel value to the convolution unit (410). For example, the kernel value may include a sine value specifying a positive or negative signal and a multiplier value for adjusting the gain so that both positive and negative gains can be applied.

[0055] FIG. 2 is a drawing exemplarily showing an analog operation unit (400a) using a bipolar PGA according to one embodiment of the present invention.

[0056] Referring to Fig. 2, the analog operation unit (400a) may include a PGA (Programmable Gain Amplifier, 412a), and further may include a bipolar PGA, i.e., BPGA circuit (414a). The PGA (412a) is an operational amplifier with adjustable gain, and is classified into an analog type and a digital type depending on the type of gain control signal. In the case of the analog type, variable transconductance and resistance are used, and in the digital type, control is possible with a digital signal using a switch.

[0057] If the kernel value is expressed in a format divided into a sign bit and a magnitude bit, in the BPGA (414a), the magnitude bit is connected to the PGA (412a) having only a positive gain, and the image data is converted from a digital signal to an analog signal in a positive range between 0 and 1. The value of the analog data signal passing through the PGA (412a) is proportional to the product of the image data and the gain, and is inverted depending on the sign bit or transferred to the original value to be output as a negative or positive value.

[0058] Fig. 3 is a drawing showing the configuration of the PGA circuit of Fig. 2.

[0059] Referring to FIG. 3, in the PGA (412a), the gain is a digital gain having a positive value, each connected to a MOSFET, and the gain is determined by changing the conductance connected to the cathode terminal of the amplifier and the ground according to the digital value.

[0060] FIG. 4 is a drawing exemplarily showing an analog operation unit (400b) using a bipolar VGA according to another embodiment of the present invention.

[0061] Referring to FIG. 4, the analog operation unit (400b) may include a VGA (Variable-gain amplifier, 412b) and further may include a bipolar BGA, i.e., a BVGA (414b). Furthermore, the analog operation unit (400b) may further include a bipolar DAC unit (250) connected between the kernel buffer unit (200) and the convolution unit (410) to change the kernel value into an analog value. The convolution unit (410) may include a BVGA (414b).

[0062] A VGA (Variable-gain amplifier, 412b) is an electronic amplifier whose gain varies depending on a control voltage. In the BVGA (414b), when a kernel value is output as an 8-bit digital signal, the absolute value of the kernel value converted to analog through a bipolar DAC unit (250) is extracted and input to the VGA (412a), and the kernel value is compared through a discrimination circuit. When the kernel value is positive, it is output as is, and when the kernel value is negative, it is inverted to a negative number and output.

[0063] At this time, a comparator circuit using an amplifier can be used as a determination circuit to determine whether the kernel value is negative or positive.

[0064] Fig. 5 is a drawing showing the configuration of the VGA circuit (412b) of Fig. 4.

[0065] As shown in Fig. 5, the conductance of the MOSFET connected to the amplifier increases as the gate voltage increases, so the gain of the amplifier can be adjusted by adjusting the gate voltage.

[0066] Referring to FIGS. 1 to 5, the values ​​calculated through the aforementioned PGA (412a) and VGA (412b) circuits can be calculated through an analog adder (413 in FIG. 8). The current flowing into the anode of the amplifier flows through the feedback resistor to generate a voltage, and the voltage at the anode of the amplifier is maintained at 0 V, the same as the cathode of the amplifier. Therefore, since the product of the sum of the currents flowing into the anode and the feedback resistor is the voltage at the output terminal, the output voltage is proportional to the sum of the input voltages of each voltage input terminal.

[0067] The signal calculated through the adder circuit of the above convolution unit (410) can be activated and max-pooled through the activation / pooling unit (420). The activation / pooling unit (420) can perform ReLU operation and max-pooling operation to obtain the maximum value and output 0 if the maximum value is less than 0.

[0068] The above activation / pooling unit (420) may include a plurality of amplifiers and a plurality of resistors, perform operations using the amplifiers, and may perform ReLU operations and Max-pooling.

[0069] FIG. 6 is a diagram exemplarily showing the configuration of an activation / pooling unit (420) in the neural network analog operation system (1000) of FIG. 1.

[0070] The output value calculated through the adder circuit goes through activation and max pooling stages. The activation performs the operation of the Rectified Linear Unit (ReLU) function, which returns itself if the input signal is positive, and 0 if it is negative. The max pooling stage is an operation that extracts the maximum value and can be implemented using an amplifier circuit.

[0071] When a value including 0 is input to the above activation / pooling unit (420), the circuit performs an operation to compare the voltage values ​​input as input and output a larger value, thereby obtaining the maximum value and outputting 0 if the maximum value is less than 0.

[0072] FIG. 7 is a diagram illustrating a neural network analog operation system that implements kernel operation and activation and max pooling using a BPGA circuit (414a) according to one embodiment of the present invention.

[0073] As illustrated in Fig. 7, image data output from the data buffer unit (100) and analog-converted by the DAC unit (200) and the kernel value output from the kernel buffer unit (200) are input to the BPGA (414a) of the convolution unit (410) of the analog operation unit (400), are calculated, and output. The signals output from each BPGA (414a) are added through an adder (413) according to matrix operation, and are input to the activation / pooling unit (420) and calculated.

[0074] FIG. 8 is a diagram illustrating a neural network analog operation system that implements kernel operation and activation and max pooling using a BVGA circuit (412) according to another embodiment of the present invention.

[0075] Referring to Fig. 8, since the gain is transmitted through a single line, it is possible to configure a parallel operation circuit with high integration, thereby improving the processing speed.

[0076] The signal processed by the first layer, which implements the above kernel operation, activation, and max pooling, can be digitized via an ADC and used as a digital input for other layers, or connected to the subsequent analog layer for post-processing. When connected to several dependent lower layers through analog, the final output is determined the moment the digital data input from the upper layer is completed, eliminating the time difference between calculations in different layers.

[0077] FIG. 9 is a diagram exemplarily showing a process of optimizing the shape of a kernel in a neural network analog operation system according to another embodiment of the present invention.

[0078] Referring to Figure 9, it is necessary to determine the most efficient kernel shape for object classification optimization in a neural network analog operation system. For example, when obtaining a kernel optimized for circular objects, multiple circular images can be input into the image data and the kernel component that maximizes the kernel operation value can be selected. In this case, optimization can be achieved in a shorter time than when the kernel shape optimization process is performed digitally.

[0079] This neural network analog operation system may further include at least one AC power supply unit (600) connected between the kernel buffer unit (200) and the convolution unit (410) to apply AC voltage to the output terminal of the kernel buffer unit (200) in order to optimize the kernel value input to the convolution unit (410).

[0080] When two types of images are sequentially input to the input stage, the kernel that causes the greatest change in the output of the final stage is the optimal kernel for distinguishing between two objects.

[0081] By applying AC inputs with different frequencies to the above kernels, the optimal kernel can be obtained in a short time through frequency analysis.

[0082] Fig. 10 is a diagram exemplarily showing the structure of the ADC section in the neural network analog operation system of Fig. 1.

[0083] The image processing backend of networks like CNNs typically arranges processed image data linearly according to pixel location and then connects it to a neural network for inference. In this case, the neural network for inference must be digital. In the case of object classification, the ID assigned to an object is a digital value, but the size or order of these values ​​is not meaningful, so analog processing is meaningless. Therefore, parallel processing of images and voices using analog operations must have a hybrid structure with a digital inference stage. In other words, when the subject matter being processed is a non-significant signal value, such as an image pixel value or a voice signal, analog signal processing, which allows for parallel operations on a large number of highly integrated circuits, is advantageous. In this case, subtle changes in the image color or RGB values ​​do not alter the object's identity, and recognition must be robust even when the voice input contains external background noise or lacks clarity.

[0084] Therefore, the final stage analog data must be converted to digital, so high-density integration and fast conversion are required, and high precision is not required.

[0085] A simple ADC configuration that satisfies the above requirements can be configured as shown in Fig. 10.

[0086] The ADC unit (500) uses an analog signal output from the analog operation unit (400) as an input signal, compares the input signal with a reference signal, and if the input signal is greater than the reference value, outputs a high signal as a digital signal (D7=1), outputs a signal obtained by removing the reference value from the input signal as the next input, and if the input signal is less than the reference signal, outputs a low signal as a digital signal (D7=0), outputs the input signal in the same manner as the next input, and in the next stage, compares the output signal with a reference signal that is half the reference value, thereby sequentially outputting digital signals.

[0087] The network output of the digitized image and voice data through the above ADC unit (500) is used as the input of a fully-connected network (FC-Net) for recognition, and the fully-connected network must be processed digitally in the same way as a digital neural network.

[0088] As described above, when a convolutional neural network analog operation circuit is implemented using a neural network analog operation circuit according to an embodiment of the present invention, matrix operation, activation, and max pooling are configured as analog circuits, and when these are formed into a hierarchical structure to perform the operation, the time required for the operation depends on the speed at which data input is completed or changed, so a faster operation speed than a digital operation can be implemented.

[0089] In addition, since analog amplifier circuits have fewer bus lines than digital circuits, analog multiplier adder circuits are simpler than digital multipliers and adders, making it easy to construct highly integrated parallel circuits, enabling multiple parallel processing. In addition, if a multi-layer configuration is used, no matter how many layers are used, once the input of the input stage is completed, the output of the final stage is calculated almost simultaneously depending on the response time of the circuit.

[0090] Therefore, compared to conventional devices, it is advantageous in terms of performance and power consumption compared to the existing method.

[0091] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and equivalent alternative embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. DAC section that receives digital signals for image or voice data, converts them into analog signals, and outputs them; An analog operation unit that receives the above analog signal, performs parallel operation, and outputs analog data; and ADC section that receives the above analog data, converts it into a digital signal, and outputs it; A neural network analog computation system for implementing a convolutional neural network (CNN) including:

2. In paragraph 1, The above analog operation unit includes a convolution unit for performing sum and multiplication operations, The above convolutional part, Performing summation and multiplication operations using at least one BPGA (Bipolar Programmable Gain Amplifier) ​​or at least one BVGA (Bipolar Variable gain amplifier) ​​circuit, Neural network analog computing system.

3. In paragraph 2, The above convolutional unit further includes at least one adder connected to the at least one PGA or the at least one VGA. Neural network analog computing system.

4. In paragraph 2, The above analog operation unit further includes an activation / pooling unit that receives the output of the convolution unit and performs activation and pooling operations. Neural network analog computing system.

5. In paragraph 3, The above analog operation unit further includes a kernel buffer unit connected to the convolution unit to output a kernel value to the convolution unit, The above kernel value includes a sine value specifying a positive or negative signal and a multiplier value for adjusting the gain so that both positive and negative gains can be applied. Neural network analog computing system.

6. In paragraph 5, The above analog operation unit further includes a bipolar DAC unit connected between the kernel buffer unit and the convolution unit to change the kernel value into an analog value. Neural network analog computing system.

7. In paragraph 5, In order to optimize the kernel value input to the convolution unit, at least one AC power supply unit connected between the kernel buffer unit and the convolution unit and applying AC voltage to the output terminal of the kernel buffer unit is further included. Neural network analog computing system.

8. In paragraph 4, The above activation / pooling unit performs ReLU operation and Max-pooling operation to find the maximum value and output 0 if the maximum value is less than 0. Neural network analog computing system.

9. A convolution unit for receiving analog signals for image or voice data, performing parallel operations to output analog data, and performing sum and multiplication operations; and Including a kernel buffer unit connected to the convolution unit to output a kernel value to the convolution unit, The above convolutional part, Performing summation and multiplication operations using at least one BPGA (Bipolar Programmable Gain Amplifier) ​​or at least one BVGA (Bipolar Variable gain amplifier) ​​circuit, Neural network analog computation unit.

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