Dynamic video timing for display devices

Abstract

Systems and methods for dynamic video timing in display devices. A display control system includes an active matrix, a column driver, a row driver, and a controller. The active matrix includes a plurality of pixels forming a plurality of rows and a plurality of columns. The column driver is configured to control the plurality of columns of pixels. The row driver is configured to control the plurality of rows of pixels. The controller is configured to receive a plurality of scanlines forming a video frame, receive an indication of a scanline order, reorder the plurality of scanlines according to the scanline order, and control the row driver according to the reordered plurality of scanlines. The scanline order is indicative of an order at which the plurality of rows of pixels are controlled.

Description

DYNAMIC VIDEO TIMING FOR DISPLAY DEVICES1. Cross-Reference to Related Applications

[0001] This application claims the benefit of priority from U.S. Provisional Application Ser. No. 63 / 599,872, filed on 16 November 2023 and European Patent Application No. 24156656.1, filed 8 February72024, each of which is incorporated by reference herein in its entirety7.2. Field of the Disclosure

[0002] This application relates generally to systems and methods of dynamic video timing for active matrix displays, imaging sensors, video interfaces, and video pipelines.3. Background

[0003] As used herein, the term "dynamic range’ (DR) may relate to a capability of the human visual system (HVS) to perceive a range of intensity (e.g.. luminance, luma) in an image, e.g., from darkest grays (blacks) to brightest whites (highlights). In this sense, DR relates to a ‘scene-referred’ intensity7. DR may also relate to the ability7of a display device to adequately or approximately render an intensity7range of a particular breadth. In this sense. DR relates to a ‘display -referred’ intensity. Unless a particular sense is explicitly specified to have particular significance at any point in the description herein, it should be inferred that the term may be used in either sense, e.g. interchangeably.

[0004] As used herein, the term high dynamic range (HDR) relates to a DR breadth that spans some 14-15 orders of magnitude of the human visual system (HVS). In practice, the DR over which a human may simultaneously perceive an extensive breadth in intensity7range may be somewhat truncated, in relation to HDR. As used herein, the terms enhanced dynamic range (EDR) or visual dynamic range (VDR) may individually or interchangeably relate to the DR that is perceivable within a scene or image by a human visual system (HVS) that includes eye movements, allowing for some light adaptation changes across the scene or image.

[0005] In practice, images comprise one or more color components (e.g., luma Y and chroma Cb and Cr) wherein each color component is represented by a precision of n-bits per pixel (e.g., n=8). Using linear luminance coding, images where n<8 (e.g., color 24-bit JPEG images) are considered images of standard dynamic range, while images where n>8 may be considered images of enhanced dynamic range. EDR and HDR images may also be stored and distributedusing high-precision (e.g., 16-bit) floating-point formats, such as the OpenEXR file format developed by Industrial Light and Magic.

[0006] As used herein, the term ‘‘metadata” relates to any auxiliary information that is transmitted as part of the coded bitstream and assists a decoder to render a decoded image. Such metadata may include, but are not limited to, color space or gamut information, reference display parameters, and auxiliary signal parameters, as those described herein.

[0007] Most consumer desktop displays currently support luminance of 200 to 300 cd / m2or nits. Most consumer HDTVs range from 300 to 500 nits with new models reaching 1000 nits (cd / m2). Such conventional displays thus typify a lower dynamic range (LDR), also referred to as a standard dynamic range (SDR), in relation to HDR or EDR. As the availability of HDR content grows due to advances in both capture equipment (e.g., cameras) and HDR displays (e.g., the PRM-4200 professional reference monitor from Dolby Laboratories), HDR content may be color graded and displayed on HDR displays that support higher dynamic ranges (e.g., from 1,000 nits to 5,000 nits or more). As the luminance capabilities of HDR displays increases, viewers experience more drastic changes between dark and bright luminance that may cause discomfort.

[0008] Additionally, High Dynamic Range (HDR) content authoring is now becoming widespread as this technology offers more realistic and lifelike images than earlier formats. However, many display systems, including hundreds of millions of consumer television displays, are not capable of reproducing HDR images. Furthermore, because of the wide range of HDR displays (say, from 1,000 nits to 5,000 nits or more) HDR content optimized on one HDR display may not be suitable for direct playback on another HDR display. Additionally, HDR content often has false-contouring, or “banding”, due to higher bit depth information being represented (and quantized) using a lower bit-depth signal. For example, 8-bit offers only 256 codewords.BRIEF SUMMARY OF THE DISCLOSURE

[0009] Traditionally, video timing for display devices is a progressive scan or an interlaced scan having a fixed pattern of scanline latency. Particularly, frames are generated beginning at the top of the display device moving downwards. Accordingly, the bottom scanlines have higher transmission and display latency than the top scanlines. This latency causes noticeable delay in interactive applications and latency-sensitive applications such as gaming (for example,augmented reality [AR], virtual reality [VR], and mixed reality [MR]) and for tall framebuffer applications such as scrolling on mobile phones.

[0010] To achieve latency prioritized video timing and a sub-frame-time spatially variablerate scan, existing active matrix displays (for example, LCDs and OLEDs) are modified with a timing controller. The timing controller controls the timing of the scanline selection by row drivers and column drivers. Row drivers are also commonly known as ‘gate drivers’ as they drive gate contacts of pixel transistors. The update of pixels on the same scanline is achieved by column drivers, which are also commonly known as ‘source drivers’ as they drive the source contacts of the pixel transistors.

[0011] In one exemplary aspect of the present disclosure, there is provided a display control system comprising an active matrix, a column driver, a row driver, and a controller. The active matrix includes a plurality of pixels forming a plurality of rows and a plurality of columns. The column driver is configured to control the plurality of columns of pixels. The row driver is configured to control the plurality of row s of pixels. The controller is configured to receive a plurality of scanlines forming a video frame, receive an indication of a scanline order, reorder the plurality of scanlines according to the scanline order, and control the row driver according to the reordered plurality of scanlines. The scanline order is indicative of an order at which the plurality of rows of pixels are controlled.

[0012] In another exemplary aspect of the present disclosure, there is provided a method for dynamic video timing on display devices. The method includes receiving a plurality of scanlines forming a video frame. The video frame is provided on an active matrix including a plurality of pixels forming a plurality of rows and a plurality of columns. The method includes receiving an indication of a scanline order, reordering the plurality of scanlines according to the scanline order, and controlling a row driver according to the reordered plurality of scanlines. The scanline order is indicative of an order at which the plurality of row-s of pixels are controlled.

[0013] In another exemplary aspect of the present disclosure, there is provided a non- transitory computer-readable medium storing instructions that, when executed by a processor of a video delivery pipeline, causing the video delivery' pipeline to perform operations comprising receiving a plurality of scanlines forming a video frame, receiving an indication of a scanline order, reordering the plurality of scanlines according to the scanline order, and controlling a row driver according to the reordered plurality of scanlines. The video frame is provided on an activematrix including a plurality of pixels forming a plurality of rows and a plurality of columns. The scanline order is indicative of an order at which the plurality of rows of pixels are controlled.

[0014] In this manner, various aspects of the present disclosure provide for the display of images having a high dynamic range and high resolution, and effect improvements in at least the technical fields of image projection, holography, signal processing, and the like.DESCRIPTION OF THE DRAWINGS

[0015] These and other more detailed and specific features of various embodiments are more fully disclosed in the following description, reference being had to the accompanying drawings, in which:

[0016] FIG. 1 illustrates an example process for a video delivery pipeline

[0017] FIG. 2 A illustrates video timing for controlling a display device according to a first example.

[0018] FIG. 2B illustrates video timing for controlling a display device according to a second example.

[0019] FIG. 2C illustrates video timing for controlling a display device according to a third example.

[0020] FIG. 3A illustrates an example display panel for a display device.

[0021] FIG. 3B illustrates a detailed view of the display panel of FIG. 3 A.

[0022] FIG. 4 illustrates an example display panel for a display device including a row scheduler.

[0023] FIG. 5 illustrates an example frame provided on the display panel of FIG. 4.

[0024] FIG. 6 illustrates a flowchart of an example method performed by the row scheduler of FIG. 4.

[0025] FIG. 7 illustrates an example display panel for a display device including a column scheduler.

[0026] FIG. 8 illustrates an example frame provided on the display panel of FIG. 7.

[0027] FIG. 9 illustrates a flowchart of an example method performed by the column scheduler of FIG. 7.

[0028] FIG. 10 illustrates an example display panel for a display device including a tile scheduler.

[0029] FIG. 11 illustrates an example frame provided on the display panel of FIG. 10.

[0030] FIG. 12 illustrates a flowchart of an example method performed by the tile scheduler of FIG. 10.

[0031] FIG. 13 illustrates a flowchart of another example method performed by the tile scheduler of FIG. 10.

[0032] FIGS. 14A-14B illustrate example workflows for updating a screen during a scrolling operation.

[0033] FIG. 15 illustrates an example buffering of an image for a scrolling operation.

[0034] FIGS. 16A-16C illustrate example foveated views having different scanline orders.DETAILED DESCRIPTION

[0035] This disclosure and aspects thereof can be embodied in various forms, including hardware, devices or circuits controlled by computer-implemented methods, computer program products, computer systems and networks, user interfaces, and application programming interfaces; as well as hardware-implemented methods, signal processing circuits, memory arrays, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and the like. The foregoing is intended solely to give a general idea of various aspects of the present disclosure, and does not limit the scope of the disclosure in any way.

[0036] In the following description, numerous details are set forth, such as optical device configurations, timings, operations, and the like, in order to provide an understanding of one or more aspects of the present disclosure. It will be readily apparent to one skilled in the art that these specific details are merely exemplary' and not intended to limit the scope of this application.

[0037] Moreover, while the present disclosure focuses mainly on examples in which the various circuits are used in digital projection systems, it will be understood that these are merely examples. It will further be understood that the disclosed systems and methods can be used in any device in which there is a need to proj ect light; for example, cinema, consumer, and other commercial projection systems, heads-up displays, virtual reality displays, and the like. Disclosed systems and methods may be implemented in additional display devices, such as with an OLED display, an LCD display, a waveguide display, a quantum dot display, or the like.Video Coding of Display Signals

[0038] FIG. 1 depicts an example process of a video delivery pipeline 100 showing various stages from video capture to video content display. A sequence of video frames 102 is captured or generated using image generation block 105. Video frames 102 may be digitally captured (e.g. by a digital camera) or generated by a computer (e.g. using computer animation) to provide video data 107. Alternatively, video frames 102 may be captured on film by a film camera. The film is converted to a digital format to provide video data 107. In a production phase 110, video data 107 is edited to provide a video production stream 112.

[0039] The video data of production stream 112 is then provided to a processor (or one or more processors such as a central processing unit (CPU)) at block 115 for post-production editing. Post-production editing block 115 may include adjusting or modifying colors or brightness in particular areas of an image to enhance the image quality or achieve a particular appearance for the image in accordance with the video creator’s creative intent. This is sometimes called “color timing” or “color grading.” Other editing (e.g. scene selection and sequencing, image cropping, addition of computer-generated visual special effects, etc.) may be performed at post-production editing block 115 to yield a final version 117 of the production for distribution. For example, scanline frame timing and pixel order timing may be established during post-production editing block 115. During post-production editing block 115, video images are viewed on a reference display 125.

[0040] Following post-production editing block 115, video data of final production 117 may be delivered to encoding block 120 for delivering downstream to decoding and playback devices such as television sets, set-top boxes, movie theaters, and the like. In some embodiments, coding block 120 may include audio and video encoders, such as those defined by ATSC, DVB, DVD, Blu-Ray, and other delivery formats, to generate coded bit stream 122. Methods described herein may be performed by the processor at block 120. In a receiver, the coded bit stream 122is decoded by decoding unit 130 to generate a decoded signal 132 representing an identical or close approximation of signal 117. The receiver may be attached to a target display 140 which may have completely different characteristics than the reference display 125. In that case, a display management block 135 may be used to map the dynamic range of decoded signal 132 to the characteristics of the target display 140 by generating display-mapped signal 137. Additional methods described herein may be performed by the decoding unit 130 or the display management block 135. Both the decoding unit 130 and the display management block 135 may include their own processor, or may be integrated into a single processing unit.Video Timing

[0041] Traditionally, video data is transmitted to the target display 140 as individual scanlines. Scanlines are voltage values for each pixel in a single row of pixels forming the target display 140. Accordingly, while images may be considered as two-dimensional matrices, a scanline represents the image as a series of one-dimensional vectors. The scanlines are then used to control pixels in the target display 140 row by row . starting at the top-most row of pixels. For example, FIG. 2A provides an example display 200. As scanlines are received, a first line (Line 1) of pixels (the top-most line) are controlled according to the voltage values indicated by the scanline for each respective pixel. Once the last pixel value in the first line is set, the subsequent line (Line 2) of pixels are controlled according to the voltage values indicated by the subsequent scanline for each respective pixel. This process continues until the final, bottom-most line of pixels (Line N) is controlled according to the voltage values indicated by the final scanline for each respective pixel. Once the bottom-most line of pixels is set, the full image is provided, and the process begins from the beginning of the first line for the next image frame.

[0042] As pixels are controlled beginning with the top-most row, the top-most row of pixels have a relatively low latency and the bottom-most row of pixels have a relatively high latency compared to the top-most row of pixels. Additionally, as control of the pixels is independent of the content being displayed, a portion of the frame that is of high interest may be displayed after a portion of the frame that is low interest. For example, while movement may be occurring at a bottom of the video frame, the top of the video frame is updated first.

[0043] Accordingly, embodiments described herein provide for reordering the control of pixel rows based on scanlines. FIG. 2B provides the example display 200. Rather than controlling the rows of pixels beginning with the first line (Line 1 ) of pixels, the second line (Line 2) is first controlled according to the voltage values indicated by the first scanline for eachrespective pixel. Next, the third line (Line 3) of pixels is controlled according to the voltage values indicated by the second scanline for each respective pixel. This process is continued until each scanline is provided on the display 200, and the process begins from the beginning for the next image frame. In some instances, one scanline may be refreshed prior to completion of the image on the display 200, such as Line 3 in FIG. 2B. The ordering at which the scanlines are provided on the display 200 may stay constant for the duration of a displayed video, or may vary from frame to frame.

[0044] In the example of FIG. 2B, the ordering of the scanlines may be predetermined and indicated during post-production editing block 115. However, in other instances, the ordering of the scanlines may be determined by the target display 140 itself. For example, FIG. 2C provides the example display 200. Rather than the ordering of the scanlines being predetermined, a rule 205 is applied to received scanlines to determine the ordering of the scanlines. In some instances, the entire image is analyzed to determine which scanlines should be provided first. For example, a viewing direction of a gamer playing a first person shooter (FPS) game may first provide scanlines where a gun or similar in-game object is pointing. In instances where a headset includes eye-tracking, scanlines are first provided at the eye gaze of the user.

[0045] FIG. 3 A provides an example display panel 300 for a target display 140. The display panel includes an active matrix display 305 controlled by a row driver 310 and a column driver 315. The active matrix display 305 includes a pixel array circuit and may be, for example, a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, a quantum dot light-emitting diode (QLED) display, a microLED display, or the like. The row driver 310 selects a horizontal scanline of pixels by driving the gate contacts of the pixel transistors of said scanline. The column driver 315 selects a vertical scanline of pixels by driving the source contacts of the pixel transistors of said scanline. The row driver 310 and the column driver 315 work in tandem to control the order of control of pixels within the active matrix display 305. A timing controller 320 controls the timing of the scanline selection by the row driver 310 and the column driver 315.

[0046] FIG. 3B illustrates the display panel 300 in more detail. As shown in FIG. 3B, the active matrix display 305 includes a plurality of pixels 330. Each pixel 330 is composed of a first capacitor 335A, a second capacitor 335B, and a third capacitor 335C, individually referred to as capacitor 335. Each capacitor 335 stores a voltage value that controls an amount of emitted light. Additionally, each capacitor 335 emits a different colored light. For example, the firstcapacitor 335A emits a red light, the second capacitor 335B emits a green light, and the third capacitor 335C emits a blue light.

[0047] The row driver 310 selects which row of pixels 330 receives power. Particularly, in the illustrated example, the row driver 310 includes a flip flop circuit 340 for each row of pixels 330. By controlling the state of the flip flop circuits 340, the row driver 310 controls whether a row of pixels 330 receives power from the column driver 315. The column driver 315 sets the voltage value of each capacitor 335 forming a pixel. In the illustrated example, the column driver 315 includes a plurality of digital-to-analog converters (DAC) 345 configured to convert a binary value indicative of an amount of light to be emitted by each capacitor 335 to the voltage value provided to the capacitor 335. Operation of the row driver 310 and the column driver 315, including synchronizing operation of the flip flop circuits 340 and the DACs 345, are controlled by the timing controller 320. While FIG. 3B illustrates a plurality of pixels 330, capacitors 335, flip flop circuits 340. and DACs 345, only a single pixel 330, first capacitor 335A, second capacitor 335B, third capacitor 335C, flip flop circuit 340, and DAC 345 are labelled for purposes of clarity.

[0048] Scheduling Techniques

[0049] In some implementations, to dynamically order the scanlines, an additional controller (or scheduler) may be provided in addition to the timing controller 320. For example, FIG. 4 illustrates a display panel 400 that, in addition to the active matrix 305. the row driver 310. the column driver 315, and the timing controller 320, further includes a row scheduler 405. The row scheduler 405 changes the scheduling of the scanline selection by generating and outputting new timing control signals to the row driver 310 based on timing signals from the timing controller 320 and a new scanline schedule. In some implementations, timing instructions are predetermined and provided to the timing controller 320 (which reflects the order of the column data). The row scheduler 405 may receive metadata from the timing controller 320 indicating an order of the rows. The row schedule 405 may then shift the valid bit multiple times before output enable is high (thus controlling rows out of order), or in some instances, the rows are addressable and the row scheduler 405 addresses the rows as indicated by the metadata.

[0050] The new scanline schedule (e.g., an ordering of the scanlines) may be provided by an originator of the associated video data. For example, with reference to FIG. 1, the production block 110 receives video data 107 and, after editing, provides production stream 112 to the postproduction editing block 115. A scanline schedule may be established during post-productionediting block 115. The coding block 120 generates scanline metadata indicating a scanline scheduling. The scanline metadata is provided as part of coded bit stream 122. When the display management block 135 receives the scanlines and the metadata, the display management block 135 (or, for example, the row scheduler 405) reorders the scanlines according to the scanline scheduling. Rather than beginning updating of the active matrix 305 at the top-most row, a first row 410 is controlled based on the scanline scheduling.

[0051] In another example, the scanline scheduling is determined by the row scheduler 405. For example, the row scheduler 405 analyzes received video data to identify content of interest. Content of interest may include, for example, a face or object present over a large portion of the image, an area of varying colors, movement over several video frames, or the like. In some instances, the row scheduler 405 applies a machine-learned model to the video data to identify content of interest. The row scheduler 405 then prioritizes scanlines that create the content of interest such that the active matrix 305 is controlled to provide the scanlines associated with content of interest first.

[0052] FIG. 5 illustrates an example process of scheduling a frame for display. At step 500, a video frame is received by the timing controller 320. The video frame includes content of interest 502. At step 505, the frame is buffered as a buffered frame by the row scheduler 405. The buffered frame illustrates the order at which the scanlines of the video frame are provided. The first scanline 508 selected by the row scheduler 405 aligns with a beginning of the content of interest 502. At step 510, the buffered frame is provided on the active matrix 305 beginning with the first scanline 508.

[0053] FIG. 6 illustrates an example method 600 performed by the row scheduler 405. The steps provided within FIG. 6 are merely examples, and may instead be conducted in a different order or simultaneously.

[0054] At block 605, the row scheduler 405 receives a plurality of scanlines forming a video frame. For example, the timing controller 320 receives a coded bit stream 122 including a plurality of scanlines. The timing controller 320 provides the plurality of scanlines to the row scheduler 405. At block 610, the row scheduler 405 receives an indication of a scanline order. For example, the row scheduler 405 receives a scanline schedule included within the coded bit stream 122. In another example, the row scheduler 405 analyzes the plurality of scanlines to identify content of interest, as previously described.

[0055] At block 615. the row scheduler 405 reorders the plurality of scanlines according to the scanline order. At block 620, the row scheduler 405 controls the row driver 310 according to the reordered plurality of scanlines. For example, the row scheduler 405 controls the plurality of flip-flop circuits 340 according to the reordered plurality of scanlines.

[0056] In some implementations, in addition to the row scheduler 405, a column scheduler may be provided to control the order at which pixels within a scanline are updated. For example, FIG. 7 illustrates a display panel 700 that, in addition to the active matrix 305, the row driver 310, the column driver 315, the timing controller 320. and the row scheduler 405, further includes a column scheduler 705. The column scheduler 705 is situated between the timing controller 320 and the column driver 315. The column scheduler 705 reorders the order at which pixels on a scanline are updated within the active matrix 305 according to a pixel schedule. In some instances, data in the scanlines is partial column data, and the timing controller 320 receives metadata indicating how many columns and / or which columns need to be updated before an output enable on a row- is issued. In such instances, the column scheduler 705 loads the required columns and stops based on the metadata.

[0057] Similar to the scanline schedule, the pixel schedule may be provided by an originator of the associated video data. For example, with reference to FIG. 1 , the production block 110 receives video data 107 and, after editing, provides production stream 112 to the postproduction editing block 115. A pixel schedule may be established during post-production editing block 115. The coding block 120 generates pixel metadata indicating a pixel scheduling. The pixel metadata is provided as part of coded bit stream 122. When the display management block 135 receives the scanlines and the metadata, the display management block 135 (or, for example, the column scheduler 705) reorders the pixel control according to the pixel scheduling. Rather than beginning updating of the active matrix 305 at the left-most pixel, a first pixel 710 is controlled based on the pixel scheduling.

[0058] FIG. 8 illustrates an example process of scheduling a frame for display. At step 800, a video frame is received by the timing controller 320. The video frame includes content of interest 802. At step 805, the frame is buffered as a buffered frame by the row scheduler 405. The buffered frame illustrates the order at w hich the scanlines of the video frame are provided. The first scanline 806 selected by the row scheduler 405 aligns w ith a beginning of the content of interest 802. Additionally, the buffered frame illustrates the order in which pixels are updated within the scanlines. For example, a first pixel 808 selected by the column scheduler 705 alignswith the beginning of the content of interest 802. At step 810, the buffered frame is provided on the active matrix 305 beginning with the first scanline 806 and the first pixel 808.

[0059] FIG. 9 illustrates an example method 900 performed by the column scheduler 705. The steps provided within FIG. 9 are merely examples, and may instead be conducted in a different order or simultaneously.

[0060] At block 905, the column scheduler 705 receives a plurality of pixel values forming a scanline. For example, the timing controller 320 receives a coded bit stream 122 including a plurality of scanlines. The timing controller 320 provides the plurality of scanlines to the row scheduler 405. The timing controller 320 provides the values of pixels forming the scanline to the column scheduler 705. At block 910, the column scheduler 705 receives a pixel value order indicating an order in which the pixels forming the scanline are updated. For example, the column scheduler 705 receives a pixel schedule included within the coded bit stream 122. At block 915, the column scheduler 705 controls the column driver 315 according to the pixel value order. For example, the plurality of digital-to-analog converters 345 are controlled in the order of the pixel value order.

[0061] In some implementations, in addition to the row scheduler 405 and the column scheduler 705, a tile scheduler may be provided to update only a subset of the pixels provided on the active matrix 305. For example, FIG. 10 illustrates a display panel 1000 that, in addition to the active matrix 305, the row driver 310, the column driver 315, the timing controller 320, the row scheduler 405, and the column scheduler 705, further includes a tile scheduler 1005. The tile scheduler 1005 receives the coded bit stream 122 and provides the coded bit stream 122, including video data and the scanlines, to the timing controller 320. The tile scheduler 1005 schedules for only a subset of pixels in the active matrix 305 to be updated, while previous data stored in a memory 1010 is used for the remaining pixels on the same scanline to update the full scanline via the column driver 315.

[0062] Similar to the scanline schedule and the pixel schedule, a tile of pixels may be provided by an originator of the associated video data. For example, a tile of pixels (e.g., a subset of the pixels to be updated) may be established during post-production editing block 115. The tile of pixels may be, for example, content of high priority or high interest. The tile of pixels is then provided alongside the coded bit stream 122 as metadata. When the tile scheduler 1005 receives the tile of pixels, the tile scheduler 1005 fills in the remainder of the scanline with pixel values from the previous frame that are stored in the memory 1010. The column scheduler 705and the row scheduler 405 may then be controlled to provide the pixels in the tile of pixels first, and then control the remaining pixels within the scanline.

[0063] In another example, the tile of pixels is determined by the tile scheduler 1005. For example, the tile scheduler 1005 analyzes received video data to identify content of interest. Content of interest may include, for example, a face or object present over a large portion of the image, an area of varying colors, or the like. The tile scheduler 1005 then prioritizes pixels that create the content of interest such that the active matrix 305 is controlled to provide the pixels associated with content of interest first.

[0064] FIG. 11 illustrates an example process of scheduling a frame having a tile of pixels for display. At step 1100, a video frame is received by the tile scheduler 1005. The video frame includes content of interest 1102. At step 1105, the frame is buffered as a buffered frame by the tile scheduler 1005. The buffered frame illustrates the order at which the pixels of the video frame are provided. The tile of pixels 1108 selected by the tile scheduler 1005 aligns with a beginning of the content of interest 1102. Additionally, the buffered frame illustrates the order in which pixels are updated by the timing controller 320. At step 1110, the buffered frame is provided on the active matrix 305 beginning with the tile of pixels 1108. After the tile of pixels 1108 are provided on the active matrix 305, remaining pixels 1112 are provided on the active matrix 305.

[0065] FIG. 12 illustrates an example method 1200 performed by the tile scheduler 1005. In some implementations, the method 1200 is performed by the tile scheduler 1005 in conjunction with the timing controller 320. The steps provided within FIG. 12 are merely examples, and may instead be conducted in a different order or simultaneously.

[0066] At block 1205, the tile scheduler 1005 receives a plurality of pixels forming scanlines within a video frame. For example, the tile scheduler 1005 receives a coded bit stream 122 including a plurality7of scanlines, the scanlines formed of a plurality7of pixels. At block 1210, the tile scheduler 1005 receives an indication of a tile of pixels. For example, the tile scheduler 1005 receives a tile of pixels included within the coded bit stream 122. In some instances, the tile scheduler 1005 determines a tile of pixels by identifying content of interest within the video frame. In some instances, the coded bit stream 122 only includes the tile of pixels.

[0067] At block 1215, the tile scheduler 1005 reorders the pixel value order and the scanline order according to the tile of pixels. For example, the tile scheduler 1005 reorders the scanlines and the pixel value order w ithin each scanline to prioritize the tile of pixels, as shown in step1110 of FIG. 11. At block 1220. the tile scheduler 1005 controls the row driver 310 according to the reordered scanlines. For example, the tile scheduler 1005 controls the plurality of flip-flop circuits 340 according to the reordered plurality of scanlines. In some instances, the tile scheduler 1005 controls the row driver 310 by transmitting commands to the timing controller 320 and, therefore, the row scheduler 405. At block 1225, the tile scheduler 1005 controls the column driver 315 according to the reordered pixel values. For example, the tile scheduler 1005 controls the plurality of digital-to-analog converters 345 in the order of the reordered pixel value order. In some instances, the tile scheduler 1005 controls the column driver 315 by transmitting commands to the timing controller 320 and, therefore, the column scheduler 705.

[0068] FIG. 13 illustrates another example method 1300 performed by the tile scheduler 1005. In some implementations, the method 1300 is performed by the tile scheduler 1005 in conjunction with the timing controller 320. The steps provided within FIG. 13 are merely examples, and may instead be conducted in a different order or simultaneously.

[0069] At block 1305, the tile scheduler 1005 receives a tile of pixels forming a portion of a video frame. For example, the tile scheduler 1005 receives a coded bit stream 122 including a tile of pixels. At block 1310, the tile scheduler 1005 obtains remaining pixel values from memory. For example, the tile scheduler 1005 obtains remaining pixels 1112 from the memory 1010. At block 1315, the tile scheduler 1005 controls the row driver 310 and the column driver 315 to provide the tile of pixels. For example, the tile scheduler 1005 controls the row driver 310 and the column driver 315 to provide the tile of pixels 1108, as shown in FIG. 11. At block 1320, the tile scheduler 1005 controls the row driver 310 and the column driver 315 to provide the remaining pixel values. For example, the tile scheduler 1005 controls the row driver 310 and the column driver 315 to provide the remaining pixels 1112, as shown in FIG. 11.

[0070] Any one or more of the timing controller 320, the row scheduler 405, the column scheduler 705, and the tile scheduler 1005 may include an electronic processor and a memory to perform the methods described herein. The electronic processor and the memory communicate over one or more control and / or data buses. In some examples, the electronic processor is implemented as a microprocessor with separate memory. In other examples, the electronic processor is implemented as a microcontroller where the memory is on the same chip. The electronic processor may be implemented with multiple processors, and may be implemented partially or entirely as, for example, a field-programmable gate array (FPGA) or an applications specific integrated circuit (ASIC).

[0071] The memory included in any one or more of the timing controller 320, the row scheduler 405, the column scheduler 705, and the tile scheduler 1005, or the memory 1010, includes non-transitory, computer-readable memory' that stores instructions that are received and executed by the respective electronic processor to carry out the functionality of the display panels described herein. The memory may include, for example, combinations of different types of memory, such as read-only memory and random-access memory.

[0072] Additionally, the example display panels described in FIG. 4, FIG. 7, and FIG. 10 are not intended to be exclusive. Embodiments described herein include various combinations of said display panels, such as a display panel including only a column scheduler 705, a display panel including only a tile scheduler 1005 and a row scheduler 405, and the like. Accordingly, in some embodiments, the method 600, the method 900, the method 1200, and / or the method 1300 may be combined and / or altered for each display system. Rather than being implemented via separate hardware, the row scheduler 405, the column scheduler 705, the tile scheduler 1005. and the timing controller 320 may instead be implemented onto the same hardware (e.g., a single controller or two or more controllers performing the operations described herein).

[0073] Example Use Cases

[0074] Embodiments described herein provide many advantages in responsiveness, latency, and power usage of display devices. One example use case is found in scrolling on a display device of a mobile phone or personal computer. For example, the row scheduler 405 assists in decoupling updating the screen during touch events from rendering with the local central processing unit (CPU) and graphics processing unit (GPU). For example, an extended framebuffer may be pre-rendered such that content that may be shown based on a user scrolling on the screen is pre-prepared for viewing by the timing controller 320. When the scrolling exceeds the extended framebuffer, the CPU and GPU are utilized to update the extended framebuffer.

[0075] For example, FIG. 14A illustrates a traditional workflow 1400 for updating a display during a scrolling operation. A touchscreen 1405 receives a touch input from a user. The touch input is provided to a CPU 1410 (event A). The CPU 1410 generates a command provided to a GPU 1415 instructing the GPU 1415 on how to update the image provided on the display in response to the touch input (event B). The GPU 1415 renders the image and provides the rendering as a framebuffer 1420 (event C) (for example, a plurality of scanlines). The framebuffer 1420 is then provided (e.g., scanned) to the display 1425 (event D). Accordingly,several operations occur from receiving the user input to updating the display to reflect the user input.

[0076] However, the use of the row scheduler 405 (or, in some cases, the row scheduler 405 in combination with the column scheduler 705 and / or the tile scheduler 1005) allows the workflow 1400 to be streamlined. For example, FIG. 14B illustrates a revised workflow 1450 for updating a display during a scrolling operation. In the workflow 1450, a frame is fully loaded and stored as a framebuffer. For example, FIG. 15 illustrates a buffered image 1500 and a displayed image 1505. The displayed image 1505 is an image actively provided on a display. However, a user may scroll to view an additional portion of the image that is not shown within the displayed image 1505. Accordingly, the buffered image 1500 illustrates the displayed image 1505 as well as an additional buffer should a user scroll either upwards or downw ards. The buffered image 1500 may be an entire buffered image, or may be only a portion of an image. In some instances, the buffered image 1500 and the displayed image 1505 also include a top status bar 1510 and a bottom status bar 1520 that are displayed regardless of touch events. The buffered image 1500 may be stored in, for example, a memory of the timing controller 320.

[0077] Referring back to FIG. 14B, when a touch event is received by the touchscreen 1405. the timing controller 320 determines whether the touch event moves the displayed image 1505 within scroll limits (e.g., within what is buffered by the image 1500). When the touch event moves the displayed image 1505 beyond the scroll limits, the events A, B, C, and D are performed as described with respect to FIG. 14A. However, when the touch event is within the scroll limits, the image to be displayed is already buffered, and the timing controller 320 automatically updates the display (e.g., goes from event A directly to event D). Accordingly, usage of the CPU and GPU may be reduced, providing for a faster updating of the display.

[0078] Embodiments described herein may also provide advantages for foveated display rendering. Virtual reality (VR) view s are traditionally updated in the same manner as television, beginning with updating the top-most left-most pixel. However, in VR settings, a user may not be looking in the direction of the top-most left-most pixel, causing latency in updating the view where the user is actually looking. For example, FIG. 16A provides a foveated view 1600 that may be provided in a VR environment. The foveated view 1600 is updated as a plurality of scanlines 1605 beginning at time t. The total amount of time to update all of the plurality of scanlines 1605 is t-Tfr. However, the view of the user is traditionally approximately 30° downwards from the top of the foveated view 1600. provided by region of interest 1610. The scanlines associated with the region of interest 1610 have a latency of Tfr / 3.

[0079] Accordingly, a first scanline may instead by selected based on where the user is looking (fovea first), where new events are anticipated (salient region of interest first), or where motion and latency is most sensitive to the viewer (peripheral first). For example, as shown in FIG. 16B, a first scanline may be set at the region of interest 1610 such that the region of interest 1610 is updated first. The remainder of the scanlines are then provided simultaneously upwards and downwards from the region of interest 1610 until the entire frame is updated.

[0080] In other instances, it may be advantageous to provide more of the image quickly albeit at a lower quality (for example, instances where latency is preferred over image quality). In such instances, alternating scanlines may be updated, as shown in FIG. 16C. In FIG. 16C, every other scanline is updated beginning at the top of the foveated view 1600. Once the bottom scanline is updated, the remaining scanlines are updated to “fill in the blanks'’ of the updated foveated view. Accordingly, a low-resolution view is initially provided before the high- resolution final frame.

[0081] Embodiments described herein may also provide advantages to non-traditional display systems. For example, augmented reality and mixed reality systems implement a camera to display the real world to a viewer. The camera captures the full image frame and provides the image frame to a GPU. The GPU renders the captured image and transmits the image to the display, which is then provided as scanlines beginning with the top-most scanline. Embodiments described herein may prioritize providing scanlines based on a view' of the user, as described with respect to FIG. 16B in a virtual reality environment.

[0082] Similarly, cameras are commonly used in driver-assist systems for automotive vehicles. Driver-assist systems implement one or more cameras to observ e the environment around the vehicle. Scanlines are provided to machine-learned models to make response decisions. For example, when a machine-learned model detects a pedestrian about to walk in front of the vehicle, the machine-learned model may control the vehicle to brake. As these decisions are made quickly, scanlines may be provided to the machine-learned model in a different order, speeding up the decision-making process.

[0083] The above video delivery' systems and methods may provide for dynamic video timing for display devices. Systems, methods, and devices in accordance with the present disclosure may take any one or more of the following configurations.

[0084] (1) A display control system comprising: an active matrix including a plurality of pixels forming a plurality' of rows and a plurality' of columns; a column driver configured tocontrol the plurality of columns of pixels; a row driver configured to control the plurality of rows of pixels; and a controller configured to: receive a plurality of scanlines forming a video frame, receive an indication of a scanline order, the scanline order indicative of an order at which the plurality' of rows of pixels are controlled, reorder the plurality of scanlines according to the scanline order, and control the row driver according to the reordered plurality of scanlines.

[0085] (2) The display control system according to (1), wherein the controller is further configured to: receive a plurality of pixel values forming the plurality of scanlines, receive a pixel value order indicating an order in which the pixels forming at least one of the scanlines are updated, and control the column driver according to the pixel value order.

[0086] (3) The display control system according to any one of (1) to (2), wherein the controller is further configured to: receive a plurality of pixel values forming the plurality of scanlines, receive an indication of a tile of pixels, reorder the plurality' of scanlines according to the tile of pixels, reorder an order in which the pixels forming at least one of the scanlines are updated based on the tile of pixels, control the row driver according to the reordered scanlines, and control the column driver according to the reordered pixels.

[0087] (4) The display control system according to any one of (1) to (3), wherein the controller is further configured to: receive a plurality' of pixel values forming the plurality' of scanlines, receive an indication of a tile of pixels, obtain remaining pixel values that are not included in the tile of pixels from a memory, control the row driver and the column driver to provide the tile of pixels, and control, after providing the tile of pixels, the row driver and the column driver to provide the remaining pixel values.

[0088] (5) The display control sy stem according to any one of (1) to (4), wherein the indication of a scanline order is received as metadata alongside the plurality' of scanlines.

[0089] (6) The display control system according to any one of (1) to (5), wherein the controller is further configured to reorder the plurality of scanlines according to the scanline order by selecting a first scanline that aligns with content of interest in the video frame.

[0090] (7) The display control system according to any one of (1) to (6), wherein the indication of a scanline order indicates an alternating pattern of the plurality of scanlines.

[0091] (8) The display control system according to any one of (1) to (7), wherein the display control system is implemented in one selected from the group consisting of an augmented reality system, a mixed reality system, and a virtual reality system.

[0092] (9) The display control system according to (7), wherein the display control system is implemented within a virtual reality headset, and wherein the controller is further configured to reorder the plurality7of scanlines according to the scanline order by selecting a first scanline that aligns with a view of a user of the virtual reality headset.

[0093] (10) The display control system according to any one of (1) to (9), wherein the controller is further configured to: buffer the plurality of scanlines in a memory', control the row driver to provide a subset of the plurality' of scanlines, receive a touch command indicative of a scrolling operation, obtain, in response to the touch command, additional scanlines from the memory, and control the row driver to provide the additional scanlines.

[0094] (11) A method for dynamic video timing on display devices, the method comprising: receiving a plurality of scanlines forming a video frame, wherein the video frame is provided on an active matrix including a plurality of pixels forming a plurality of rows and a plurality of columns; receiving an indication of a scanline order, the scanline order indicative of an order at which the plurality' of rows of pixels are controlled, reordering the plurality' of scanlines according to the scanline order, and controlling a row driver according to the reordered plurality of scanlines.

[0095] (12) The method according to (11), further comprising: receiving a plurality' of pixel values forming the plurality of scanlines, receiving a pixel value order indicating an order in which the pixels forming at least one of the scanlines are updated, and controlling a column driver according to the pixel value order.

[0096] (13) The method according to any one of (11) to (12), further comprising: receiving a plurality of pixel values forming the plurality of scanlines, receiving an indication of a tile of pixels, reordering the plurality of scanlines according to the tile of pixels, reordering an order in which the pixels forming at least one of the scanlines are updated based on the tile of pixels, controlling a row driver according to the reordered scanlines, and controlling a column driver according to the reordered pixels.

[0097] (14) The method according to any one of (11) to (13), further comprising: receiving a plurality' of pixel values forming the plurality' of scanlines, receiving an indication of a tile of pixels, obtaining remaining pixel values that are not included in the tile of pixels from a memory, controlling a row driver and a column driver to provide the tile of pixels, and controlling the row driver and the column driver to provide the remaining pixel values.

[0098] (15) The method according to any one of (11) to (14), wherein the indication of a scanline order is received as metadata alongside the plurality of scanlines.

[0099] (16) The method according to any one of (11) to (15), wherein reordering the plurality of scanlines according to the scanline order includes selecting a first scanline that aligns with content of interest in the video frame.

[0100] (17) The method according to any one of (11) to (16), wherein the indication of a scanline order indicates an alternating pattern of the plurality of scanlines.

[0101] (18) The method according to any one of (11) to (17), wherein the method is performed by one selected from the group consisting of an augmented reality device, a mixed reality device, and a virtual reality device.

[0102] (19) The method according to claim 18, wherein the method is performed by a virtual reality headset, wherein reordering the plurality of scanlines according to the scanline order includes selecting a first scanline that aligns with a view of a user of the virtual reality headset.

[0103] (20) A non-transitory computer-readable medium storing instructions that, when executed by a processor of a video delivery' pipeline, cause the video delivery pipeline to perform operations comprising the method according to any one of (11) to (19).

[0104] (21) A video pipeline for providing video data, the video pipeline comprising: a processor configured to: receive a video frame from an image generation device, convert the video frame to a plurality of scanlines, each scanline representing a row of pixels, generate scanline metadata indicative of an order of the scanlines, and encode the video frame and the scanline metadata as encoded video data.

[0105] (22) A method for providing video data, the method comprising: receiving a video frame from an image generation device; converting the video frame to a plurality of scanlines, each scanline representing a row of pixels; generating scanline metadata indicative of an order of the scanlines; and encoding the video frame and the scanline metadata as encoded video data.

[0106] (23) A non-transitory computer-readable medium storing instructions that, when executed by a processor of a video delivery pipeline, cause the video delivery' pipeline to perform operations comprising the method according to (22).

[0107] With regard to the processes, systems, methods, heuristics, etc. described herein, it should be understood that, although the steps of such processes, etc. have been described asoccurring according to a certain ordered sequence, such processes could be practiced with the described steps performed in an order other than the order described herein. It further should be understood that certain steps could be performed simultaneously, that other steps could be added, or that certain steps described herein could be omitted. In other words, the descriptions of processes herein are provided for the purpose of illustrating certain embodiments, and should in no way be construed so as to limit the claims.

[0108] Accordingly, it is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments and applications other than the examples provided would be apparent upon reading the above description. The scope should be determined, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. It is anticipated and intended that future developments will occur in the technologies discussed herein, and that the disclosed systems and methods will be incorporated into such future embodiments. In sum, it should be understood that the application is capable of modification and variation.

[0109] All terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those knowledgeable in the technologies described herein unless an explicit indication to the contrary' is made herein. In particular, use of the singular articles such as “a,” “the,’' “said,’' etc. should be read to recite one or more of the indicated elements unless a claim recites an explicit limitation to the contrary.

[0110] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted w ith the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments incorporate more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in fewer than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

Claims

CLAIMSWhat is claimed is:

1. A display control system comprising: an active matrix including a plurality of pixels forming a plurality of rows and a plurality of columns; a column driver configured to control the plurality of columns of pixels; a row driver configured to control the plurality of rows of pixels; and a controller configured to: receive a plurality' of scanlines forming a video frame, each scanline comprising a voltage value for each pixel of a single row of pixels forming the video frame; receive an indication of a scanline order, the scanline order indicative of an order at which the plurality of rows of pixels are controlled, reorder the plurality' of scanlines according to the scanline order, and control the row driver according to the reordered plurality of scanlines; wherein the indication of the scanline order is received as metadata alongside the plurality of scanlines.

2. The display control system of claim 1, wherein the controller is configured to: receive a plurality of pixel values forming the plurality of scanlines. receive a pixel value order indicating an order in which the pixels forming at least one of the scanlines are updated, and control the column driver according to the pixel value order.

3. The display control system of claim 2. wherein the pixel value order is received as metadata alongside the plurality of scanlines.

4. The display control system of any of claims 1 to 3, wherein the controller is configured to: receive a plurality of pixel values forming the plurality of scanlines, receive an indication of a tile of pixels. reorder the plurality of scanlines according to the tile of pixels,reorder an order in which the pixels forming at least one of the scanlines are updated based on the tile of pixels, control the row driver according to the reordered scanlines, and control the column driver according to the reordered pixels.

5. The display control system of any of claims 1 to 4, wherein the controller is configured to: receive a plurality of pixel values forming the plurality of scanlines, receive an indication of a tile of pixels, obtain remaining pixel values that are not included in the tile of pixels from a memory, control the row driver and the column driver to provide the tile of pixels, and control, after providing the tile of pixels, the row driver and the column driver to provide the remaining pixel values.

6. The display control system of any of claims 1 to 5, wherein the controller is further configured to reorder the plurality of scanlines according to the scanline order by selecting a first scanline that aligns with content of interest in the video frame.

7. The display control system of any of claims 1 to 6, wherein the indication of a scanline order indicates an alternating pattern of the plurality of scanlines.

8. The display control system of any of claims 1 to 7, wherein the display control system is implemented in one selected from the group consisting of an augmented reality system, a mixed reality system, and a virtual reality system.

9. The display control system of claim 8, wherein the display control system is implemented within a virtual reality headset, and wherein the controller is further configured to reorder the plurality of scanlines according to the scanline order by selecting a first scanline that aligns with a view of a user of the virtual reality headset.

10. The display control system of any of claims 1 to 9, wherein the controller is further configured to: buffer the plurality of scanlines in a memory, control the row driver to provide a subset of the plurality of scanlines, receive a touch command indicative of a scrolling operation,obtain, in response to the touch command, additional scanlines from the memory, and control the row driver to provide the additional scanlines.

11. The display control system of any of claims 1 to 10, wherein the controller is configured, in response to receiving metadata indicating a scanline order, to shift a valid bit multiple times before output enable is high, thereby controlling the row driver in accordance with the scanline order.

12. The display control system of any of claims 1 to 10, wherein the controller is configured, in response to receiving metadata indicating a scanline order, to address the rows as indicated by the metadata, thereby controlling the row driver in accordance with the scanline order.

13. The display control system of claim 3, wherein the metadata indicating a pixel order value indicates how many columns and / or which columns are to be updated before an output enable on a row is issued; and wherein the controller is configured to load the required columns and stop according to the metadata.

14. The display control system of any preceding claim, wherein controlling the row driver according to the reordered plurality of scanlines comprises refreshing at least one scanline prior to completion of the plurality of scanlines on a display.

15. A video pipeline for providing video data, the video pipeline comprising: a processor configured to: receive a video frame from an image generation device, convert the video frame to a plurality of scanlines, each scanline representing a row of pixels. generate scanline metadata indicative of an order of the scanlines, and encode the video frame and the scanline metadata as encoded video data.

16. A method for dynamic video timing on display devices, the method comprising: receiving a plurality’ of scanlines forming a video frame, each scanline comprising a voltage value for each pixel of a single row of pixels forming the video frame, wherein the video frame is provided on an active matrix including a plurality of pixels forming a plurality' of rows and a plurality’ of columns;receiving an indication of a scanline order, the scanline order indicative of an order at which the plurality of rows of pixels are controlled, reordering the plurality of scanlines according to the scanline order, and controlling a row driver according to the reordered plurality of scanlines; wherein the indication of a scanline order is received as metadata alongside the plurality of scanlines.

17. The method of claim 16, further comprising: receiving a plurality’ of pixel values forming the plurality of scanlines, receiving a pixel value order indicating an order in which the pixels forming at least one of the scanlines are updated, and controlling a column driver according to the pixel value order.

18. The method of claim 16 or 17, further comprising: receiving a plurality of pixel values forming the plurality of scanlines, receiving an indication of a tile of pixels, reordering the plurality of scanlines according to the tile of pixels. reordering an order in which the pixels forming at least one of the scanlines are updated based on the tile of pixels, controlling a row driver according to the reordered scanlines, and controlling a column driver according to the reordered pixels.

19. The method of any of claims 16-18, further comprising:Receiving an indication of a tile of pixels,Obtaining remaining pixel values that are not included in the tile of pixels from a memory, controlling a row driver and a column driver to provide the tile of pixels, and controlling the row driver and the column driver to provide the remaining pixel values.

20. The method of any of claims 16-19, wherein reordering the plurality of scanlines according to the scanline order includes selecting a first scanline that aligns with content of interest in the video frame.

21. The method of any of claims 16-20, wherein the indication of a scanline order indicates an alternating pattern of the plurality of scanlines.

22. The method of any of claims 16-21, wherein the method is performed by one selected from the group consisting of an augmented reality device, a mixed reality device, and a virtual reality device.

23. The method of claim 22, wherein the method is performed by a virtual reality headset, wherein reordering the plurality of scanlines according to the scanline order includes selecting a first scanline that aligns with a view of a user of the virtual reality' headset.

24. The method of claim 17 or any claim dependent thereon, wherein the pixel value order is received as metadata alongside the plurality of scanlines.

25. The method of any of claims 16-24, comprising, based on the metadata indicating a scanline order, shifting a valid bit multiple times before output enable is high, thereby controlling the row driver in accordance with the scanline order.

26. The method of any of claims 16-25, comprising addressing the rows as indicated by the metadata, thereby controlling the row driver in accordance with the scanline order.

27. The method of claim 24, wherein the metadata indicating a pixel order value indicates how many columns and / or which columns are to be updated before an output enable on a row is issued; and wherein the controller is configured to load the required columns and stop according to the metadata.

28. The method of any of claims 16-27, wherein controlling the row driver according to the reordered plurality of scanlines comprises refreshing at least one scanline prior to completion of the plurality of scanlines on a display.

29. A method for providing video data, the method comprising: receiving a video frame from an image generation device; converting the video frame to a plurality of scanlines, each scanline representing a row of pixels; generating scanline metadata indicative of an order of the scanlines; and encoding the video frame and the scanline metadata as encoded video data.

30. A non-transitory computer-readable medium storing instructions that, when executed by a processor of a video delivery pipeline, cause the video delivery pipeline to perform operations comprising the method according to any of claims 16 to 29 .

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