Thin film transistor and manufacturing method therefor, and display panel

Abstract

The present application provides a thin film transistor and a manufacturing method therefor, and a display panel. The thin film transistor comprises: a middle part comprising a carrier transport portion and a gate insulating portion, wherein the carrier transport portion is located on a side of the gate insulating portion in a first direction; and a first end and a second end respectively connected to opposite sides of the middle part in a second direction, the first end comprising a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, the second end comprising a second heavily doped portion connected to the carrier transport portion and the gate insulating portion, the thickness of the first and second heavily doped portions in the first direction is greater than the thickness of the carrier transport portion in the first direction, and the second direction intersecting with the first direction.

Description

Thin film transistor, manufacturing method thereof, and display panel

[0001] This application claims priority to Chinese patent application No. 202311581384.6 filed on November 22, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to, but is not limited to, the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, and a display panel. Background Art

[0003] Currently, integrating the control circuits of a display panel, such as a gate-on-array (GOA), a source driver circuit, and a timing controller, on an insulating substrate can greatly improve the integration of the display panel and reduce the manufacturing cost of the display panel. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a thin film transistor, a manufacturing method thereof, and a display panel to improve the electrical performance of the thin film transistor, thereby improving the display effect of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a thin film transistor, comprising:

[0006] An active layer, the active layer comprising:

[0007] a middle portion, the middle portion including a carrier transport portion and a gate insulating portion, the carrier transport portion being located on one side of the gate insulating portion in the first direction; and

[0008] a first end portion and a second end portion, wherein the first end portion and the second end portion are respectively connected to opposite sides of the middle portion in a second direction, the first end portion includes a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, and the second end portion includes a second heavily doped portion connected to the carrier transport portion and the gate insulating portion, the thickness of the first heavily doped portion and the second heavily doped portion along the first direction is greater than the thickness of the carrier transport portion along the first direction, and the second direction intersects the first direction;

[0009] a gate located on a side of the gate insulating portion away from the carrier transport portion in the first direction and overlapping with the carrier transport portion; and

[0010] The source and the drain are connected to the first heavily doped portion and the second heavily doped portion respectively.

[0011] In a second aspect, an embodiment of the present application further provides a display panel, the display panel including a thin film transistor and a light emitting device, wherein the light emitting device is connected to the thin film transistor; the thin film transistor includes:

[0012] An active layer, the active layer comprising:

[0013] a middle portion, the middle portion including a carrier transport portion and a gate insulating portion, the carrier transport portion being located on one side of the gate insulating portion in the first direction; and

[0014] a first end portion and a second end portion, wherein the first end portion and the second end portion are respectively connected to opposite sides of the middle portion in a second direction, the first end portion includes a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, and the second end portion includes a second heavily doped portion connected to the carrier transport portion and the gate insulating portion, the thickness of the first heavily doped portion and the second heavily doped portion along the first direction is greater than the thickness of the carrier transport portion along the first direction, and the second direction intersects the first direction;

[0015] a gate located on a side of the gate insulating portion away from the carrier transport portion in the first direction and overlapping with the carrier transport portion; and

[0016] The source and the drain are connected to the first heavily doped portion and the second heavily doped portion respectively.

[0017] In a third aspect, an embodiment of the present application further provides a method for manufacturing a thin film transistor, the method comprising:

[0018] forming an amorphous silicon layer on the base layer;

[0019] performing oxidation treatment on a portion of the surface of the amorphous silicon layer to form a gate insulating portion, wherein a portion of the amorphous silicon layer remaining in the first direction is located between the gate insulating portion and the base layer; and

[0020] The remaining amorphous silicon is processed by an excimer laser annealing process to form a first polycrystalline portion, a second polycrystalline portion and an initial crystallization inducing portion, wherein the first polycrystalline portion is located between the gate insulating portion and the base layer in the first direction, and the initial crystallization inducing portion is located between the second polycrystalline portion and the base layer in the first direction, and the second polycrystalline portion is adjacent to and connected to the gate insulating portion in the second direction, and the initial crystallization inducing portion is adjacent to and connected to the first polycrystalline portion in the second direction, and the first direction and the second direction intersect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic cross-sectional view of an optional display device provided in an embodiment of the present application;

[0022] FIG2 is a schematic cross-sectional view of an optional array substrate provided in an embodiment of the present application;

[0023] FIG3 is a schematic diagram of a partial planar structure of an optional array substrate provided in an embodiment of the present application;

[0024] FIG4 is a schematic diagram of a process for manufacturing an optional thin film transistor provided in an embodiment of the present application;

[0025] 5A to 5F are schematic structural diagrams of an optional thin film transistor manufacturing process provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0027] The embodiments of the present application provide a thin film transistor, a method for manufacturing the same, and a display panel, which can improve the electrical performance of the thin film transistor and thereby improve the display effect of the display panel.

[0028] An embodiment of the present application provides a thin film transistor, including:

[0029] An active layer, the active layer comprising:

[0030] a middle portion, the middle portion including a carrier transport portion and a gate insulating portion, the carrier transport portion being located on one side of the gate insulating portion in the first direction; and

[0031] a first end portion and a second end portion, wherein the first end portion and the second end portion are respectively connected to opposite sides of the middle portion in a second direction, the first end portion includes a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, and the second end portion includes a second heavily doped portion connected to the carrier transport portion and the gate insulating portion, the thickness of the first heavily doped portion and the second heavily doped portion along the first direction is greater than the thickness of the carrier transport portion along the first direction, and the second direction intersects the first direction;

[0032] a gate located on a side of the gate insulating portion away from the carrier transport portion in the first direction and overlapping with the carrier transport portion; and

[0033] The source and the drain are connected to the first heavily doped portion and the second heavily doped portion respectively.

[0034] According to an embodiment of the present application, the gate insulating portion includes silicon oxide, and a thickness of the gate insulating portion is greater than or equal to 300 angstroms and less than or equal to 700 angstroms.

[0035] According to an embodiment of the present application, the sum of the thickness of the gate insulating portion along the first direction and the thickness of the carrier transport portion along the first direction is greater than the thickness of the first heavily doped portion and the second heavily doped portion along the first direction.

[0036] According to one embodiment of the present application, the carrier transport portion includes a first lightly doped portion, a second lightly doped portion and a channel portion, and in the second direction, the first lightly doped portion and the second lightly doped portion are connected to opposite sides of the channel portion, the first lightly doped portion is connected to the first heavily doped portion, and the second lightly doped portion is connected to the second heavily doped portion.

[0037] According to an embodiment of the present application, the carrier transport portion includes a crystalline phase material;

[0038] At least one of the first end portion and the second end portion includes a crystallization inducing portion, the crystallization inducing portion is located on one side of at least one of the first heavily doped portion and the second heavily doped portion in the first direction and is connected to the carrier transport portion.

[0039] According to an embodiment of the present application, a thickness of the crystallization inducing portion along the first direction is smaller than a thickness of the carrier transporting portion along the first direction.

[0040] According to an embodiment of the present application, the first heavily doped portion, the second heavily doped portion, and the carrier transport portion include polycrystalline silicon, and the crystallization inducing portion includes amorphous silicon.

[0041] According to an embodiment of the present application, a thickness of the crystallization inducing portion along the first direction is greater than 0 angstrom and less than or equal to 100 angstroms.

[0042] According to the thin film transistor provided in the above embodiments of the present application, an embodiment of the present application further provides a display panel, which includes the thin film transistor provided in any one of the above embodiments and a light-emitting device, wherein the light-emitting device is connected to the thin film transistor.

[0043] Beneficial effects of embodiments of the present application: In some embodiments of the thin-film transistor, an active layer includes a middle portion, a first end portion, and a second end portion, with the first end portion and the second end portion connected to opposite sides of the middle portion in the second direction. The middle portion includes a carrier transport portion and a gate insulating portion. In the first direction, the gate is located on the side of the gate insulating portion facing away from the carrier transport portion and overlaps with the carrier transport portion. The first end portion includes a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, and the second end portion includes a second heavily doped portion connected to the carrier transport portion and the gate insulating portion. The thickness of the first and second heavily doped portions along the first direction is greater than the thickness of the carrier transport portion along the first direction. With this arrangement, the active layer includes a gate insulating portion, which can be formed using a semiconductor layer. The gate insulating portion has good density and few interface defects, and the gate insulating portion is thin and uniform. Furthermore, the thin gate insulating portion facilitates the reduction of the size of the thin-film transistor, facilitating miniaturization of the thin-film transistor design. It also enhances the gate's ability to control the carrier transport portion, reduces leakage risk, and improves the electrical performance of the thin-film transistor. In addition, the thickness of the carrier transport portion is also relatively thin, which further reduces the size of the thin film transistor, is more conducive to the miniaturization design of the thin film transistor, and further enhances the gate's control over the carrier transport portion, reduces the risk of leakage of the thin film transistor, and improves the electrical performance of the thin film transistor. Furthermore, the thickness of the first heavily doped portion and the second heavily doped portion along the first direction is greater than the thickness of the carrier transport portion along the first direction, which reduces the contact impedance between the first heavily doped portion and the second heavily doped portion and the carrier transport portion, optimizes the spatial electric field distribution, and improves the short channel effect that exists when the size of the carrier transport portion is small. Therefore, the above-mentioned thin film transistor can have a smaller size, is suitable for miniaturized structural design, and also has a lower leakage current.

[0044] In some embodiments of the present invention, in a method for manufacturing a thin-film transistor, a portion of the surface of an amorphous silicon layer is oxidized to form a gate insulating portion. During the crystallization process of the remaining amorphous silicon layer, the gate insulating portion acts as a heat-insulating agent for the amorphous silicon layer below it, promoting the melting and crystallization of the amorphous silicon layer below the gate insulating portion. Furthermore, the amorphous silicon layer below the gate insulating portion and a portion of the remaining amorphous silicon layer are melted by an excimer laser annealing process, while another portion of the amorphous silicon layer adjacent to the amorphous silicon layer below the gate insulating portion remains solid and becomes an initial crystallization-inducing portion. The initial crystallization-inducing portion acts to induce crystallization of the melted amorphous silicon layer. Through this method, the crystallization-inducing portion cooperates with the gate insulating portion, making it easier to form a carrier transport portion containing larger grains below the gate insulating portion, thereby improving the mobility of the thin-film transistor. Furthermore, the carrier transport portion obtained by this method is thinner, which improves the gate's ability to control the carrier transport portion, thereby improving leakage problems of the thin-film transistor and improving the electrical performance of the thin-film transistor.

[0045] The present disclosure is further described below with reference to the accompanying drawings and specific embodiments:

[0046] Please refer to Figure 1, which is a schematic diagram of the cross-sectional structure of the display device of some embodiments of the present application. The display device 100 can be applied to any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc. The display device 100 can be any one of a liquid crystal display device, an organic light emitting diode display device, a quantum dot display device, a micro light emitting diode display device, and a sub-millimeter light emitting diode display device. The display device 100 includes a display panel 200. In the case where the display device 100 is a liquid crystal display device, the display device 100 may further include a backlight module located on the light incident side of the display panel 200.

[0047] Referring to Figures 2 and 3 , Figure 2 is a schematic cross-sectional view of an array substrate according to some embodiments of the present application, and Figure 3 is a schematic partial plan view of an array substrate according to some embodiments of the present application. A display panel 200 includes an array substrate 300, which includes a base layer 12 and a plurality of thin film transistors 11 disposed on the base layer 12.

[0048] The base layer 12 may include an insulating substrate such as a glass substrate and a flexible substrate. In a specific embodiment, the base layer 12 includes a glass substrate.

[0049] The thin film transistor 11 may include any one of a top-gate thin film transistor and a bottom-gate thin film transistor. The thin film transistor 11 may also include both a bottom gate and a top gate. The thin film transistor 11 may be a polycrystalline silicon thin film transistor, but is not limited thereto. To describe the technical solution of the present application, the thin film transistor 11 is taken as an example of a polycrystalline silicon thin film transistor including a top gate, but is not limited thereto. The thin film transistor 11 includes an active layer 13, a gate 14, a source electrode 151, and a drain electrode 152.

[0050] The active layer 13 includes a middle portion 131, which includes a carrier transport portion 132 and a gate insulating portion 133. The carrier transport portion 132 transports carriers. The gate insulating portion 133 isolates the carrier transport portion 132 from the gate 14. In the first direction x, the carrier transport portion 132 is located on one side of the gate insulating portion 133. The carrier transport portion 132 is disposed between the gate insulating portion 133 and the base layer 12 and is in direct contact with the gate insulating portion 133.

[0051] The active layer 13 also includes a first end portion 134 and a second end portion 135. The first end portion 134 and the second end portion 135 are respectively connected to the source electrode 151 and the drain electrode 152. In the second direction y, the first end portion 134 and the second end portion 135 are respectively connected to opposite sides of the middle portion 131. The first end portion 134 includes a first heavily doped portion 1341 connected to the carrier transport portion 132 and the gate insulating portion 133. The second end portion 135 includes a second heavily doped portion 1351 connected to the carrier transport portion 132 and the gate insulating portion 133. The first heavily doped portion 1341 and the second heavily doped portion 1351 are both obtained by ion doping the semiconductor layer. The thickness d2 of the first heavily doped portion 1341 and the second heavily doped portion 1351 along the first direction x is greater than the thickness d1 of the carrier transport portion 132 along the first direction x, and the second direction y intersects the first direction x.

[0052] The first direction x is the direction from the active layer 13 to the gate 14. In some embodiments, the second direction y may be perpendicular to the first direction x, but is not limited thereto. In other embodiments, the second direction y may also be at an acute angle or an obtuse angle to the first direction x.

[0053] Because the active layer 13 includes the gate insulating portion 133, the gate insulating portion 133 can be formed using a semiconductor layer. This provides good density and fewer interface defects, and the gate insulating portion 133 is thin and has good thickness uniformity. Furthermore, the thinness of the gate insulating portion 133 facilitates reducing the size of the thin-film transistor 11, facilitating the miniaturization of the thin-film transistor 11. This also enhances the gate 14's ability to control the carrier transport portion 132, reduces the risk of leakage in the thin-film transistor 11, and improves the electrical performance of the thin-film transistor 11.

[0054] In addition, the thickness of the carrier transport portion 132 is also relatively thin, which further reduces the size of the thin film transistor 11, is more conducive to the miniaturization design of the thin film transistor 11, and further enhances the control ability of the gate 14 over the carrier transport portion 132, reduces the leakage risk of the thin film transistor 11, and improves the electrical performance of the thin film transistor 11.

[0055] Furthermore, the thickness d2 of the first heavily doped portion 1341 and the second heavily doped portion 1351 along the first direction x is greater than the thickness d1 of the carrier transport portion 132 along the first direction x. The thickness of the first heavily doped portion 1341 and the second heavily doped portion 1351 is larger, which reduces the contact impedance between the first heavily doped portion 1341 and the second heavily doped portion 1351 and the carrier transport portion 132, optimizes the spatial electric field distribution, and improves the short channel effect that exists when the size of the thin film transistor is small.

[0056] Therefore, the thin film transistor 11 can have a smaller size, is suitable for miniaturized structural design, and has a lower leakage current.

[0057] In some embodiments, the carrier transport portion 132 includes a first lightly doped portion 1322, a second lightly doped portion 1323, and a channel portion 1321. The first lightly doped portion 1322 and the second lightly doped portion 1323 are connected to opposite sides of the channel portion 1321 in the second direction y. The first lightly doped portion 1322 is connected to the first heavily doped portion 1341. The second lightly doped portion 1323 is connected to the second heavily doped portion 1351. The ion doping concentration in the first lightly doped portion 1322 and the second lightly doped portion 1323 is lower than the ion doping concentration in the second heavily doped portion 1351 and the first heavily doped portion 1341. This configuration further reduces the risk of leakage in the thin film transistor 11 and further improves the electrical performance of the thin film transistor 11.

[0058] In some embodiments, the carrier transport portion 132 includes a crystalline material to ensure that the carrier transport portion 132 has high mobility. In a specific embodiment, the carrier transport portion 132 includes polycrystalline silicon, so that the channel portion 1321 of the carrier transport portion 132 has high mobility and the carrier transport portion 132 can be manufactured under low temperature conditions.

[0059] In some embodiments, thicknesses of the first lightly doped portion 1322 , the second lightly doped portion 1323 , and the channel portion 1321 in the first direction x are the same and are all equal to d1 .

[0060] In some embodiments, a thickness d1 of the channel portion 1321 in the first direction x is greater than or equal to 200 angstroms and less than or equal to 500 angstroms. Alternatively, the thickness of the channel portion 1321 is greater than or equal to 250 angstroms and less than or equal to 450 angstroms. Alternatively, the thickness of the channel portion 1321 is greater than or equal to 300 angstroms and less than or equal to 400 angstroms. A thinner thickness of the channel portion 1321 can reduce the size of the thin film transistor 11 while improving the control capability of the gate 14 over the channel portion 1321, thereby reducing leakage current.

[0061] In some embodiments, the gate insulating portion 133 includes a thermal insulation material, such as silicon oxide, which has a lower thermal conductivity than polysilicon. The thermal insulation material has a thermal insulation effect. During the formation of the carrier transport portion 132, the gate insulating portion 133 plays a role in local thermal insulation for the carrier transport portion 132, which is conducive to the formation of larger grains in the carrier transport portion 132, improving the mobility of carriers transported by the carrier transport portion 132, and thus improving the mobility of the thin film transistor 11. In addition, the gate insulating portion 133 includes silicon oxide, and the gate insulating portion 133 can be formed by oxidizing the silicon-containing semiconductor layer, eliminating the process of forming the gate insulating layer by chemical deposition in the related art, simplifying the manufacturing process of the thin film transistor 11. In addition, the gate insulating portion 133 obtained by the oxidation treatment is thin and has good thickness uniformity, which not only helps to reduce the size of the thin film transistor 11, but also further improves the control ability of the gate 14 over the carrier transport portion 132, reduces the leakage risk of the thin film transistor 11, and improves the electrical performance of the thin film transistor 11.

[0062] In some embodiments, a thickness d3 of the gate insulating portion 133 in the first direction x is less than a thickness d2 of the first heavily doped portion 1341 and the second heavily doped portion 1351 along the first direction x. This reduces the thickness of the gate insulating portion 133, improving the gate 14's ability to control the channel portion 1321 while also reducing the size of the thin film transistor 11.

[0063] In some embodiments, the thickness d3 of the gate insulating portion 133 in the first direction x can be greater than the thickness of the channel portion 1321 in the first direction x, thereby simplifying the manufacturing process of the gate insulating portion 133. In other embodiments, the thickness of the gate insulating portion 133 in the first direction x can also be less than the thickness of the channel portion 1321 in the first direction x, thereby further improving the control ability of the gate 14 over the channel portion 1321.

[0064] In some embodiments, the thickness d3 of the gate insulating portion 133 in the first direction x is greater than or equal to 300 angstroms and less than or equal to 700 angstroms. Optionally, the thickness d3 of the gate insulating portion 133 is greater than or equal to 400 angstroms and less than or equal to 600 angstroms. Optionally, the thickness d3 of the gate insulating portion 133 is greater than or equal to 450 angstroms and less than or equal to 550 angstroms. With this configuration, the thickness of the gate insulating portion 133 is relatively thin. If the thickness of the gate insulating portion 133 is too thin, it will increase its manufacturing difficulty. If the thickness of the gate insulating portion 133 is too large, it is not conducive to reducing the leakage current of the thin film transistor 11, nor is it conducive to the miniaturization of the thin film transistor 11.

[0065] In some embodiments, the sum of the thickness d3 of the gate insulating portion 133 along the first direction x and the thickness d1 of the carrier transporting portion 132 along the first direction x is greater than the thickness d2 of the first heavily doped portion 1341 and the second heavily doped portion 1351 along the first direction x. With this configuration, when the thickness of the first heavily doped portion 1341 and the second heavily doped portion 1351 along the first direction x is greater than the thickness of the carrier transporting portion 132 along the first direction x, the thickness of the first heavily doped portion 1341 and the second heavily doped portion 1351 is prevented from being excessively large, thereby ensuring that the thickness of the carrier transporting portion 132 is relatively small.

[0066] In some embodiments, the thicknesses of the first heavily doped portion 1341 and the second heavily doped portion 1351 in the first direction x can be the same. This configuration simplifies the manufacturing of the first heavily doped portion 1341 and the second heavily doped portion 1351. In some embodiments, the first heavily doped portion 1341 and the second heavily doped portion 1351 can comprise polysilicon.

[0067] In some embodiments, the thickness d2 of the first heavily doped portion 1341 and the second heavily doped portion 1351 in the first direction x may be greater than or equal to 500 angstroms and less than or equal to 1200 angstroms. Alternatively, the thickness d2 of the first heavily doped portion 1341 and the second heavily doped portion 1351 in the first direction x may be greater than or equal to 600 angstroms and less than or equal to 1000 angstroms. In this way, the contact resistance between the first heavily doped portion 1341 and the second heavily doped portion 1351 and the carrier transport portion 132 is reduced, while also reducing the difficulty in manufacturing the first heavily doped portion 1341 and the second heavily doped portion 1351.

[0068] In some embodiments, at least one of the first end portion 134 and the second end portion 135 includes a crystallization-inducing portion 136. The crystallization-inducing portion 136 serves as a seed crystal, inducing the formation of larger grains during the carrier transport portion 132, thereby improving the mobility of the carrier transport portion 132 and, in turn, the mobility of the thin film transistor 11. The crystallization-inducing portion 136 is located on one side of at least one of the first heavily doped portion 1341 and the second heavily doped portion 1351 in the first direction x and is connected to the carrier transport portion 132. The crystallization-inducing portion 136 is located between at least one of the first heavily doped portion 1341 and the second heavily doped portion 1351 and the base layer 12.

[0069] It should be noted that, when the gate insulating portion 133 includes a thermal insulation material, the thermal insulation effect of the gate insulating portion 133 matches at least one of the first end portion 134 and the second end portion 135 including the crystallization inducing portion 136, which can better ensure that the induced carrier transport portion 132 includes larger grains during its formation, thereby improving the mobility of the carrier transport portion 132 and thereby improving the mobility of the thin film transistor 11.

[0070] In a specific embodiment, both the first end portion 134 and the second end portion 135 include a crystallization-inducing portion 136. Therefore, the two crystallization-inducing portions 136 are respectively connected to the two sides of the carrier transport portion 132 in the first direction x. The two crystallization-inducing portions 136, in conjunction with the gate insulating portion 133, can better ensure that the carrier transport portion 132 includes larger grains during its formation. It is understood that either the first end portion 134 or the second end portion 135 can also include a crystallization-inducing portion 136.

[0071] In some embodiments, the thickness of the crystallization inducing portion 136 along the first direction x is less than the thickness of the carrier transporting portion 132 along the first direction x. In this manner, the crystallization inducing portion 136 is thinner and can more easily serve as a nucleation seed.

[0072] In some embodiments, the sum of the thickness d4 of the crystallization inducing portion 136 along the first direction x and the thickness d2 of the second heavily doped portion 1351 is equal to the sum of the thickness d3 of the gate insulating portion 133 along the first direction x and the thickness d1 of the carrier transport portion 132 along the first direction x. With this arrangement, the active layer 13 including these structures can be formed by processing a single semiconductor layer, simplifying the manufacturing process of the active layer 13.

[0073] In some embodiments, the thickness d4 of the crystallization-inducing portion 136 along the first direction x is greater than 0 angstroms and less than or equal to 100 angstroms. Alternatively, the thickness d4 of the crystallization-inducing portion 136 along the first direction x is greater than 5 angstroms and less than or equal to 80 angstroms. Alternatively, the thickness of the crystallization-inducing portion 136 along the first direction x is greater than 10 angstroms and less than or equal to 70 angstroms. Alternatively, the thickness of the crystallization-inducing portion 136 along the first direction x is greater than 20 angstroms and less than or equal to 30 angstroms. This configuration reduces the difficulty of forming the crystallization-inducing portion 136 while ensuring the crystallization-inducing performance of the crystallization-inducing portion 136.

[0074] In a specific embodiment, the crystallization inducing portion 136 may include amorphous silicon, which is advantageous for the crystallization inducing portion 136 to induce the carrier transporting portion 132 to include large-sized grains.

[0075] The gate 14 is located on a side of the gate insulating portion 133 facing away from the carrier transport portion 132 in the first direction x, and overlaps with the carrier transport portion 132. The gate 14 is made of a material including a metal and a transparent conductive material. The metal includes at least one of molybdenum, aluminum, titanium, copper, and silver. The transparent conductive material includes at least one of indium tin oxide and indium zinc oxide.

[0076] The source electrode 151 and the drain electrode 152 are connected to the first heavily doped portion 1341 and the second heavily doped portion 1351, respectively. In one specific embodiment, the source electrode 151 is connected to the first heavily doped portion 1341, and the drain electrode 152 is connected to the second heavily doped portion 1351. The material of the source electrode 151 and the drain electrode 152 includes any one of a metal and a transparent conductive material. The metal includes at least one of molybdenum, aluminum, titanium, copper, and silver. The transparent conductive material includes at least one of indium tin oxide and indium zinc oxide.

[0077] The array substrate 300 also includes a light shielding layer 16, which is disposed between the thin-film transistor 11 and the base layer 12. The orthographic projection of the thin-film transistor 11 on the base layer 12 overlaps with the orthographic projection of the light shielding layer 16 on the base layer 12. The light shielding layer 16 blocks light, reducing the risk of leakage current when the thin-film transistor 11 is exposed to light, thereby ensuring the electrical performance of the thin-film transistor 11. The material of the light shielding layer 16 includes any one of a metal and a transparent conductive material.

[0078] The array substrate 300 also includes a buffer layer 17, which is disposed between the light shielding layer 16 and the thin-film transistor 11. The buffer layer 17 not only isolates the light shielding layer 16 from the thin-film transistor 11, but also mitigates the problem of impurities in the base layer 12 diffusing into the thin-film transistor 11 and affecting the electrical performance of the thin-film transistor 11. The material of the buffer layer 17 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0079] The design of the active layer 13 of the thin film transistor 11 is suitable for miniaturized thin film transistors. Furthermore, while being suitable for miniaturized designs, the thin film transistor 11 has high mobility, low leakage current, and improved short channel effects. Thus, the thin film transistor 11 has excellent electrical performance.

[0080] The display device 100 also includes display circuits such as a pixel driver circuit, a gate driver circuit, a source driver circuit, a demultiplexer circuit (Demux circuit), a timing control circuit, and a power supply circuit. At least one of these display circuits includes the aforementioned thin film transistor 11. This configuration facilitates integrating all integrated circuits other than the pixel driver circuit onto an insulating substrate layer, thereby achieving a system-on-glass (SOG) integrated circuit design. This significantly improves the integration level of the display panel 200, reduces the display device 100's reliance on integrated chips, reduces manufacturing costs, and meets the requirements of SOG technology for thin film transistors with miniaturized dimensions and good electrical performance. For example, at least one of the gate driver circuit and the source driver circuit includes the aforementioned thin film transistor 11.

[0081] In some embodiments, the display device 100 may further include a light-emitting device, which may be connected to the thin film transistor 11. The on and off switching of the thin film transistor 11 may control the light-emitting device to emit light, thereby controlling the display of the display device 100. The light-emitting device may include at least one of an inorganic light-emitting diode and an organic light-emitting diode.

[0082] In some embodiments, the display device 100 may further include a pixel electrode connected to the thin film transistor 11 to control the writing of a data signal into the pixel electrode.

[0083] Referring to FIG. 4 , the present application further provides a method for manufacturing the thin film transistor 11 , which includes the following steps:

[0084] Step S101: forming an amorphous silicon layer on a base layer;

[0085] Step S102: performing oxidation treatment on a portion of the surface of the amorphous silicon layer to form a gate insulating portion, wherein the remaining portion of the amorphous silicon layer in the first direction x is located between the gate insulating portion and the base layer; and

[0086] Step S103: The remaining amorphous silicon is processed by an excimer laser annealing process to form a first polycrystalline portion, a second polycrystalline portion and an initial crystallization inducing portion. In the first direction, the first polycrystalline portion is located between the gate insulating portion and the base layer. In the first direction, the initial crystallization inducing portion is located between the second polycrystalline portion and the base layer. In the second direction, the second polycrystalline portion is adjacent to and connected to the gate insulating portion. In the second direction, the initial crystallization inducing portion is adjacent to and connected to the first polycrystalline portion. The first direction intersects with the second direction.

[0087] The manufacturing method of the thin film transistor 11 will be described in detail below with reference to FIG. 5A to FIG. 5F , but the manufacturing method of the thin film transistor 11 is not limited thereto.

[0088] 5A , before performing step S101 , the method further includes forming a light shielding layer 16 on the base layer 12 , and forming a buffer layer 17 covering the light shielding layer 16 and the base layer 12 .

[0089] 5B , the above step S101 is performed to form an amorphous silicon layer 21 on the base layer 12 .

[0090] Forming the amorphous silicon layer 21 on the base layer 12 includes forming the amorphous silicon layer 21 on a side of the buffer layer 17 away from the base layer 12. The amorphous silicon layer 21 may be formed by physical sputtering deposition. The thickness of the amorphous silicon layer 21 may be greater than or equal to 500 angstroms and less than or equal to 1200 angstroms.

[0091] 5C , the above step S102 is performed to oxidize part of the surface of the amorphous silicon layer 21 to form a gate insulating portion 133 . The remaining part of the amorphous silicon layer 21 in the first direction x is located between the gate insulating portion 133 and the base layer 12 .

[0092] Before oxidizing a portion of the surface of the amorphous silicon layer 21 , the method further includes forming a patterned mask layer 22 on the amorphous silicon layer 21 . The patterned mask layer 22 includes an opening 221 . The opening 221 exposes a portion of the surface of the amorphous silicon layer 21 .

[0093] In some embodiments, the patterned mask layer 22 may include a hard mask to reduce the risk of damage to the patterned mask layer 22 due to oxidation in an oxygen atmosphere. The hard mask may include silicon nitride.

[0094] During the oxidation process of a portion of the surface of the amorphous silicon layer 21, the patterned mask layer 22 protects the amorphous silicon layer 21 outside the opening 221. By controlling the oxidation time, the oxidation thickness of the amorphous silicon layer 21 and, therefore, the thickness of the gate insulating portion 133 can be controlled.

[0095] In some embodiments, after forming the gate insulating portion 133 , the patterned mask layer 22 is removed. For example, a hot phosphoric acid wet process can be used to remove the patterned mask layer 22 .

[0096] It should be noted that, compared to the gate insulating layer prepared by a general chemical vapor deposition process, the gate insulating portion 133 in step S102 is formed by thermal oxidation. The gate insulating portion 133 is denser, has fewer interface defects, and can be thinner (can be a few nanometers to tens of nanometers). The thinner gate insulating portion 133 is conducive to enhancing the control ability of the gate 14 over the subsequently formed channel portion 1321, and can improve the short channel effect caused by the miniaturization of the thin film transistor 11. In addition, the gate insulating portion 133 includes silicon oxide, which has a heat-insulating effect. In step S103, the gate insulating portion 133 can also play a role in heat preservation, which is conducive to accelerating the melting of the amorphous silicon layer 21 below the gate insulating portion 133, and is conducive to the crystallization of the amorphous silicon layer 21 below the gate insulating portion 133 to form large-sized grains.

[0097] 5D , the above-mentioned step S103 is performed, and the remaining amorphous silicon is processed by an excimer laser annealing process to form a first polycrystalline portion 211, a second polycrystalline portion 212, and an initial crystallization inducing portion 213. In the first direction x, the first polycrystalline portion 211 is located between the gate insulating portion 133 and the base layer 12. In the first direction x, the initial crystallization inducing portion 213 is located between the second polycrystalline portion 212 and the base layer 12. In the second direction y, the second polycrystalline portion 212 is adjacent to and connected to the gate insulating portion 133. In the second direction y, the initial crystallization inducing portion 213 is adjacent to and connected to the first polycrystalline portion 211. The first direction x intersects with the second direction y.

[0098] In step S103, the remaining amorphous silicon layer 21 is irradiated with an excimer laser, causing the remaining amorphous silicon layer 21 to heat up under the laser irradiation. For the portion of the amorphous silicon layer 21 other than the portion below the gate insulating portion 133 (at point A in FIG. 5C ), the temperature of the upper surface of the amorphous silicon layer 21, which is farther from the base layer 12, rises more rapidly, while the temperature of the lower surface of the amorphous silicon layer 21, which is closer to the base layer 12, rises more slowly.

[0099] By controlling the energy of the excimer laser, the remaining portions of the amorphous silicon layer 21, excluding the amorphous silicon layer 21 below the gate insulating portion 133, can be melted, while the smaller portion of the amorphous silicon layer 21 near the base layer 12 remains solid. The solid amorphous silicon layer 21 acts as a seed crystal. Under the induced crystallization effect of the seed crystal and the heat preservation effect of the gate insulating portion 133, grains begin to grow from the seed crystal. Ultimately, the amorphous silicon layer 21 below the gate insulating portion 133 forms a first polycrystalline portion 211 comprising larger grains. After the excimer laser treatment, the solid amorphous silicon layer 21 forms an initial crystallization-inducing portion 213. The amorphous silicon layer 21 above the solid amorphous silicon layer 21 undergoes crystallization to form a second polycrystalline portion 212. The average size of the grains in the second polycrystalline portion 212 can be larger than the average size of the grains in the first polycrystalline portion 211.

[0100] 5E , after step S103, the method further includes step S104 of patterning the crystallized amorphous silicon layer 21 and performing a first doping process on the patterned second polycrystalline portion 212 and the initial crystallization inducing portion 213 to form a first heavily doped portion 1341, a second heavily doped portion 1351, and a crystallization inducing portion 136, respectively. One crystallization inducing portion 136 is located between one first heavily doped portion 1341 and the buffer layer 17, with the adjacent first heavily doped portion 1341 and the crystallization inducing portion 136 forming a first end portion 134. Another crystallization inducing portion 136 is located between the second heavily doped portion 1351 and the buffer layer 17, with the adjacent second heavily doped portion 1351 and the crystallization inducing portion 136 forming a second end portion 135.

[0101] Continuing with FIG. 5E , the method further includes step S105 of forming a gate 14 on a side of the gate insulating portion 133 away from the base layer 12 and performing a second doping treatment on the first polycrystalline portion 211 using the gate 14 as a mask. The doped portion of the first polycrystalline portion 211 forms a first lightly doped portion 1322 and a second lightly doped portion 1323, while the undoped portion of the first polycrystalline portion 211 forms a channel portion 1321. The first lightly doped portion 1322 and the second lightly doped portion 1323 are connected to opposite sides of the channel portion 1321. The first lightly doped portion 1322, the second lightly doped portion 1323, and the channel portion 1321 constitute a carrier transport portion 132. The gate insulating portion 133 is located on the carrier transport portion 132, and the two together constitute the middle portion 131. The middle portion 131, the second end portion 135, and the first end portion 134 constitute the active layer 13. The ion concentration of the second doping treatment is lower than that of the first doping treatment.

[0102] 5F , the method further includes step S105, and further includes: forming an interlayer insulating layer 18 on the side of the gate 14 away from the base layer 12, and forming a source 151 and a drain 152 on the side of the interlayer insulating layer 18 away from the base layer 12, the source 151 and the drain 152 being respectively connected to the first heavily doped portion 1341 and the second heavily doped portion 1351 through at least vias penetrating the interlayer insulating layer 18.

[0103] In some thin-film transistor manufacturing methods of the present application, a portion of the surface of an amorphous silicon layer is oxidized to form a gate insulating portion. During the crystallization process of the remaining amorphous silicon layer, the gate insulating portion acts as a heat insulator for the amorphous silicon layer below it, promoting melting and crystallization of the amorphous silicon layer below the gate insulating portion. Furthermore, the amorphous silicon layer below the gate insulating portion and a portion of the remaining amorphous silicon layer are melted during an excimer laser annealing process, while another portion of the amorphous silicon layer adjacent to the amorphous silicon layer below the gate insulating portion remains solid and becomes an initial crystallization inducing portion. The initial crystallization inducing portion acts to induce crystallization of the melted amorphous silicon layer. In this method, the initial crystallization inducing portion cooperates with the gate insulating portion, making it easier to form a carrier transport portion containing larger grains below the gate insulating portion, thereby improving the mobility of the thin-film transistor. Furthermore, the carrier transport portion obtained by this method is thinner, which improves the gate's ability to control the carrier transport portion, thereby reducing leakage current of the thin-film transistor and improving the electrical performance of the thin-film transistor.

[0104] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A thin film transistor, comprising: An active layer, the active layer comprising: a middle portion, the middle portion comprising a carrier transport portion and a gate insulating portion, the carrier transport portion being located on one side of the gate insulating portion in a first direction; and a first end portion and a second end portion, wherein the first end portion and the second end portion are respectively connected to opposite sides of the middle portion in a second direction, the first end portion includes a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, the second end portion includes a second heavily doped portion connected to the carrier transport portion and the gate insulating portion, the thickness of the first heavily doped portion and the second heavily doped portion along the first direction is greater than the thickness of the carrier transport portion along the first direction, and the second direction intersects the first direction; a gate, located on a side of the gate insulating portion away from the carrier transport portion in the first direction and overlapping with the carrier transport portion; and A source electrode and a drain electrode are connected to the first heavily doped portion and the second heavily doped portion respectively.

2. The thin film transistor according to claim 1, wherein: The gate insulating portion includes silicon oxide, and a thickness of the gate insulating portion is greater than or equal to 300 angstroms and less than or equal to 700 angstroms.

3. The thin film transistor according to claim 1, wherein: A sum of a thickness of the gate insulating portion along the first direction and a thickness of the carrier transport portion along the first direction is greater than a thickness of the first heavily doped portion and the second heavily doped portion along the first direction.

4. The thin film transistor according to claim 1, wherein: The carrier transport portion includes a first lightly doped portion, a second lightly doped portion and a channel portion. In the second direction, the first lightly doped portion and the second lightly doped portion are connected to opposite sides of the channel portion, the first lightly doped portion is connected to the first heavily doped portion, and the second lightly doped portion is connected to the second heavily doped portion.

5. The thin film transistor according to claim 1, wherein: The carrier transport portion includes a crystalline phase material; At least one of the first end portion and the second end portion includes a crystallization inducing portion, the crystallization inducing portion is located on one side of at least one of the first heavily doped portion and the second heavily doped portion in the first direction and is connected to the carrier transporting portion.

6. The thin film transistor according to claim 5, wherein: A thickness of the crystallization inducing portion along the first direction is smaller than a thickness of the carrier transporting portion along the first direction.

7. The thin film transistor according to claim 5, wherein: The first heavily doped portion, the second heavily doped portion, and the carrier transport portion include polysilicon, and the crystallization inducing portion includes amorphous silicon.

8. The thin film transistor according to any one of claims 5 to 7, wherein: A thickness of the crystallization inducing portion along the first direction is greater than 0 angstroms and less than or equal to 100 angstroms.

9. A display panel, comprising a thin film transistor; The thin film transistor comprises: An active layer, the active layer comprising: a middle portion, the middle portion comprising a carrier transport portion and a gate insulating portion, the carrier transport portion being located on one side of the gate insulating portion in a first direction; and a first end portion and a second end portion, wherein the first end portion and the second end portion are respectively connected to opposite sides of the middle portion in a second direction, the first end portion includes a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, the second end portion includes a second heavily doped portion connected to the carrier transport portion and the gate insulating portion, the thickness of the first heavily doped portion and the second heavily doped portion along the first direction is greater than the thickness of the carrier transport portion along the first direction, and the second direction intersects the first direction; a gate, located on a side of the gate insulating portion away from the carrier transport portion in the first direction and overlapping with the carrier transport portion; and A source electrode and a drain electrode are connected to the first heavily doped portion and the second heavily doped portion respectively.

10. The display panel according to claim 9, wherein: The gate insulating portion includes silicon oxide, and a thickness of the gate insulating portion is greater than or equal to 300 angstroms and less than or equal to 700 angstroms.

11. The display panel according to claim 9, wherein: A sum of a thickness of the gate insulating portion along the first direction and a thickness of the carrier transport portion along the first direction is greater than a thickness of the first heavily doped portion and the second heavily doped portion along the first direction.

12. The display panel according to claim 9, wherein: The carrier transport portion includes a first lightly doped portion, a second lightly doped portion and a channel portion. In the second direction, the first lightly doped portion and the second lightly doped portion are connected to opposite sides of the channel portion, the first lightly doped portion is connected to the first heavily doped portion, and the second lightly doped portion is connected to the second heavily doped portion.

13. The display panel according to claim 9, wherein: The carrier transport portion includes a crystalline phase material; At least one of the first end portion and the second end portion includes a crystallization inducing portion, the crystallization inducing portion is located on one side of at least one of the first heavily doped portion and the second heavily doped portion in the first direction and is connected to the carrier transporting portion.

14. The display panel according to claim 13, wherein: A thickness of the crystallization inducing portion along the first direction is smaller than a thickness of the carrier transporting portion along the first direction.

15. The display panel according to claim 13, wherein: The first heavily doped portion, the second heavily doped portion, and the carrier transport portion include polysilicon, and the crystallization inducing portion includes amorphous silicon.

16. The display panel according to any one of claims 13 to 15, wherein: A thickness of the crystallization inducing portion along the first direction is greater than 0 angstroms and less than or equal to 100 angstroms.

17. A method for manufacturing a thin film transistor, the thin film transistor comprising a thin film transistor, comprising: An active layer, the active layer comprising: a middle portion, the middle portion comprising a carrier transport portion and a gate insulating portion, the carrier transport portion being located on one side of the gate insulating portion in a first direction; and a first end portion and a second end portion, wherein the first end portion and the second end portion are respectively connected to opposite sides of the middle portion in a second direction, the first end portion includes a first heavily doped portion connected to the carrier transport portion and the gate insulating portion, the second end portion includes a second heavily doped portion connected to the carrier transport portion and the gate insulating portion, the thickness of the first heavily doped portion and the second heavily doped portion along the first direction is greater than the thickness of the carrier transport portion along the first direction, and the second direction intersects the first direction; a gate, located on a side of the gate insulating portion away from the carrier transport portion in the first direction and overlapping with the carrier transport portion; and a source electrode and a drain electrode, connected to the first heavily doped portion and the second heavily doped portion respectively; The method comprises: forming an amorphous silicon layer on the base layer; performing oxidation treatment on a portion of the surface of the amorphous silicon layer to form a gate insulating portion, wherein a portion of the amorphous silicon layer remaining in the first direction is located between the gate insulating portion and the base layer; and The remaining amorphous silicon is processed by an excimer laser annealing process to form a first polycrystalline portion, a second polycrystalline portion and an initial crystallization inducing portion, wherein the first polycrystalline portion is located between the gate insulating portion and the base layer in the first direction, the initial crystallization inducing portion is located between the second polycrystalline portion and the base layer in the first direction, the second polycrystalline portion is adjacent to and connected to the gate insulating portion in the second direction, the initial crystallization inducing portion is adjacent to and connected to the first polycrystalline portion in the second direction, and the first direction intersects with the second direction.

18. The method for manufacturing a thin film transistor according to claim 17, wherein: The gate insulating portion includes silicon oxide, and a thickness of the gate insulating portion is greater than or equal to 300 angstroms and less than or equal to 700 angstroms.

19. The method for manufacturing a thin film transistor according to claim 17, wherein: A sum of a thickness of the gate insulating portion along the first direction and a thickness of the carrier transport portion along the first direction is greater than a thickness of the first heavily doped portion and the second heavily doped portion along the first direction.

20. The method for manufacturing a thin film transistor according to claim 17, wherein: The carrier transport portion includes a first lightly doped portion, a second lightly doped portion and a channel portion. In the second direction, the first lightly doped portion and the second lightly doped portion are connected to opposite sides of the channel portion, the first lightly doped portion is connected to the first heavily doped portion, and the second lightly doped portion is connected to the second heavily doped portion.

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