Semiconductor structure and preparation method therefor

Abstract

The present disclosure provides a semiconductor structure and a preparation method therefor. The semiconductor structure comprises a substrate and a plurality of resistive devices located on the substrate. Each resistive device comprises: a lower electrode located on the substrate; a plurality of resistive layers respectively located on the periphery of the lower electrode and in contact with side walls of the lower electrode; and a plurality of upper electrodes wrapped by the resistive layers and isolated from the lower electrode by means of the resistive layers.

Description

Semiconductor structure and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 22, 2023, with application number 202311562614.4, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0004] Resistive Random Access Memory (RRAM) is a non-volatile memory that uses the variable resistance properties of materials to store information. It has the advantages of low power consumption, high density, fast read and write speed, and good durability.

[0005] Existing RRAM is a planar RRAM. The resistive switching area is determined by the planar area of ​​the RRAM, which is limited by the area of ​​the RRAM itself. This is not conducive to miniaturizing the RRAM size while obtaining a large resistive switching area. In addition, achieving a 1TnR device structure will significantly increase the area.

[0006] Summary of the Invention

[0007] The present disclosure provides a semiconductor structure and a method for manufacturing the same, to at least solve the above technical problems existing in the prior art.

[0008] According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0009] substrate;

[0010] A plurality of resistive switching devices are located on the substrate, wherein each of the resistive switching devices comprises:

[0011] a lower electrode, located on the substrate;

[0012] A plurality of resistive switching layers are respectively located around the lower electrode and in contact with the sidewalls of the lower electrode;

[0013] A plurality of upper electrodes are wrapped by the resistive switching layer and isolated from the lower electrodes by the resistive switching layer.

[0014] In one embodiment, the plurality of resistive switching devices are arranged along a first direction and a second direction, wherein the plurality of resistive switching devices are arranged along the first direction to form a column, and the plurality of resistive switching devices are arranged along the second direction to form a row, the resistive switching devices in adjacent columns and adjacent rows are arranged alternately, and the resistive switching devices in every other column and every other row are aligned with each other;

[0015] The semiconductor structure further comprises:

[0016] a plurality of first bit lines extending along the first direction and arranged along the second direction, each of the first bit lines being connected to one upper electrode of the plurality of resistive switching devices in each column, and opposite upper electrodes of the resistive switching devices in adjacent columns being connected to the same first bit line;

[0017] A plurality of second bit lines extending along the second direction and arranged along the first direction, each second bit line is connected to an upper electrode of the plurality of resistive switching devices in each row, and opposite upper electrodes of the resistive switching devices in adjacent rows are connected to the same second bit line.

[0018] In one embodiment, the invention further includes:

[0019] A first dielectric layer and a second dielectric layer are stacked in sequence on the substrate; the lower electrode penetrates the first dielectric layer and the second dielectric layer, the resistive layer penetrates the second dielectric layer and is located on the first dielectric layer; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity.

[0020] In one embodiment, the invention further includes:

[0021] a third dielectric layer located on the lower electrode, wherein the third dielectric layer completely covers the lower electrode;

[0022] A fourth dielectric layer, the fourth dielectric layer at least covers surfaces of the third dielectric layer, the resistive switching layer, and the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity ratio.

[0023] In one embodiment, in a projection perpendicular to the plane of the substrate, the shape of the lower electrode includes a rectangle or a circle, and the shape of the upper electrode includes a rectangle, a circle, or an ellipse.

[0024] According to a second aspect of the present disclosure, a method for preparing a semiconductor structure is provided, the method comprising:

[0025] providing a substrate;

[0026] A plurality of resistive switching devices are formed on the substrate, wherein forming each of the resistive switching devices comprises:

[0027] forming a lower electrode on the substrate;

[0028] forming a plurality of resistive switching layers around the lower electrode, wherein the resistive switching layers are in contact with sidewalls of the lower electrode;

[0029] A plurality of upper electrodes wrapped by the resistive switching layer are formed, and the upper electrodes are isolated from the lower electrodes by the resistive switching layer.

[0030] In one embodiment, the plurality of resistive switching devices are arranged along a first direction and a second direction, wherein the plurality of resistive switching devices are arranged along the first direction to form a column, and the plurality of resistive switching devices are arranged along the second direction to form a row, the resistive switching devices in adjacent columns and adjacent rows are arranged alternately, and the resistive switching devices in every other column and every other row are aligned with each other;

[0031] The method further comprises:

[0032] After forming the resistive switching devices, forming a plurality of first bit lines extending along the first direction and arranged along the second direction, each of the first bit lines being connected to one upper electrode of the plurality of resistive switching devices in each column, and opposite upper electrodes of the resistive switching devices in adjacent columns being connected to the same first bit line;

[0033] A plurality of second bit lines extending along the second direction and arranged along the first direction are formed, each of the second bit lines is connected to an upper electrode of the plurality of resistive switching devices in each row, and opposite upper electrodes of the resistive switching devices in adjacent rows are connected to the same second bit line.

[0034] In one embodiment, the method further comprises:

[0035] After providing the substrate, a first dielectric layer and a second dielectric layer stacked in sequence are formed on the substrate; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity ratio.

[0036] In one embodiment, forming the lower electrode includes: forming a first trench penetrating the first dielectric layer and the second dielectric layer; and forming the lower electrode filling the first trench.

[0037] The resistive switching layer is formed, including: forming a second trench penetrating the second dielectric layer, the second trench stopping on the first dielectric layer; and forming the resistive switching layer covering the sidewall and bottom of the second trench.

[0038] In one embodiment, the method further comprises:

[0039] forming a third dielectric layer on the lower electrode, wherein the third dielectric layer completely covers the lower electrode;

[0040] A fourth dielectric layer is formed, the fourth dielectric layer at least covering surfaces of the third dielectric layer, the resistive switching layer and the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity.

[0041] In one embodiment, in a projection perpendicular to the plane of the substrate, the shape of the lower electrode includes a rectangle or a circle, and the shape of the upper electrode includes a rectangle, a circle, or an ellipse.

[0042] The semiconductor structure and preparation method disclosed herein form multiple resistive switching layers around a lower electrode and then form an upper electrode within the resistive switching layers. The resistive switching area is determined by the area of ​​the region where the resistive switching layer contacts the lower electrode. The formation of multiple resistive switching layers in the present disclosure is equivalent to forming a 1TnR structure, thereby increasing the resistive switching area while reducing the planar area occupied by the RRAM, which is beneficial for increasing the RRAM density.

[0043] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0045] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0046] FIG1 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.

[0047] FIG. 2 is a cross-sectional view along the line AA′ in FIG. 1 .

[0048] FIG3 is a cross-sectional view along the BB' direction in FIG1 .

[0049] 4a to 4d are top views of the resistive switching device provided by an embodiment of the present disclosure.

[0050] FIG5 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

[0051] 6a to 18c are schematic diagrams of the semiconductor structure provided by an embodiment of the present disclosure during the preparation process. DETAILED DESCRIPTION

[0052] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0053] An embodiment of the present disclosure provides a semiconductor structure. FIG1 is a top view of the semiconductor structure provided by the embodiment of the present disclosure, FIG2 is a cross-sectional view along the AA' direction in FIG1 , and FIG3 is a cross-sectional view along the BB' direction in FIG1 .

[0054] As shown in Figures 1 to 3, the semiconductor structure includes:

[0055] substrate 10;

[0056] A plurality of resistive switching devices 20 are located on a substrate 10, wherein each resistive switching device 20 includes:

[0057] A lower electrode 21 is located on the substrate 10;

[0058] A plurality of resistive switching layers 22 are respectively located around the lower electrode 21 and in contact with the sidewalls of the lower electrode 21;

[0059] The plurality of upper electrodes 23 are wrapped by the resistive layer 22 and isolated from the lower electrodes 21 by the resistive layer 22 .

[0060] In one embodiment, the substrate 10 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0061] A plurality of active regions 101 are formed in the substrate 10 .

[0062] As shown in Figures 2 and 3, the semiconductor structure further includes: a first interlayer dielectric layer 31 and a second interlayer dielectric layer 32 stacked sequentially on the substrate 10. The material of the first interlayer dielectric layer 31 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The second interlayer dielectric layer 32 can be a metal interlayer dielectric layer, such as aluminum oxide, zinc oxide, or the like.

[0063] The semiconductor structure also includes: a first contact plug 40 located in the first interlayer dielectric layer 31; a metal layer 51 and a source line 52 located in the second interlayer dielectric layer 32, the metal layer 51 and the source line 52 are connected to the substrate 10 through the first contact plug 40, the metal layer 51 is connected to the lower electrode 21 of the resistive device 20, and the source line 52 is isolated from the resistive device 20.

[0064] As shown in Figure 2, the semiconductor structure also includes: a gate structure 102 located on the surface of the substrate 10, the gate structure 102 is located in the first interlayer dielectric layer 31, the gate structure 102 includes a gate dielectric layer (not shown in the figure) and a gate conductive layer (not shown in the figure) located on the gate dielectric layer, and the sidewalls of the gate structure 102 can also be covered with a sidewall structure (not shown in the figure).

[0065] In one embodiment, the semiconductor structure further includes: a first dielectric layer 61 and a second dielectric layer 62 stacked in sequence on the substrate 10; the lower electrode 21 penetrates the first dielectric layer 61 and the second dielectric layer 62, and the resistive layer 22 penetrates the second dielectric layer 62 and is located on the first dielectric layer 61; wherein the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity ratio.

[0066] As shown in FIG. 2 , specifically, the first dielectric layer 61 is located on the second interlayer dielectric layer 32 .

[0067] In the embodiment of the present disclosure, the materials of the first dielectric layer and the second dielectric layer have a high selectivity ratio. Thus, when a groove for forming a resistive layer is etched in the second dielectric layer, the first dielectric layer can serve as an etching stop layer, thereby preventing over-etching of the underlying metal layer and effectively controlling the consistency of the groove depth.

[0068] In one embodiment, the material of the first dielectric layer 61 includes but is not limited to silicon nitride, and the material of the second dielectric layer 62 includes but is not limited to silicon dioxide. However, it should be explained that the materials of the first dielectric layer 61 and the second dielectric layer 62 are not limited thereto, as long as the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity and have an insulating effect.

[0069] As shown in FIG. 2 , each resistive switching device 20 includes a lower electrode 21 , a plurality of resistive switching layers 22 and a plurality of upper electrodes 23 .

[0070] The materials of the lower electrode 21 and the upper electrode 23 include conductive materials such as titanium nitride or tungsten, and the material of the resistive layer 22 includes transition metal oxides, specifically, hafnium oxide, aluminum oxide, and the like.

[0071] FIG4 a is a top view of the resistive switching device provided in an embodiment of the present disclosure.

[0072] In one embodiment, as shown in FIG4 a , the resistive switching device 20 has a 1T4R structure, i.e., includes four resistive switching layers 22, thus forming four resistors. In other embodiments, the resistive switching device may have a 1T3R structure or a 1T2R structure, i.e., only three or two resistive switching layers may be formed around the bottom electrode. In other embodiments, the resistive switching device may have more than four resistive switching layers.

[0073] In traditional planar RRAM, if an nR structure is to be formed, n transistors (Tansistors) are required, which almost increases the device structure area by n times. However, in the embodiment of the present disclosure, multiple resistors (R) can be integrated on a transistor (T), which is equivalent to forming an nR structure. The area of ​​the RRAM in the present disclosure is only one-nth of the area of ​​the planar RRAM, reducing the planar area occupied by the RRAM and facilitating an increase in RRAM density.

[0074] As shown in Figure 4a, multiple resistive switching devices 20 are arranged along the first direction and the second direction, wherein multiple resistive switching devices 20 are arranged along the first direction to form a column, and multiple resistive switching devices 20 are arranged along the second direction to form a row. The resistive switching devices 20 in adjacent columns and adjacent rows are arranged alternately, and the resistive switching devices 20 that are one column away and one row away are aligned with each other.

[0075] As shown in FIG. 4 a , the distance h1 between two resistive devices 20 diagonally arranged in two adjacent columns or two adjacent rows is equal to the distance h2 between two adjacent source lines 52 .

[0076] The angle a between the extension direction of two resistive switching devices 20 arranged diagonally in two adjacent columns or rows and the first direction is 30° to 60°. In a preferred embodiment, a is 45°. When the angle a is within this range, the packing density of the resistive switching devices can be increased.

[0077] 4b to 4d are top views of resistive switching devices provided in other embodiments of the present disclosure.

[0078] In one embodiment, in a projection perpendicular to the plane of the substrate 10 , the shape of the lower electrode 21 includes a rectangle or a circle, and the shape of the upper electrode 23 includes a rectangle, a circle, or an ellipse.

[0079] Specifically, as shown in Figure 4a, the shape of the lower electrode 21 is rectangular, and the shape of the upper electrode 23 is also rectangular; as shown in Figure 4b, the shape of the lower electrode 21 is circular, and the shape of the upper electrode 23 is rectangular; as shown in Figure 4c, the shape of the lower electrode 21 is rectangular, and the shape of the upper electrode 23 is elliptical; as shown in Figure 4d, the shape of the lower electrode 21 is circular, and the shape of the upper electrode 23 is circular.

[0080] In one embodiment, the shape of the resistive layer 22 is the same as that of the upper electrode 23 .

[0081] As shown in FIG2 , the semiconductor structure further includes: a third dielectric layer 63 located on the lower electrode 21 , wherein the third dielectric layer 63 completely covers the lower electrode 21 ;

[0082] The fourth dielectric layer 64 at least covers the surfaces of the third dielectric layer 63 , the resistive layer 22 and the upper electrode 23 . The materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity.

[0083] Because the thickness of the resistive layer is generally thin, if there is no third dielectric layer, the upper electrode and the lower electrode are likely to contact and cause a short circuit. In this embodiment, the third dielectric layer completely covers the lower electrode, so that the upper electrode and the lower electrode can be isolated to avoid a short circuit.

[0084] The third dielectric layer and the fourth dielectric layer have a high selectivity. Thus, when a trench for forming a first bit line is etched in the fourth dielectric layer, the third dielectric layer will not be etched away. Therefore, the third dielectric layer can still isolate the upper electrode from the lower electrode.

[0085] In one embodiment, the material of the third dielectric layer 63 includes but is not limited to silicon nitride, and the material of the fourth dielectric layer 64 includes but is not limited to silicon dioxide. However, it should be explained that the materials of the third dielectric layer 63 and the fourth dielectric layer 64 are not limited thereto, as long as the materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity and have an insulating effect.

[0086] In one embodiment, the fourth dielectric layer 64 further covers the surface of the second dielectric layer 62 .

[0087] As shown in Figures 1 and 2, the semiconductor structure also includes: multiple first bit lines 71 extending along the first direction and arranged along the second direction, each first bit line 71 is connected to an upper electrode 23 of a plurality of resistive devices 20 in each column, and the relative upper electrodes 23 of the resistive devices 20 in adjacent columns are connected to the same first bit line 71.

[0088] The first bit line 71 passes through the fourth dielectric layer 64 .

[0089] The material of the first bit line 71 includes but is not limited to metals such as tungsten and copper.

[0090] As shown in FIG. 1 and FIG. 3 , the semiconductor structure further includes a plurality of second contact plugs 80 . The second contact plugs 80 are located on the upper electrodes 23 that are not in contact with the first bit lines 71 .

[0091] In one embodiment, the upper surface of the second contact plug 80 is higher than the upper surface of the first bit line 71 , so that a certain gap exists between the second bit line formed on the second contact plug and the first bit line, thereby preventing contact and causing a short circuit.

[0092] As shown in FIG1 and FIG3 , the semiconductor structure further includes: a fifth dielectric layer 65 located on the fourth dielectric layer 64;

[0093] Multiple second bit lines 72 extend along the second direction and are arranged along the first direction. Each second bit line 72 is connected to an upper electrode 23 of multiple resistive devices 20 in each row, and the opposite upper electrodes 23 of the resistive devices 20 in adjacent rows are connected to the same second bit line 72.

[0094] Specifically, the second bit line 72 passes through the fifth dielectric layer 65 and is located on the second contact plug 80 .

[0095] The material of the second bit line 72 includes, but is not limited to, metals such as tungsten and copper.

[0096] In one embodiment, the first bit line 71 and the second bit line 72 can realize the interconnection and array operation of the resistive switching device 20 .

[0097] In the embodiment of the present disclosure, a 1TnR structure is formed, which greatly improves the device density, but the interconnection of n RRAMs requires n layers of metal interconnection. In order to ensure that each resistive switching device can be connected and no short circuit occurs, the 1TnR structure usually requires n layers of bit line interconnection. Taking the formation of a 1T4R structure as an example, four resistors usually require four layers of bit lines, which also requires four layers of interconnection. However, in the 1T4R structure of the present disclosure, because the first and second bit lines are arranged in a layered staggered manner, only two layers of bit lines are needed to connect the four resistors, and no short circuit occurs, because the number of n / 2 layers of bit lines is reduced, that is, the number of n / 2 layers of interconnection is reduced, and one layer of interconnection includes a process flow with many steps and high mask costs. Therefore, reducing the interconnection also greatly reduces the process flow and cost.

[0098] The present disclosure also provides a method for preparing a semiconductor structure. FIG5 is a flow chart of the method for preparing a semiconductor structure provided by the present disclosure. Referring to FIG5 , the method includes the following steps:

[0099] Step 501: providing a substrate;

[0100] Step 502: forming a plurality of resistive switching devices on a substrate, wherein forming each resistive switching device includes: forming a lower electrode on the substrate; forming a plurality of resistive switching layers around the lower electrode, wherein the resistive switching layers are in contact with sidewalls of the lower electrode; and forming a plurality of upper electrodes wrapped by the resistive switching layers, wherein the upper electrodes are isolated from the lower electrodes by the resistive switching layers.

[0101] The following is a further detailed description of the method for preparing the semiconductor structure provided by the embodiments of the present disclosure, in conjunction with specific embodiments. Figures 6a to 18c are schematic diagrams of the semiconductor structure provided by the embodiments of the present disclosure during the preparation process, wherein Figures 6a, 7a, 8a to 18a are top views of the semiconductor structure during the preparation process, and Figures 6b, 7b, 8b to 17b, 17c, 18b, and 18c are cross-sectional views of the semiconductor structure during the preparation process.

[0102] First, referring to FIG. 6 a and FIG. 6 b , step 501 is performed to provide a substrate 10 .

[0103] As shown in FIG. 3 , a plurality of active regions 101 are formed in the substrate 10 .

[0104] In one embodiment, the substrate 10 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc.

[0105] Continuing to refer to FIG6b , the method further includes: forming a gate structure 102 on the surface of the substrate, the gate structure 102 including a gate dielectric layer (not shown in the figure) and a gate conductive layer (not shown in the figure) located on the gate dielectric layer, and the sidewalls of the gate structure 102 may also be covered with a sidewall structure (not shown in the figure).

[0106] A first interlayer dielectric layer 31 is formed on the surface of the substrate 10, and the first interlayer dielectric layer 31 covers the gate structure 102. The material of the first interlayer dielectric layer 31 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0107] A first contact plug 40 is formed in the first interlayer dielectric layer 31 .

[0108] A second interlayer dielectric layer 32 is formed on the first interlayer dielectric layer 31 . The second interlayer dielectric layer 32 may be a metal interlayer dielectric layer, such as aluminum oxide, zinc oxide, or the like.

[0109] A metal layer 51 and a source line 52 are formed in the second interlayer dielectric layer 32 . The metal layer 51 and the source line 52 are connected to the substrate 10 through the first contact plug 40 . The metal layer 51 is connected to the lower electrode of the resistive switching device formed subsequently, and the source line 52 is isolated from the resistive switching device.

[0110] 6 b , the method further includes: after providing the substrate 10 , forming a first dielectric layer 61 and a second dielectric layer 62 stacked in sequence on the substrate 10 ; wherein the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity ratio.

[0111] Specifically, the first dielectric layer 61 is located on the second interlayer dielectric layer 32 .

[0112] In the embodiment of the present disclosure, the materials of the first dielectric layer and the second dielectric layer have a high selectivity ratio. Thus, when a groove for forming a resistive layer is subsequently etched in the second dielectric layer, the first dielectric layer can serve as an etching stop layer, thereby preventing over-etching of the underlying metal layer and effectively controlling the consistency of the groove depth.

[0113] In one embodiment, the material of the first dielectric layer 61 includes but is not limited to silicon nitride, and the material of the second dielectric layer 62 includes but is not limited to silicon dioxide. However, it should be explained that the materials of the first dielectric layer 61 and the second dielectric layer 62 are not limited thereto, as long as the materials of the first dielectric layer 61 and the second dielectric layer 62 have a high selectivity and have an insulating effect.

[0114] Next, referring to Figures 7a to 13b, step 502 is performed to form a plurality of resistive switching devices 20 on the substrate 10, wherein the formation of each resistive switching device 20 includes: forming a lower electrode 21 on the substrate 10; forming a plurality of resistive switching layers 22 around the lower electrode 21, the resistive switching layers 22 contacting the sidewalls of the lower electrode 21; and forming a plurality of upper electrodes 23 wrapped by the resistive switching layers 22, the upper electrodes 23 being isolated from the lower electrodes 21 by the resistive switching layers 22.

[0115] 7 a to 9 b , forming the lower electrode 21 includes: forming a first trench 201 penetrating the first dielectric layer 61 and the second dielectric layer 62 ; and forming the lower electrode 21 filling the first trench 201 .

[0116] 7 a and 7 b , a first trench 201 is formed first.

[0117] In actual operation, a mask layer can be formed on the second dielectric layer 62, and then the mask layer can be patterned by photolithography to form a first groove position located on the mask layer. According to the first groove position, the second dielectric layer 62 and the first dielectric layer 61 are etched, and the first groove position is transferred to the second dielectric layer 62 and the first dielectric layer 61 to form the first groove 201.

[0118] In one embodiment, the etching process may be a wet etching process or a dry etching process. Preferably, the etching process is a dry etching process. The dry etching process includes but is not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation.

[0119] Next, referring to FIG. 8 a and FIG. 8 b , an initial lower electrode 210 is formed in the first trench 201 and on the surface of the second dielectric layer 62 .

[0120] 9 a and 9 b , the initial lower electrode 210 located on the surface of the second dielectric layer 62 is removed by etching to form the lower electrode 21 located in the first trench 201 .

[0121] The material of the lower electrode 21 includes conductive materials such as titanium nitride or tungsten.

[0122] 10a to 13b , the resistive switching layer 22 is formed, including: forming a second trench 202 penetrating the second dielectric layer 62 , the second trench 202 stopping on the first dielectric layer 61 ; and forming the resistive switching layer 22 covering the sidewalls and bottom of the second trench 202 .

[0123] Specifically, referring to FIG. 10 a and FIG. 10 b , a second trench 202 is formed. The second trench 202 is located around the lower electrode 21 .

[0124] In actual operation, a mask layer can be formed on the second dielectric layer 62, and then the mask layer can be patterned by photolithography to form a second groove position located on the mask layer. According to the second groove position, the second dielectric layer 62 is etched and the second groove position is transferred into the second dielectric layer 62 to form a second groove 202.

[0125] In one embodiment, the etching process may be a wet etching process or a dry etching process. Preferably, the etching process is a dry etching process. The dry etching process includes but is not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation.

[0126] In one embodiment, the materials of the second dielectric layer 62 and the lower electrode 21 have a high selectivity ratio, so that the lower electrode will not be etched away when the second trench is etched.

[0127] Next, referring to FIG. 11 a and FIG. 11 b , an initial resistive switching layer 220 is formed. The initial resistive switching layer 220 covers the sidewalls and the bottom of the second trench 202 and the surface of the second dielectric layer 62 .

[0128] Next, referring to FIG. 12 a and FIG. 12 b , an initial upper electrode 230 is formed. The initial upper electrode 230 covers the surface of the initial resistive layer 220 and fills the second trench 202 .

[0129] 13 a and 13 b , the initial resistive layer 220 and the initial upper electrode 230 on the surface of the second dielectric layer 62 are removed to form the resistive layer 22 and the upper electrode 23 in the second trench 202 . Thus, the resistive device 20 is formed.

[0130] The material of the upper electrode 23 includes a conductive material such as titanium nitride or tungsten, and the material of the resistive layer 22 includes a transition metal oxide, specifically, hafnium oxide, aluminum oxide, etc.

[0131] In one embodiment, as shown in FIG13 a , the resistive switching device 20 has a 1T4R structure, i.e., includes four resistive switching layers 22. In other embodiments, the resistive switching device may have a 1T3R structure or a 1T2R structure, i.e., only three or two resistive switching layers may be formed around the bottom electrode. In other embodiments, the resistive switching device may have more than four resistive switching layers.

[0132] As shown in Figure 4a, multiple resistive switching devices 20 are arranged along the first direction and the second direction, wherein multiple resistive switching devices 20 are arranged along the first direction to form a column, and multiple resistive switching devices 20 are arranged along the second direction to form a row. The resistive switching devices 20 in adjacent columns and adjacent rows are arranged alternately, and the resistive switching devices 20 that are one column away and one row away are aligned with each other.

[0133] As shown in FIG. 4 a , the distance h1 between two resistive devices 20 diagonally arranged in two adjacent columns or two adjacent rows is equal to the distance h2 between two adjacent source lines 52 .

[0134] The angle a between the extension direction of two resistive switching devices 20 arranged diagonally in two adjacent columns or rows and the first direction is 30° to 60°. In a preferred embodiment, a is 45°. When the angle a is within this range, the packing density of the resistive switching devices can be increased.

[0135] In one embodiment, in a projection perpendicular to the plane of the substrate 10 , the shape of the lower electrode 21 includes a rectangle or a circle, and the shape of the upper electrode 23 includes a rectangle, a circle, or an ellipse.

[0136] Specifically, as shown in Figure 4a, the shape of the lower electrode 21 is rectangular, and the shape of the upper electrode 23 is also rectangular; as shown in Figure 4b, the shape of the lower electrode 21 is circular, and the shape of the upper electrode 23 is rectangular; as shown in Figure 4c, the shape of the lower electrode 21 is rectangular, and the shape of the upper electrode 23 is elliptical; as shown in Figure 4d, the shape of the lower electrode 21 is circular, and the shape of the upper electrode 23 is circular.

[0137] In one embodiment, the shape of the resistive layer 22 is the same as that of the upper electrode 23 .

[0138] In the embodiment of the present disclosure, the resistive switching area is determined by the area of ​​the region where the resistive switching layer contacts the lower electrode. Because multiple resistive switching layers are formed in the present disclosure, which is equivalent to forming a 1TnR structure, the resistive switching area is increased while reducing the planar area occupied by the RRAM, which is beneficial to improving the RRAM density.

[0139] Next, referring to FIG. 14 a to FIG. 15 b , the method further includes: forming a third dielectric layer 63 on the lower electrode 21 , wherein the third dielectric layer 63 completely covers the lower electrode 21 .

[0140] Specifically, a third dielectric layer 63 is first formed to cover the second dielectric layer 62 , the lower electrode 21 , the resistive layer 22 and the upper electrode 23 , and then a portion of the third dielectric layer 63 is removed so that the remaining third dielectric layer 63 completely covers the lower electrode 21 but does not cover or partially covers the upper electrode 23 .

[0141] Because the thickness of the resistive layer is generally thin, if there is no third dielectric layer, the upper electrode and the lower electrode are likely to contact and cause a short circuit. In this embodiment, the third dielectric layer completely covers the lower electrode, so that the upper electrode and the lower electrode can be isolated to avoid a short circuit.

[0142] 16a and 16b, a fourth dielectric layer 64 is formed, which covers at least the surfaces of the third dielectric layer 63, the resistive layer 22 and the upper electrode 23; wherein the materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity.

[0143] The third dielectric layer and the fourth dielectric layer have a high selectivity. Thus, when a trench for forming a first bit line is etched in the fourth dielectric layer, the third dielectric layer will not be etched away. Therefore, the third dielectric layer can still isolate the upper electrode from the lower electrode.

[0144] In one embodiment, the material of the third dielectric layer 63 includes but is not limited to silicon nitride, and the material of the fourth dielectric layer 64 includes but is not limited to silicon dioxide. However, it should be explained that the materials of the third dielectric layer 63 and the fourth dielectric layer 64 are not limited thereto, as long as the materials of the third dielectric layer 63 and the fourth dielectric layer 64 have a high selectivity and have an insulating effect.

[0145] In one embodiment, the fourth dielectric layer 64 further covers the surface of the second dielectric layer 62 .

[0146] Next, referring to Figures 17a to 17c, where Figure 17b is a cross-sectional view taken along line AA' in Figure 17a, and Figure 17c is a cross-sectional view taken along line BB' in Figure 17a, the method further includes: after forming the resistive switching devices 20, forming a plurality of first bit lines 71 extending along the first direction and arranged along the second direction, each first bit line 71 being connected to one upper electrode 23 of the plurality of resistive switching devices 20 in each column, and opposing upper electrodes 23 of the resistive switching devices 20 in adjacent columns being connected to the same first bit line 71.

[0147] In actual operation, a mask layer can be formed on the fourth dielectric layer 64, and then the mask layer can be patterned by photolithography to form a first bit line groove position located on the mask layer. According to the first bit line groove position, the fourth dielectric layer 64 is etched, and the first bit line groove position is transferred into the fourth dielectric layer 64 to form a first bit line groove, and then a metal material is filled in the first bit line groove to form a first bit line 71.

[0148] The first bit line 71 passes through the fourth dielectric layer 64 .

[0149] The material of the first bit line 71 includes but is not limited to metals such as tungsten and copper.

[0150] As shown in FIG. 17 a and FIG. 17 c , the method further includes: forming a second contact plug 80 while forming the first bit line 71 , wherein the second contact plug 80 is located on the upper electrode 23 that is not in contact with the first bit line 71 .

[0151] In one embodiment, the upper surface of the second contact plug 80 is higher than the upper surface of the first bit line 71 , so that a certain gap exists between the second bit line subsequently formed on the second contact plug and the first bit line, thereby preventing contact and causing a short circuit.

[0152] Next, referring to Figures 18a to 18c, where Figure 18b is a cross-sectional view taken along line AA' in Figure 18a, and Figure 18c is a cross-sectional view taken along line BB' in Figure 18a, the method further includes forming a plurality of second bit lines 72 extending along the second direction and arranged along the first direction, each second bit line 72 being connected to one upper electrode 23 of the plurality of resistive switching devices 20 in each row, and opposing upper electrodes 23 of the resistive switching devices 20 in adjacent rows being connected to the same second bit line 72.

[0153] In actual operation, a mask layer can be formed on the fifth dielectric layer 65, and then the mask layer can be patterned by photolithography to form a second bit line trench position located on the mask layer. According to the second bit line trench position, the fifth dielectric layer 65 is etched to transfer the second bit line trench position into the fifth dielectric layer 65 to form a second bit line trench, and then metal material is filled in the second bit line trench to form a second bit line 72.

[0154] Specifically, the second bit line 72 passes through the fifth dielectric layer 65 and is located on the second contact plug 80 .

[0155] The material of the second bit line 72 includes, but is not limited to, metals such as tungsten and copper.

[0156] In one embodiment, the first bit line 71 and the second bit line 72 can realize the interconnection and array operation of the resistive switching device 20 .

[0157] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0158] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0159] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, wherein: include: substrate; A plurality of resistive switching devices are located on the substrate, wherein each of the resistive switching devices comprises: A lower electrode, located on the substrate; A plurality of resistive switching layers are respectively located around the lower electrode and contact the side wall of the lower electrode; A plurality of upper electrodes are wrapped by the resistive switching layer and isolated from the lower electrodes by the resistive switching layer.

2. The semiconductor structure according to claim 1, wherein: A plurality of the resistive switching devices are arranged along a first direction and a second direction, wherein the plurality of the resistive switching devices are arranged along the first direction to form a column, and the plurality of the resistive switching devices are arranged along the second direction to form a row, the resistive switching devices in adjacent columns and adjacent rows are arranged alternately, and the resistive switching devices in alternate columns and alternate rows are aligned with each other; The semiconductor structure further comprises: A plurality of first bit lines extending along the first direction and arranged along the second direction, each of the first bit lines being connected to an upper electrode of a plurality of the resistive switching devices in each column, and opposite upper electrodes of the resistive switching devices in adjacent columns being connected to the same first bit line; A plurality of second bit lines extending along the second direction and arranged along the first direction, each of the second bit lines is connected to an upper electrode of the plurality of resistive switching devices in each row, and the opposite upper electrodes of the resistive switching devices in adjacent rows are connected to the same second bit line.

3. The semiconductor structure according to claim 1, wherein: Also includes: A first dielectric layer and a second dielectric layer are stacked in sequence on the substrate; the lower electrode penetrates the first dielectric layer and the second dielectric layer, the resistive layer penetrates the second dielectric layer and is located on the first dielectric layer; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity.

4. The semiconductor structure according to claim 1, wherein: Also includes: a third dielectric layer located on the lower electrode, wherein the third dielectric layer completely covers the lower electrode; A fourth dielectric layer, wherein the fourth dielectric layer at least covers surfaces of the third dielectric layer, the resistive layer and the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity.

5. The semiconductor structure according to claim 1, wherein: In a projection perpendicular to the substrate plane, the shape of the lower electrode includes a rectangle or a circle. The shape of the upper electrode includes rectangle, circle or ellipse.

6. A method for preparing a semiconductor structure, wherein: The method comprises: providing a substrate; A plurality of resistive switching devices are formed on the substrate, wherein forming each of the resistive switching devices comprises: forming a lower electrode on the substrate; A plurality of resistive switching layers are formed around the lower electrode, wherein the resistive switching layers are in contact with the sidewalls of the lower electrode; A plurality of upper electrodes wrapped by the resistive switching layer are formed, and the upper electrodes are isolated from the lower electrodes by the resistive switching layer.

7. The method according to claim 6, wherein: A plurality of the resistive switching devices are arranged along a first direction and a second direction, wherein the plurality of the resistive switching devices are arranged along the first direction to form a column, and the plurality of the resistive switching devices are arranged along the second direction to form a row, the resistive switching devices in adjacent columns and adjacent rows are arranged alternately, and the resistive switching devices in alternate columns and alternate rows are aligned with each other; The method further comprises: After forming the resistive switching devices, forming a plurality of first bit lines extending along the first direction and arranged along the second direction, each of the first bit lines being connected to an upper electrode of a plurality of the resistive switching devices in each column, and the opposite upper electrodes of the resistive switching devices in adjacent columns being connected to the same first bit line; A plurality of second bit lines extending along the second direction and arranged along the first direction are formed, each of the second bit lines is connected to an upper electrode of the plurality of resistive switching devices in each row, and the opposite upper electrodes of the resistive switching devices in adjacent rows are connected to the same second bit line.

8. The method according to claim 6, wherein: The method further comprises: After providing the substrate, a first dielectric layer and a second dielectric layer stacked in sequence are formed on the substrate; wherein the materials of the first dielectric layer and the second dielectric layer have a high selectivity.

9. The method according to claim 8, wherein: Forming the lower electrode includes: forming a first trench penetrating the first dielectric layer and the second dielectric layer; forming the lower electrode filling the first trench; The resistive switching layer is formed, including: forming a second trench penetrating the second dielectric layer, the second trench stopping on the first dielectric layer; and forming the resistive switching layer covering the sidewall and bottom of the second trench.

10. The method according to claim 6, wherein: The method further comprises: forming a third dielectric layer on the lower electrode, wherein the third dielectric layer completely covers the lower electrode; A fourth dielectric layer is formed, wherein the fourth dielectric layer at least covers the third dielectric layer and the resistive switching layer. and the surface of the upper electrode; wherein the materials of the third dielectric layer and the fourth dielectric layer have a high selectivity.

11. The method according to claim 6, wherein: In a projection perpendicular to the plane direction of the substrate, the shape of the lower electrode includes a rectangle or a circle, and the shape of the upper electrode includes a rectangle, a circle or an ellipse.

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