Oring FET control circuit and power supply system

Abstract

Embodiments of the present application relate to the technical field of switching power supplies. Disclosed are an Oring field effect transistor (FET) control circuit and a power supply system. The ORing FET control circuit is connected between a power supply module and an output bus, and comprises: an FET, a source of the FET being connected to a power supply module, and a drain of the FET being connected to the output bus; a first triode, an emitter of the first triode being connected to the source of the FET, and a collector of the first triode being connected to a gate of the FET; a second triode, a first end of the second triode being connected to the drain of the FET, and a base of the second triode being in short circuit with a second end; a third triode, a collector of the third triode being connected to a base of the first triode, and a base of the third triode being in short circuit with an emitter; and a fourth triode, a first end of the fourth triode being connected to the base and an emitter of the second triode, and a base of the fourth triode being in short circuit with a second end and being connected to the base and the emitter of the third triode.

Description

ORing FET control circuit and power supply system

[0001] Cross-references

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 21, 2023, with application number 202311569393.3 and invention name “ORing FET control circuit and power supply system”. The entire contents of the application are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the technical field of switching power supplies, and in particular to an ORing FET control circuit and a power supply system. Background Art

[0004] In a power system where many power products are connected in parallel to a single output bus, an ORing (or gate) circuit is typically installed between a single power module and the output bus. This circuit prevents a malfunction in a single power module from causing a malfunction in the entire system.

[0005] Currently, commonly used ORing circuits can usually include one or more FETs (Field-Effect Transistors) and a comparator circuit that controls them. The comparator circuit is generally composed of two transistors, which compare the voltage changes between the source and drain of the field-effect transistors and thus control the on and off of the field-effect transistors.

[0006] However, the comparison circuit in the related art uses the base-collector voltage of one transistor to match the base-emitter voltage of another transistor, which will result in a larger threshold voltage required for the field-effect transistor to turn on, insufficient control sensitivity, and inability to achieve the fastest protection when the source and drain voltages of the field-effect transistor are close.

[0007] Summary of the Invention

[0008] The main purpose of the embodiments of the present application is to provide an ORing FET control circuit and a power supply system.

[0009] To achieve the above-mentioned objectives, an embodiment of the present application provides an ORing FET control circuit, which is connected between a single power module and an output bus. The ORing FET control circuit includes: a field effect transistor, wherein the source of the field effect transistor is connected to the power module, and the drain of the field effect transistor is connected to the output bus; a first transistor, wherein the emitter of the first transistor is connected to the source of the field effect transistor, and the collector of the first transistor is connected to the gate of the field effect transistor; a second transistor, wherein the first end of the second transistor is connected to the drain of the field effect transistor, and the base and the second end of the second transistor are short-circuited; a third transistor, wherein the collector of the third transistor is connected to the base of the first transistor, and the base and emitter of the third transistor are short-circuited; and a fourth transistor, wherein the first end of the fourth transistor is connected to the base and emitter of the second transistor, the base and the second end of the fourth transistor are short-circuited, and the base and emitter of the third transistor are connected.

[0010] In addition, to achieve the above-mentioned purpose, an embodiment of the present application further provides a power supply system, which includes: at least one power supply module, and the power supply module is connected to the output bus through the ORing FET control circuit as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0012] FIG1 is a schematic structural diagram of an ORing FET control circuit provided in one embodiment of the present application;

[0013] FIG2 is a schematic structural diagram of an ORing FET control circuit provided in another embodiment of the present application;

[0014] FIG3 is a schematic structural diagram of an ORing FET control circuit provided in yet another embodiment of the present application;

[0015] FIG4 is a schematic structural diagram of a power supply system provided in an embodiment of the present application.

[0016] The purpose, features and advantages of the embodiments of the present application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0017] Description of Figure Numbers: DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0019] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0020] In addition, in the embodiments of the present application, descriptions such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the embodiments of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, the meaning of "and / or" appearing throughout the text is to include three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme in which both A and B are satisfied.

[0021] In the embodiments of the present application, unless otherwise specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean a fixed connection, a detachable connection, or an integral connection; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal connection between two elements or the interaction between two elements, unless otherwise specified. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0022] It should also be understood that references to "one embodiment" or "some embodiments" in the description of the embodiments of the present application mean that one or more embodiments of the embodiments of the present application include specific features, structures, or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0023] In the field of telecommunication power supply, multiple power supplies are often connected in parallel to the same busbar. The ORing circuit is used between a single power module and the output busbar to prevent a problem with one power module from affecting the entire power system, thereby improving the reliability of the entire power system.

[0024] The commonly used ORing circuit solution currently uses one or more field-effect transistors connected in parallel between the power module and the output bus, along with a control circuit with a comparison function. When the power module voltage is greater than the output bus voltage, current is allowed to flow from the power module to the output bus. When the power module voltage is lower than the output bus voltage, current from the output bus is prevented from flowing back into the power module.

[0025] Related art discloses an improved controller for O-ring field-effect transistors, which uses two bipolar transistors to selectively control the on / off switching of the field-effect transistor to achieve the ORing function. The emitter of the first bipolar transistor is connected to the source of the field-effect transistor, and the collector of the second bipolar transistor is connected to the drain of the field-effect transistor. The two bipolar transistors act as a comparison circuit, comparing the voltage changes at the source and drain of the field-effect transistor to control the on / off switching of the field-effect transistor. However, in this solution, there is a difference between the base-emitter voltage of the first bipolar transistor and the base-collector voltage of the second bipolar transistor, so that the comparison circuit still has an input offset, and cannot achieve the fastest protection when the voltages at the source and drain of the field-effect transistor are close.

[0026] Based on this, the embodiments of the present application provide an ORing FET control circuit and power supply system, overcoming the problem in related art that the comparison circuit results in a large threshold voltage required for the field-effect transistor to turn on, resulting in insufficient control sensitivity. The embodiments of the present application provide four transistors in the ORing FET control circuit. When comparing the source and drain voltages of the field-effect transistors, the base-collector voltage plus the base-emitter voltage of two transistors is used to match the base-emitter voltage plus the base-collector voltage of the other two transistors. This achieves a more symmetrical match than the technical solutions in related art, significantly reduces the threshold voltage required for the field-effect transistor to turn on, and improves control sensitivity.

[0027] The ORing FET control circuit and power supply system provided in the embodiments of the present application are specifically described through the following embodiments. First, the ORing FET control circuit in the embodiments of the present application is described.

[0028] The embodiment of the present application provides an ORing FET control circuit. Referring to FIG1 , FIG1 is a structural diagram of an ORing FET control circuit provided by the embodiment of the present application. The FET control circuit is connected between the power module and the output bus, and includes: a field effect transistor Q5, wherein the source of the field effect transistor Q5 is connected to the power module, and the drain of the field effect transistor Q5 is connected to the output bus; a first transistor Q1, wherein the emitter of the first transistor Q1 is connected to the source of the field effect transistor Q5, and the collector of the first transistor Q1 is connected to the gate of the field effect transistor Q5; a second transistor Q2, wherein the first end of the second transistor Q2 is connected to the drain of the field effect transistor Q5, and the base and the second end of the second transistor Q2 are short-circuited; a third transistor Q3, wherein the collector of the third transistor Q3 is connected to the base of the first transistor Q1, and the base and emitter of the third transistor Q3 are short-circuited; and a fourth transistor Q4, wherein the first end of the fourth transistor Q4 is connected to the base and emitter of the second transistor Q2, the base and the second end of the fourth transistor Q4 are short-circuited, and the base and emitter of the third transistor Q3 are connected.

[0029] It should be noted that in this embodiment, four triodes (bipolar transistors) are used to selectively control the on or off of the field-effect transistor Q5. When comparing the source and drain voltages of the field-effect transistor Q5, the base-collector voltage plus the base-emitter voltage of the two bipolar transistors is used to match the base-emitter voltage plus the base-collector voltage of the other two bipolar transistors. Compared with the technical solution in the related art that uses two bipolar transistors and uses the base-collector voltage of one bipolar transistor to match the base-emitter voltage of the other bipolar transistor when comparing the source and drain voltages of the field-effect transistor Q5, the two reference objects used to represent the source voltage and drain voltage of the field-effect transistor Q5 in this embodiment are more symmetrically matched, allowing the field-effect transistor Q5 to have a smaller threshold voltage (the lowest voltage drop between the output voltage of the power module and the output bus voltage when the field-effect transistor Q5 can be biased on is called the "threshold voltage" of the circuit), and the circuit control sensitivity is higher.

[0030] As an example, in this embodiment, when the first end of the second transistor Q2 is the collector, the first end of the fourth transistor Q4 is the emitter; when the first end of the second transistor Q2 is the emitter, the first end of the fourth transistor Q4 is the collector.

[0031] As an example, the working power supply in this embodiment can be realized by connecting an auxiliary power supply to a resistor, or can be realized by other feasible methods, which is not limited in this embodiment.

[0032] In some feasible embodiments, when the source voltage and the drain voltage of the field effect transistor Q5 are equal, the first bias voltage is equal to the second bias voltage; wherein the first bias voltage is the voltage between the base of the third transistor Q3 and the emitter of the first transistor Q1, and the second bias voltage is the voltage between the base of the fourth transistor Q4 and the first end of the second transistor Q2.

[0033] In this embodiment, the first bias voltage is the sum of the base-collector voltage of the third transistor Q3 and the base-emitter voltage of the first transistor Q1, and the second bias voltage is the sum of the voltage between the base and the first end of the fourth transistor Q4 and the voltage between the base and the first end of the second transistor Q2. Since the first end of the second transistor Q2 is the collector, the first end of the fourth transistor Q4 is the emitter, and the first end of the second transistor Q2 is the emitter, the first end of the fourth transistor Q4 is the collector. Therefore, it is equivalent to that the first bias voltage and the second bias voltage are both generated by the base-collector voltage of one transistor. The first bias voltage and the second bias voltage are obtained by adding the base-emitter voltage of the first and second transistors. Since the four transistors are all of the same type, when the source voltage and the drain voltage of the field-effect transistor Q5 are equal, the first bias voltage and the second bias voltage are also equal. However, in the related art, the base-collector voltage of one bipolar transistor is matched to the base-emitter voltage of another bipolar transistor. Since the base-collector and base-emitter structures of the transistors are inevitably different, the solution in the related art still has an input offset, resulting in the threshold voltage of the field-effect transistor Q5 and the circuit control sensitivity being inferior to the technical solution provided by this embodiment.

[0034] In some feasible embodiments, the collector of the first transistor Q1 is connected to a first bias current, the base of the fourth transistor Q4 is connected to a second bias current, and the gate voltage of the field effect transistor Q5 is determined according to the flow direction of the first bias current and the second bias current.

[0035] In this embodiment, as an example, the first bias current and the second bias current may be input through a working power supply and a resistor, or may be directly given through other feasible methods, which is not limited in this embodiment.

[0036] In this embodiment, when the ORing FET control circuit is operating, the on-state of the field-effect transistor Q5 is mainly determined by the difference between the input voltage and the output bus voltage of the power module. Depending on the difference between the input voltage and the output bus voltage of the power module, the bias states of the second transistor and the fourth transistor are affected, thereby affecting the flow direction of the first bias current and the second bias current, and ultimately affecting the gate voltage of the field-effect transistor Q5 and the conduction state between the source and drain.

[0037] In some feasible embodiments, when the source voltage of the field effect transistor Q5 is less than the drain voltage, the second transistor Q2 and the fourth transistor Q4 are reverse biased, so that the second bias current flowing into the base of the third transistor Q3 increases, the current flowing into the base of the first transistor Q1 increases, the first bias current increases, the collector voltage of the first transistor Q1 decreases, and the gate voltage of the field effect transistor Q5 is pulled down.

[0038] In this embodiment, the source voltage of the field-effect transistor Q5 is lower than the drain voltage, indicating that the input voltage of the power module is lower than the output bus voltage. At this time, the ORing FET control circuit provided in this embodiment can lower the gate voltage of the field-effect transistor Q5, so that the source and drain of the field-effect transistor Q5 are cut off, thereby preventing the bus current from flowing back.

[0039] In some feasible embodiments, when the source voltage of the field effect transistor Q5 is greater than the drain voltage, the second transistor Q2 and the fourth transistor Q4 are forward biased, so that the second bias current flowing into the base of the third transistor Q3 is reduced, the current flowing into the base of the first transistor Q1 is reduced, the first bias current is reduced, the collector voltage of the first transistor Q1 is increased, and the gate voltage of the field effect transistor Q5 is pulled up.

[0040] In this embodiment, the source voltage of the field-effect transistor Q5 is greater than the drain voltage, indicating that the input voltage of the power module is less than the output bus voltage. At this time, the ORing FET control circuit provided in this embodiment can increase the gate voltage of the field-effect transistor Q5, so that the source and drain of the field-effect transistor Q5 are conductive, thereby enabling the power module to normally output current to the output bus.

[0041] In some feasible embodiments, the first transistor Q1 and the second transistor Q2 are disposed in a first package, and the third transistor Q3 and the fourth transistor Q4 are disposed in a second package.

[0042] As an example, the first package and the second package are DFN2020-6 packages.

[0043] It should be noted that, in this embodiment, in order to further reduce the impact of device differences on the threshold voltage, the first transistor Q1 and the second transistor Q2 can be placed in the same DFN2020-6 package, and the third transistor Q3 and the fourth transistor Q4 can be placed in the same DFN2020-6 package, so that the ORing FET control circuit can obtain a lower threshold voltage and can potentially further increase the repeatability of the ORing FET control circuit.

[0044] In some feasible embodiments, the ORing FET control circuit further includes: a first resistor R1, one end of the first resistor R1 being connected to the collector of the first transistor Q1; a second resistor R2, one end of the second resistor R2 being connected to the base of the fourth transistor Q4; an auxiliary power supply VCC, the auxiliary power supply VCC being connected to the other end of the first resistor R1 and the other end of the second resistor R2, the auxiliary power supply VCC being used to provide an operating voltage for the field effect transistor Q5, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4.

[0045] It can be understood that, in this embodiment, the auxiliary power supply VCC is the working power supply for each transistor, the first bias current flows to the transistor through the first resistor R1, and the second bias current flows to the transistor through the second resistor R2.

[0046] 2 , in some feasible embodiments, the first end of the second transistor 106 is a collector, the second end of the second transistor 106 is an emitter, the first end of the fourth transistor 110 is an emitter, and the second end of the fourth transistor 110 is a collector.

[0047] In this embodiment, as shown in FIG2 , FIG2 shows a node 120 of the power module output voltage and an output node 122 for providing voltage to the output bus; the field effect transistor 102 is connected between the power module output voltage node 120 and the output bus voltage node 122, wherein the source of the field effect transistor 102 is connected to the node 120, and the drain of the field effect transistor 102 is connected to the output node 122; the emitter of the first transistor 104 is connected to the source of the field effect transistor 102, and the collector of the first transistor 104 is connected to the gate of the field effect transistor 102; the collector of the second transistor 106 is connected to the gate of the field effect transistor 102. The drain of the second transistor 106 is connected to the base of the second transistor 106, and the base is connected to the emitter of the second transistor 106, and the connection is in the form of a diode; the collector of the third transistor 108 is connected to the base of the first transistor 104, and the base of the third transistor 108 is connected to the emitter of the third transistor 108, and the connection is in the form of a diode; the emitter of the fourth transistor 110 is connected to the base and emitter of the second transistor 106, and the base and collector of the fourth transistor 110 are connected together, and the connection is in the form of a diode; the base and collector of the fourth transistor 110 are connected together with the base and emitter of the third transistor 108.

[0048] In this embodiment, the ORing FET control circuit's operating power supply is an auxiliary power supply ORing_Vcc, which is connected to the collector of the first transistor 104 via a first resistor 112. The auxiliary power supply ORing_Vcc is connected to the base and collector of the fourth transistor 110 via a second resistor 114. Second resistor 114 is also connected to the base and emitter of the third diode 108. During operation, the ORing FET control circuit's on / off state is determined by the difference between the power module output voltage 120 and the output bus voltage 122.

[0049] When the power module output voltage 120 is lower than the bus voltage 122, the body diode of FET 102 is reverse biased. Since the output bus voltage is now higher than the power module voltage, the second transistor 106 and the fourth transistor 110, connected in a diode configuration, are also reverse biased. At this point, the current flowing into the base and emitter of third transistor 108 increases, which in turn increases the current flowing into the base of first transistor 104. The increased collector current and decreased collector voltage of first transistor 104 lower the gate voltage of FET 102, turning FET 102 off and preventing the output bus current from flowing back into the power module.

[0050] When the power module voltage 120 is higher than the bus voltage 122, the body diode of the field-effect transistor 102 is forward-biased. At this point, the second and fourth transistors 106, 110, connected in a diode configuration, are also forward-biased, increasing the current flowing through them. The current flowing into the base of the third transistor 108 decreases, causing the collector current of the third transistor 108 to decrease. This, in turn, causes the collector current of the first transistor 104 to decrease and the collector voltage to increase. As the collector voltage of the first transistor 104 increases, the gate voltage of the field-effect transistor 102 also increases. When the gate turn-on voltage is reached, the field-effect transistor 102 turns on, allowing current to flow from the power module to the output bus.

[0051] In this embodiment, the base-emitter voltage of the fourth transistor 110 and the base-collector voltage of the second transistor 106 can better match the base-collector voltage of the third transistor 108 and the base-emitter voltage of the first transistor 104, and the ORing FET control circuit can obtain a lower threshold voltage and more sensitive control.

[0052] In the ORing FET control circuit provided in this embodiment, when the second transistor 106 is connected in a diode manner, the base and emitter of the second transistor 106 are short-circuited together; when the fourth transistor 110 is connected in a diode manner, the base and collector of the fourth transistor 110 are short-circuited together. In other embodiments provided in this application, the second transistor 106 may also be connected in a diode manner by shorting the base and collector together, and the fourth transistor 110 may also be connected in a diode manner by shorting the base and emitter together.

[0053] 3 , in some feasible embodiments, the first end of the second transistor 106 is an emitter, the second end of the second transistor 106 is a collector, the first end of the fourth transistor 110 is a collector, and the second end of the fourth transistor 110 is an emitter.

[0054] In this embodiment, as shown in FIG3 , FIG3 shows a node 120 of the power module output voltage and an output node 122 for providing voltage to the output bus; the field effect transistor 102 is connected between the power module output voltage node 120 and the output bus voltage node 122, wherein the source of the field effect transistor 102 is connected to the node 120, and the drain of the field effect transistor 102 is connected to the output node 122; the emitter of the first transistor 104 is connected to the source of the field effect transistor 102, and the collector of the first transistor 104 is connected to the gate of the field effect transistor 102; the emitter of the second transistor 106 is connected to the gate of the field effect transistor 102. The drain of the second transistor 106 is connected to the base of the second transistor 106, and the base of the third transistor 108 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108, and the base of the fourth transistor 110 is connected to the emitter of the third transistor 108.

[0055] In this embodiment, the operating power source of the ORing FET control circuit is an auxiliary power supply ORing_Vcc, which is connected to the collector of the first transistor 104 via a first resistor 112. The auxiliary power supply ORing_Vcc is connected to the base and emitter of the fourth transistor 110 via a second resistor 114. Second resistor 114 is also connected to the base and emitter of the third diode 108. During operation, the ORing FET control circuit turns on and off the field-effect transistor 102 based on the difference between the power module output voltage 120 and the output bus voltage 122.

[0056] When the power module output voltage 120 is lower than the bus voltage 122, the body diode of FET 102 is reverse biased. Since the output bus voltage is now higher than the power module voltage, the second transistor 106 and the fourth transistor 110, connected in a diode configuration, are also reverse biased. At this point, the current flowing into the base and emitter of third transistor 108 increases, which in turn increases the current flowing into the base of first transistor 104. The increased collector current and decreased collector voltage of first transistor 104 lower the gate voltage of FET 102, turning FET 102 off and preventing the output bus current from flowing back into the power module.

[0057] When the power module voltage 120 is higher than the bus voltage 122, the body diode of the field-effect transistor 102 is forward-biased. At this point, the second and fourth transistors 106, 110, connected in a diode configuration, are also forward-biased, increasing the current flowing through them. The current flowing into the base of the third transistor 108 decreases, causing the collector current of the third transistor 108 to decrease. This, in turn, causes the collector current of the first transistor 104 to decrease and the collector voltage to increase. As the collector voltage of the first transistor 104 increases, the gate voltage of the field-effect transistor 102 also increases. When the gate turn-on voltage is reached, the field-effect transistor 102 turns on, allowing current to flow from the power module to the output bus.

[0058] In this embodiment, the base-collector voltage of the fourth transistor 110 and the base-emitter voltage of the second transistor 106 can better match the base-collector voltage of the third transistor 108 and the base-emitter voltage of the first transistor 104, and the ORing FET control circuit can obtain a lower threshold voltage and more sensitive control.

[0059] In the ORing FET control circuit provided in this embodiment, when the second transistor 106 is connected in a diode manner, the base and collector of the second transistor 106 are short-circuited together; when the fourth transistor 110 is connected in a diode manner, the base and emitter of the fourth transistor 110 are short-circuited together. In other embodiments provided in this application, the second transistor 106 may also be connected in a diode manner by shorting the base and emitter together, and the fourth transistor 110 may also be connected in a diode manner by shorting the base and collector together.

[0060] In addition, an embodiment of the present application further provides a power supply system. Referring to FIG. 4 , the power supply system includes a power supply module 100 , an output bus 202 , and an ORing FET control circuit 200 provided in any of the above embodiments.

[0061] In this embodiment, as an example, the power supply system includes at least one power supply module 100, which is connected to the output bus 202 through the above-mentioned ORing FET control circuit 200, the output 120 of the power supply module 100 is connected to the input end of the corresponding ORing FET control circuit 200, and the output end 122 of the ORing FET control circuit 200 is connected to the output bus 202.

[0062] When the entire power system is operating normally, the voltage at the output 120 of each power module 100 is always slightly higher than the voltage at the input 122 of the output bus 202. Therefore, the field effect transistor in the corresponding ORing FET control circuit 200 is in the on state, allowing the current of the power module 100 to flow to the output bus 202.

[0063] If one of the power modules 100 fails, the voltage at the output 120 of the corresponding power module 100 will be lower than the voltage at the input 122 of the output bus 202. At this point, the corresponding field-effect transistor 102 in the ORing FET control circuit is turned off, preventing current from flowing back from the output bus into the power module. This effectively prevents a single power failure from affecting the entire power system.

[0064] Those skilled in the art will understand that the structure shown in FIG4 does not constitute a limitation on the power supply system, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0065] The power supply system proposed in this embodiment and the ORing FET control circuit proposed in the above embodiments belong to the same inventive concept. Technical details not fully described in this embodiment can be referred to any of the above embodiments, and this embodiment has the same beneficial effects as the above embodiments of the ORing FET control circuit.

[0066] It should be noted that the technical solutions of the various embodiments of the present application can be combined with each other, but it must be based on the fact that technical personnel in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the embodiments of the present application.

[0067] The above are only optional embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the embodiments of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the embodiments of the present application.

Claims

1. An ORing FET control circuit, the ORing FET control circuit is connected between a power module and an output bus, and the ORing FET control circuit comprises: A field effect tube, wherein the source of the field effect tube is connected to the power module, and the drain of the field effect tube is connected to the output bus; A first triode, wherein the emitter of the first triode is connected to the source of the field effect tube, and the collector of the first triode is connected to the gate of the field effect tube; A second triode, wherein a first end of the second triode is connected to the drain of the field effect tube, and a base and a second end of the second triode are short-circuited; a third triode, wherein the collector of the third triode is connected to the base of the first triode, and the base and emitter of the third triode are short-circuited; A fourth triode, wherein the first end of the fourth triode is connected to the base and emitter of the second triode, the base and the second end of the fourth triode are short-circuited and connected to the base and emitter of the third triode.

2. The ORing FET control circuit as claimed in claim 1, wherein: When the source voltage and the drain voltage of the field effect transistor are equal, the first bias voltage is equal to the second bias voltage; wherein the first bias voltage is the voltage between the base of the third transistor and the emitter of the first transistor, and the second bias voltage is the voltage between the base of the fourth transistor and the first end of the second transistor.

3. The ORing FET control circuit as claimed in claim 1, wherein: The collector of the first transistor is connected to the first bias current, the base of the fourth transistor is connected to the second bias current, and the gate voltage of the field effect transistor is determined according to the flow direction of the first bias current and the second bias current.

4. The ORing FET control circuit as claimed in claim 3, wherein: When the source voltage of the field effect transistor is less than the drain voltage, the second transistor and the fourth transistor are reverse biased, so that the second bias current flowing into the base of the third transistor increases, the current flowing into the base of the first transistor increases, the first bias current increases, the collector voltage of the first transistor decreases, and the gate voltage of the field effect transistor is pulled down.

5. The ORing FET control circuit as claimed in claim 3, wherein: When the source voltage of the field effect transistor is greater than the drain voltage, the second transistor and the fourth transistor are forward biased, so that the second bias current flowing into the base of the third transistor is reduced, the current flowing into the base of the first transistor is reduced, the first bias current is reduced, the collector voltage of the first transistor is increased, and the gate voltage of the field effect transistor is pulled up.

6. The ORing FET control circuit as claimed in claim 1, wherein: The first transistor and the second transistor are arranged in a first package, and the third transistor and the fourth transistor are arranged in a second package.

7. The ORing FET control circuit as claimed in claim 6, wherein: The first package and the second package are DFN2020-6 packages.

8. The ORing FET control circuit as claimed in claim 1, wherein: The first end of the second triode is a collector, the second end of the second triode is an emitter, the first end of the fourth triode is an emitter, and the second end of the fourth triode is a collector.

9. The ORing FET control circuit as claimed in claim 1, wherein: The first end of the second triode is an emitter, the second end of the second triode is a collector, the first end of the fourth triode is a collector, and the second end of the fourth triode is an emitter.

10. The ORing FET control circuit as claimed in claim 1, wherein: The ORing FET control circuit further includes: a first resistor, one end of which is connected to the collector of the first transistor; a second resistor, one end of which is connected to the base of the fourth transistor; An auxiliary power supply, the auxiliary power supply is connected to the other end of the first resistor and the other end of the second resistor, and the auxiliary power supply is used to power the field effect transistor, the first transistor, the second transistor, the third transistor and the fourth transistor.

11. A power supply system, comprising: A power module, an output bus and an ORing FET control circuit as claimed in any one of claims 1 to 10, wherein the power module is connected to the output bus via the ORing FET control circuit.

Images