Method for performing a characterization of intrinsic stresses within layers of a semiconductor layer stack

Abstract

The invention concerns a method for performing a characterization of intrinsic stresses within layers of a semiconductor layer stack, the method comprises a step of providing a substrate with a structured semiconductor layer stack arranged on a support element on the substrate. A plurality of separated first portions of the semiconductor layer stack each form an electronic component and at least one separated second portion of the semiconductor layer stack forms a test component. The at least one second portion misses at least one layer of the semiconductor layer stack on a side opposite the support element. The at least one second portion is adjacent to at least one of the plurality of first portions. The support element comprises a plurality of first support pillars each arranged between the substrate and the first portions and the at least one second portion, respectively. The at least one second portion is arranged on a top surface of an associated first support pillar, such that the at least one second portion protrudes a projection of the top surface at least in a first direction. The method further comprises applying a force to the at least one second portion in a first area outside the projection of the top surface and determining the deflection of the at least one second portion and / or the force applied to the at least one second portion over time.

Description

[0001] METHOD FOR PERFORMING A CHARACTERIZATION OF INTRINSIC STRESSES WITHIN

[0002] LAYERS OF A SEMICONDUCTOR LAYER STACK

[0003] The present invention is in the field of wafer level characterization of intrinsic stresses within layers of a semiconductor layer stack of electronic components .

[0004] BACKGROUND

[0005] Due to process variations , the intrinsic stresses within layers of a semiconductor layer stack of electronic components on for example wafer level , e . g . thin oxide layers , metal layers , highly doped layers , or strained layers with regard to their growth substrate can vary throughout the whole wafer, in particular along the whole lateral extensions of the wafer . Such variations can however cause efficiency losses of the later electronic components and / or affect latter post processing of the electronic components .

[0006] Since single layers of a semiconductor layer stack can behave differently despite nominally identical processes , a test at wafer level is particularly interesting . However, there are no mechanical test methods known which can be used for characterization of intrinsic stresses within layers of a semiconductor layer stack of electronic components and in particular embedded layers of the semiconductor layer stack .

[0007] Various other conventional test methods , not being suitable for aforementioned use , are for example :

[0008] X-Ray diffraction (XRD ) . By this , the atomic and molecular structure of the crystal can be experimentally determined, in which the crystalline structure causes a beam of incident X-rays to diffract into many specific directions . By measuring the angles and intensities of these diffracted beams , a crystallographer can produce a three-dimensional picture of the density of electrons within the crystal . From this electron density, the mean positions of the atoms in the crystal can be determined, as well as their chemical bonds , their crystallographic disorder , and various other information .

[0009] FIB cross section . A Focused Ion Beam ( FIB ) instrument uses a finely focused ion beam to modify and image the sample of interest . FIB is chiefly used to create very precise cross sections of a sample for subsequent imaging via SEM, STEM or TEM or to perform circuit modification .

[0010] Optical wafer curvature measurements . By means of this a curvature of a sample can optically be measured .

[0011] Nano indentation by means of for example a dedicated nano indentor or atomic force microscopy (AFM) . By means of this the mechanical properties of a thin film layer can be determined due to the deformation of the material of the layer around a needle indentation .

[0012] All those measurements can however be either very time consuming , come short in local resolution, are limited to surfaces , require special sample preparation or are destructive . In addition to this , the above shown methods are difficult to implement in high-volume production and are only conditionally suitable for characterization of intrinsic stresses within layers of a semiconductor layer stack of electronic components .

[0013] The obj ect of the invention is thus to counteract the aforementioned problems and to provide a method for characterization of intrinsic stresses within layers of a semiconductor layer stack of electronic components which is easy to be implemented in a high-volume production and is in addition suitable for embedded layers .

[0014] SUMMARY OF THE INVENTION

[0015] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0016] A method for performing a characterization of intrinsic stresses within layers of a semiconductor layer stack according to the invention comprises the step of providing a substrate with a structured semiconductor layer stack arranged on a support element on the substrate . The semiconductor layer stack can for example be an optoelectronic structure and comprises a layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type and an active region arranged between the first and the second layer . The semiconductor layer stack further comprises a plurality of separated first portions each forming an electronic component and at least one separated second portion forming a test component . The at least one second portion with regard to the first portion is missing at least one layer of the semiconductor layer stack on a side opposite the support element . This is the electronic components and the at least one test component comprising a similar structure of the same semiconductor layer stack however with at least one of the layers of the semiconductor layer stack being removed .

[0017] The at least one second portion, or in other words the at least one test component is thereby arranged adj acent to at least one of the plurality of first portions , or in other words , adj acent to at least one of the plurality of electronic components . The support element comprises a plurality of first support pillars each arranged between the substrate and the first portions and the at least one second portion, respectively . Further , the at least one second portion, or in other words the at least one test component , is arranged on a top surface of an associated first support pillar, such that the at least one second portion protrudes a proj ection of the top surface at least in a first direction .

[0018] In addition, the method further comprises the steps of applying a force to the at least one second portion in a first area outside the proj ection of the top surface and determining the deflection of the at least one second portion and / or the force applied to the at least one second portion over time .

[0019] In this regard, the electronic components may be optoelectronic components like LEDs or pLEDs but also circuitry components based on silicon or other semiconductor material . These components may provide functionality, may comprise logic functionality, like inverter logic gates and the like , as well as analogue functionality like amplifiers , comparators , limiters , controlled sources , registers , filters and the like . The components may also comprise processing unit and processors as well as any combination thereof . For the purpose of simplicity, the electronic component is further referred to as optoelectronic component .

[0020] The electronic component can in particular be a small light emitting component / element such as a small LED or p-LED . A p-LED can in particular be a very small LED with edge lengths down to 40 pm, down to 10 pm, down to 5 pm or even less . Such small LEDs can be free of a growth substrate and require a special handling and processing to improve their IQE and light outcoupling efficiency . Therefore an accurate characterization of the properties during the manufacturing of such components can be desired .

[0021] By means of the method according to the invention, the intrinsic stresses of embedded layers of the semiconductor layer stack can be qualitatively and quantitatively investigated via a special test component in combination with an associated support element that can be implemented at wafer level . The test component consists of a bar of material that can be machined out or wet / dry etched of a stack of layers resting on one or more support pillars . To test the intrinsic stresses , a force is applied to one end of the test component and the deflection over time curve and / or the force versus time curve is recorded during this time to determine the intrinsic stresses from the deflection until the test component touches the underlying substrate . The test component can for example be formed as a horizontal bar , which rests asymmetrically on the one or more support pillars in order to adj ust the sensitivity of the test component via a leverage effect . In addition the test component can be provided such that the layer of the layer stack to be characterized is exposed from the top such that its intrinsic stresses dominantly influence the bending characteristics of the test component . In some aspects , the step of applying a force to the at least one second portion is conducted until the at least one second portion touches the substrate . By means of determining the deflection of the test component over time until the at least one second portion touches the substrate , it can be determined, if the at least one second portion is due to intrinsic stresses already bent without any force being applied . Hence if the at least one second portion is due to intrinsic stresses already bent in the direction of the substrate , a determined deflection until the at least one second portion touches the substrate is smaller as if the at least one second portion is not bent or due to intrinsic stresses even bent in the direction away from the substrate . Hence by determining the deflection in combination with the removal of layers of the semiconductor layer stack of the at least one second portion, conclusion can be drawn about the intrinsic stresses of respective layer ( s ) of the semiconductor layer stack that predominate a bending of the at least one second portion .

[0022] In some aspects , the test component can be formed as a horizontal bar , which rests asymmetrically or symmetrically on one support pillar . In particular at least a portion of the horizontal bar protrudes a proj ection of the support pillar . The first area , in which the force is applied to the test component , thereby lies outside the proj ection of the support pillar .

[0023] In some aspects , the at least one test component and the associated first support pillar are arranged in an edge region of the substrate . In some aspects , several test components and their associated first support pillars are arranged throughout the whole lateral extensions of the substrate .

[0024] In some aspects , the step of applying a force to the at least one test component is performed by use of an AFM ( atomic force microscope ) tip or an indentor . Hence , an AFM can be used, for example , to bend the test component . The use of an AFM makes the test for example suitable for mass production . In some embodiments , a piezo transducer with cantilever / tip is suitable as a micromanipulator for applying the force to the test component in order to be able to infer the applied force via the spring force and deflection of the cantilever .

[0025] In some aspects , the step of providing the substrate with the structured semiconductor layer stack arranged on the support element comprises a removal of at least one layer of the semiconductor layer stack opposite the support element in the region of the at least one second portion . In particular after growing the semiconductor layer stack and structuring the semiconductor layer stack into the first and second portions , the method can comprise a removal of at least one layer of the semiconductor layer stack opposite the support element in the region of the at least one second portion, to expose an embedded layer of the semiconductor layer stack .

[0026] As a result , the top layer of the at least one second portion is formed from a layer which, in the first portions , is a layer embedded in the semiconductor layer stack . If this layer now comprises intrinsic stresses the removal of the overlying layers may result in the test component to bend in the direction of the substrate or the direction away from the substrate as the intrinsic stresses may dominate the bending behaviour of the test component . By now determining the deflection of the test component and / or the force applied to the test component over time , conclusions can be drawn about the properties of the remaining layer stack, which can for example be compared to measurements of other test components comprising more or less of the initial layers of the semiconductor layer stack .

[0027] In some aspects , at least one separated third portion of the semiconductor layer stack forms a further test component , with the at least one third portion missing at least one other layer of the semiconductor layer stack on a side opposite the support element compared to the at least one second portion . The least one separated third portion can be arranged adj acent to one of the plurality of first portions and can comprise a similar structure as the first and second portions however with at least one other layer of the semiconductor layer stack missing as compared to the first and second portions . Hence several test components can be arranged on the substrate to be tested with some test components comprising more or less of the initial layers of the semiconductor layer stack .

[0028] In some aspects , the method further comprises a step of providing a characterization map indicative of intrinsic stress levels of layers of the semiconductor layer stack throughout the whole lateral extensions of the semiconductor layer stack . In particular by repeating the step of determining the deflection of the at least one second portion and / or the force applied to the at least one second portion over time for all test components present on the substrate , conclusions can be drawn about the properties of the tested layers of the semiconductor layer stack, and a characterization map indicative of intrinsic stress levels of layers of the semiconductor layer stack throughout the whole lateral extensions of the semiconductor layer stack can be provided .

[0029] By arranging several test components with some of them missing the same layers and other missing other layers , throughout the whole wafer structure , a characterization of intrinsic stresses of several embedded layers all throughout the whole wafer can be conducted .

[0030] In some aspects , the support element comprises at least one second support pillar in addition to the first support pillars arranged between the at least one second portion and the substrate . The at least one second support pillar can be arranged adj acent to the first support pillar being associated to the at least one test component . Further to this , the at least one test component protrudes in some embodiments a proj ection of the at least one second support pillar at least in the first direction . The at least one test component is thus arranged on two adj acent support pillars , a first support pillar and a second support pillar, such that , when viewing in a direction perpendicular to the substrate , the test component overlaps the top surface of the first support pillar and a top surface of the second support pillar at least in the first direction .

[0031] In some aspects , the first area is selected to be arranged, along the first direction, after the proj ections of the at least one second support pillar and the top surface of the first support pillar . The first area can thus be selected to be outside the proj ection of the at least one second support pillar and the top surface , such that the proj ection of the at least one second support pillar is , along the first direction, arranged between the first area and the proj ection of the top surface . In other words , the first area can be selected substantially along a virtual line , for example a line along the first direction, defined through the proj ections of the first and the at least one second support pillar outside a portion of said virtual line between said proj ections of the first and the at least one second support pillar . By placing a second support pillar between the test component and the substrate , a compression movement between the test component and the substrate can be redirected into a tensile movement . Thus , the test component can be tested with different loading modes .

[0032] The test component can be formed as a horizontal bar , which lies asymmetrically on a first and second support pillar . This can help to limit a resulting force in an interface between the first support pillar ad the test component to a pure tensile force , as the second support pillar can be arranged under the test component to redirect the force applied in the first area, as in a rocker . By this , a reproducibility of the test can be improved . The spacing of the support pillars can thereby be varied and optimized to improve reproducibility and sensitivity of the method .

[0033] In some aspects , the proj ection of the top surface of the first support pillars and / or the proj ection of the at least one second support pillar comprises one of the following shapes :

[0034] Rectangle ;

[0035] Square ;

[0036] Oval ;

[0037] Circle ;

[0038] Triangle ; and

[0039] Trapezoid .

[0040] The shape of the support pillars can in particular be varied and optimized to improve reproducibility and sensitivity of the method . A wafer structure according to the invention comprises a substrate a substrate , a structured semiconductor layer stack with at least a first layer of a first conductivity type , a second layer of a second conductivity type and an active region arranged between the first and the second layer , and a support element arranged between the substrate and the semiconductor layer stack .

[0041] The wafer structure can in particular be a structure which is used with a method for performing a characterization of intrinsic stresses within layers of a semiconductor layer stack according to some of aforementioned aspects . Hence all features and aspects already described can be applied to the wafer structure and vice versa .

[0042] The semiconductor layer stack comprises a plurality of separated first portions of the semiconductor layer stack each forming an electronic component and at least one separated second portion of the semiconductor layer stack forming a test component . The at least one second portion is missing at least one layer of the semiconductor layer stack on a side opposite the support element , in particular compared to the first portions .

[0043] Further the at least one second portion is arranged adj acent to at least one of the plurality of first portions and in particular comprises a size multiple times larger than the first portions . In particular the second portion comprises a size integral multiple times larger than the first portions such that the at least one second portion first into a pitch given by the plurality of first portions .

[0044] The support element comprises a plurality of first support pillars each arranged between the substrate and the first portions and the at least one second portion, respectively . The at least one second portion is thereby arranged on a top surface of an associated first support pillar , such that the at least one second portion protrudes a proj ection of the top surface at least in a first direction .

[0045] According to some aspects , the support element comprises at least one second support pillar in addition to the first support pillars arranged between the at least one second portion and the substrate . The at least one second support pillar can be arranged adj acent to the first support pillar being associated to the at least one second portion and the at least one second portion protrudes a proj ection of the at least one second support pillar at least in the first direction .

[0046] The test component can be formed as a horizontal bar, which lies in particular asymmetrically on a first and a second support pillar , such that , when viewing in a direction perpendicular to the substrate , the test component overlaps a top surface of the first support pillar and a top surface of the second support pillar at least in the first direction . The first and the second support pillar can thereby be arranged adj acent to each other on the substrate .

[0047] In some aspects , the at least one test component and the associated first support pillar are arranged in an edge region of the substrate . In some aspects , several test components and their associated first support pillars are arranged throughout the whole lateral extensions of the substrate .

[0048] In some aspects , the proj ection of the first support pillars and / or the proj ection of the at least one second support pillar comprises one of the following shapes :

[0049] Rectangle ;

[0050] Square ;

[0051] Oval ;

[0052] Circle ;

[0053] Triangle ; and

[0054] Trapezoid .

[0055] In some aspects , at least one separated third portion of the semiconductor layer stack forms a further test component , with the at least one third portion missing at least one other layer of the semiconductor layer stack on a side opposite the support element compared to the at least one second portion . Hence several test components can be arranged on the substrate to be tested with some test components comprising more or less of the initial layers of the semiconductor layer stack . In some aspects , an atomic force microscope tip is used to perform a characterization of intrinsic stresses within layers of a semiconductor layer stack of a test component of a wafer structure according to some of the aforementioned aspects . The atomic force microscope tip is thereby configured to apply a force to the test component in a first area, wherein the first area is selected to be arranged, along the first direction, after the proj ections of the associated first support pillar and the optionally associated second support pillar .

[0056] SHORT DESCRIPTION OF THE DRAWINGS

[0057] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0058] Fig . 1 a side view of a wafer structure according to some aspects of the proposed principle ,

[0059] Fig . 2A and 2B steps of a method for performing a characterization of intrinsic stresses within layers of a semiconductor layer stack according to some aspects of the proposed principle ,

[0060] Fig . 3 a side view of a further embodiment of a wafer structure according to some aspects of the proposed principle , and

[0061] Fig . 4A to 4 F each a top view of a test component according to some aspects of the proposed principle .

[0062] DETAILED DESCRIPTION

[0063] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however, contradicting the inventive idea .

[0064] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0065] Figure 1 shows a side view of a wafer structure 1 according to some aspects of the proposed principle . The wafer structure 1 comprises a substrate 2 , a structured semiconductor layer stack 6 with at least a first layer of a first conductivity type 6a, a second layer of a second conductivity type 6b and an active region 6c arranged between the first and the second layer 6a , 6b , and a support element 4 arranged between the substrate 2 and the semiconductor layer stack 6 .

[0066] In the embodiment show, the semiconductor layer stack comprises a plurality of separated first portions 3a of the semiconductor layer stack 6 each forming an electronic component , a separated second portion 3b of the semiconductor layer stack 6 forming a test component , and a separated third portion 3c of the semiconductor layer stack 6 forming a further test component .

[0067] The second and the third portion 3b, 3c are each missing layers of the "initial" semiconductor layer stack on a side opposite the support element 4 , in particular compared to the first portions 3a . This is indicated by means of the dotted boxes around the second and third portions which show the size and shape of the initial "initial" semiconductor layer stack 6 compared to what is left of the second and third portion .

[0068] The number of layers of the semiconductor layer stack 6 shown in figure 1 is to be understood as exemplary and the number of layers can also be larger or smaller depending on the configuration and later use of the electronic components . In addition, the type of layers can be different to that explained for the specific embodiment of figure 1 . In the specific embodiment shown, the electronic components can for example be pLEDs each comprising an active region 6c a quantum well structure with barrier layers 10b and a quantum well 10a arranged between the barrier layers 10b . In addition, the semiconductor layer stack 6 comprises current spreading layers 6d, 6e forming a top and a bottom surface of the semiconductor layer stack 6 .

[0069] The second portion 3b is arranged between two first portions 3a as well as the third portion 3c is arranged between two first portions 3a . The arrangement is however also to be understood as exemplary and the arrangement of first , second and third portions can vary throughout the whole wafer structure 1 in any other way . At the same time it is to be understood that the number of first second and third portions can be larger than the number shown in the exemplary figures .

[0070] The second and third portion 3b , 3c miss some layers of the semiconductor layer stack 6 , in particular the second portion 3b misses a second current spreading layer 6e , the second layer 6b , a second barrier layer 10b and the quantum well 10a . The third portion on the other hand "only" misses the second current spreading layer 6e and the second layer 6b .

[0071] Due to the missing layers , and in particular due to the remaining layers , an intrinsic stress within the remaining layers of the third and second portions 3b , 3c leads to the third and second portions 3b , 3c being bent . The second portion 3b in particular due to an intrinsic strain within the remaining three layers comprises a bending away from the substrate 2 caused due to the intrinsic stresses . The term bending is thereby to be understood as a deflection of the layers with regard to the initial structure that is not caused by applying an external force to the layers . These stresses can be compensated by the other layers of the semiconductor layer stack 6 when being complete but can dominate the bending in unloaded condition when several layers of the semiconductor layer stack are removed .

[0072] The support element 4 comprises a plurality of first support pillars 5 each arranged between the substrate 2 and the first portions 3a , the second portion 3b and the third portion 3c , respectively . The second and the third portion 3b, 3c are each arranged on a top surface 5a of an associated first support pillar 5 , such that the portions 3b , 3c protrude a proj ection of the top surfaces 5a at least in a first direction X . In the example shown, the test components 3b , 3c are arranged asymmetrically on the top surface 5a and protrude the top surface 5a into the first direction X but not in the direction opposite to the direction X . This is however to be understood as exemplary and the test components 3b, 3c can also protrude the top surface 5a into a direction opposite the direction X . Such an arrangement is chosen as the second and third portion 3b , 3c acting as a test component are to be suspended like a cantilever in order to be able to perform bending tests on them .

[0073] Figs . 2A and 2B show steps of a method for performing a characterization of intrinsic stresses within layers of the semiconductor layer stack 6 of the wafer structure shown in figure 1 . The method comprises a step of applying a force F to the test components 3b , 3c in a first area 8 by means of an AFM tip 9 . The first area 8 is thereby located on the test components in an area outside the proj ection of the top surface 5a . Due to the force F, the test components 3b , 3c start to tilt ( see Fig . 2B ) until the test components 3b , 3c touch the substrate 2 . At the same time , the force F, applied to the test components 3b , 3c and the therefrom resulting deflection y of the test components 3b, 3c is determined over the time t . By means of the determined deflection y of the test components while applying a force F, conclusions can be drawn to the bending due to intrinsic stresses and thus to a level of intrinsic stress in the remaining layers . The determined deflection y can thereby result from the position of the AFM tip 9 on the test component 3b, 3c in unloaded condition shown in figure 2a compared to the position of the AFM tip 9 on the test component 3b, 3c when the test component 3b , 3c touches the substrate , as shown in figure 2b .

[0074] Figure 3 shows a side view of a further embodiment of a wafer structure 1 according to some aspects of the proposed principle . In addition to the embodiment shown in Fig . 1 a second support pillar 7 is arranged between the test components 3b, 3c and the substrate 2 adj acent to the first support pillars 5 . The test components 3b, 3c not only protrude the proj ection of the first support pillar 5 at least in the first direction X but in addition protrudes the proj ection of the second support pillar 7 at least in the first direction X . The first area 8 is thereby located on the test components in an area outside the proj ection of the top surface 5a and the second support pillar 7 . In particular, the first area 8 is selected to be arranged, along the first direction X, after the proj ections of the second support pillar 7 and the top surface 5a ( see therefore also Figs . 4D to 4 F ) .

[0075] Due to an arrangement of the test components 3 on only one first support pillar 5 , as shown in Fig . 1 both a compressive and tensile force results in the interface between the test components 3b, 3c and the first support pillar 5 , as the test component starts to tilt due to the applied force F . Due to an arrangement of the test components 3b , 3c on a first support pillar 5 and a second support pillar 7 , as shown in Fig . 3 , the aforementioned compression force between the test components 3b, 3c and the first support pillar 5 can be redirected into a tensile force . The test components 3b , 3c are thus arranged on the first and a second support pillar 5 , 7 as in a rocker . This can help to limit the resulting force in the interface to a pure tensile force , as the compression force acts to the second support pillar 7 and not the interface .

[0076] Figs . 4A to 4 F show embodiments of a top view of a test components with first support pillars 5 connected to the test component with different cross sectional shapes . Thus , the top surfaces 5a of the support pillars 5 comprise a different shape . In a first example , the top surface 5a comprises the shape of a square ( see Fig . 4A) , in a second example , the top surface 5a comprises the shape of a rectangle ( see Fig . 4B ) , and in a third example , top surface 5a comprises the shape of a circle ( see Fig . 4C ) . Figures 4D to 4 F show respective embodiments with each a second support pillar 7 in addition . The shape of the top surface 5a / cross section of the support pillars 5 can in particular be varied and optimized to improve reproducibility and sensitivity of the method .

[0077] The above examples can be distributed across a wafer , such that a plurality of test structures are arranged on the wafer . This will allow determining a respective characterization map of intrinsic stresses of layers of the semiconductor layer stack across the wafer . Further, one may consider using some electronic devices themselves as test structures . This will significantly simplify the processing steps of the wafer , as not all mas ks have to be re-designed . Rather , only some few masks needs to be changed in order , -for example- , to form the second support structure . Furthermore , a method, in which one or more electronic devices are used as test structures , may offer an additional flexibility in selecting test structures across the wafer .

[0078] LIST OF REFERENCES wafer structure substrate

[0079] 3a, 3b, 3c portions

[0080] 4 support element

[0081] 5 first support pillar

[0082] 5a top surface

[0083] 6 semiconductor layer stack

[0084] 6a, 6b layer

[0085] 6c active region

[0086] 6d, 6e current spreading layer

[0087] 7 second support pillar

[0088] 8 first area

[0089] 9 AFM tip

[0090] 10a quantum well

[0091] 10b barrier layer

[0092] X first direction

[0093] F force y deflection

Claims

CLAIMS1. A method for performing a characterization of intrinsic stresses within layers of a semiconductor layer stack, the method comprising the steps of : providing a substrate (2) with a structured semiconductor layer stack (6) arranged on a support element (4) on the substrate (2) , the semiconductor layer stack (6) in particular comprising at least a first layer (6a) of a first conductivity type, a second layer (6b) of a second conductivity type and an active region (6c) arranged between the first and the second layer (6a, 6b) , wherein a plurality of separated first portions (3a) of the semiconductor layer stack (6) each form an electronic component and at least one separated second portion (3b) of the semiconductor layer stack (6) forms a test component, with the at least one second portion (3b) missing at least one layer of the semiconductor layer stack (6) on a side opposite the support element (4) , wherein the at least one second portion (3b) is adjacent to at least one of the plurality of first portions (3a) , wherein the support element (4) comprises a plurality of first support pillars (5) each arranged between the substrate (2) and the first portions (3a) and the at least one second portion (3b) , respectively, wherein the at least one second portion (3b) is arranged on a top surface (5a) of an associated first support pillar (5) , such that the at least one second portion () protrudes a projection of the top surface (5a) at least in a first direction (X) ; applying a force to the at least one second portion (3b) in a first area (8) outside the projection of the top surface (5a) ; and determining the deflection (y) of the at least one second portion (3b) and / or the force (F) applied to the at least one second portion (3b) over time.

2. The method according to claim 1, wherein the step of applying a force (F) to the at least one second portion (3b) is performed by use of a force transducer e.g. AFM (9) or indentor.

3. The method according to claim 1 or 2, wherein the step of providing the substrate (2) with the structured semiconductor layer stack (6) arranged on the support element (4) , comprises a removal of at least one layer of the semiconductor layer stack (6) opposite the support element (4) in the region of the at least one second portion (3b) .

4. The method according to any one of the preceding claims, wherein the support element (4) comprises at least one second support pillar (7) in addition to the first support pillar (5) arranged between the at least one second portion (3b) and the substrate (2) .

5. The method according to claim 4, wherein the at least one second support pillar (7) is arranged adjacent to the first support pillar (5) being associated to the at least one second portion (3b) and the at least one second portion (3b) protrudes a projection of the at least one second support pillar (7) at least in the first direction (X) .

6. The method according to claim 5, wherein the first area (8) is selected to be arranged, along the first direction (X) , after the projections of the at least one second support pillar (7) and the top surface (5a) .

7. The method according to any one of the preceding claims, wherein at least one separated third portion (3c) of the semiconductor layer stack (6) forms a further test component, with the at least one third portion (3c) missing at least one other layer of the semiconductor layer stack (6) on a side opposite the support element (4) compared to the at least one second portion (3b) .

8. The method according to any one of the preceding claims, wherein the projection of the top surface (5a) and / or the projection of the at least one second support pillar (7) comprises one of the following shapes : Rectangle;Square ;Oval ;Circle ;Triangle; andTrapezoid .

9. The method according to any one of the preceding claims, further comprising a step of providing a characterization map indicative of intrinsic stress levels of layers of the semiconductor layer stack (6) throughout the whole lateral extensions of the semiconductor layer stack (6) .

10. The method according to any one of the preceding claims, wherein the step of applying a force (F) to the at least one second portion (3b) is conducted until the at least one second portion (3b) touches the substrate (2) .

11. A wafer structure (1) comprising: a substrate (2) ; a structured semiconductor layer stack (6) in particular with at least a first layer (6a) of a first conductivity type, a second layer (6b) of a second conductivity type and an active region (6c) arranged between the first and the second layer (6a, 6b) ; and a support element (4) arranged between the substrate (2) and the semiconductor layer stack (6) : wherein a plurality of separated first portions (3a) of the semiconductor layer stack (6) each form an electronic component and at least one separated second portion (3b) of the semiconductor layer stack (6) forms a test component, with the at least one second portion (3b) missing at least one layer of the semiconductor layer stack (6) on a side opposite the support element (4) ; wherein the at least one second portion (3b) is adjacent to at least one of the plurality of first portions (3a) ; wherein the support element (4) comprises a plurality of first support pillars (5) each arranged between the substrate (2) and the first portions (3a) and the at least one second portion (3b) , respectively; andwherein the at least one second portion (3b) is arranged on a top surface (5a) of an associated first support pillar (5) , such that the at least one second portion (3b) protrudes a projection of the top surface (5a) at least in a first direction (X) .

12. The wafer structure according to claim 11, wherein the support element (4) comprises at least one second support pillar (7) in addition to the first support pillars (5) arranged between the at least one second portion (3b) and the substrate (2) .

13. The wafer structure according to claim 12, wherein the at least one second support pillar (7) is arranged adjacent to the first support pillar (5) being associated to the at least one second portion (3b) and the at least one second portion (3b) protrudes a projection of the at least one second support pillar (7) at least in the first direction (X) .

14. The wafer structure according to any one of the claims 11 to 13, wherein the projection of the first support pillars (5) and / or the projection of the at least one second support pillar (7) comprises one of the following shapes:Rectangle;Square ;Oval ;Circle ;Triangle; andTrapezoid .

15. The wafer structure according to any one of the claims 11 to 14, wherein at least one separated third portion (3c) of the semiconductor layer stack (6) forms a further test component (3) , with the at least one third portion (3c) missing at least one other layer of the semiconductor layer stack (6) on a side opposite the support element (4) compared to the at least one second portion16. Use of an atomic force microscope tip (9) to perform a characterization of intrinsic stresses within layers of a semiconductor layer stack of a test component of a wafer structure (1) according to any one of the claims 11 to 15, wherein the atomic force microscope tip (9) is configured to apply a force (F) to the test component in a first area (8) , which is selected to be arranged, along the first direction (X) , after the projections of the associated first support pillar (5) and the optionally associated second support pillar (7) .

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