Method for testing semiconductor chips and testing device for testing semiconductor chips

Abstract

A method for testing semiconductor chips which are arranged in a wafer in a matrix having columns and rows comprises steps: - for moving a pressing device of a testing device from row to row relative to the wafer, a contact arrangement of the testing device being pressed by the pressing device onto the wafer such that measuring contacts of the contact arrangement, which are assigned to one column each, electrically contact the semiconductor chips in the associated columns of a row when said row is reached, the measuring contacts comprising a reference measuring contact associated with a reference column, the reference measuring contact being connected to a current source; - for capturing a measurement signal caused by the contacting of the semiconductor chip arranged in the reference column of the particular row; and - for beginning a test process for a plurality of semiconductor chips of the particular row according to the capturing of the measurement signal.

Description

[0001]2023PF01224 - 1 - METHOD FOR TESTING SEMICONDUCTOR CHIPS AND TEST DEVICE FOR TESTING SEMICONDUCTOR CHIPS DESCRIPTION The present invention relates to a method for testing semiconductor chips and a test device for testing semiconductor chips. The patent application claims priority from German patent application 102023 132 727.5, the disclosure of which is hereby incorporated by reference. It is known to test semiconductor chips for functionality and compliance with specified parameters during or after their manufacture. Since semiconductor chips are manufactured in very large quantities, a complete test is associated with a high level of effort. One object of the present invention is to specify a method for testing semiconductor chips. A further object of the present invention is to provide a test device for testing semiconductor chips. These objects are achieved by a method for testingof semiconductor chips and by a test device for testing semiconductor chips with the features of the independent claims. Various further developments are specified in the dependent claims. A method for testing semiconductor chips arranged in a wafer in a matrix with columns and rows comprises steps for moving a pressing device of a test device from row to row relative to the wafer, wherein a contact arrangement of the test device is pressed against the wafer by the pressing device in such a way that measuring contacts of the contact arrangement, each assigned to a column, electrically contact the semiconductor chips in the assigned columns of the respective row upon reaching a row, wherein the measuring contacts comprise a reference measuring contact assigned to a reference column, wherein the reference measuring contact is connected to a current source for detecting a measuring signal whichcaused by contacting the semiconductor chip arranged in the reference column of the respective row, and for starting a test process for several semiconductor chips in the respective row depending on the detection of the measurement signal. This method enables testing of many or even all semiconductor chips arranged in a wafer. The individual semiconductor chips are tested row by row, one after the other, with several or all semiconductor chips in a common row always being tested simultaneously. For this purpose, the semiconductor chips in the individual rows are electrically contacted one after the other by the test device. The semiconductor chips located in a column of the matrix arrangement serve as a reference to detect electrical contact between the semiconductor chips in the respective row. If the semiconductor chip located in the reference column is electrically contacted, the remaining semiconductor chips in theThe respective row is electrically contacted separately. From the detection of the measurement signal caused by contacting the semiconductor chip arranged in the reference column, it can be concluded that the remaining semiconductor chips in the respective row are also electrically contacted. This makes it possible to subsequently start the test procedure at a time when all semiconductor chips in the respective row are in a known, defined state. This can reduce the risk of damage to the semiconductor chips caused by the test procedure and increase the reliability of the test results obtained by the test procedure. In one variant of the method, the measurement signal is a voltage drop across the semiconductor chip arranged in the reference column of the respective row. By contacting the semiconductor chip arranged in the reference column with the 2023PF01224 - 3 - reference measurement contact, theA current source connected to the reference measuring contact is connected to the semiconductor chip, so that an electrical voltage drops across the semiconductor chip in the reference column. This voltage drop can be detected simply and reliably, allowing the time of electrical contacting of the semiconductor chip arranged in the reference column to be determined with high accuracy. In one variant of the method, the reference column has a semiconductor chip in each row of the wafer. For this purpose, the reference column can, for example, be a column arranged near the center of the wafer. If the reference column has a semiconductor chip in each row of the wafer, the contacting of the semiconductor chip arranged in the reference column by the reference measuring contact can advantageously be detected in each row of the wafer. In one variant of the method, the test procedure is terminated after a specified period of time has elapsed after the acquisition of the measurement signal.started. This can, for example, make it possible to start the test process only after a transient response, which can increase the meaningfulness or reliability of the test results obtained through the test process. In one variant of the method, the specified time period is between 1 ms and 10 ms. Advantageously, such a time period represents a sensible compromise between rapid execution of the method and high reliability of the test processes performed during the method. In one variant of the method, the contact arrangement electrically contacts all semiconductor chips of the respective row. Advantageously, the method then enables a particularly complete testing of the semiconductor chips of the wafer. 2023PF01224 - 4 - In one variant of the method, starting the test process comprises activating current sources connected to the measuring contacts. This can, for example, activate all measuring contactsexcept for the reference measuring contact. This advantageously makes it possible to only supply current to the semiconductor chips once they have been reliably electrically contacted. This avoids any current peaks that might otherwise occur during contacting, which could result in damage to the semiconductor chips. Furthermore, the method then advantageously makes it possible to supply current to the semiconductor chips only for a specified period of time. In one variant of the method, the test procedure comprises several consecutive measurements. Advantageously, this allows several different measurements to be carried out one after the other for each semiconductor chip, whereby only one pass through the test device is required. In one variant of the method, the multiple measurements are carried out in different orders for different semiconductor chips in the respective row. This makes it possible, for example, to carry out measurements thatentails a strong heating of the semiconductor chips, not to be performed on all semiconductor chips in a row simultaneously, thus preventing excessive heating of the wafer. Performing multiple measurements on different semiconductor chips in different sequences can also make it possible to maintain a smaller number of test devices required for performing the measurements, such as current sources, than the number of columns in the matrix. In one variant of the method, the movement of the pressing device is interrupted during the test process. Advantageously, an arbitrarily long time is then available in each row for the testing of the semiconductor chips in the respective row. In one variant of the method, each measuring contact is electrically short-circuited to a mating contact, while the measuring contact is not connected to a semiconductor chip. This canFor example, they allow current sources connected to the measuring contacts to remain permanently activated, even while the pressing device is moved from one row of the matrix to the next. By short-circuiting the measuring contacts, excessive overshoot of the current sources can be prevented in this case. A test device for testing semiconductor chips is designed to accommodate a wafer having semiconductor chips arranged in a matrix with columns and rows. The test device comprises a pressing device that is movable from row to row relative to the wafer. Furthermore, the test device comprises a contact arrangement with measuring contacts, each of which is assigned to a column. The measuring contacts comprise a reference measuring contact that is assigned to a reference column. The reference measuring contact is connectable to a current source. The contact arrangement can be pressed against the wafer by the pressing device in such a way thatWhen a row is reached, the measuring contacts electrically contact the semiconductor chips in the columns of the respective row assigned to the measuring contacts. The test device is designed to detect a measuring signal caused by contacting the semiconductor chip arranged in the reference column of the respective row. The test device is also designed to start a test process for several semiconductor chips in the respective row depending on the detection of the measuring signal. This test device enables testing of many or even all semiconductor chips arranged in a wafer. The testing of the individual semiconductor chips takes place row by row, one after the other, with several or all semiconductor chips of a common row being tested simultaneously. For this purpose, the semiconductor chips of the individual rows are electrically contacted one after the other by the test device. The semiconductor chips arranged in a column of theThe semiconductor chips located in the matrix arrangement serve as a reference to detect electrical contact between the semiconductor chips located in the respective row. If the semiconductor chip located in the reference column is electrically contacted, the remaining semiconductor chips in the respective row are also electrically contacted. From the detection of the measurement signal caused by contacting the semiconductor chip located in the reference column, it can be concluded that the remaining semiconductor chips in the respective row are also electrically contacted. This makes it possible to subsequently start the test procedure at a time when all semiconductor chips in the respective row are in a known, defined state. This can reduce the risk of damage to the semiconductor chips caused by the test procedure and increase the reliability of the test results obtained through the test procedure.In one variant of the test device, the contact arrangement is designed to electrically contact all semiconductor chips in a row. Advantageously, the test device thus enables particularly complete testing of the semiconductor chips arranged in a wafer. In one variant of the test device, the contact arrangement has a z-diode for each measuring contact, which is connected in anti-parallel to a semiconductor chip contacted by the measuring contact. A current flow caused by a current source connected to a measuring contact can then pass through the z-diode while the measuring contact is not connected to a semiconductor chip. This prevents excessive oscillation of the current source after contacting a semiconductor chip. 2023PF01224 - 7 - In one variant of the test device, it has a counter-contact that is provided to electrically contact all semiconductor chips of a wafer accommodated in the test device.contact. Individual control of the individual semiconductor chips is nevertheless possible through the measuring contacts of the contact arrangement. In one variant of the test device, the counter contact is arranged on a side of a wafer accommodated in the test device that is opposite the contact arrangement. The test device thus advantageously enables testing of semiconductor chips that have electrical contact surfaces arranged on opposite sides. In one variant of the test device, the contact arrangement has a switch for each measuring contact to electrically short-circuit the respective measuring contact to the counter contact while the measuring contact is not connected to a semiconductor chip. This makes it possible to connect the measuring contacts to permanently activated current sources without causing a strong oscillation of the respective current source after contacting a semiconductor chip. In one variantIn the test device, the contact arrangement has a flexible carrier. The measuring contacts are designed as conductor tracks arranged on the flexible carrier. This advantageously results in a simple and reliable design of the test device. In one variant of the test device, the pressing device is designed as a squeegee. Advantageously, a pressing device designed in this way enables reliable pressing of the contact arrangement onto the wafer. The properties, features, and advantages of this invention described above, as well as the manner in which they are achieved, will become clearer and more clearly understandable in connection with the following description of the exemplary embodiments, which are explained in more detail in connection with the drawings. In each case, Fig. 1 shows a test device for testing semiconductor chips; Fig. 2 shows a wafer with a matrix with columnsand rows of semiconductor chips arranged; Fig. 3 shows a contact arrangement of the test device; Fig. 4 shows a timing diagram during a method for testing semiconductor chips; and Fig. 5 shows a variant of the contact arrangement of the test device. Fig. 1 shows a highly schematic representation of a test device 200 for testing semiconductor chips 150. The semiconductor chips 150 are arranged undivided in a wafer 100, which is shown schematically in Fig. 2. The semiconductor chips 150 can be, for example, optoelectronic semiconductor chips, in particular, for example, light-emitting semiconductor chips, for example light-emitting diode chips (LED chips). In the wafer 100, the semiconductor chips 150 are arranged in a matrix 110 with columns 120 and rows 130. In the schematic representation in Fig. 2, only a few columns 120 and rows 130 are shown. In fact, the matrix 110 can comprise several hundred columns 120 and rows 130 each. The semiconductor chips 150each have a front side 151, which is arranged on a front side 101 of the wafer 100. In addition, the semiconductor chips 150 each have a back side 152 opposite the front side 151, which is arranged on a back side 102 of the wafer 100. In the example shown in the 2023PF01224 - 9 - figures, the semiconductor chips 150 each have electrical contacts on their front sides 151 and on their back sides 152, which enable electrical contacting of the semiconductor chips 150. However, it would also be possible for all electrical contact surfaces of the semiconductor chips 150 to be arranged on the front sides 151 of the semiconductor chips 150. The test apparatus 200 shown in Fig. 1 serves to test the semiconductor chips 150. It is desirable to test a large part or even all of the semiconductor chips 150 arranged in the wafer 100. The tests performed on the semiconductor chips 150 can, for example, verify functionality and compliancepredetermined parameters. The test device 200 has a carrier 260 on which the wafer 100 can be held. In the example shown, the wafer 100 is held such that the front side 101 of the wafer 100 faces away from the carrier 260 and the back side 102 of the wafer 100 is in contact with an upper side of the carrier 260. The carrier 260 can be designed, for example, as a chuck. The test device 200 further has a contact arrangement 210, which is arranged above the front side 101 of the wafer 100 held in the test device 200. Fig. 3 shows a top view of the contact arrangement 210 in a schematic representation. The contact arrangement 210 has measuring contacts 220, which are assigned to the columns 120 of the matrix 110 of the semiconductor chips 150 arranged in the wafer 100. Each column 120 can be assigned its own measuring contact 220. If the semiconductor chips 150 have several electricalContacts, then each column 120 can also be assigned a plurality of measuring contacts 220. If not all columns 120 of semiconductor chips 150 are to be tested, then not all columns 120 have to be assigned measuring contacts 220 of the contact arrangement 210. 2023PF01224 - 10 - In the example of the test device 200 shown schematically in Fig. 1, the contact arrangement 210 has a flexible carrier, which can also be referred to as a flexboard. The measuring contacts 220 are designed as conductor tracks arranged on the flexible carrier. The flexible carrier is arranged above the front side 101 of the wafer 100 in such a way that the conductor tracks forming the measuring contacts 220 face the front side 101 of the wafer 100. The test device 200 further comprises a pressing device 230, which is movable along a movement direction 231 relative to the wafer 100 accommodated in the test device 200. The movement direction 231 is parallel to the gaps120 and oriented perpendicular to the rows 130 of the matrix 110, so that the pressing device 230 is movable along the direction of movement 231 relative to the wafer 100 from row 130 to row 130. The contact arrangement 210 can be pressed locally against the wafer 100 by the pressing device 230 such that the measuring contacts 220 always electrically contact the semiconductor chips 150 of a row 130 during the movement of the pressing device 230 when the pressing device 230 reaches the respective row 130 during its movement. In this case, each measuring contact 220 of the contact arrangement 210 contacts the semiconductor chip 150 in the column 120 of the respective row 130 assigned to the measuring contact 220. Thus, during the movement of the pressing device 230, the measuring contacts 220 of the contact arrangement 210 contact at any time only either the semiconductor chips 150 of a current row 130, 135 or no semiconductor chips 150 at all. This is the case when thePressing device 230 is located between two rows 130 of the matrix 110. In Fig. 2, an exemplary row 130 is marked as the current row 130, 135. 2023PF01224 - 11 - In the example of the test device 200 shown in the figures, the pressing device 230 is designed, for example, as a squeegee. In the example of the test device 200 shown in Fig. 1, the carrier 260 has a mating contact 270 that electrically contacts the electrical contact surfaces formed on the rear sides 152 of the semiconductor chips 150. In this case, all semiconductor chips 150 of the wafer 100 accommodated in the test device 200 are jointly contacted by the one mating contact 270. However, it would also be possible to provide different counter contacts 270 for different semiconductor chips 150. If all electrical contacts of the semiconductor chips 150 are arranged on the front sides 151 of the semiconductor chips 150, the counter contacts 270alternatively, it can be formed by additional measuring contacts 220 on the contact arrangement 210. In this case, the additional measuring contacts 220 can optionally also be electrically conductively connected to one another in such a way that a common mating contact 270 is formed for all semiconductor chips 150 of the wafer 100. The measuring contacts 220 of the contact arrangement 210 of the test device 200 can be connected to current sources 240. As shown schematically in Fig. 3, a separate current source 240 can be provided for each measuring contact 220. However, it is also possible for several measuring contacts 220 to share a common current source 240. In this case, a current source 240 can, for example, be connected simultaneously to several measuring contacts 220 or sequentially to different measuring contacts 220. It is also possible that several sets of different power sources 240 are provided, for example power sources 240 with different power. The power sources240 are always connected between a measuring contact 220 and the associated mating contact 270. 2023PF01224 - 12 - One of the columns 120 of the matrix 110 of semiconductor chips 150 of the wafer 110 forms a reference column 125. This is illustrated schematically in Fig. 2. The measuring contact 220 assigned to the reference column 125 forms a reference measuring contact 225, which is shown in Fig. 3. It is expedient if the reference column 125 is formed by a column 120 of the matrix 110 that has a semiconductor chip 150 in each row 130 of the matrix 110. This can be the case, for example, with columns 120 arranged near the center of the wafer 100. It is possible for two or more columns 120 to form reference columns 120. This may be useful to increase the probability that the reference columns 120 have at least one functional semiconductor chip 150 in each row 130. During the movement of the pressing device 230, the reference measuring contact250 is connected to an activated current source 240. As soon as the reference measuring contact 225 makes electrical contact with a semiconductor chip 150 arranged in the reference column 125 of a then current row 130, 135, the test device 200 detects a measurement signal 330. This is shown schematically in a timing diagram 300 shown in Fig. 4. A time 360 ​​progressing to the right is shown on the horizontal axis. The vertical axis shows a measured variable comprising the measurement signal 330, which in the example shown is a voltage drop 320 across the semiconductor chip 150 contacted by the reference measuring contact 225. The voltage drop 320 can be detected in the example of the test device 200 shown in Fig. 1 in a four-wire measurement using a voltage measuring device 250. Instead of the voltage drop 320, however, a current flowing through the semiconductor chip 150 could also be used as the measured variable comprising the measurement signal 330.be used. As soon as the reference measuring contact 225 electrically contacts the semiconductor chip 150 arranged in the reference column 125 of the then current row 130, 135, a non-zero voltage drop 320 results across the semiconductor chip 150. The rising edge of the voltage drop 320 forms the measuring signal 330, based on which the contacting of the semiconductor chip 150 arranged in the reference column 125 of the current row 130, 135 can be reliably detected. Since the measuring contacts 220 of the contact arrangement 210 always electrically contact the semiconductor chips 150 arranged in the respectively assigned columns 120 of the current row 130, 135 simultaneously or almost simultaneously, it can be concluded from the detection of the measuring signal 330 that after a specified time period 311 has elapsed after the occurrence of the measuring signal 330, the semiconductor chips 150 in the columns 120 of the current row 130, 135 assigned to the further measuring contacts 220Rows 130, 135 are electrically contacted. Therefore, after the expiration of the specified time period 311 following the acquisition of the measurement signal 330, a test process can be started on the semiconductor chips 150 of the current row 130, 135. The specified time period 311 can be, for example, between 1 ms and 10 ms, for example 3 ms. The testing of the semiconductor chips 150 of the current row 130, 135 takes place during a test period 312 following the expiration of the specified time period 311. The test process is carried out simultaneously for all semiconductor chips 150 contacted by the measurement contacts 220. During the entire test period 312, the measuring contacts 220 of the contact arrangement 210 are connected to the semiconductor chips 150 in the associated columns 120 of the current row 130, 135. The test procedure can comprise several consecutive measurements for each semiconductor chip 150. If the semiconductor chips 150 are optoelectronicSemiconductor chips, measurements can be included in both the forward and reverse directions of the semiconductor chip 150. 2023PF01224 - 14 - It is possible to interrupt the movement of the pressing device 230 during the test process. In this case, the test period 312 can have any length. This can make it possible to perform time-consuming measurements or multiple consecutive measurements on the semiconductor chips 150 of the current row 130, 135 during the test process. After the test process for the semiconductor chips 150 of the current row 130, 135 has been completed, the movement of the pressing device 230 is then continued. After completion of the test procedure in the current row 130, 135, the pressing device 230 moves on to the next row 130 of the matrix 110. Reaching the next row 130, which then forms the current row 130, 135, is again recognizable by the occurrence of the measuring signal 330, which is generated by contacting the contact element 130 in theReference column 125 of the then current row 130, 135 is caused. Depending on this renewed acquisition of the measurement signal 330, the test process then begins for the semiconductor chips 150 of the then current row 130, 135. This repeating sequence can be seen in the timing diagram 300 of Fig. 4. Starting the test process in the respective current row 130, 135 can include activating the current sources 240 connected to the measuring contacts 220. In this case, the current sources 240 can be switched off between the individual test processes. Activating the current sources 240 at the beginning of the test process makes it possible to supply current to the semiconductor chips 150 for a precisely defined period of time. Activating the current sources 240 at the beginning of the test procedure can also allow the current sources 240 to settle before starting the actual measurement. Furthermore, activating and deactivating theCurrent sources 240 prevent current peaks that might otherwise occur during contacting of the semiconductor chips 150. 2023PF01224 - 15 - Fig. 5 shows, in a highly schematic representation, an optional additional embodiment of the contact arrangement 210 of the test device 200. Here, the contact arrangement 210 has a z-diode 280 for each measuring contact 220, which is connected in antiparallel to a semiconductor chip 150 contacted by the measuring contact 220. It is expedient if a breakdown voltage of the z-diode 280 is somewhat higher than an operating voltage of the tested semiconductor chips 150. In this case, the measuring contacts 220 can remain permanently connected to activated current sources 240. Between the individual rows 130 of the matrix 110, a current flow then occurs via the respective z-diode 280. After contacting the semiconductor chip 150 of a then current row 130, 135, the current flow occurs through theSemiconductor chip 150. This prevents a significant change in the voltage at the respective current source 240 when switching between the rows 130 of the matrix 110. Alternatively or additionally, the contact arrangement 210 can have a switch 290 for each measuring contact 220. The switch 290 makes it possible to electrically short-circuit the respective measuring contact 220 to the mating contact 270, while the measuring contact 220 between two rows 130 of the matrix 110 is not connected to a semiconductor chip 150. This also makes it possible to maintain constant current regulation of the respective current source 240 between the rows 130 of the matrix 110. In this variant, the measuring contacts 220 of the contact arrangement 210 can therefore also remain connected to permanently activated current sources 240 throughout the entire test procedure. The reference measuring contact 225 can be connected to a permanently activated current source 240 throughout the entire test procedure across all lines 130remain connected. However, it is also possible to connect the reference measuring contact 225 to an active current source 240 only while the pressing device 230 is moving from one row 130 to the next row 130. During the test periods 312, the current source 240 connected to the reference measuring contact 225 is then deactivated or the current source 240 is disconnected from the reference measuring contact 225. In any case, it is possible to also perform the measurements performed in each row 130 during the test process on the semiconductor chip 150 arranged in the reference column 125. The test process can comprise several consecutive measurements in each row 130 and for each semiconductor chip 150. It is possible to perform the multiple measurements on different semiconductor chips 150 of the respective current row 130, 135 in a different order. For this purpose, the semiconductor chips 150 of a row 130 can, for example, bedivided into two or more groups. For example, a left half of the columns 120 can be assigned to a first group and a right half of the columns 120 to a second group. Alternatively, the columns 120 can be assigned alternately to the two groups, for example. The multiple successive measurements of the test procedure then take place in different orders in the two groups. This can make it possible, for example, to use the current sources 240 or other devices required to perform the measurements consecutively for both groups. It can also be avoided, for example, excessive heating of the entire wafer 100 during a measurement accompanied by heating of the individual semiconductor chips 150. The invention has been illustrated and described in more detail using the preferred embodiments. Nevertheless, the invention is not limited to the disclosed examples. Other variationscan be derived by a person skilled in the art. 2023PF01224 - 17 - LIST OF REFERENCE SYMBOLS 100 wafer 101 front side 102 back side 110 matrix 120 column 125 reference column 130 row 135 current row 150 semiconductor chip 151 front side 152 back side 200 test device 210 contact arrangement 220 measuring contact 225 reference measuring contact 230 pressing device 231 direction of movement 240 current source 250 voltage measuring device 260 carrier 270 counter contact 280 zener diode 290 switch 300 timing diagram 310 time 311 fixed time period 2023PF01224 - 18 - 312 test period 320 voltage drop 330 measuring signal

Claims

2023PF01224 - 19 - PATENT CLAIMS 1. Method for testing semiconductor chips (150) arranged in a wafer (100) in a matrix (110) with columns (120) and rows (130), comprising the following steps: - moving a pressing device (230) of a test device (200) from row (130) to row (130) relative to the wafer (100), wherein a contact arrangement (210) of the test device (200) is pressed against the wafer (100) by the pressing device (230) in such a way that measuring contacts (220) of the contact arrangement (210), each assigned to a column (120), electrically test the semiconductor chips (150) in the assigned columns (120) of the respective row (130) upon reaching a row (130). contact, wherein the measuring contacts (220) comprise a reference measuring contact (225) which is assigned to a reference column (125), wherein the reference measuring contact (225) is connected to a current source (240), - detecting a measuring signal (330),which is caused by contacting the semiconductor chip (150) arranged in the reference column (125) of the respective row (130), - starting a test process for several semiconductor chips (150) of the respective row (130) depending on the detection of the measurement signal (330).

2. The method according to claim 1, wherein the measurement signal (330) is a voltage drop (320) across the semiconductor chip (150) arranged in the reference column (125) of the respective row (130).

3. The method according to one of the preceding claims, wherein the reference column (125) has a semiconductor chip (150) in each row (130) of the wafer (100). 2023PF01224 - 20 - 4. The method according to one of the preceding claims, wherein the test process is started after a specified time period (311) has elapsed after the detection of the measurement signal (330).

5. The method according to claim 4, wherein the specified time period (311) is between 1 ms and 10 ms.

6. The method according to one of the preceding claims, wherein the contact arrangement (210) electrically contacts all semiconductor chips (150) of the respective row (130).

7. The method according to one of the preceding claims, wherein starting the test process comprises activating current sources (240) connected to the measurement contacts (220).

8. The method according to one of the preceding claims, wherein the test process comprises a plurality of successive measurements.

9. The method according to claim 8, wherein the multiple measurements are performed on different semiconductor chips (150) of the respective row (130) in different orders. 10.Method according to one of the preceding claims, wherein the movement of the pressing device (230) is interrupted during the testing process.

11. Method according to one of the preceding claims, wherein each measuring contact (220) is electrically short-circuited to a mating contact (270) while the measuring contact (220) is not connected to a semiconductor chip (150). 2023PF01224 - 21 - 12. Testing device (200) for testing semiconductor chips (150), designed to receive a wafer (100) having semiconductor chips (150) arranged in a matrix (110) with columns (120) and rows (130), with a pressing device (230) that is movable relative to the wafer (100) from row (130) to row (130), and with a contact arrangement (210) with measuring contacts (220), each associated with a column (120), wherein the measuring contacts (220) comprise a reference measuring contact (225) associated with a reference column (125), wherein the reference measuring contact (225) is connectable to a current source (240), wherein the contact arrangement (210) is connected by the pressing device (230) can be pressed onto the wafer (100) in such a way that the measuring contacts (220) electrically contact the semiconductor chips (150) in the associated columns (120) of the respective row (130) when a row (130) is reached,wherein the test device (200) is designed to detect a measurement signal (330) caused by the contacting of the semiconductor chip (150) arranged in the reference column (125) of the respective row (130), wherein the test device (200) is designed to begin a test process for a plurality of semiconductor chips (150) of the respective row (130) depending on the detection of the measurement signal (330).

13. Test device (200) according to claim 12, wherein the contact arrangement (210) is designed to electrically contact all semiconductor chips (150) of a row (130).

14. Test device (200) according to one of claims 12 and 13, wherein the contact arrangement (210) has a z-diode (280) for each measurement contact (220), which 2023PF01224 - 22 - is connected in antiparallel with the semiconductor chip (150) contacted by the measuring contact (220).

15. Test device (200) according to claim 14, wherein a breakdown voltage of the z-diode (280) is higher than an operating voltage of the semiconductor chip (150).

16. Test device (200) according to one of claims 12 to 15, wherein the test device (200) has a counter contact (270) which is provided for electrically contacting all semiconductor chips (150) of a wafer (100) accommodated in the test device (200).

17. Test device (200) according to claim 16, wherein the counter contact (270) is arranged on a side (102) of a wafer (100) received in the test device (200) opposite the contact arrangement (210). 18.Testing device (200) according to one of claims 16 and 17, wherein the contact arrangement (210) has a switch (290) for each measuring contact (220) in order to electrically short-circuit the respective measuring contact (220) to the counter contact (270) while the measuring contact (220) is not connected to a semiconductor chip (150).

19. Testing device (200) according to one of claims 12 to 18, wherein the contact arrangement (210) has a flexible carrier, wherein the measuring contacts (220) are designed as conductor tracks arranged on the flexible carrier.

20. Testing device (200) according to one of claims 12 to 19, wherein the pressing device (230) is designed as a squeegee.

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