Power factor correction device for a motor vehicle charger

Abstract

The invention relates to a method comprising receiving a sinusoidal reference current that is in phase with a sinusoidal supply voltage; generating a regulated current corresponding to the current drawn by the electrical charger; generating a measured current on the basis of the regulated current; generating an error signal by comparing the sinusoidal reference current with the measured current; the step of generating the regulated current comprising: generating a gain factor on the basis of the error signal; applying the gain factor to the error signal to generate a weighted error signal; applying a regulation function to the weighted error signal to generate the regulated current.

Description

[0001] Power factor correction device for a motor vehicle charger

[0002] DESCRIPTION

[0003] Technical field

[0004] This description relates to a power factor correction device and an on-board charger for a motor vehicle incorporating such a charger.

[0005] Technical background

[0006] On-board automotive chargers can be connected to a wide variety of power supply networks. One of their characteristics is the line impedance (mainly, a line inductance), which depends mainly on the distance from the vehicle to the power transformer and the quality of the power cable(s) through which the charger is connected to the power supply network. A good approximation is to consider that the equivalent line inductance increases from 1 H to 1.6 H per linear meter of power cable.

[0007] This line inductance adds to the power inductance and affects the stability and performance of the power factor correction module integrated in the on-board charger. There is therefore a need to improve the situation.

[0008] Summary

[0009] A first aspect concerns a power factor correction device for an on-board electric charger of a motor vehicle battery.

[0010] According to a first aspect, a power factor correction device for an on-board electrical charger of a motor vehicle battery is described.The power factor correction device comprises a current regulation loop; the regulation loop comprising a forward chain generating a regulated current corresponding to the current drawn by the electrical charger and a feedback chain generating a current measured from the regulated current; the regulation loop being configured to receive as input a sinusoidal setpoint current in phase with a sinusoidal supply voltage and to generate an error signal by comparing the sinusoidal setpoint current with the measured current supplied by the feedback chain; the forward chain comprising a controller of the regulation loop, a gain adapter configured to generate a gain factor, an amplifier configured to apply the gain factor to the input signal of the controller, the gain factor being generated on the basis of the error signal.

[0011] In one or more embodiments, the gain adapter is configured to generate the gain factor based on a tracking error of the control loop determined from the error signal.

[0012] In one or more embodiments, the tracking error is determined as the root mean square (rms) value of the error signal.

[0013] In one or more embodiments, the tracking error is determined as the average, over a period of the supply voltage, of the error signal.

[0014] In one or more embodiments, the gain adapter is configured to generate the gain factor based on a gain weighting coefficient of the open-loop transfer function.

[0015] In one or more embodiments, the gain adapter is configured to determine an error rate from the error signal and to normalize the error rate between 0 and 1 based on the setpoint sinusoidal current or the measured current to generate a normalized error rate.

[0016] In one or more embodiments, the gain adapter is configured to compare the normalized error rate with a setpoint error rate.

[0017] According to another aspect, an electric battery charger for on-board use in a motor vehicle is described. The electric charger comprises a power factor correction device according to the first aspect.

[0018] A second aspect relates to a power factor correction method for an on-board electric charger of a motor vehicle battery.

[0019] The method comprises: receiving a setpoint sinusoidal current in phase with a sinusoidal supply voltage; generating a regulated current corresponding to the current drawn by the electrical charger; generating a measured current from the regulated current; generating an error signal by comparing the setpoint sinusoidal current with the measured current; generating the regulated current comprising: generating a gain factor based on the error signal; applying the gain factor to the error signal to generate a weighted error signal; applying a regulation function to the weighted error signal to generate the regulated current. A third aspect relates to a computer program comprising instructions adapted to cause the execution of the steps of a power factor correction method according to the second aspect.These instructions are intended to be stored in a device's memory, loaded and then executed by a processor of that device.

[0020] Generally, the device according to the first aspect may comprise means for performing one or more or all of the steps of a power factor correction method according to any of the embodiments described in this document.

[0021] These means may comprise software and / or hardware means. These means may comprise, for example, one or more circuits configured to execute one or more or all of the steps of a power factor correction method according to the second aspect or according to any of the embodiments described in this document. These means may comprise, for example, at least one processor and at least one memory comprising instructions, the memory and the instructions being configured to, with the processor, cause a device to execute one or more or all of the steps of a power factor correction method according to any of the embodiments disclosed in this document.

[0022] The term "circuit" may refer to one or more analog and / or digital circuits, whether or not combined with software and / or firmware to perform one or more functions described in this document. These circuits may include one or more memories and / or one or more hardware processors (e.g., a microprocessor or microcontroller) that cooperate to enable a host device including this circuit to implement one or more functions described in this document. These hardware processors may or may not require software (e.g., firmware) to implement the corresponding function(s).

[0023] Brief description of the Figures

[0024] Other characteristics and advantages will appear during the reading of the detailed description which follows for the understanding of which one will refer to the attached drawings among which:

[0025] [Fig.1] - Figure 1 schematically represents an on-board charger in a motor vehicle according to an exemplary embodiment.

[0026] [Fig. 2] - Figure 2 shows curves illustrating the effect on the current of a power factor correction device according to an exemplary embodiment. [Fig. 3] - Figure 3 schematically represents a system comprising an electrical supply network and a charger including a power factor correction device according to an exemplary embodiment in the case where the network includes the line inductances.

[0027] [Fig. 4] - Figure 4 schematically represents a system comprising an electrical power supply network and a charger including a power factor correction device according to an exemplary embodiment in the case where the line inductances are reduced to the power inductances to constitute an equivalent inductance

[0028] [Fig. 5] - Figure 5 shows the open-loop transfer function of a power factor correction device with different types of controller according to exemplary embodiments and for two line inductance values.

[0029] [Fig. 6] - Figure 6 schematically represents a power factor correction device integrating an adapter of the gain of the open loop transfer function according to an exemplary embodiment.

[0030] [Fig. 7] - Figure 7 schematically represents a device for adapting the gain of the open-loop transfer function for a power factor correction device according to an exemplary embodiment.

[0031] [Fig. 8] - Figure 8 is a flowchart of a method of activating a gain matching device for a power factor correction device according to an exemplary embodiment.

[0032] [Fig. 9] - Figure 9 shows curves illustrating the operation of a power factor correction device in the absence of gain adaptation according to an exemplary embodiment.

[0033] [Fig. 10] - Figure 10 shows curves illustrating the operation of a power factor correction device with gain adaptation according to an exemplary embodiment.

[0034] Detailed description

[0035] In the following description, identical, similar or analogous elements will be designated by the same reference numbers.

[0036] This description relates to a vehicle charger (also called an on-board charger) installed in a motor vehicle and a power factor correction device for such a charger. Such a charger is called a “High Voltage On-board Charger” in English terminology.

[0037] Figure 1 schematically represents such a charger 100.

[0038] When charging the vehicle, it is this charger 100 inside the vehicle that receives the voltage VGRID supplied by the electrical supply network and optimizes the charging of the battery 190. The voltage supplied by the electrical network, here called GRID supply voltage, is an alternating, sinusoidal voltage of frequency considered to be fixed (in practice, this frequency varies around a reference value, for example 50Hz, depending on the different loads / power sources connected to the network). This voltage can be supplied via a single-phase or three-phase electrical energy source. For the sake of simplification, only the single-phase case will be described in detail. But the invention is also applicable to a three-phase source, the gain adaptation being applied to each phase.

[0039] The charger contains a power factor correction device 110 (also called PFC for "Power Factor Corrector" in English terminology) whose purpose is to draw a current lo from the electrical network so that the drawn current lo is as sinusoidal as possible and as in phase as possible with the voltage VGRID of the electrical supply network in order to optimize the power factor. Indeed, the power factor is linked to the instantaneous power which is the product of the voltage by the current, so that the power factor will be maximum if the current and the voltage are in phase (and of the same sign). Power losses are thus reduced.

[0040] Figure 2 shows the action of the PFC 120 on the current lo drawn by the charger. The shape of the current drawn by the charger, passively without corrective action from the PFC, depends on the battery and the PFC 110 and is not necessarily sinusoidal, nor in phase with the sinusoidal supply voltage as illustrated by Figure 2. According to the example of subfigure 2A, the current drawn lo, before correction by the PFC, is neither sinusoidal nor in phase with the alternating voltage VGRID of the electrical network. Power losses are shown schematically in subfigure 2A and depend in particular on the phase shift between the voltage and the current. In subfigure 2B, we see that the corrected current lo drawn by the charger, as corrected under the action of the PFC, is sinusoidal and in phase with the alternating voltage VGRID of the electrical network.

[0041] The PFC 110 receives as input the alternating voltage VGRID from the electrical network and supplies current h to a direct voltage bus 120. The direct voltage bus 120 is also called a “DC link” in English terminology. The DC link 120 may comprise one or more capacitors. In the schematic example of Figure 1, a single capacitor C1 is shown.

[0042] The PFC 110 thus ensures a power transfer between an alternating input voltage VGRID and an output voltage, which is a constant direct voltage and which is the voltage VDC at the terminals of the DC Link. This voltage can be imposed at a value of, for example, 400 Volts or 800 Volts.

[0043] The output of the DC link 120 is connected to a power transfer device 130 (called “high voltage DC-DC” in English terminology) which receives the voltage VDC at the terminals of the DC Link 120, carries out a power transfer between the DC link with direct and fixed voltage and the input voltage VBAT of the battery 190. The input voltage of the battery VBAT is also a direct voltage, but variable: this input voltage VBAT of the battery 190 depends on the charge level of the battery 190. The voltage at the terminals of the battery 190 drops as the battery 190 discharges and increases when the battery 190 is charged. The nominal voltage at the terminals of the battery 190, in the fully charged state, can be, for example, 400 Volts or 800 Volts.

[0044] Figures 3 and 4 schematically represent a system comprising a power supply network and a charger including a power factor correction device according to an exemplary embodiment. Compared to Figure 3, Figure 4 shows the effect of the line inductances on the PFC by an additional inductance applied to the power inductances, the sum of which constitutes the equivalent inductance.

[0045] According to what is shown in Figure 3 and for this embodiment of the PFC, there is, on each of the arms in the case of a three-phase power supply, in the charger 300, a power inductance denoted LBOOST. on each arm A switching cell 350 includes, for each phase of the power signal, 2 switches: a high switch 351 and a low switch 352. The power transfer is done between the electrical power supply network and the DC link by a set of activation and deactivation of these switches so that the power inductance is charged then discharged in the DC link via the PFC 330. In a known manner, the control signals of these switches are produced by a control device 360 ​​of the PFC 330, from signals produced in the current regulation loop 340 of the PFC. The LBOOST power inductance has a nominal value in the order of several hundred pH (micro Henri), for example between 2 and 300 pH.

[0046] Depending on the power supply network 310, the distance from the vehicle to the last power transformer may vary. As a result, additional inductances, called LUNE line inductances, are added to the power inductances. The value of these line inductances depends mainly on the distance between the vehicle being charged and the last power transformer isolating the power supply network. This increase in inductance is of the order of 1 pH per meter. For example, for 2 km from the last transformer, the cumulative line inductance on one phase is 2000 pH, or 2 mH.

[0047] A small signal analysis characterizes the effect of the line inductances and shows that the value of the cumulative line inductance adds up to the power inductance of the phase concerned so that, as shown in Figure 4, for each phase, the equivalent inductance LEQ is the sum of the power inductance LBOOST and the line inductance LUNE, with LEQ much greater than LBOOST.

[0048] For example, with a power inductance of 200 pH, the equivalent inductance taking into account the line inductances will be 2.2 mH, or a factor of 10 on the value of the power inductance. As a result, the charger's response is significantly modified, in particular the current regulation function implemented by the control device 360 ​​of the PFC 330 aimed at generating a sinusoidal current as much in phase as possible with the supply voltage.

[0049] The PFC 330 receives the sinusoidal supply voltage as input. If the input current drawn by the PFC 110 is not controlled, it is the load, i.e. the battery in this case, which will dictate the shape of the current drawn by the charger. The function of the PFC 330 is to dictate that the load draws a sinusoidal current from the DC link input.

[0050] The current regulation function is performed by the PFC by means of the current regulation loop 340 which receives as input a sinusoidal setpoint current ISET (set point) in phase with the sinusoidal supply voltage. The regulation loop thus regulates the current lo drawn by the charger. The amplitude of the sinusoidal setpoint current is adapted over time: the amplitude at a given instant is that which makes it possible to supply the terminals of the DC link with power sufficient to meet the battery charging current requirements.

[0051] The PFC current control loop can be a digital loop. The current control loop includes a forward chain and a feedback chain. The forward chain includes a current control loop controller. This controller can be a digital controller.

[0052] This controller can be for example a 1-pole, 1-z controller (1p / 1z controller) or a PI (proportional-integral) controller. PI controllers (numerical expression of HPi(z) = Kp + Ki / z) are a common implementation of current control loop controllers because these controllers require a limited number of computational steps and provide high gain at low frequencies.More precisely, as the line impedance increases, the cutoff frequency of the open-loop transfer function decreases, the phase margin (which corresponds to the deviation between the phase of the open-loop transfer function and -180° at the frequency corresponding to the cancellation of the gain of this same open-loop transfer function) of the current loop decreases, becomes lower than the stability threshold (often considered to be 40 to 45°, stability being more generally determined by the combination of gain and phase margins) and the system begins to oscillate.

[0053] This is why other types of controllers such as 1 zero / 1 pole (denoted "1z / 1p"), also called phase-delay controllers, are usable. These controllers are characterized by a lower gain at the fundamental frequency. A high line impedance has the effect of shifting the open-loop transfer function to a lower gain, which results in too little gain at the fundamental. As a result, the ability of the current control loop to follow the sinusoidal setpoint signal is reduced and a permanent error appears.

[0054] The profile (in particular the phase) of the current reference signal ISET over time is determined based on the detection of the phase of the supply voltage by a phase-locked loop (PLL). The amplitude of the current reference signal is that which allows the generation of power at the DC link to meet the battery charging needs. To meet the battery's needs, the PFC must therefore draw sufficient power from the power supply network, which results in a corresponding amplitude of the current lo drawn at the PFC input.

[0055] The harmonic distortion rate, which determines the rate at which the drawn current contains harmonics of the fundamental frequency, is also considered for the generation of the current itself. In particular, when the value of the equivalent inductance (sum of the power inductance and the line inductance) increases, this can increase the harmonic distortion rate. The control loop can then become unstable to the point that the regulation no longer works. The more the line inductances increase, the more the phase margin drops and the more the control loop becomes unstable.

[0056] The current control loop controller must be robust against high line impedances. However, the variations in equivalent line inductance from one network outlet to another are so significant that it is not possible to calibrate a PI controller that will guarantee the stability requirements for all inductance values ​​(especially in terms of gain margin, phase margin).

[0057] Furthermore, the controller aims to control high frequency switching in such a way as to ensure correct tracking of the sinusoidal waveform of the input voltage, which results in a displacement factor as close as possible to the setpoint signal (factor 1 if the PFC 110 does not manage reactive power control).

[0058] An unintentional mismatch between the current drawn at the PFC 110 input and the network voltage can have various effects such as:

[0059] - Produce unexpected reactive power, i.e. power losses that must be dissipated;

[0060] - disrupt the power supply network because the expected power factor is not respected.

[0061] - increase the apparent power required from the supply network (and possibly oversize the supply network).

[0062] Figure 5 shows the open-loop transfer function of a power factor correction (PFC) device with different types of controller according to exemplary embodiments.

[0063] The curves in subfigures 5A-5B show the delay (phase shift) and attenuation (gain) between the ISET current setpoint signal and the measured IMES current for different types of controller, with and without line inductance, depending on the current frequency.

[0064] More precisely, the Bode diagrams of subfigures 5A-5B, curves 51, 52 represent the open-loop transfer function (gain in subfigure 5A and phase in subfigure 5B) of a PFC 110 controlled by a PI controller, with a line inductance of 2200pH (curve 52) and without line inductance (curve 51). Similarly, curves 53, 54 represent the open-loop transfer function (gain and phase) of a PFC 110 controlled by a 1z / 1p controller, with a line inductance of 2200pH (curve 54) and without line inductance (curve 53).

[0065] For both types of controller, the phase of the open-loop transfer function does not depend on the line impedance: for a 1z / 1p controller, the phase has a local minimum while the phase tends to decrease to -180 with a PI controller. As a result, the 1z / 1p controller can be made robust to any inductance. This is also applicable for a PI controller. However, the 1z1p controller has a local minimum and is therefore robust to any line inductance. Indeed, if the line inductance increases, it decreases the gain. The gain crossing through 0 will be obtained for lower frequencies: thus the phase margin will be obtained for lower frequencies. Since the phase increases again from the phase minimum when moving towards lower and lower frequencies, the phase margin would only be greater, and therefore the system is more stable.

[0066] A disadvantage of a 1z / 1p controller compared to a PI controller is a significantly lower open-loop transfer function gain at the fundamental frequency (power supply network frequency, typically 50 or 60 Hz): almost 20 dB, as shown in the curves in subfigure 5A. A low gain at the fundamental frequency leads to a tracking error between the current drawn at the input of the PFC 110 and the ISET setpoint signal.

[0067] On the other hand, a 1z / 1p controller cannot be tuned to provide sufficient gain at the maximum expected line impedance value, as this would lead to an open-loop transfer function with no gain margin (which is the difference between the open-loop transfer function gain in dB and OdB, at the frequency corresponding to a phase of this same transfer function equal to -180°) when the line impedance is low or non-existent. A 1z / 1p controller is less powerful than a PI controller and generates a lower fundamental gain.

[0068] The solution proposed here thus consists of a real-time adaptation of the gain of the open-loop transfer function of the current control loop. This regulation is implemented by means of a dedicated device, also called an "open-loop transfer function gain adaptation device", or "gain adapter" or, in simplified terms, "adapter". This gain adaptation is carried out so as to compensate for the effects on the open-loop transfer function gain of the equivalent inductance of the power supply line. The gain adapter can be implemented by means of an integrating controller.

[0069] This regulation can be implemented by means of a computer program implemented by a 360 control device of the PFC. The gain adapter can thus be a digital device, forming part of the 360 ​​control device of the PFC.

[0070] The gain adapter makes it possible in particular to compensate for the variations produced on the open loop transfer function by the equivalent inductance due to the power inductances and line inductances.

[0071] The gain adapter is designed to minimize the tracking error of the current control loop (e.g., to minimize the effective value of the tracking error determined from the error signal) and determines a gain factor F to be applied to the error signal E of the current control loop. The gain adapter performs an adaptation (or modulation) of the gain of the open-loop transfer function of the current control loop by applying a gain factor determined on the basis of the error signal E. This adaptation (or modulation) can be applied on the basis of the effective value, normalized with respect to the current itself, of the error signal E.

[0072] Advantageously, the gain adapter is designed to ensure the adaptation of the regulation of the normalized effective value of the error signal E around a calibration set point which is not fixed at 0% but close to zero (for example 1%) in order to prevent the strategy from overcompensating the line inductance effect and reducing the gain margin.

[0073] Figure 6 schematically represents a power factor correction device integrating a gain adapter according to an exemplary embodiment.

[0074] The power factor correction device 600 comprises a current control loop. The control loop comprises a forward chain generating a regulated current lo corresponding to the current drawn by the electrical charger and a feedback chain acquiring this current (for example, by acquisition in block 630) IMES from the regulated current lo.

[0075] The direct chain of the control loop receives as input a sinusoidal setpoint current ISET in phase with a sinusoidal supply voltage and generates an error signal E by comparing the sinusoidal setpoint current with the measured current supplied by the feedback chain.

[0076] The forward chain comprising a controller 620 of the regulation loop, a gain adapter 610 configured to generate a gain factor F and an amplifier 615 to apply the gain factor F in the forward chain to the error signal and generated a weighted error signal, provided as an input to the controller 620 (PI or 1z1P) of the current regulation loop. The controller 620 applies a regulation function to the weighted error signal.

[0077] The gain factor is generated based on the error signal.

[0078] According to Figure 6, the direct chain of the control loop further comprising an integrator block 640 corresponding to the modeling (for example, according to a small signal model) according to the Laplace formalism (using the parameter s) of the inductive effect of the equivalent inductance LEQ.

[0079] Figure 7 schematically represents a gain adaptation (or adapter) device 700 for a power factor correction device according to an exemplary embodiment of the gain adapter 610 of Figure 6. The gain adapter receives the error signal and generates the gain factor F based on the error signal.

[0080] The gain factor F is generated from the error signal E obtained by comparing (for example, by calculating the difference) the sinusoidal setpoint current ISET with the measured current IMES, this measured current being provided (see Figure 6) by the feedback chain of the control loop: E = ISET - IMES.

[0081] The gain factor F can be determined based on a tracking error rate obtained from the error signal.

[0082] A tracking error R(E) is calculated based on the error signal E.

[0083] This tracking error R(E) can be calculated as the effective value (RMS value, "root mean square" in English terminology) of the error signal: R(E)=RMS(E). This effective value can be calculated over a period of the supply voltage (for example, using the zero crossing information provided by the PLL). This effective value is usually calculated as the square root of the average of the squared error signal, the average being calculated over a period of the supply voltage. This average can be calculated by integration of the error signal or by a discrete sum of sampled values.

[0084] The tracking error R(E) can also be calculated as the average, over a period of the supply voltage, of the error signal. This variant allows reducing the processor load by eliminating the square root operation.

[0085] The error rate T(E) is determined based on this tracking error R(E). The determination may include normalization (block 710), weighting (block 720) and / or integration (block 730) including a clipping function (saturation block 731). The error rate may thus be a normalized error rate, then weighted and / or integrated.

[0086] The normalization (block 710) of the tracking error can be performed on the basis of the setpoint sinusoidal current or the measured current. The normalization can be performed by calculating a normalization coefficient N and dividing the tracking error R(E) by the normalization coefficient to determine a relative tracking error R(E) / N. The normalization coefficient N can be the effective value (or respectively the average value) R(ISET) of the setpoint sinusoidal current or respectively that R(IMES) of the measured current.

[0087] Optionally, a setpoint error rate RC (either zero or non-zero and between 0 and 1) can also be chosen for the relative effective value R(E) / N: this setpoint error rate RC is used to define an optimum to be achieved. The normalized error rate can thus be determined at TN(E) =RC-R(E) / N.

[0088] The dynamics of the adaptation can be adjusted using a weighting coefficient K applied (block 720) to the normalized error rate so as to determine a weighted error rate:

[0089] TP(E)= K*TN(E).

[0090] The value of K can be calibrated to strike a balance between the need for rapid adaptation (the system must be stabilized quickly enough to prevent any oscillation from deactivating the PFC 110) and learning slow enough that it is uncorrelated with the current control dynamics.

[0091] The integration is performed by an integral controller 730 including a clipping function 731, and applied to the weighted error rate TP(E) so as to obtain an integrated error rate TI(E) at the output. The integral controller has a discrete transfer function of the form K / z, the block 720 applying the adjustment coefficient K. The function of the saturation block 731 is to limit the value of the integrated error rate TI(E).

[0092] The gain factor F is then calculated based on the error rate (normalized, weighted or integrated). The gain factor is calculated based on the error rate (normalized, weighted or integrated) so that the gain factor F (F= 1- TI(E) in the example of Figure 7, the reference value being equal to 1) is an increasing function of the tracking error.

[0093] Indeed, the more the normalized error rate R(E) / R(ISET) increases, the more RC-R(E) / R(ISET) decreases (towards negative values). The more negative this error is, the more the integration drifts towards negative values. And the more the value of F=1 -TI(E) increases.

[0094] In case a 1z / 1p controller is used in the control loop and calibrated to provide a minimum phase margin satisfying the stability requirements.

[0095] The F gain regulation strategy aims to improve the gain of the open-loop transfer function, i.e. to compensate for the potential gain drop associated with the line inductances, which, if not compensated, would result in poorer tracking of the sinusoidal current setpoint, i.e. a poorer harmonic distortion rate.

[0096] The PFC is thus robust to any line impedance value.

[0097] The on-board charger thus configured is resistant to a wide range of parasitic inductances, i.e. to many configurations of the electrical supply network, including in the case of power supply by static inverters. Figure 8 illustrates an exemplary embodiment of a method for activating the calculation of the gain factor.

[0098] The initial value of the gain factor may be reset to 1 (step 880) after a precharge period (step 810) during which the gain matching device is not activated.

[0099] Then, according to embodiments, we wait until the synchronization of the phase-locked loop (PLL) is obtained (step 815) so that it is possible to detect the zero crossings of the supply voltage. Then a first value of the measured current IMES can be obtained (step 820).

[0100] Furthermore, the gain matching device is disabled (step 830) when no load is in progress, so that the gain factor is frozen (step 870) at its current value.

[0101] Furthermore, the gain matching device may be disabled (so that the gain factor is in this case also frozen at its current value, step 870) when the effective value (or the average value) of the setpoint current ISET is low (for example if R(ISET) is below a threshold, according to the test of step 840) for several reasons:

[0102] - The calculation of the effective value is less precise when the ISET setpoint current is low (less than a threshold);

[0103] - For topologies including diodes characterized by a discontinuous conduction mode, the open-loop gain in DCM mode (discontinuous conduction mode) is significantly different from that in CCM mode (continuous conduction mode), which would require a dedicated controller for each mode.

[0104] The gain factor calculation is performed in step 850, when the gain adaptation device is not deactivated following the cumulative tests of steps 830 and 840. The gain factor calculation is performed for example according to what is described in Figure 7.

[0105] After activation, when implementing the gain factor calculation method in step 850, the measurement of the error E and the calculation of the cumulative sums to obtain R(E) and the normalization coefficient N are performed at the switching period. The calculation of the gain factor F, on the basis of these cumulative sums over a period, is performed at each zero crossing of the supply voltage, in order to save the load of the central unit of the gain adaptation device which performs the calculation of the gain factor to be applied.

[0106] Then, following the calculation of the gain factor and a zero crossing of the supply voltage (step 860), step 820 of measuring the IMES current is carried out again (according to what has been described in this document, for example with reference to FIG. 6). Following step 820, steps 830, 840 are repeated again according to the logic described above.

[0107] Figures 9 and 10 show the behavior of the charger with a 1z1p controller for a value of 2.27mH as line inductance, when gain matching is enabled (Figure 10) or disabled (Figure 9).

[0108] With this high line inductance, the error signal E oscillates between -0.6 A and +0.6 A (cosine wave at the network frequency, since sin(wt+cp)-sin(wt) = 2*cos(wt+ cp / 2)*sin((p / 2) « (p* cos(wt+ (p / 2)) in the absence of gain adaptation (sub-figure 9A).

[0109] When the gain factor is kept constant, equal to 1 (sub-figure 9D): the effective value of the error signal E converges towards 0.4A (sub-figure 9B), i.e. a relative effective value RMS(E) / RMS(ISET) of almost 3% (sub-figure 9C) of the effective value RMS(ISET) of the sinusoidal reference current ISET.

[0110] When F gain adaptation is enabled:

[0111] - the amplitude of the error signal E is reduced to + / -0.16A: it is therefore divided by a factor of 4 (sub-figure 10A);

[0112] - the effective RMS(E) value of the error signal E is maintained below 0.1 A (sub-figure 10B)

[0113] - the relative effective value RMS(E) / RMS(ISET) is limited to approximately 0.7% (setpoint error rate chosen for this simulation) (sub-figure 10C); ; and

[0114] - the gain factor F converges to 4, within about 1 second (sub-figure 10D).

[0115] In describing the various signal processing functions and methods, although the steps are described sequentially, those skilled in the art will understand that certain steps may be omitted, combined, performed in a different order and / or in parallel.

[0116] One or more or all of the functions, steps and methods described in this document may be implemented by software (e.g., via software on one or more processors, for execution on a general purpose or special purpose computer) and / or by hardware (e.g., one or more electronic circuits, programmable or not, specific or not and / or any other hardware component).

[0117] The devices described in this document include means for implementing the functions described for these devices. These means may include software means (e.g., instructions of one or more components of a program) and / or hardware means (e.g., data memory(ies), processor(s), communication bus, hardware interface(s), electronic circuits, etc.).

[0118] These means may for example comprise one or more electronic circuits configured to perform one or more or all of the functions described for these devices. These means may for example comprise at least one processor and at least one memory comprising program instructions configured to, when executed by the processor, cause the device concerned to perform one or more or all of the functions described for the device concerned.

[0119] The present description thus relates to a software or computer program, capable of being executed by a host device (such as for example a power factor correction device or gain adaptation arrangement), by means of one or more data processors, this software / program comprising instructions to cause the execution by this host device of all or part of the steps of methods and / or functions described in this document for this host device. These instructions are intended to be stored in a memory of the host device, loaded and then executed by one or more processors of this host device so as to cause the execution by this host device of the method.

[0120] This software / program may be coded using any programming language, and may be in the form of source code, object code, or code intermediate between source code and object code, such as in a partially compiled form, or in any other desirable form.

Claims

CLAIMS 1. Power factor correction device (600) for an on-board electric charger of a motor vehicle battery, the power factor correction device comprising a current regulation loop; the regulation loop comprising a direct chain generating a regulated current (I0) corresponding to the current drawn by the electric charger and a feedback chain generating a current measured from the regulated current; the regulation loop being configured to receive as input a sinusoidal setpoint current (ISET) in phase with a sinusoidal supply voltage and to generate an error signal by comparing the sinusoidal setpoint current with the measured current supplied by the feedback chain;the direct chain comprising a controller (620) of the regulation loop, a gain adapter (610) configured to generate a gain factor, an amplifier (615) configured to apply the gain factor to the input signal of the controller, the gain factor being generated on the basis of the error signal.; 2. The power factor correction device of claim 1, wherein the gain adapter (610) is configured to generate the gain factor based on a tracking error of the control loop determined from the error signal.

3. A power factor correction device according to claim 2, wherein the tracking error is determined as the effective value of the error signal.

4. A power factor correction device according to claim 2, wherein the tracking error is determined as the average, over a period of the supply voltage, of the error signal.

5. A power factor correction device according to any preceding claim, wherein the gain adapter is configured to generate the gain factor based on a weighting coefficient (K) of the gain of the open-loop transfer function.

6. A power factor correction device according to any preceding claim, wherein the gain adapter (610) is configured to determine an error rate from the error signal and to normalize the error rate between 0 and 1 based on the setpoint sinusoidal current or the measured current so as to generate a normalized error rate.

7. A power factor correction device according to any preceding claim, wherein the gain adapter is configured to compare the normalized error rate with a setpoint error rate.

8. Electric battery charger intended to be installed in a motor vehicle, the electric charger comprising a power factor correction device according to any one of the preceding claims.

9. Method (600) for correcting power factor for an on-board electric charger of a motor vehicle battery, the method comprising - reception of a sinusoidal setpoint current (ISET) in phase with a sinusoidal supply voltage; - generation of a regulated current (I0) corresponding to the current drawn by the electric charger; - generation of a measured current (IMES) from the regulated current; - generation of an error signal by comparing the set sinusoidal current with the measured current; generation of the regulated current comprising: - generation of a gain factor based on the error signal; - an application of the gain factor to the error signal to generate a weighted error signal; - an application to the weighted error signal of a regulation function to generate the regulated current (I0).

10. Computer program comprising instructions adapted to, when the instructions are executed by at least one processor, cause the execution of the steps of the method according to claim 9.

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