Transistor and method for manufacturing same

Abstract

A columnar device region (131) in which a channel layer (102) and a barrier layer (103) are laminated is formed in an element formation region (130) of a selective growth mask (121) by crystal growth (selective growth using the selective growth mask (121)) of a nitride semiconductor in the c-axis direction. For example, a nitride semiconductor constituting the channel layer (102) is crystal-grown in the +c-axis direction to form the channel layer (102), and then a nitride semiconductor constituting the barrier layer (103) is crystal-grown on the channel layer (102) in the +c-axis direction to form the barrier layer (103).

Description

Transistor and manufacturing method thereof

[0001] The present invention relates to a transistor made of a nitride semiconductor and a method for manufacturing the same.

[0002] Transistors such as heterojunction field effect transistors (HFETs) and high electron mobility transistors (HEMTs) are turned on and off by changing the carrier density in the channel layer using an electric field generated by a gate voltage.

[0003] When this transistor is made of a nitride semiconductor, for example, a heterostructure such as AlGaN / GaN is used. In this heterostructure, a two-dimensional electron gas (2DEG) formed by electrons gathering at the interface between AlGaN and GaN to compensate for the difference in polarization magnitude between the two is often used as the channel.

[0004] In a typical HEMT using the above-mentioned nitride semiconductor, a gate electrode is formed on a barrier layer made of AlGaN with a thickness of several to several tens of nanometers, and the concentration of 2DEG formed near the interface between the barrier layer made of AlGaN and the channel layer made of GaN is controlled.

[0005] In this type of transistor, suppressing gate leakage is important regardless of its application. Gate leakage degrades the ON / OFF ratio and limits the frequency band and breakdown voltage. Since the magnitude of gate leakage is greatly affected by the layered structure under the gate electrode, a structure is used in which an insulating film is formed on top of the AlGaN / GaN HEMT structure to suppress gate leakage.

[0006] In transistors such as HEMTs, the gate electrode is formed very thin in the device operating region. It is very difficult to make contact with a thin gate electrode, whose gate length can be several nanometers to several tens of nanometers. To make contact with the measurement probe, it is possible to provide a large area on the gate electrode.

[0007] However, a large area of ​​the gate electrode may affect the high frequency characteristics of the device. Therefore, it is required to locate the large area of ​​the contact portion away from the device (outside the device operating region). In order to locate the contact portion away from the device, the gate electrode is extended outside the device operating region.

[0008] In transistors such as the HEMT described above, the device operating region is generally separated from other regions by processing the device operating region into a columnar shape (including a mesa shape). The sidewalls (side surfaces) of the device region thus formed expose the AlGaN / GaN heterojunction interface where the 2DEG is formed. In such a structure, if the gate electrode is extended beyond the device operating region, the extended portion of the gate electrode comes into contact with the device sidewall, which can cause gate leakage (see Non-Patent Document 1 and Non-Patent Document 2).

[0009] Sandeep R. Bahl et al., "Mesa-sidewall gate leakage in InAlAs / InGaAs Heterostructure field-effect transistors", IEEE Transactions Electron Devices, vol. 39, no. 9, pp. 2037-2043, 1992.HR Mojaver and P. Valizadeh, "Reverse Gate-Current of AlGaN / GaN HFETs: Evidence of Leakage at "Mesa Sidewalls", IEEE Transactions Electron Devices, vol. 63, no. 4, pp. 1444-1449, 2016.

[0010] To suppress the above-mentioned leakage, it is conceivable to fabricate a structure in which the 2DEG and the gate electrode metal do not come into contact. This includes covering the sidewalls of the device region with a protective film, or achieving device isolation through ion implantation in the first place, thereby fabricating a structure in which the device region does not have sidewalls. However, when covering the sidewalls of the device region with a protective film, it is difficult to selectively cover only the sidewalls. In particular, the protective film remains on the periphery of the device operating region, making it difficult to apply gate voltage. Even when ion implantation is used, issues remain regarding the damage to the crystal caused by the implantation and the stability of the ions at high temperatures. As such, conventional techniques for suppressing gate leakage have had problems that limit device performance.

[0011] The present invention has been made to solve the above problems, and has as its object to suppress gate leakage without limiting device performance.

[0012] The method for manufacturing a transistor according to the present invention includes a first step of forming a selective growth mask on a substrate, the selective growth mask having an opening in an element formation region; a second step of forming a columnar device region in the element formation region of the selective growth mask, in which a channel layer and a barrier layer are stacked, by crystal growth of a nitride semiconductor in the c-axis direction; and a third step of removing the selective growth mask and then depositing a gate electrode material from above the device region by a deposition method with high vertical anisotropy, to form a gate electrode and an extension extending beyond the device region in a planar view.

[0013] The transistor according to the present invention comprises a columnar device region in which a channel layer and a barrier layer made of a nitride semiconductor crystal grown in the c-axis direction on a substrate are stacked, a gate electrode formed on the device region, and an extension portion continuous with the gate electrode and extending laterally of the device region, and the channel layer and the barrier layer have an inclined structure inclined from the c-plane on the outer periphery of the device region.

[0014] As described above, according to the present invention, a columnar device region in which a channel layer and a barrier layer are stacked is formed in an element formation region by crystal growth of a nitride semiconductor in the c-axis direction through selective growth using a selective growth mask formed on a substrate, thereby making it possible to suppress gate leakage without restricting device performance.

[0015] FIG. 1A is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a first embodiment of the present invention. FIG. 1B is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a first embodiment of the present invention. FIG. 1C is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a first embodiment of the present invention. FIG. 1D is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a first embodiment of the present invention. FIG. 1E is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a first embodiment of the present invention. FIG. 1F is a plan view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a first embodiment of the present invention. FIG. 2A is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a second embodiment of the present invention. FIG. 2B is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a second embodiment of the present invention. FIG. 2C is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a second embodiment of the present invention. FIG. 2D is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a second embodiment of the present invention. FIG. 2E is a cross-sectional view showing a state of a transistor in an intermediate step for explaining a method for manufacturing a transistor according to a second embodiment of the present invention. FIG. 2F is a plan view showing the state of a transistor in the middle of a process for explaining a method for manufacturing a transistor according to the second embodiment of the present invention.

[0016] A method for manufacturing a transistor according to an embodiment of the present invention will now be described.

[0017] First Embodiment First, a method for manufacturing a transistor according to a first embodiment of the present invention will be described with reference to Figures 1A to 1F. Figures 1A to 1E show cross sections parallel to the gate width direction.

[0018] 1A, GaN is grown in the c-axis direction on a substrate 101 to form a buffer layer 111. For example, the buffer layer 111 can be formed by epitaxially growing GaN on the substrate 101 using a known nitride semiconductor epitaxial growth technique such as metalorganic chemical vapor deposition or molecular beam epitaxy. The same applies to the formation of nitride semiconductor layers, which will be described later.

[0019] For example, the buffer layer 111 can be formed by growing GaN crystals (in the +c-axis direction) on the substrate 101 with group III polarity (Ga polarity). In this case, the surface of the buffer layer 111 is the (0001) plane. The substrate 101 can be, for example, a sapphire substrate whose main surface is the C-plane. The substrate 101 can also be a crystalline substrate such as SiC, Si, or GaN.

[0020] The buffer layer 111 can have a single-layer or multi-layer structure of a nitride semiconductor such as GaN. The buffer layer 111 can be configured with an appropriate material depending on the substrate 101 and the desired performance. For example, when a Si substrate is used, a nucleation layer made of AlN is required in the initial stage of growth. The buffer layer 111 may also be a high-resistance layer, in which case the buffer layer 111 may contain GaN doped with carbon, iron, or the like.

[0021] 1B, a selective growth mask 121 having an opening corresponding to the device formation region 130 is formed on the buffer layer 111 (substrate 101) (first step). Because the selective growth mask 121 is exposed to high temperatures exceeding 1000°C during selective growth, it is desirable to make the selective growth mask 121 from a highly heat-resistant material, such as SiO2. The selective growth mask 121 can be formed in a frame shape with a rectangular opening corresponding to the device formation region 130 in plan view.

[0022] Next, the nitride semiconductor is crystal-grown in the c-axis direction (selectively grown using the selective growth mask 121), thereby forming a columnar device region 131 in which the channel layer 102 and the barrier layer 103 are stacked in the device formation region 130 of the selective growth mask 121, as shown in Fig. 1C (second step). In the first embodiment, the second step includes a step of forming the channel layer 102 by crystal-growing the nitride semiconductor that constitutes the channel layer 102 in the +c-axis direction, and a step of subsequently forming the barrier layer 103 on the channel layer 102 by crystal-growing the nitride semiconductor that constitutes the barrier layer 103 in the +c-axis direction.

[0023] For example, a group III polarity channel layer 102 made of GaN can be formed by growing GaN crystals with group III polarity (in the +c-axis direction) on the buffer layer 111 (substrate 101) on which the selective growth mask 121 has been formed. In this case, the surface of the channel layer 102 is the (0001) plane. After the channel layer 102 is formed in this manner, a group III polarity barrier layer 103 is formed in contact with the channel layer 102 by subsequently growing AlGaN crystals with group III polarity (in the +c-axis direction).

[0024] The thickness and composition of the barrier layer 103 can be set appropriately within the range that allows operation as a HEMT. For example, the barrier layer 103 made of AlGaN can have an Al composition of 0.25 and a thickness of approximately 20 nm. The surface of the barrier layer 103 also has a (0001) plane. The barrier layer 103 can also be made of AlN.

[0025] As is well known, a two-dimensional electron gas (2DEG) 104 is formed in the channel layer 102 near the interface between the channel layer 102 and the barrier layer 103. For example, near the interface between an AlGaN layer and a GaN layer, electrons gather at the interface to form a 2DEG that compensates for the difference in polarization between these layers. The concentration of the 2DEG thus formed depends on the difference in polarization between the AlGaN and GaN, and it is known that the polarization depends on the plane orientation of the GaN. The polarization is maximized in the direction parallel to the c-axis and zero in the direction perpendicular to the c-axis. For example, there have been reports of utilizing this characteristic to fabricate a normally-off HEMT by stacking an AlGaN layer and a GaN layer in the m-plane or a-plane direction (References 1 and 2).

[0026] Here, we focus on selective growth. In crystal growth using the selective growth mask 121 described above, a portion of the growth surface on which the nitride semiconductor is to be grown is covered with a mask, and crystal growth occurs only in the mask-free region. Because crystal growth does not proceed on the mask, the source gas is not consumed, and the source gas that reaches the mask moves to the mask-free region (element formation region 130) and is consumed in crystal growth at the end of the mask.

[0027] Therefore, in the region where crystal growth proceeds without the mask (the element formation region 130), the growth rate is faster in the region near the mask. Due to this difference in growth rate, a gradient structure 102a is formed in the channel layer 102 in the region near the mask, and similarly, a gradient structure 103a is formed in the barrier layer 103, as shown in FIG.

[0028] The interface between the channel layer 102 having the inclined structure 102a and the barrier layer 103 having the inclined structure 103a is inclined significantly from the c-plane (+c-plane), suppressing the formation of the 2DEG 104. The peak heights of the inclined structures 102a and 103a as viewed from the flat surfaces of the respective layers can be set to some extent by the shape of the selective growth mask 121 and the growth time.

[0029] The larger the planar area of ​​the selective growth mask 121 surrounding the device region 131 and the longer the growth time, the more raw material reaches the top of the selective growth mask 121, moves to the device region 131, and is used for crystal growth, resulting in a higher peak slope. If the peaks of the inclined structures 102a and 103a become high, this may cause disconnection of the gate electrode, which will be described later. Therefore, it is desirable to keep the peaks of the inclined structures 102a and 103a to a maximum of several hundred nanometers so that they are lower than the metal layer formed as the gate electrode.

[0030] The inclined structures 102a and 103a are inclined significantly from the c-plane (group III plane) near the peak, and the inclination becomes gentler and approaches the c-plane (+c-plane) as they move away from the peak. Therefore, the inclined structures 102a and 103a, each having a peak of several hundred nanometers, can sufficiently achieve the intended effect of preventing the 2DEG 104 from being exposed on the side surface of the device region 131.

[0031] Furthermore, the inclined structures 102a and 103a, each having a peak height of about several hundred nanometers, continue to have a gentle slope up to a distance of about several micrometers from the end of the selective growth mask 121. The size in the direction parallel to the gate electrode (the direction of the gate width) depends on the gate width design, but is generally about several tens of micrometers, which is larger than the width of the inclined structures 102a and 103a. The effect of the step of the inclined structures 102a and 103a can be suppressed by, for example, increasing the dimension of the gate electrode by several micrometers.

[0032] Next, the selective growth mask 121 is removed to expose the side surfaces of the columnar device region 131, as shown in FIG. 1D. The selective growth mask 121 can be removed by a known method for each material. For example, the selective growth mask 121 made of SiO can be dissolved and removed using diluted hydrofluoric acid.

[0033] Next, a gate electrode material is deposited on the device region 131 (barrier layer 103) by a deposition method with high vertical anisotropy, such as sputtering or vacuum evaporation, to form the gate electrode 105 and an extension 106 extending from the device region 131 in a plan view, as shown in FIG. 1E (step 3). The extension 106 includes, for example, a gate wiring, a contact portion of a measurement probe, etc. For example, the gate electrode 105 and the extension 106 can be formed by a lift-off method using a lift-off mask.

[0034] For example, the gate electrode 105 (extension 106) can have a Ni / Au laminated structure. Furthermore, a gate insulating layer can be formed before forming the gate electrode 105 (extension 106). The gate insulating layer can be made of, for example, a nitride or oxide such as SiN or Al2O3. Forming a gate insulating layer using these materials can be achieved using known techniques such as p-CVD or atomic layer deposition (ALD).

[0035] Furthermore, a source electrode 107 that makes an ohmic contact with the channel layer 102 and a drain electrode 108 that makes an ohmic contact with the channel layer 102 are formed ( FIG. 1F ). For example, the source electrode 107 and the drain electrode 108 can be formed by a known formation method. For example, an ohmic contact can be obtained by forming a stacked structure of Ti / Al / Ni / Au and annealing it. For example, the source electrode 107 and the drain electrode 108 can be formed before forming the gate electrode 105 (extension 106). Furthermore, the gate electrode 104 is formed between the source electrode 107 and the drain electrode 108. As a result of these steps, for example, a high electron mobility transistor is formed.

[0036] Here, the gate electrode 105 is formed so as to straddle the device region 131 in which the channel layer 102 and the barrier layer 103 are stacked. Due to this structure, the gate electrode 105 is in contact with the sidewall of the device region 131. However, in the embodiment, by forming the sloped structures 102a and 103a, the formation of the 2DEG 104 near the side surface of the device region 131 is suppressed. As a result, the leakage current generated between the gate electrode 105 and the 2DEG 104 on the side surface of the device region 131 can be reduced.

[0037] Second Embodiment A method for manufacturing a transistor according to a second embodiment of the present invention will now be described with reference to Figures 2A to 2F, which show cross sections parallel to the gate width direction.

[0038] 2A , GaN is grown in the c-axis direction on a substrate 201 to form a buffer layer 211. For example, the buffer layer 211 can be formed by epitaxially growing GaN on the substrate 201 using a known nitride semiconductor epitaxial growth technique such as metalorganic chemical vapor deposition or molecular beam epitaxy. The same applies to the formation of nitride semiconductor layers, which will be described later.

[0039] For example, the buffer layer 211 can be formed by growing GaN crystals (in the −c-axis direction) with group V polarity (N polarity) on the substrate 201. In this case, the surface of the buffer layer 211 is the (000-1) plane. For example, the substrate 201 is a sapphire substrate whose main surface is the C-plane, and the surface of the substrate 201 is subjected to high-temperature heat treatment in a source gas atmosphere such as ammonia, thereby forming a nitride layer on the substrate surface. On the nitride layer formed by nitriding, a nitride semiconductor can be grown in the −c-axis direction with group V polarity (N polarity).

[0040] The buffer layer 211 can have a single-layer or multi-layer structure of a nitride semiconductor such as GaN. The buffer layer 211 can be configured with an appropriate material depending on the substrate 201 and the desired performance. The buffer layer 211 may be a high-resistance layer, in which case the buffer layer 211 may contain GaN doped with carbon, iron, or the like.

[0041] Furthermore, when a GaN single crystal substrate or an AlN single crystal substrate with group V polarity (N polarity) is used as the substrate 201, it is possible to grow a nitride semiconductor crystal in the −c-axis direction with group V polarity (N polarity) without using the nitride layer described above. Furthermore, when a GaN single crystal substrate or an AlN single crystal substrate with group V polarity is used as the substrate 201, it is not necessary to form the buffer layer 211.

[0042] 2B, a selective growth mask 221 having an opening corresponding to the device formation region 230 is formed on the buffer layer 211 (substrate 201) (first step). Because the selective growth mask 221 is exposed to high temperatures exceeding 1000°C during selective growth, it is desirable to make the selective growth mask 221 from a highly heat-resistant material, such as SiO2. The selective growth mask 221 can be formed in a frame shape with a rectangular opening corresponding to the device formation region 230 in plan view.

[0043] Next, by performing crystal growth of the nitride semiconductor in the c-axis direction (selective growth using the selective growth mask 221), a columnar device region 231 is formed in the device formation region 230 of the selective growth mask 221, in which the barrier layer 202 and the channel layer 203 are stacked, as shown in Figure 2C (second step). In the second embodiment, the second step includes a step of forming the barrier layer 202 by performing crystal growth of the nitride semiconductor that constitutes the barrier layer 202 in the -c-axis direction, and a step of forming the channel layer 203 by performing crystal growth of the nitride semiconductor that constitutes the channel layer 203 on the barrier layer 202 in the -c-axis direction after this step. In this way, the barrier layer 202 formed below the channel layer 203 when viewed from the substrate 201 can be referred to as a back barrier.

[0044] For example, a barrier layer 202 made of AlGaN with group V polarity can be formed by growing GaN crystals with group V polarity (in the −c-axis direction) on the buffer layer 211 (substrate 201) on which a selective growth mask 221 has been formed. In this case, the surface of the barrier layer 202 is the (000-1) plane. After the barrier layer 202 is formed in this manner, a channel layer 203 with group V polarity is formed in contact with the barrier layer 202 by subsequently growing GaN crystals with group V polarity (in the −c-axis direction).

[0045] The thickness and composition of the barrier layer 202 can be set appropriately within the range in which it operates as a HEMT. For example, a barrier layer 202 made of AlGaN can have an Al composition of 0.25 and a thickness of approximately 20 nm. The barrier layer 202 can also be made of AlGaN in which the Al composition varies in the thickness direction, with the Al composition decreasing closer to the substrate 201. The surface of the barrier layer 202 also has a (000-1) plane. The barrier layer 202 can also be made of AlN.

[0046] As is well known, a two-dimensional electron gas (2DEG) 204 is formed in the channel layer 203 near the interface between the barrier layer 202 and the channel layer 203. Here, in the crystal growth using the selective growth mask 221 described above, as explained in the first embodiment, the source gas is not consumed because crystal growth does not proceed on the mask, and the source gas that reaches the mask moves to a region where there is no mask (the element formation region 230) and is consumed in the crystal growth at the end of the mask.

[0047] As a result, the growth rate is faster in the region near the mask in the mask-free region (device formation region 230) where crystal growth progresses. Due to this difference in growth rate, a gradient structure 202a is formed in the barrier layer 202 in the region near the mask, and similarly, a gradient structure 203a is formed in the channel layer 203, as shown in FIG.

[0048] The interface between the barrier layer 202 having the inclined structure 202a and the channel layer 203 having the inclined structure 203a is inclined significantly from the c-plane (−c-plane), suppressing the formation of the 2DEG 204. The peak heights of the inclined structures 202a and 203a as viewed from the flat surfaces of the respective layers can be set to some extent by the shape of the selective growth mask 221 and the growth time.

[0049] The larger the planar area of ​​the selective growth mask 221 surrounding the device region 231 and the longer the growth time, the more raw material reaches the top of the selective growth mask 221, moves to the device region 231, and is used for crystal growth, resulting in a higher peak slope. If the peaks of the sloped structures 202a and 203a become high, this may cause disconnection of the gate electrode, which will be described later. Therefore, it is desirable to keep the peaks of the sloped structures 202a and 203a to a maximum of several hundred nanometers so that they are lower than the metal layer formed as the gate electrode.

[0050] The inclined structures 202a and 203a are inclined significantly from the c-plane (group V plane) near the peak, and the inclination becomes gentler and approaches the c-plane (-c-plane) as they move away from the peak. Therefore, the inclined structures 202a and 203a, each having a peak of several hundred nanometers, can sufficiently achieve the intended effect of preventing the 2DEG 204 from being exposed on the side surface of the device region 231.

[0051] The inclined structures 202a and 203a, each having a peak height of about several hundred nanometers, continue to have a gentle slope up to a distance of about several micrometers from the end of the selective growth mask 221. The size in the direction parallel to the gate electrode (the direction of the gate width) depends on the gate width design, but is generally about several tens of micrometers, which is larger than the width of the inclined structures 202a and 203a. The influence of the step of the inclined structures 202a and 203a can be suppressed by, for example, increasing the dimension of the gate electrode by several micrometers.

[0052] Next, the selective growth mask 221 is removed to expose the side surfaces of the columnar device region 231, as shown in FIG. 2D. The selective growth mask 221 can be removed by a known method for each material. For example, the selective growth mask 221 made of SiO can be dissolved and removed using diluted hydrofluoric acid.

[0053] Next, a gate electrode material is deposited from above the device region 231 (channel layer 203) by a deposition method with high vertical anisotropy, such as sputtering or vacuum evaporation, to form a gate electrode 205 and an extension 206 extending from the device region 231 in a plan view, as shown in FIG. 2E (step 3). The extension 206 includes, for example, a gate wiring, a contact portion of a measurement probe, etc. For example, the gate electrode 205 and the extension 206 can be formed by a lift-off method using a lift-off mask.

[0054] For example, the gate electrode 205 (extension 206) may have a Ni / Au laminated structure. Furthermore, a gate insulating layer may be formed before forming the gate electrode 205 (extension 206). The gate insulating layer may be made of, for example, a nitride or oxide such as SiN or Al2O3. Forming a gate insulating layer using these materials can be achieved using known techniques such as p-CVD or atomic layer deposition (ALD).

[0055] Furthermore, a source electrode 207 that makes an ohmic contact with the barrier layer 202 and a drain electrode 208 that makes an ohmic contact with the barrier layer 202 are formed ( FIG. 2F ). For example, the source electrode 207 and the drain electrode 208 can be formed by a known formation method. For example, an ohmic contact can be obtained by forming a stacked structure of Ti / Al / Ni / Au and annealing it. For example, the source electrode 207 and the drain electrode 208 can be formed before forming the gate electrode 205 (extension 206). Furthermore, the gate electrode 204 is formed between the source electrode 207 and the drain electrode 208. As a result of these steps, for example, a high electron mobility transistor is formed.

[0056] Here, the gate electrode 205 is formed so as to straddle the device region 231 in which the barrier layer 202 and the channel layer 203 are stacked. Due to this structure, the gate electrode 205 is in contact with the sidewall of the device region 231. However, in the embodiment, by forming the sloped structures 202a and 203a, the formation of the 2DEG 204 near the side surface of the device region 231 is suppressed. As a result, the leakage current generated between the gate electrode 205 and the 2DEG 204 on the side surface of the device region 231 can be reduced.

[0057] As described above, according to the present invention, a columnar device region in which a channel layer and a barrier layer are stacked is formed in an element formation region by crystal growth of a nitride semiconductor in the c-axis direction through selective growth using a selective growth mask formed on a substrate, thereby making it possible to suppress gate leakage without restricting device performance.

[0058] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0059] [References] [References 1] T. Fujiwara et al., "Enhancement-Mode m-plane AlGaN / GaN Heterojunction Field-Effect Transistors", Applied Physics Express, vol. 2, 011001, 2009. [References 2] M. Kuroda et al., "Nonpolar (11-20) plane AlGaN / GaN heterojunction field effect transistors on (1-102) plane sapphire", Journal of Applied Physics, vol. 102, 093703, 2007.

[0060] 101...substrate, 102...channel layer, 102a...graded structure, 103...barrier layer, 103a...graded structure, 104...two-dimensional electron gas (2DEG), 105...gate electrode, 106...extension, 107...source electrode, 108...drain electrode, 111...buffer layer, 130...element formation region, 131...device region.

Claims

1. A first step of forming a selective growth mask having an element formation region opened on a substrate; a second step of forming a columnar device region in which a channel layer and a barrier layer are stacked in the element formation region of the selective growth mask by crystal-growing a nitride semiconductor in the c-axis direction; and a third step of forming a gate electrode and an extension portion extending from the device region in a plan view by depositing a gate electrode material from above the device region by a deposition method having high perpendicular anisotropy after removing the selective growth mask. A method for manufacturing a transistor comprising the steps.

2. In the method for manufacturing a transistor according to claim 1, the second step includes a step of crystal-growing a nitride semiconductor constituting the channel layer in the +c-axis direction to form the channel layer, and then crystal-growing a nitride semiconductor constituting the barrier layer in the +c-axis direction on the channel layer to form the barrier layer, or a step of crystal-growing a nitride semiconductor constituting the barrier layer in the -c-axis direction to form the barrier layer, and then crystal-growing a nitride semiconductor constituting the channel layer in the -c-axis direction on the barrier layer to form the channel layer. A method for manufacturing a transistor comprising the steps.

3. A transistor comprising a columnar device region in which a channel layer and a barrier layer made of a nitride semiconductor crystal-grown in the c-axis direction are stacked, a gate electrode formed on the device region, and an extension portion extending continuously to the side of the device region from the gate electrode, wherein the channel layer and the barrier layer have an inclined structure inclined from the c-plane at an outer peripheral portion of the device region.

4. In the transistor according to claim 3, the device region is composed of the channel layer made of a nitride semiconductor crystal-grown in the +c-axis direction and the barrier layer made of a nitride semiconductor crystal-grown in the +c-axis direction formed on the channel layer when viewed from the side of the substrate, or the barrier layer made of a nitride semiconductor crystal-grown in the -c-axis direction and the channel layer made of a nitride semiconductor crystal-grown in the -c-axis direction formed on the barrier layer when viewed from the side of the substrate. A transistor.

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