SPAD-based image sensor and operating method thereof

Abstract

The present disclosure provides an SPAD-based image sensor and an operating method thereof, the sensor comprising: a pixel array including a plurality of pixel pairs which are connected to a plurality of first and second row lines extending in a row direction and a plurality of common column line groups extending in a column direction and are arranged in a matrix form; and a peripheral circuit for, when first and second pixels of a pixel pair disposed in a selected row in the pixel array sequentially transmit first and second pixel values through the common column line groups to which the first and second pixels are commonly connected, receiving and storing the transmitted first and second pixel values, and while storing the first and second pixel values, outputting first and second pixel values applied and stored in a previously selected pixel pair, wherein the SPAD-based image sensor can maintain operation performance while reducing the number of column lines.

Description

SPAD-based image sensor and its operating method

[0001] The present disclosure relates to an image sensor and an operating method thereof, and more particularly, to a SPAD-based image sensor and an operating method thereof.

[0002] An image sensor is a device that detects incident light and converts it into an electrical signal to create an image. It may include various sensing elements capable of detecting light. Conventional optical sensing elements have mainly used CMOS elements or CCD elements. However, due to the increasing demand for ultra-sensitive optical sensors, single photon avalanche diodes (SPADs), which can directly detect a single photon, the smallest unit of light, have been developed recently, and research on image sensors using SPAD elements is actively underway.

[0003] The SPAD element can detect light with ultra-high sensitivity by applying a reverse bias voltage higher than the breakdown voltage, so that it can be triggered by even a single photon and cause an avalanche breakdown phenomenon. When the SPAD element detects a photon and an avalanche breakdown phenomenon occurs, a large current temporarily flows, outputting a signal in the form of an impulse waveform. After outputting the impulse signal, the SPAD element quenches and returns to its previous state. Accordingly, a SPAD-based image sensor detects the intensity of incident light by counting the number of impulse signals output from the SPAD element provided in each of a plurality of pixels, thereby acquiring an image.

[0004] In a SPAD-based image sensor, each pixel is equipped with a SPAD element and a counter for counting the number of impulse signals generated from the SPAD element, where the count range and bit number of the counter are determined in advance depending on the intended use of the image sensor.

[0005] The pixel values ​​counted by the counter are temporarily stored in a memory module included within the chip implemented as an image sensor via a readout circuit, and then output to the outside of the chip. At this time, the pixel values ​​counted by the counter of each of the multiple pixels are transmitted to the memory module via the connected column line when the corresponding pixel is selected and activated by the word line.

[0006] Since the pixel value counted by the counter consists of multiple bits, in SPAD-based image sensors, multiple column lines corresponding to the number of bits in the counter are connected to each pixel. In other words, the multiple bit values ​​that constitute the pixel value in the counter of each pixel are transferred in parallel to the memory module through a column line group consisting of multiple column lines. Here, the bit values ​​of the pixel value are transferred in parallel to satisfy the operating speed required for the image sensor.

[0007] However, recently, as the performance required for image sensors has greatly increased, not only has the number of pixels equipped with them increased significantly, but also the number of bits of pixel value that each pixel can identify has increased. Even if one column in the pixel array of the image sensor increases, the column lines must increase in units of column line groups according to the number of bits of the pixel value, so a very large number of column lines must be increased. In addition, as the number of bits of the pixel value increases, the number of column lines included in each column line group also increases. The increase in the number of bits of the pixel value not only indicates an increase in the number of columns in the image sensor, but also causes an increase in the area occupied by the column line group in each pixel, which poses a problem of restricting the size of the SPAD or other components.

[0008] In particular, as the number of column lines included in a column line group increases, the parasitic cache resistance component increases, requiring an increase in the lead time for reading pixel values ​​or the size of the transistors driving the column lines. Consequently, there are limitations, such as a decrease in the operating speed of the image sensor or an increase in the size of each pixel.

[0009] The purpose of the present disclosure is to provide a SPAD-based image sensor and an operating method thereof that can maintain operating performance while reducing the number of column lines.

[0010] The purpose of the present disclosure is to provide a SPAD-based image sensor and an operating method thereof that can suppress an increase in operating speed by allowing adjacent pixels to share and use column lines, and allowing a two-stage memory composed of three memories to store pixel values ​​transmitted from pixels sharing column lines and simultaneously output them to the outside.

[0011] The SPAD-based image sensor of the present disclosure and its operating method allow adjacent pixels to share and use column lines, and a two-stage memory composed of three memories can store pixel values ​​transmitted from pixels sharing column lines and simultaneously output them to the outside, thereby reducing the number of column lines while maintaining operating performance.

[0012] Figure 1 shows a schematic configuration of a SPAD-based image sensor.

[0013] Figure 2 shows a schematic configuration of the pixels of Figure 1.

[0014] FIG. 3 illustrates a schematic configuration of a SPAD-based image sensor according to one embodiment.

[0015] Fig. 4 shows a configuration for outputting pixel values ​​in the peripheral circuit of Fig. 3.

[0016] Figure 5 also shows a timing diagram for explaining the operation of the peripheral circuit of Figure 4.

[0017] FIG. 6 illustrates an operation method of a SPAD-based image sensor according to one embodiment.

[0018] According to one embodiment of the present disclosure, a base image sensor includes a pixel array including a plurality of pixel pairs arranged in a matrix form and connected to a plurality of first and second row lines extending in a row direction and a plurality of common column line groups extending in a column direction; and a peripheral circuit for sequentially transmitting first and second pixel values ​​through the common column line groups to which first and second pixels of a pixel pair arranged in a selected row in the pixel array are commonly connected, receiving and storing the transmitted first and second pixel values, and outputting the first and second pixel values ​​applied and stored from a previously selected pixel pair while storing the first and second pixel values.

[0019] The first pixel is connected to a first low line and a common column line group, and when the first low line is activated, the acquired first pixel value can be transmitted to the peripheral circuit through the common column line group, and the second pixel is connected to a second low line and the common column line group, and when the second low line is activated, the acquired second pixel value can be transmitted to the peripheral circuit through the common column line group.

[0020] The peripheral circuit may include a first stage memory that sequentially receives and stores first and second pixel values ​​acquired by first and second pixels of a pair of pixels in a selected row; and a second stage memory that receives and stores the first and second pixel values ​​stored in the first stage memory together, and outputs the first and second pixel values ​​previously received and stored in the first stage memory while the first stage memory stores the first and second pixel values ​​for another pair of pixels.

[0021] The first stage memory may include a first memory that receives and stores a first pixel value transmitted through the common column line group from a first pixel of a pair of pixels in a selected row; and a second memory that receives and stores a second pixel value transmitted through the common column line group alternately with the first pixel from a second pixel of a pair of pixels in a selected row.

[0022] The peripheral circuit may include a pixel bit transfer circuit that transfers each bit value of the pixel value acquired by a pixel connected to the activated row line among the pixel pair to the first stage memory when one of the first and second row lines is activated.

[0023] Each of the first and second pixels may include a SPAD that detects photons and generates a pulse signal; and a counter that counts the number of pulse signals to obtain a pixel value.

[0024] The above common column line group can be composed of a number of column lines according to the number of bits of the first and second pixel values.

[0025] The above peripheral circuit sequentially activates the first and second row lines according to a command authorized by an external control module, and can precharge a plurality of column lines of the common column line group before each of the first and second row lines is activated.

[0026] The peripheral circuit can detect the voltage level of each of a plurality of column lines changed according to each bit value of the first and second pixel values ​​obtained from the first and second pixels, and determine and store the first and second pixel values.

[0027] In another embodiment of the present disclosure, an operating method of an image sensor comprises a pixel array including a plurality of pixel pairs arranged in a matrix form, the pixel array including first and second pixels connected to first and second row lines extending in a row direction, respectively, and commonly connected to a common column line group extending in a column direction, and peripheral circuitry, the operating method comprising: a step of obtaining first and second pixel values ​​from the first and second pixels of the plurality of pixel pairs, respectively; a step of sequentially receiving and storing the first and second pixel values ​​obtained by the first and second pixels through the common column line group from a pixel pair arranged in a selected row by the peripheral circuitry; and a step of outputting previously stored first and second pixel values ​​while the first and second pixel values ​​are being stored.

[0028] Hereinafter, specific embodiments according to the present disclosure will be described with reference to the drawings. The following detailed description is provided to facilitate a comprehensive understanding of the methods, devices, and / or systems described herein. However, these are merely examples and the present invention is not limited thereto.

[0029] In describing embodiments of the present disclosure, if a detailed description of a known technology related to the present invention is judged to unnecessarily obscure the gist of the embodiments, the detailed description will be omitted. In addition, the terms described below are terms defined in consideration of their functions in the present invention, and this may vary depending on the intention or custom of the user or operator. Therefore, the definitions should be made based on the contents throughout this specification. The terminology used in the detailed description is only for the purpose of describing one embodiment and should never be limited. Unless clearly used otherwise, the singular form includes the plural form. In this description, expressions such as “comprises” or “comprising” are intended to indicate certain features, numbers, steps, operations, elements, parts or combinations thereof, and should not be construed to exclude the presence or possibility of one or more other features, numbers, steps, operations, elements, parts or combinations thereof other than those described. Additionally, terms such as “...unit,” “...device,” “module,” and “block” described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware, software, or a combination of hardware and software.

[0030] Fig. 1 shows a schematic configuration of a SPAD-based image sensor, and Fig. 2 shows a schematic configuration of a pixel of Fig. 1.

[0031] Referring to FIG. 1, a SPAD-based image sensor (10) includes a pixel array (11) and peripheral circuits (12). The pixel array (11) includes a plurality of pixels (px) arranged in an array, and may include pixels (px) arranged in an array of L × M, for example. FIG. 2 shows an example of a configuration for one pixel (30) among the plurality of pixels (px) of the pixel array (11) of FIG. 1.

[0032] The pixel (30) illustrated in FIG. 2 can be configured to include a SPAD (31), a shear module (32), and a counter (33).

[0033] SPAD(31) has a reverse bias voltage (V) greater than the breakdown voltage SPAD ) (e.g., 23 V) can be applied and implemented as an avalanche diode operating in Geiger Mode. The SPAD (31) can generate an impulse signal by reacting to photons with high sensitivity and causing an avalanche breakdown phenomenon.

[0034] The shear module (32) controls the operation of the SPAD (31) and can convert the impulse signal output from the driven SPAD (31) into a pulse signal and transmit it to the counter (33).

[0035] For example, the shear module (32) can prevent the SPAD (31) from being driven by applying a certain level of driving control voltage to the anode terminal of the SPAD (31) so that the voltage difference between the two terminals of the SPAD (31) becomes lower than the breakdown voltage, but the method of controlling the driving of the SPAD (31) can be changed in various ways.

[0036] In addition, the front module (32) can convert the pulse signal into a pulse signal with a lower voltage level than the impulse signal and transmit it to the counter (33). As described above, in the SPAD (31), a reverse bias voltage (V) of high voltage (e.g., 23 V) SPAD ) is applied and a photon is incident, causing an avalanche breakdown phenomenon, a high-voltage impulse signal may be generated. To prevent such an impulse signal from being transmitted to the counter (33) as is, the front module (32) can level-shift the applied high-voltage impulse signal to a low-voltage level (e.g., 3 V) and convert it into a pulse signal to transmit it to the counter (33).

[0037] Additionally, the shear module (32) can cause the SPAD (31) in which the avalanche breakdown phenomenon has occurred to be quickly quenched and returned to its previous state, and can reset the counter (33) to initialize the pixel value counted by the counter (33).

[0038] The front module (32) can operate according to various signals applied from the peripheral circuit (12) to drive the SPAD (31) and reset the counter (33). The front module (32) can drive the SPAD (31) for a set exposure time to generate a number of impulse signals according to the number of photons incident during the exposure time. After the exposure time, when the pixel value counted in the counter (33) is transmitted to the peripheral circuit (12), the counter (33) can be reset.

[0039] The front module (32) may include a plurality of switches implemented with transistors, a plurality of logic elements, and a level shift circuit; however, the components and circuit configurations constituting the front module (32) may be designed in various ways, and thus a detailed description thereof is omitted here.

[0040] The counter (33) counts the number of pulse signals applied from the front module (32) and obtains a pixel value that measures the amount of light (or intensity of light) incident on the pixel (30). At this time, the counter (33) can be implemented as an N-bit counter, and the number of bits (N) of the counter (33) can be preset depending on the intended use of the image sensor. When the counter (33) is implemented as an N-bit counter, the counter (33) includes N bit cells for storing N-bit pixel values. Each of the N bit cells stores a corresponding bit value from the counted N-bit pixel value.

[0041] The peripheral circuit (12) generates and outputs various control signals for operating the front module (32) in response to commands applied from the outside (here, the control module (20) as an example). The peripheral circuit (12) can cause the front module (32) to drive the SPAD (31) and control the counter by applying the control signal to the front module (32) during the exposure time. However, for the convenience of explanation, the line provided to transmit the control signal from the peripheral circuit (12) to the front module (32) is not separately indicated here.

[0042] Meanwhile, the peripheral circuit (12) receives and stores the pixel values ​​counted from the counter (33) of each of the plurality of pixels (xp) of the pixel array (11) after the exposure time. To this end, the peripheral circuit (12) selects a pixel from among the plurality of pixels (px) in the pixel array (11) to which the pixel value is to be applied. Then, the pixel value stored in the counter of the selected pixel (px) is received and stored. The peripheral circuit (12) can transmit the stored pixel value to the outside of the image sensor (10) (here, the control module (20)).

[0043] Here, the peripheral circuit (12) can selectively activate a plurality of row lines (RL) to select a pixel (px) to output a pixel value from the pixel array (11). That is, a plurality of pixels (px) arranged in the pixel array (11) can be selected in row units. Then, the pixel values ​​stored in the N bit cells of the counter (33) in each of the selected pixels (px) connected to the activated row lines (RL) are transmitted to the peripheral circuit (12) through the corresponding column line group (CLG).

[0044] In Fig. 1, for convenience, a column line group (CLG) is illustrated as a single line, but each of the plurality of column line groups (CLG) illustrated in Fig. 1 is composed of N column lines (Column Lines) (CL) each connected to N bit cells of a counter (33). That is, each bit of the pixel value counted in the counter (33) is transmitted to the peripheral circuit (12) in bit units through a connected column line among the N column lines (CL) of the column line group (CLG).

[0045] The peripheral circuit (12) can receive and store pixel values ​​from each of a plurality of pixels (px) connected to a selected low line (RL) through a plurality of column line groups (CLG). Then, the stored pixel values ​​can be output to the outside (here, the control module (20)).

[0046] The control module (20) controls the operation of the SPAD (31) included in each pixel (px) by applying a command to the peripheral circuit (12) so that the peripheral circuit (12) generates various control signals for controlling the front module (32) of each of the plurality of pixels (px) of the pixel array (11). For example, the control module (20) can enable a plurality of pixels (px) of the pixel array (11) to detect light simultaneously, or to detect pixels in units of rows or columns.

[0047] In addition, the control module (20) can receive pixel values ​​for each pixel stored in the peripheral circuit (12) and configure an image. The control module (20) can not only operate as a control circuit that controls the pixel array (11), but can also operate as an image processing circuit.

[0048] The pixel array (11) and peripheral circuit (12) of the image sensor (10) can be implemented within a single chip, and the control module (20) can also be implemented within the same chip, but the control module (20) is typically implemented separately outside the chip. In addition, the SPAD (31), the front-end module (32), and the counter (33) can be implemented on the same layer in the chip, but in some cases, the SPAD (31), the front-end module (32), and the counter (33) can be implemented on different layers.

[0049] However, in the image sensor (10) of Fig. 1, since the pixel values ​​are transmitted to the peripheral circuit (12) through the column line group (CLG) in which the counters (33) of each of the plurality of pixels (px) in the pixel array (11) correspond one to one, a very large number of column lines (CL) must be formed. As described above, when L × M pixels are arranged in the pixel array (11) and the counter (33) is an N-bit counter, M column line groups (CLG), i.e., M × N column lines (CL), must be formed in the pixel array (11).

[0050] FIG. 3 illustrates a schematic configuration of a SPAD-based image sensor according to one embodiment.

[0051] In Fig. 3, the image sensor (40) includes a pixel array (41) and a peripheral circuit (42), and a plurality of pixels (px) are arranged in a matrix form in the pixel array (41). However, in the pixel array (11) of Fig. 1, a plurality of arranged pixels (px) are connected to one column line group (CLG) for each individual column, whereas in Fig. 3, two adjacent pixel columns share and use one column line group (CCLG) in common. Here, the column line group (CCLG) commonly used by two pixel columns can be referred to as a common column line group. In other words, among a plurality of pixel columns, pixel column pairs arranged adjacent to each other use one common column line group (CCLG). In each row of the pixel column pair, two pixels (px) commonly connected to the common column line group (CCLG) form a pixel pair (pxA, pxB), which are conveniently distinguished here as a first pixel (pxA) and a second pixel (pxB).

[0052] However, in a structure where a pixel column pair is commonly connected to a common column line group (CCLG), if the first and second pixels (pxA, pxB) are selected at the same time and the pixel values ​​are transmitted to the common column line group (CCLG), the pixel values ​​transmitted from the first and second pixels (pxA, pxB) in the common column line group (CCLG) will collide. Accordingly, in the pixel array (41) of FIG. 3, two low lines (RL1, RL2) are formed for each pixel row so that the first and second pixels (pxA, pxB) of the pixel pair are not selected at the same time. Among the two low lines (RL1, RL2), the first low line (RL1) may be connected to the first pixel (pxA), while the second low line (RL2) may be connected to the second pixel (pxB).

[0053] The first and second pixels (pxB) can be configured identically to the pixels (px) illustrated in FIG. 2 in terms of the shape, except that they are connected to the first and second row lines (RL1, RL2), respectively, and are commonly connected to a common column line group (CCLG).

[0054] In the pixel array (41) of Fig. 3, the first and second pixels (pxA, pxB) are connected to different low lines (RL1, RL2), so the number of low lines (RL) is doubled compared to the pixel array (11) of Fig. 1. However, since two pixel columns share and use a common column line group (CCLG), the pixel array (41) of Fig. 3 can reduce the number of common column line groups (CCLG) to half compared to the pixel array (11) of Fig. 1.

[0055] Even though two low lines (RL1, RL2) are formed for each pixel row, since the common column line group (CCLG) is composed of N column lines (CL) as described above, if the number of common column line groups (CCLG) is reduced by half, the size of the area required to form a line from the perspective of each pixel (pxA, pxB) can be greatly reduced. For example, if the counter provided in the pixels (pxA, pxB) is a 10-bit counter, each pixel (px) in the pixel array (11) of FIG. 1 requires an area in which one low line (RL) and 10 column lines (CL) are formed. On the other hand, in the pixel array (41) of FIG. 3, each pixel (pxA, pxB) requires an area in which two low lines (RL) and five column lines (CL) are formed. Therefore, the size of the area can be reduced by approximately four line sizes. If the size of the area where a line must be formed in each pixel (pxA, pxB) is reduced, the size of the image sensor (10) can be reduced. Alternatively, the size of the image sensor (10) can be maintained, but the size of the SPAD (31) included in each pixel (pxA, pxB) can be increased, thereby increasing the area where light is incident, thereby further improving the light sensitivity of the SPAD (31).

[0056] In addition, since the total number of column lines (CL) in the pixel array (41) is greatly reduced, the parasitic capacitance component of the column lines (CL) is reduced. Accordingly, pixel values ​​can be effectively transmitted even with low driving capability.

[0057] However, as described above, in the image sensor (40) of FIG. 3, since the first and second pixels (pxA, pxB) are connected together through a common column line group (CCLG), the pixel values ​​cannot be transmitted to the peripheral circuit (42) at the same time. That is, the first and second pixels (pxA, pxB) must be sequentially selected and the counted pixel values ​​transmitted. This causes a problem in that the read-out time required for the pixel values ​​of the pixel array (41) to be transmitted to the peripheral circuit (42) and output to the outside increases.

[0058] Fig. 4 shows a configuration for outputting pixel values ​​in the peripheral circuit of Fig. 3, and Fig. 5 shows a timing diagram for explaining the operation of the peripheral circuit of Fig. 4.

[0059] In order to suppress the increase in the above-mentioned readout time, the peripheral circuit (42) in the image sensor (40) according to one embodiment has a memory having a two-stage structure, as illustrated in FIG. 4. The first stage memory (50) receives and stores a pixel value from a counter (33) of a selected pixel among a plurality of pixels (pxA, pxB) of the pixel array (41). In addition, the second stage memory (60) receives and stores the pixel value stored in the first stage memory (50), and outputs the stored pixel value to the outside.

[0060] Meanwhile, the first stage memory (50) may be equipped with first and second memories (51, 52). The first and second memories (51, 52) store pixel values ​​of pixel pairs (pxA, pxB) that are alternately transmitted through a common column line group (CCLG), but the stored pixel values ​​may be simultaneously transmitted to the second stage memory (60).

[0061] When the first pixel (pxA) is selected from among the pixel pairs (pxA, pxB), the first memory (51) of the first stage memory (50) receives and stores the pixel value transmitted from the counter (33) of the selected first pixel (pxA) through the common column line group (CCLG). In addition, when the second pixel (pxB) is selected, the second memory (52) receives and stores the pixel value transmitted from the counter (33) of the selected second pixel (pxB) through the common column line group (CCLG). When the pixel values ​​of the pixel pairs (pxA, pxB) are all stored in the first and second memories (51, 52) of the first stage memory (50), the pixel values ​​stored in each can be simultaneously transmitted to the second stage memory (60). Accordingly, the second stage memory (60) can receive and store the pixel values ​​transmitted from the first and second memories (51, 52) of the first stage memory (50) together.

[0062] And while the first and second memories (51, 52) of the first stage memory (50) alternately receive and store pixel values ​​of another pixel pair (pxA, pxB), the second stage memory (60) can output the pixel values ​​that were previously received and stored. That is, while the first and second memories (51, 52) of the first stage memory (50) receive and store pixel values, the second stage memory (60) outputs the stored pixel values ​​to the outside, thereby reducing the readout time for outputting the pixel values ​​of the pixel pair (pxA, pxB) to the outside. That is, the readout time can be suppressed so as not to increase as much as possible due to the pixel pair (pxA, pxB) sharing and using a common column line group (CCLG).

[0063] Hereinafter, with reference to FIG. 4, an example of a configuration of a pixel bit transfer circuit (80) for transferring pixel values ​​of a pixel pair (pxA, pxB) to a first stage memory (50) and its operation will be described.

[0064] In Fig. 4, for convenience of explanation, only the transmission circuit along the path in which 1 bit of the N-bit pixel value in the pixel pair (pxA, pxB) is transmitted to the first stage memory (50) through one column line (CL) is briefly illustrated. However, the common column line group (CCLG) is composed of N column lines (CL) to transmit the N-bit pixel value. Therefore, in reality, N pixel bit transmission circuits having the same configuration can be implemented for each pixel column pair. In addition, since a plurality of pixel column pairs (here, M / 2, for example) are arranged in the pixel array (41), for example, N × M / 2 pixel bit transmission circuits can be implemented in the peripheral circuit (42), but the present invention is not limited thereto.

[0065] As illustrated in FIG. 4, each of the first and second pixels (pxA, pxB) includes first and second transistors (MN1, MN2) connected in series between a column line (CL) of a commonly used common column line group (CCLG) and a ground voltage (Vss).

[0066] Here, as described above, only the path through which 1 bit of the N-bit pixel value is transmitted is described, so only one first and second bit cell transistor (MN1, MN2) for each of the first and second pixels (pxA, pxB) are illustrated, but the first and second pixels (pxA, pxB) each include N first and second bit cell transistors (MN1, MN2) corresponding to N column lines (CL) included in a common column line group (CCLG). The first and second bit cell transistors (MN1, MN2) can be implemented as NMOS transistors. Here, the gate of the first bit cell transistor (MN1) is connected to the first or second row line (RL1, RL2) for selecting one pixel from the pixel pair (pxA, pxB). And, a 1-bit value of a pixel value is applied to the gate of the second bit cell transistor (MN2) from a corresponding one of the N bit cells provided in the counter (33) of the corresponding pixel (pxA, pxB). Since the gate of the second bit cell transistor (MN2) is connected to the bit cell of the counter (33), the second bit cell transistor (MN2) is turned on or off depending on the bit value stored in the bit cell.

[0067] Meanwhile, the precharge transistor (MP) is connected between the power supply voltage (Vdd) and the column line (CL), and receives a precharge signal (pre) to its gate. The precharge transistor (MP) is implemented as a PMOS transistor, and when the precharge signal (pre) is activated, the column line (CL) can be precharged to the power supply voltage (Vdd) level. Here, the precharge transistor (MP) may be commonly connected to N column lines (CL) of a common column line group (CCLG) rather than to one column line (CL).

[0068] In Fig. 4, the precharge transistor (MP) and the first and second bit cell transistors (MN1, MN2) are configured to be included in each pixel (px) in a conventional image sensor. However, whereas in the conventional image sensor, one low line (RL) is formed for each pixel row, in Fig. 3, two low lines (RL1, RL2) are formed for each pixel row, and thus the first bit cell transistor (MN1) is connected to either the first low line (RL1) or the second low line (RL2) depending on the included pixel (pxA, pxB).

[0069] The pixel bit transmission circuit (80) may include two NAND gates (ND1, ND2) connected in parallel between the column line (CL) and the first and second memories (51, 52), respectively.

[0070] Among the two NAND gates (ND1, ND2), the first NAND gate (ND1) has a first input terminal connected to a column line (CL), and a second input terminal receives a first pixel selection signal (SA) that is activated when the first pixel (pxA) among the pixel pairs (pxA, pxB) is selected. Accordingly, the first NAND gate (ND1) transmits the result of a NAND product of the bit value of the pixel value transmitted through the column line (CL) and the first pixel selection signal (SA) to the first memory (51).

[0071] And the second NAND gate (ND1) has a first input terminal connected to a column line (CL), and a second pixel selection signal (SB) that is activated when a second pixel (pxB) is selected is applied to the second input terminal. The second NAND gate (ND2) transmits the result of a NAND product of the bit value of the pixel value transmitted through the column line (CL) and the second pixel selection signal (SB) to the second memory (52).

[0072] Here, the precharge signal (pre) and the first and second pixel selection signals (SA, SB) can be generated in the peripheral circuit (42) according to an externally applied command, and in some cases, can be applied directly from the outside in the form of a command.

[0073] The pixel bit transmission circuit (80) is connected between the column line (CL) and the first input terminal of the first and second NAND gates (ND1, ND2), and may further include a latch circuit including two inverters (IV1, IV2).

[0074] Referring to FIG. 5, the operation of the configuration of FIG. 4 will be described. First, a precharge signal (pre) is activated to turn on a precharge transistor (MP). When the precharge transistor (MP) is turned on, N column lines (CL) of each of a plurality of common column line groups (CCLG) are precharged to the power supply voltage (Vdd) level. Then, a pixel row (here, the Kth pixel row, as an example) to which a pixel value is to be applied is determined, and a first row line (RL1) of the determined pixel row is activated.

[0075] When the first low line (RL1) is activated, the first bit cell transistor (MN1) of the first pixel (pxA) in the pixel pair (pxA, pxB) is turned on, and the second bit cell transistor (MN2) is turned on or off according to the bit value stored in the bit cell of the counter (33). The second bit cell transistor (MN2) can be turned on when the bit value stored in the corresponding bit cell is 1, and in this case, since both the first and second bit cell transistors (MN1, MN2) are turned on, the voltage level of the column line (CL) precharged to the power supply voltage (Vdd) level drops. The voltage level of the column line (CL) gradually drops due to the capacitance component, etc. The latch circuit can not only allow the voltage level of the column line (CL) to drop more quickly when it falls below a certain level, but also assist in pulling down to the ground voltage level.

[0076] When the voltage level of the column line (CL) drops, the latch circuit inverts it and applies a high-level signal to the first input terminals of the first and second NAND gates (ND1, ND2). Then, among the first and second NAND gates (ND1, ND2), the first NAND gate (ND1) is activated to a high level and performs a logical AND operation on the output of the latch circuit with the first pixel selection signal (SA) applied thereto, thereby transmitting a low-level bit value to the first memory (51) of the first stage memory (50). Then, the second NAND gate (ND2) performs a logical AND operation on the output of the latch circuit with the second pixel selection signal (SB) deactivated to a low level, thereby transmitting a high-level bit value to the second memory (52).

[0077] The first memory (51) is activated and applied with the first light signal (wrA), and stores the bit value of the pixel value applied from the first NAND gate (ND1). As described above, in Fig. 4, only the path through which a 1-bit bit value is transmitted is illustrated, but in reality, all N bit values ​​constituting the pixel value are transmitted, and therefore, the pixel value obtained from the first pixel (pxA) is stored in the first memory (51).

[0078] At this time, the second light signal (wrB) applied to the second memory (52) is maintained in an inactive state. Therefore, the bit value applied from the second NAND gate (ND2) is not stored in the second memory (52).

[0079] When the pixel value obtained from the first pixel (pxA) is stored in the first memory (51), the precharge signal (pre) is activated again to precharge the column line (CL) to the power supply voltage (Vdd) level. Thereafter, the second row line (RL2) of the same pixel row (here, the Kth pixel row, for example) is activated to turn on the first bit cell transistor (MN1) of the second pixel (pxB). The second bit cell transistor (MN2) of the second pixel (pxB) is turned on or off according to the bit value stored in the bit cell of the counter (33), and if the bit value stored in the corresponding bit cell is 0, the second bit cell transistor (MN2) is maintained in the off state. When the second bit cell transistor (MN2) is maintained in the off state, the voltage level of the column line (CL) is maintained at the power supply voltage (Vdd) level. At this time, the latch circuit can assist in stably maintaining the voltage level of the column line (CL) at the power supply voltage (Vdd) level.

[0080] The latch circuit inverts the power supply voltage (Vdd) level of the column line (CL) and applies a low-level signal to the first input terminals of the first and second NAND gates (ND1, ND2). Then, among the first and second NAND gates (ND1, ND2), the second NAND gate (ND2) is activated to a high level and performs a logical AND operation on the output of the latch circuit with the second pixel selection signal (SB) applied thereto, thereby transmitting the high-level bit value to the second memory (52). Then, the first NAND gate (ND1) performs a logical AND operation on the output of the latch circuit with the first pixel selection signal (SA) deactivated to a low level, thereby transmitting the high-level bit value to the first memory (51).

[0081] The second memory (52) is activated and applied with the second light signal (wrB), and stores the pixel value applied from the second NAND gate (ND2). On the other hand, the first memory (51) does not store the bit value applied from the first NAND gate (ND1) due to the first light signal (wrA) being deactivated.

[0082] That is, the first and second memories (51, 52) alternately receive and store pixel values. Then, the first and second memories (51, 52) are activated simultaneously after the first and second light signals (wrA, wrB) are deactivated, and transfer the two stored pixel values ​​to the second stage memory (60) according to the first and second read signals (rdA, rdB) that are applied. The second stage memory (60) stores the pixel values ​​transmitted from the first and second memories (51, 52) in response to the third light (wrC) that is activated together with the first and second read signals (rdA, rdB). As in the above example, when a 10-bit pixel value is transmitted from each pixel (pxA, pxB), the first and second memories (51, 52) alternately receive and store a 10-bit pixel value, respectively. And two pixel values, each having 10 bits, can be simultaneously transferred to the second stage memory (60). That is, a 20-bit pixel value can be transferred to the second stage memory (60).

[0083] As described above, the pixel bit transfer circuit (80) detects a change in the voltage level of the precharged column line (CL) and stores the pixel values ​​of the pixel pair (pxA, pxB) in the first and second memories (51, 52) of the first stage memory (50), so the time required for the pixel values ​​to be stored in each of the first and second memories (51, 52) is very long. However, the process of transferring and storing the two stored pixel values ​​in the first and second memories (51, 52) to the second stage memory (60) is processed digitally, so it can be performed very quickly.

[0084] When the pixel values ​​for the pixel rows stored in the first and second memories (51, 52) are transferred to and stored in the second stage memory (60), the column line (CL) is precharged to the power voltage (Vdd) level according to the re-activated precharge signal (pre), the next pixel row (here, the K+1th pixel row) is selected, and the first row line (RL1) of the selected pixel row is activated, thereby storing the pixel values ​​acquired by the pixel pair (pxA, pxB) arranged in the next pixel row in the first and second memories (51, 52) of the first stage memory.

[0085] And while pixel values ​​are stored in the first and second memories (51, 52) of the first stage memory (50), the second stage memory (60) outputs the stored pixel values ​​to the outside in response to the activated third read signal (rdC).

[0086] However, in most cases, it is difficult to directly transmit data output from the memory to the outside of the device (e.g., control module (20)) due to the limitations of the driving capability of the memory. Therefore, the peripheral circuit (42) of the image sensor (40) may further include a sense amplifier (70), and the sense amplifier (70) can receive and amplify the pixel value output from the second stage memory (60) and output the pixel value to the outside with a strong driving force. In this process, although it takes time for the sense amplifier (70) to amplify the pixel value, since the time taken for the pixel bit transmission circuit (80) to store the pixel value of the pixel pair (pxA, pxB) in the first and second memories is longer, no additional time is actually generated to output the pixel value to the outside.

[0087] Accordingly, as illustrated in FIG. 3, since pixel columns arranged adjacent to each other are paired in pairs of two and share a common column line group (CCLG), even if the time for storing the pixel values ​​of the pixel pair (pxA, pxB) in the first stage memory (50) is doubled, the previously stored pixel values ​​are output externally during the time the pixel values ​​are stored in the first stage memory (50), so that no separate time is required for outputting the pixel values, thereby suppressing an increase in the operating time of the image sensor (40).

[0088] In the illustrated embodiment, each component may have different functions and capabilities beyond those described below, and may include additional components beyond those described below. Furthermore, in one embodiment, each component may be implemented using one or more physically separate devices, or may be implemented by one or more processors, or a combination of one or more processors and software, and, unlike the illustrated example, may not be clearly distinguished in their specific operations.

[0089] FIG. 6 illustrates an operation method of a SPAD-based image sensor according to one embodiment.

[0090] Referring to FIG. 6, in the SPAD-based image sensor of the present disclosure, first, each of a plurality of pixels arranged in a matrix form counts the number of photons incident thereon to obtain a pixel value (91). When each of the plurality of pixels obtains a pixel value, a pixel row from among the plurality of pixels for outputting the pixel value is selected (92). Then, N column lines (CL) of a common column line group (CCLG) shared by two adjacent pixel columns among the plurality of pixels are first precharged (93). When the column lines (CL) are precharged, a first low line (RL1) is activated (94) to select a first pixel (pxA) among two pixels (pxA, pxB) connected to the common column line group (CCLG) in the selected pixel row. When the first low line (RL1) is activated and the first pixel (pxA) is selected, the first pixel value obtained from the selected first pixel is stored in the first memory (51) of the first stage memory (50) (95).

[0091] When the first pixel value is stored in the first memory (51), N column lines (CL) of the common column line group (CCLG) are secondarily precharged (96). Then, in order to select the second pixel (pxB) among the two pixels (pxA, pxB) connected to the common column line group (CCLG) in the selected pixel row, the second low line (RL2) is activated (97). When the second low line (RL2) is activated and the second pixel (pxㅠ) is selected, the second pixel value obtained from the selected second pixel is stored in the second memory (52) of the first stage memory (50) (98).

[0092] While the first and second pixel values ​​are stored in the first and second memories (51, 52), the second stage memory (60) outputs the first and second pixel values ​​stored in the previous first and second memories (51, 52) to the outside.

[0093] Meanwhile, when the first and second pixel values ​​are stored in the first and second memories (51, 52), the first and second pixel values ​​stored in the first and second memories (51, 52) are transferred to the second stage memory (60) and stored (99). Then, it is determined whether all pixel rows for which pixel values ​​should be output externally are selected (100). If it is determined that all pixel rows are not selected, another pixel row is selected again (92). However, if it is determined that all pixel rows are selected, the number of photons incident on each of the plurality of pixels is counted again to obtain the pixel values ​​(91). However, in some cases, the operation of the image sensor may be terminated without obtaining the pixel values ​​again.

[0094] Although FIG. 6 describes each process as being executed sequentially, this is merely an example, and those skilled in the art can modify and apply various modifications and variations, such as changing the order described in FIG. 6, executing one or more processes in parallel, or adding other processes, without departing from the essential characteristics of the embodiments of the present invention.

[0095] While the present invention has been described in detail above through representative examples, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A pixel array including a plurality of pixel pairs arranged in a matrix form and connected to a plurality of first and second row lines extending in the row direction and a plurality of common column line groups extending in the column direction; and An image sensor including a peripheral circuit that sequentially transmits first and second pixel values ​​through the common column line group to which the first and second pixels of the pixel pair arranged in the selected row from the pixel array are commonly connected, receives and stores the transmitted first and second pixel values, and outputs the first and second pixel values ​​applied and stored from the previously selected pixel pair while storing the first and second pixel values.

2. In paragraph 1, The above first pixel is, Connected to the first low line and the common column line group, when the first low line is activated, the acquired first pixel value is transmitted to the peripheral circuit through the common column line group, The second pixel above An image sensor connected to a second low line and the common column line group, wherein when the second low line is activated, the acquired second pixel value is transmitted to the peripheral circuit through the common column line group.

3. In paragraph 1, The above peripheral circuits are, A first stage memory that sequentially receives and stores the first and second pixel values ​​acquired by the first and second pixels of the pixel pair of the selected row; and An image sensor including a second stage memory which receives and stores the first and second pixel values ​​stored in the first stage memory together, and outputs the first and second pixel values ​​previously applied and stored from the first stage memory while the first stage memory stores the first and second pixel values ​​for another pixel pair.

4. In paragraph 3, The above first stage memory is, A first memory for receiving and storing a first pixel value transmitted through the common column line group from the first pixel of the pixel pair of the selected row; and An image sensor including a second memory for receiving and storing a second pixel value transmitted alternately from the second pixel to the first pixel through the common column line group in a pixel pair of a selected row.

5. In paragraph 3, The above peripheral circuits are, An image sensor including a pixel bit transfer circuit that transfers each bit value of a pixel value acquired by a pixel connected to an activated row line among the pixel pair to the first stage memory when one of the first and second row lines is activated.

6. In paragraph 1, Each of the first and second pixels above, SPAD that detects photons and generates pulse signals; and An image sensor including a counter that counts the number of pulse signals to obtain a pixel value.

7. In paragraph 6, The above common column line group is, An image sensor comprising a number of column lines according to the number of bits of the first and second pixel values.

8. In paragraph 1, The above peripheral circuits are, The first and second low lines are sequentially activated according to a command authorized by an external control module. An image sensor that precharges a plurality of column lines of the common column line group before each of the first and second row lines is activated.

9. In paragraph 8, The above peripheral circuits are, An image sensor that detects voltage levels of each of a plurality of column lines that change according to each bit value of the first and second pixel values ​​obtained from the first and second pixels, and determines and stores the first and second pixel values.

10. An image sensor operating method including a pixel array and peripheral circuits, which include a plurality of pixel pairs arranged in a matrix form, each pixel being connected to a first and second row line extending in the row direction, and each pixel being connected in common to a common column line group extending in the column direction, A step of obtaining first and second pixel values, respectively, from the first and second pixels of the plurality of pixel pairs; A step of sequentially receiving and storing the first and second pixel values ​​acquired by the first and second pixels through the common column line group from the pixel pairs arranged in the selected row of the peripheral circuit; and An operating method of an image sensor, comprising the step of outputting previously stored first and second pixel values ​​while storing the first and second pixel values.

11. In paragraph 10, The steps of sequentially receiving and storing the above are: Activating the first lowline among the first and second lowlines of the selected row to select the first pixel, An operating method of an image sensor, wherein when the first pixel value acquired by the selected first pixel is transmitted through the common column line group, the first pixel value is stored in the first stage memory of the peripheral circuit.

12. In paragraph 11, The steps of sequentially receiving and storing the above are: After the first pixel value is stored, the second low line is activated to select the second pixel, An operating method of an image sensor, wherein the second pixel value acquired by the selected second pixel is transmitted through the common column line group, and the second pixel value is stored in the first stage memory.

13. In paragraph 12, The steps of sequentially receiving and storing the above are: Store the first pixel value in the first memory from the first stage memory, An operating method of an image sensor that stores the second pixel value in a second memory separated from the first memory in the first stage memory.

14. In paragraph 12, The steps of sequentially receiving and storing the above are: An operating method of an image sensor, wherein after the second pixel value is stored, the first and second pixel values ​​stored in the first stage memory are transferred to the second stage memory of the peripheral circuit and stored.

15. In paragraph 12, The step of obtaining the first and second pixel values ​​comprises: In the above plurality of pixel pairs, each of the first and second pixels drives a SPAD, The driven SPAD detects the incident photons and generates a pulse signal, An operating method of an image sensor for obtaining the first and second pixel values ​​by counting the number of generated pulse signals.

Images