Drive backplane, display panel, and display apparatus

Abstract

Provided are a drive backplane (BP) and a display panel. The drive backplane (BP) comprises a substrate (SU), a circuit layer (CL) and a bonding layer (BL), wherein the circuit layer (CL) is arranged on one side of the substrate (SU); the bonding layer (BL) is arranged on the side of the circuit layer (CL) away from the substrate (SU); and the bonding layer (BL) comprises a plurality of pads (PA) distributed in an array. The pad (PA) comprises a soldering portion (10) and a current-limiting groove (20) located outside the soldering portion (10), and the boundary of the pad (PA) is located outside the current-limiting groove (20); and / or, barrier structures (DA) distributed spaced apart from the pads (PA) are provided between the pads (PA), and the barrier structures (DA) are insulated from the pads (PA).

Description

Driving backplane, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving backplane, a display panel, and a display device. Background Art

[0002] Display panels that use LEDs, such as Micro LEDs (micro light-emitting diodes) and Mini LEDs (sub-millimeter light-emitting diodes), as pixelated light-emitting devices offer advantages such as low power consumption, high brightness, high resolution, high color saturation, fast response, long life, and high efficiency. However, the light-emitting devices in existing display panels of this type can short-circuit, causing display anomalies or even failure.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The present disclosure provides a driving backplane, a display panel, and a display device.

[0006] According to one aspect of the present disclosure, there is provided a driving backplane, comprising:

[0007] substrate;

[0008] A circuit layer is provided on one side of the substrate;

[0009] a binding layer, provided on a side of the circuit layer away from the substrate; the binding layer comprises a plurality of pads distributed in an array;

[0010] The pad includes a welding portion and a current limiting groove outside the welding portion, and the boundary of the pad is located outside the current limiting groove; and / or, a blocking structure is provided between the pads and spaced apart from the pads, and the blocking structure is insulated from the pads.

[0011] In an exemplary embodiment of the present disclosure, the flow limiting groove is a closed annular structure.

[0012] In an exemplary embodiment of the present disclosure, there are a plurality of flow limiting grooves, which are spaced apart and distributed around the welding portion.

[0013] In an exemplary embodiment of the present disclosure, the thickness of the barrier structure is smaller than the thickness of the pad.

[0014] In an exemplary embodiment of the present disclosure, at least a portion of the blocking structures are connected as an integral structure.

[0015] In an exemplary embodiment of the present disclosure, the blocking structure includes a blocking conductive layer and a blocking insulating layer covering the blocking conductive layer.

[0016] In an exemplary embodiment of the present disclosure, an extension trajectory of the current limiting groove is the same as a contour of an orthographic projection of the welding portion on the substrate.

[0017] In an exemplary embodiment of the present disclosure, the current limiting grooves on the same pad are distributed along a trajectory having the same shape as a contour of an orthographic projection of the soldering portion on the substrate.

[0018] In an exemplary embodiment of the present disclosure, the pad includes a seed layer and a conductive layer sequentially stacked in a direction away from the substrate;

[0019] The depth of the current limiting groove is less than or equal to the thickness of the conductive layer.

[0020] In an exemplary embodiment of the present disclosure, the pad includes a seed layer and a conductive layer sequentially stacked in a direction away from the substrate;

[0021] The blocking conductive layer is provided on the same layer as the seed layer.

[0022] In an exemplary embodiment of the present disclosure, any of the pads is a target pad; each of the pads adjacent to the target pad includes a first pad and a second pad; the distance between the first pad and the target pad is a first distance, and the distance between the second pad and the target pad is a second distance; the first distance is greater than the second distance;

[0023] The flow limiting groove includes an open flow limiting groove, and the open flow limiting groove is a groove with a partial area of ​​the side wall open;

[0024] The target pad is provided with the open current limiting groove, and the open current limiting groove of the target pad is open toward the first pad.

[0025] In an exemplary embodiment of the present disclosure, the flow limiting groove further comprises a closed flow limiting groove, wherein the closed flow limiting groove is a circumferentially closed groove;

[0026] The pad includes a plurality of branches extending radially; at least one of the branches is provided with the closed current limiting groove, and at least one of the branches is provided with the open current limiting groove; and the closed current limiting groove and the open current limiting groove are located in different branches.

[0027] In an exemplary embodiment of the present disclosure, the pad is divided into a plurality of welding units, each of which is arranged in an array; a welding unit includes two adjacent pads; a distance between two pads of the same welding unit is greater than a distance between two adjacent welding units;

[0028] The two welding pads of the same welding unit are respectively provided with an open current limiting groove, and the open current limiting grooves of the two welding pads are opened in opposite directions.

[0029] In an exemplary embodiment of the present disclosure, an area of ​​an orthographic projection of the current limiting groove on the substrate is smaller than an area of ​​an orthographic projection of the welding portion on the substrate.

[0030] In an exemplary embodiment of the present disclosure, the flow limiting grooves are divided into multiple groups, the flow limiting grooves in the same group are distributed along the same annular track around the welding part, and the flow limiting grooves in different groups are distributed along different annular tracks concentrically around the welding part.

[0031] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0032] A drive backplane as described in any one of the above;

[0033] A plurality of light emitting devices, any of the light emitting devices is soldered to a soldering portion of at least one of the soldering pads via a conductive solder.

[0034] In an exemplary embodiment of the present disclosure, the material of the pad includes copper, and the material of the solder includes tin; in a soldering product formed by soldering the pad and the conductive solder, an atomic weight ratio of copper to tin is 3.

[0035] In an exemplary embodiment of the present disclosure, the material of the pad includes gold, and the material of the solder includes tin; in a soldered product formed by soldering the pad and the conductive solder, an atomic weight ratio of gold to tin is 2 to 3.5.

[0036] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0039] FIG1 is a schematic top view of an embodiment of a display panel disclosed herein.

[0040] FIG2 is a partial cross-sectional view of a display panel according to a first embodiment of the first concept.

[0041] FIG3 is a partial cross-sectional view of a display panel according to a first embodiment of the first concept.

[0042] FIG4 is a partial cross-sectional view of a driving backplane of a first type of implementation of the first concept.

[0043] FIG5 is a partial cross-sectional view of a driving back plate of another first type of implementation method of the first concept.

[0044] FIG6 is a top view of a portion of a pad of the first type of implementation of the first concept.

[0045] FIG. 7 is a top view of a portion of a pad of the second first type of implementation of the first concept.

[0046] FIG8 is a top view of a portion of a pad of the third first type implementation method of the first concept.

[0047] FIG. 9 is a top view of a portion of a pad of the first second type of implementation of the first concept.

[0048] FIG. 10 is a top view of a portion of a pad of the second second type of implementation of the first concept.

[0049] FIG. 11 is a top view of a portion of a pad of the third second type embodiment of the first concept.

[0050] FIG. 12 is a top view of a portion of a pad of the fourth second type embodiment of the first concept.

[0051] FIG13 is a top view of a portion of a pad of the fifth second type embodiment of the first concept.

[0052] FIG. 14 is a top view of a portion of a pad according to an embodiment of the second concept.

[0053] FIG. 15 is a top view of a portion of a pad according to a second embodiment of the second concept.

[0054] FIG. 16 is a top view of a portion of a pad according to a third embodiment of the second concept.

[0055] FIG. 17 is a partial cross-sectional view of a display panel according to an embodiment of the third concept.

[0056] FIG18 is a partial top view of a driving backplane according to an embodiment of the third concept.

[0057] FIG19 is a partial cross-sectional view of a display panel according to an embodiment combining the first and third concepts. DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0059] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as labels and do not limit the quantity of their objects.

[0060] The row direction X and column direction Y herein are two intersecting directions, which can be perpendicular to each other. For example, in the drawings of this disclosure, the row direction X can be horizontal and the column direction Y can be vertical. However, this is not limiting, and the row direction X and column direction Y can also be non-perpendicular. Furthermore, those skilled in the art will appreciate that, as the display panel rotates, the actual orientations of the row direction X and column direction Y may change, but their relative positions remain unchanged.

[0061] In this article, A and B are "set in the same layer" means that A and B belong to different regions of the same film layer, and the film layer can be a single-layer structure; or, the film layer can also be a multi-layer structure, in which case A and B can be the same layer or different layers in the multi-layer structure.

[0062] An embodiment of the present disclosure provides a display panel, as shown in FIG1 , which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA, or a discontinuous area surrounding the display area AA.

[0063] As shown in Figure 2, the display panel may include a driving backplane BP and a plurality of light-emitting devices LD arranged on one side of the driving backplane BP. Each light-emitting device LD is located in the display area AA and is distributed along the row direction X and the column direction Y. The driving circuit in the driving backplane BP can drive the light-emitting device LD to emit light to display an image.

[0064] As shown in FIG2 , the light-emitting device LD may be a Micro-LED or a Mini LED, wherein the size of the Micro LED is below 100 μm and the size of the Mini LED is between 100 and 300 μm. Of course, other light-emitting devices may also be used.

[0065] As shown in Figures 2 and 3, in some embodiments of the present disclosure, a light-emitting device LD may include a first electrode P1, a second electrode P2, and a first semiconductor layer S1, a light-emitting functional layer MQW, and a second semiconductor layer S2 stacked in sequence. One of the first semiconductor layer S1 and the second semiconductor layer S2 may be an N-type semiconductor layer, and the other may be a P-type semiconductor layer. The first semiconductor layer S1 and the second semiconductor layer S2 may form a PN junction. The first electrode P1 is connected to the first semiconductor layer S1, and the second electrode P2 is connected to the second semiconductor layer S2. Both the first electrode P1 and the second electrode P2 are connected to the aforementioned pixel circuit. Light can be emitted from the light-emitting functional layer MQW by applying an electrical signal to the first electrode P1 and the second electrode P2.

[0066] For Mini LEDs, the light-emitting device LD may also include a substrate, and the first semiconductor layer S1, the light-emitting functional layer MQW, and the second semiconductor layer S2 may be stacked in sequence on one side of the substrate. The substrate may be made of materials such as sapphire and silicon carbide, and the first semiconductor layer S1, the light-emitting functional layer MQW, and the second semiconductor layer S2 may be formed in sequence through an epitaxial process; the materials of the first semiconductor layer S1 and the second semiconductor layer S2 may be gallium nitride, gallium phosphide, etc., depending on the luminous color of the light-emitting device LD; the light-emitting functional layer MQW may be a quantum well layer. For Micro LEDs, the above-mentioned substrate only exists during the manufacturing process. After manufacturing is completed, when the light-emitting device LD is transferred to the driving backplane BP, the light-emitting device LD does not have a substrate, that is, the substrate is peeled off from the first semiconductor layer S1, the light-emitting functional layer MQW, and the second semiconductor layer S2.

[0067] The light emitting device LD can adopt a face-up structure, a vertical structure and a flip-chip structure. For example:

[0068] Taking the front-mounted structure as an example, the substrate of the light-emitting device LD is stacked on the driver backplane BP, and the first semiconductor layer S1, the light-emitting functional layer MQW, and the second semiconductor layer S2 are arranged in sequence in a direction away from the driver backplane BP. The second semiconductor layer S2 and the light-emitting functional layer MQW expose part of the first semiconductor layer S1, that is, they do not completely cover the first semiconductor layer S1. The first electrode P1 can be provided on the exposed surface of the first semiconductor layer S1, and the second electrode P2 can be provided on the surface of the second semiconductor layer S2 away from the driver backplane BP. That is, the first electrode P1 and the second electrode P2 are located on the side of the light-emitting device LD away from the driver backplane BP. The first electrode P1 and the second electrode P2 can be connected to the pixel circuit via wires.

[0069] Taking a vertical structure as an example, the first electrode P1 of the light-emitting device LD is stacked on the driver backplane BP. It can be soldered to the pad PA of the driver backplane BP using conductive solder SO and connected to the pixel circuit through the pad PA. The substrate, first semiconductor layer S1, light-emitting functional layer MQW, second semiconductor layer S2, and second electrode P2 are arranged in sequence away from the driver backplane BP. The second electrode P2 can be connected to the driver circuit via a wire.

[0070] As shown in Figures 2 and 3 , taking a flip-chip structure as an example, the first electrode P1 and second electrode P2 of the light-emitting device LD can be arranged on the same layer and soldered to the pad PA of the driver backplane BP via conductive solder SO, thereby directly connecting the first electrode P1 and second electrode P2 to the pixel circuit of the driver backplane BP. The second semiconductor layer S2, the light-emitting functional layer MQW, and the first semiconductor layer S1 can be arranged sequentially in a direction away from the driver backplane BP. At the same time, an insulating layer S3 can be provided between the first electrode P1 and the second electrode P2 and the second semiconductor layer S2. The first electrode P1 can be connected to the first semiconductor layer S1, and the second electrode P2 can be connected to the second semiconductor layer S2.

[0071] The first electrode P1 and the second electrode P2 can be made of transparent conductive materials such as ITO (indium zinc oxide) and IZO (indium tin oxide), or metals such as titanium, aluminum, silver, and gold. The first electrode P1 and the second electrode P2 can have a single-layer or multi-layer structure, and the materials of different layers can be different.

[0072] The light-emitting devices LD in a display panel can be divided into different pixels, with each pixel including three or more light-emitting devices LD emitting different colors. The light-emitting devices LD in a single pixel can be arranged linearly along the row direction X or the column direction Y. Of course, the light-emitting devices LD in a single pixel can also be arranged in a polygonal pattern. For example, a pixel containing three light-emitting devices LD can be arranged in a triangular pattern. Furthermore, throughout the display panel, the light-emitting devices LD can be arranged in an array along the row direction X and the column direction Y, but the light-emitting devices LD in a single pixel do not necessarily reside in the same row or column.

[0073] The following is a detailed description of the structure of the driver backplane BP:

[0074] As shown in FIG2-FIG5, FIG17 and FIG19, the driving backplane BP may include a substrate SU, a circuit layer CL and a binding layer BL, wherein:

[0075] The substrate SU may be a single-layer or multi-layer structure, and its material may be a hard material such as glass, or a flexible material such as polyimide. The material and structure of the substrate SU are not particularly limited herein.

[0076] The circuit layer CL can be provided on one side of the substrate SU and can include the aforementioned drive circuit, which can include a pixel circuit PC. The pixel circuit PC can be a 7T1C pixel circuit, etc., as long as it can drive the light-emitting device LD to emit light, and its structure is not particularly limited herein. Here, nTmC indicates that a pixel circuit PC includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). At least part of the pixel circuit can be located in the display area.

[0077] The number of pixel circuits PC can be the same as the number of light-emitting devices LD, and each pixel circuit PC is connected to each light-emitting device LD in a one-to-one correspondence to control the emission of each light-emitting device LD. Of course, the number of pixel circuits PC can also be less than the number of light-emitting devices LD. For example, the same pixel circuit PC can be connected to multiple light-emitting devices LD to simultaneously drive the multiple light-emitting devices LD to emit light. This is not particularly limited here.

[0078] In addition, the driving circuit may also include a peripheral circuit located in the peripheral area WA, which may include a gate driving circuit, etc., a circuit for controlling the pixel circuit, which can be used to control the timing of the light-emitting device LD to emit light. Its specific structure is not specifically limited here.

[0079] The aforementioned driving circuit can be formed by multiple film layers. For example, taking a thin film transistor with a top-gate structure as an example, the driving backplane BP may include a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a dielectric layer, at least one source and drain layer, and a planar layer covering the source and drain layers, stacked in a direction away from the substrate SU. If multiple source and drain layers are used, adjacent source and drain layers may be separated by a planar layer. The active layer of each thin film transistor may be located in the semiconductor layer, the gate may be located in the first gate layer, one plate of the capacitor may be located in the first gate layer, and the other plate may be located in the second gate layer. In addition, the first gate layer, the second gate layer, and the source and drain layer may be provided with wiring or other connection structures for connecting the thin film transistor and the capacitor and transmitting signals. The specific patterns of the various film layers are not specifically limited here.

[0080] As shown in Figures 2-5, 17, and 19, the binding layer BL is provided on the side of the circuit layer CL away from the substrate SU. For example, the binding layer BL is provided on the surface of the flat layer farthest from the substrate SU away from the substrate SU. The binding layer BL may include a plurality of pads PA distributed in an array. The pads PA may be connected to the pixel circuit. The electrodes of the light-emitting device LD may be electrically connected to the pads PA via a conductive solder SO, thereby binding the light-emitting device LD to the driving backplane BP and connecting it to the pixel circuit.

[0081] For example, as shown in Figures 2 and 3 , for a vertical light-emitting device LD, the first electrode P1 can be soldered to the pad PA of the driver backplane using conductive solder SO. For a flip-chip light-emitting device LD, both the first electrode P1 and the second electrode P2 disposed on the same layer are soldered to the pad PA of the driver backplane BP using conductive solder SO. In other words, a vertical light-emitting device LD is soldered to one pad PA, and the number of pads PA is the same as the number of light-emitting devices LD. However, a flip-chip light-emitting device LD requires soldering to two pads PA, and the number of pads PA is twice the number of light-emitting devices.

[0082] In addition, Figures 17 and 19 show the welding of the electrode P of the light-emitting device LD and the pad PA, wherein the part of the light-emitting device LD other than the electrode P is omitted. The two electrodes P can be two electrodes of the light-emitting device LD of the same flip-chip structure or two electrodes of two vertical structure light-emitting devices LD.

[0083] The melting point of the conductive solder SO is lower than that of the pad PA. During the soldering process, the conductive solder SO melts due to heat and diffuses with the material of the pad PA, achieving eutectic bonding. For example, the conductive solder SO can be made of tin (Sn), and the pad PA can be a single-layer or multi-layer structure, made of copper (Cu) or gold (Au). Of course, the conductive solder SO and pad PA can also be made of other conductive metals, alloys, or non-metallic materials. As long as the melting point of the conductive solder SO is lower than that of the pad PA and eutectic bonding can occur between the two, it is sufficient.

[0084] As shown in Figures 2 and 3, in some embodiments of the present disclosure, the pad PA can be formed by an electroplating process in combination with a photolithography process, and may include a seed layer PA1 and a conductive layer PA2. The seed layer PA1 may be provided on the surface of the flat layer farthest from the substrate SU away from the substrate SU, and the conductive layer PA2 is stacked on the surface of the seed layer PA1 away from the substrate SU, and the thickness of the conductive layer PA2 is greater than the thickness of the seed layer PA1. The seed layer PA1 may be made of copper, nickel, and copper-containing alloys or other materials to improve the adhesion of the conductive layer PA2; the conductive layer PA2 may be made of conductive metals such as copper and gold or other materials. Among them, the seed layer PA1 and the conductive layer PA2 may be formed by processes such as electroplating and sputtering, and patterning may be achieved by a photolithography process. Of course, in other embodiments of the present disclosure, the pad PA may not include the seed layer PA1, but only include the conductive layer PA2, and the conductive layer PA2 may be directly provided on the driving backplane. In addition, in some embodiments, the sidewalls of the seed layer PA1 and the conductive layer PA2 may shrink in a direction away from the substrate SU, that is, the cross-sectional profile of the pad PA perpendicular to the substrate SU is a trapezoid shrinking in a direction away from the substrate SU.

[0085] As shown in Figures 6 to 16, the shape of the positive projection of the pad PA on the substrate SU can be a shape surrounded by smooth curves such as a circle or an ellipse, or a polygon such as a rectangle or a pentagon, or a "cross" or "M" shape with multiple branches extending radially outward. There is no special limitation on this shape.

[0086] Regarding the embodiment described above in which each light-emitting device LD is divided into multiple pixels, for flip-chip light-emitting devices LD, each light-emitting device LD is soldered to two pads PA. Based on this, as shown in Figures 2, 3, and 14, the pads PA can be divided into multiple soldering units PAU, each of which is arranged in an array. A soldering unit PAU may include two adjacent soldering pads PA, and the two soldering pads PA of a soldering unit PAU may be soldered to the first electrode and the second electrode of a light-emitting device LD. Furthermore, the distance between two adjacent soldering units PAU is the distance between a soldering pad PA in one soldering unit PAU and a soldering pad PA in another soldering unit PAU, where the two adjacent soldering pads PA are arranged adjacent to each other.

[0087] In this context, two pads being "adjacent" means that there are no other pads between the two pads.

[0088] The inventors discovered that in the eutectic bonding between the above-mentioned conductive solder SO and the pad PA, since the light-emitting device needs to withstand a certain amount of pressure, the melted conductive solder SO overflows to the surroundings due to being squeezed, and the overflow range is beyond the boundary of the pad PA; this may cause a short circuit between adjacent pads PA. In order to reduce the risk of short circuit, the distance between adjacent pads PA can be limited. This distance should be greater than the overflow range of the conductive solder SO to prevent the pads PA from short-circuiting in the event of overflow. After testing and analysis, the overflow range of the conductive solder SO is usually greater than 10μm. Therefore, the distance between adjacent pads PA should be greater than 20μm. However, for high-resolution display panels, the spacing of the light-emitting devices is difficult to meet the requirement of being greater than 20μm, and the risk of the above-mentioned short circuit problem is relatively high.

[0089] Based on the above analysis, the inventors propose that the overflow range can be limited by designing the structure of the binding layer BL, rather than simply increasing the spacing between the light-emitting devices. The details are as follows:

[0090] The first approach

[0091] A local area of ​​the pad PA can be defined as a welding portion 10, and a current limiting groove 20 recessed toward the substrate SU is opened outside the welding portion 10, and the boundary of the pad PA is located outside the current limiting groove 20; when performing eutectic bonding, the conductive solder SO can be stacked on the welding portion 10. When the conductive solder SO overflows outward due to melting, at least a portion of it can enter the current limiting groove 20 and be blocked, making it difficult to contact the adjacent pad PA, thereby improving the short circuit problem caused by overflow.

[0092] As shown in Figures 2-7 , in the first embodiment of the first approach, the current limiting groove 20 can be a closed annular structure having two concentrically arranged closed sidewalls: an inner sidewall and an outer sidewall surrounding the inner sidewall. The portion of the pad PA surrounded by the current limiting groove 20 is the soldering portion 10. The orthographic projection of the current limiting groove 20 on the substrate SU can be circular, elliptical, or even a polygonal shape such as a rectangle, and its shape is not particularly limited herein.

[0093] The extension trajectory of the current limiting groove 20 can be the same as the outline of the orthographic projection of the pad PA on the substrate SU, that is, the shape of the outline of the orthographic projection of the current limiting groove 20 on the substrate SU can be the same as the shape of the outline of the orthographic projection of the pad PA on the substrate SU, and the centers of the two projections can coincide. For example, as shown in FIG7 , the shape of the outline of the orthographic projection of the pad PA on the substrate SU is rectangular, and the shape of the outline of the orthographic projection of the current limiting groove 20 on the substrate SU is also rectangular. As shown in FIG6 , the shape of the outline of the orthographic projection of the pad PA on the substrate SU is circular, and the shape of the outline of the orthographic projection of the current limiting groove 20 on the substrate SU is also circular.

[0094] The depth of the current limiting groove 20 does not exceed the thickness of the pad PA. Take the pad PA including the seed layer PA1 and the conductive layer PA2 as an example:

[0095] In some embodiments of the first category of embodiments, as shown in FIG4 , the current limiting groove 20 is recessed from the surface of the conductive layer PA2 away from the substrate SU toward the substrate SU, and its depth is less than the thickness of the conductive layer PA2, that is, the bottom surface of the current limiting groove 20 covers the seed layer PA1. The current limiting groove 20 can be formed by etching the conductive layer PA2. The depth of the current limiting groove 20 is less than the thickness of the conductive layer PA2, which helps to reduce the difficulty of etching. For these embodiments, during manufacturing, the seed layer PA1 can be prepared on the driving backplane BP first, and patterned by a photolithography process (coating photoresist, exposure, development, etching, etc.); then the conductive layer PA2 is formed by processes such as electroplating; on the basis of the patterned seed layer PA1, a patterned conductive layer PA2 can be naturally formed by an electroplating process, and then a current limiting groove 20 is formed on the pad PA by a photolithography process. The depth of the current limiting groove 20 can be controlled by controlling the etching amount.

[0096] In some embodiments of the first category of embodiments, as shown in FIG5 , the depth of the current limiting groove 20 may be the same as the thickness of the conductive layer PA2, so that the current limiting groove 20 exposes the seed layer PA1, and the bottom surface of the current limiting groove 20 is the surface of the seed layer PA1 away from the substrate SU. In this case, the current limiting groove 20 can completely divide the conductive layer PA2, so as to facilitate accommodating more conductive solder SO and improve the effect of blocking overflow. For these embodiments, during manufacturing, a seed layer can be first formed on the driving backplane BP, but it can be unpatterned. In this case, the seed layer PA1 is a whole layer structure; then, a photoresist that defines the pattern of the conductive layer PA2 is formed on the seed layer PA1; then, the material of the conductive layer PA2 is electroplated in the position without the photoresist through a process such as electroplating, for example, thick copper is electroplated, to obtain a patterned conductive layer PA2 with a current limiting groove 20; the depth of the current limiting groove 20 is consistent with that of the conductive layer PA2. Then, the photoresist defining the pattern of the conductive layer PA2 is removed, and a photolithography process is performed again, the purpose of which is to remove the patterned seed layer PA1 between each conductive layer PA2 to obtain a plurality of pads PA.

[0097] In some embodiments of the first embodiment, the depth of the current limiting groove 20 may also be greater than the thickness of the conductive layer PA2 , that is, the current limiting groove 20 may extend into the seed layer PA1 or even penetrate the seed layer PA1 .

[0098] In some embodiments of the first category, as shown in FIG8 , multiple current limiting grooves 20 may be provided on the same pad PA. Each current limiting groove 20 may be concentrically distributed around the solder portion 10. Specifically, each current limiting groove 20 may be of different sizes and surround the solder portion 10 layer by layer from the inside out. Thus, the multiple current limiting grooves 20 can enhance the effect of preventing overflow of the conductive solder SO. Of course, due to the limited area of ​​the pad PA, to ensure that the solder portion 10 has sufficient area for contact with the conductive solder SO, the number of current limiting grooves 20 may not exceed three.

[0099] In the second embodiment of the first concept, as shown in FIG9 to FIG13 , there are multiple current limiting grooves 20 , which are spaced apart and distributed around the soldering portion 10 . That is, the overflow of the conductive solder SO can be prevented by multiple arrays of current limiting grooves 20 that are not connected to each other. The following examples illustrate this:

[0100] The current limiting grooves 20 can be spaced apart along an annular path surrounding the solder portion 10. Since the region between two adjacent current limiting grooves 20 on the pad PA lacks a current limiting groove 20, that region is continuous. The shape of the annular path can be the same as the outline of the orthographic projection of the pad PA on the substrate SU, and can be rectangular, circular, or other shapes, without particular limitation.

[0101] As shown in Figures 9 to 12, in some embodiments of the second embodiment, the current limiting grooves 20 can be spaced apart along the same annular track, and the inner sidewalls of the current limiting grooves 20 and their extended surfaces can serve as the boundaries of the soldering portion 10. In other words, although the current limiting grooves 20 are spaced apart, they can still define the boundaries of the soldering portion 10. The aforementioned annular track can have the same shape as the boundary of the pad PA.

[0102] For example, as shown in FIG9 , the flow limiting groove 20 can be an arc-shaped structure, and multiple flow limiting grooves 20 can form a circular welding portion 10. As shown in FIG11 and FIG12 , the flow limiting groove 20 can be a rectangular or L-shaped structure, and multiple flow limiting grooves 20 can form a rectangular welding portion 10. Of course, the rectangular welding portion 10 can also be formed by four L-shaped flow limiting grooves 20.

[0103] In some embodiments of the second type of embodiment, the current limiting groove 20 can also be a groove with a circular, elliptical, or polygonal blind hole structure, and multiple current limiting grooves 20 can be distributed along the same annular trajectory. At this time, the range surrounded by the boundaries of each current limiting groove 20 can be regarded as the welding portion 10. For example, as shown in Figure 10, each current limiting groove 20 can be circular and distributed along a circular trajectory, and the range of the circumscribed circle circumscribed to each current limiting groove 20 is the welding portion 10; if each current limiting groove 20 is a polygon with its vertex facing the center of the pad PA, the pad PA within the range of the line connecting each vertex can be regarded as the welding portion 10, and the line can be a straight line or a curve.

[0104] In some embodiments of the second type of embodiment, as shown in Figure 13, the current limiting grooves 20 can be divided into multiple groups. The current limiting grooves 20 of the same group can be distributed along the same annular trajectory around the welding portion 10, and the current limiting grooves 20 of different groups can be distributed along different annular trajectories concentrically around the welding portion 10, so that multiple circles (one circle is a group) of current limiting grooves 20 can be set to block the overflow of the conductive solder SO.

[0105] Furthermore, as shown in FIG13 , to improve the blocking effect, two adjacent circles of current limiting grooves 20 can be staggered in the radial direction, that is, one of the current limiting grooves 20 in one circle is located between two current limiting grooves 20 in an adjacent circle of current limiting grooves 20. When both circles of current limiting grooves 20 are spaced apart, the staggered arrangement of the two circles of current limiting grooves 20 can prevent the conductive solder SO from overflowing, thereby reducing the risk of the conductive solder SO overflowing from between the two current limiting grooves 20.

[0106] The second approach

[0107] In some embodiments of the second approach, as shown in Figures 14-16, the spacing between adjacent pads PA is uneven. That is, for a pad PA, it is adjacent to multiple pads PA, and at least two pads PA adjacent to the pad PA have different spacings from the pad PA, resulting in a size relationship between the pads PA. In this case, a portion of the current limiting groove 20 can be configured as an open groove structure, which can be defined as an open current limiting groove 210. The sidewall of the open current limiting groove 210 has a notch, which faces the aforementioned pad PA with a larger spacing therefrom. The conductive solder SO can be led out of the open current limiting groove 210, fully utilizing the larger spacing to accommodate the conductive solder SO.

[0108] For example, taking any pad PA as the target pad, the pads PA adjacent to the target pad PA include a first pad and a second pad, the distance between the first pad and the target pad is a first distance, and the distance between the second pad and the target pad is a second distance; the first distance is greater than the second distance.

[0109] The target pad is provided with a current limiting groove 20, and at least one current limiting groove 20 is the above-mentioned open current limiting groove 210, and the open current limiting groove 210 is open toward the first pad, so that the conductive solder SO entering the open current limiting groove 210 can overflow to the first pad. When the amount of conductive solder SO is relatively large and there is a risk of overflowing the current limiting groove 20, the direction of its overflow can be guided by the drainage groove so that it overflows to the first pad farther away from the target pad PA, thereby minimizing the risk of short circuit.

[0110] For a pad PA, it can be provided with only one open current limiting groove 210, or it can be provided with an open current limiting groove 210 and a closed current limiting groove 220 at the same time. The closed current limiting groove 220 is a circumferentially closed groove, that is, a closed current limiting groove 220. The closed current limiting groove 220 can block the conductive solder SO, while the open current limiting groove 210 can guide the conductive solder SO to overflow to the pad PA at a farther distance. While blocking, drainage is achieved, thereby minimizing the risk of short circuit between adjacent pads PA caused by overflow of the conductive solder SO.

[0111] The following is an exemplary description of the arrangement of the current limiting groove 20 in combination with pads PA of different shapes and distributions:

[0112] In some embodiments, as shown in Figure 14, the pad PA includes a plurality of branches PO extending radially, at least one branch PO is provided with a closed current limiting groove 220, and at least one branch PO is provided with an open current limiting groove 210, and the closed current limiting groove 220 and the open current limiting groove 210 are located in different branches PO, and the open current limiting groove 210 is open along the extension direction of the branch PO where it is located toward the pad PA where it is located, which is the largest distance away from the pad PA.

[0113] As shown in Figure 14, taking the "X"-shaped pad PA as an example, it has four branches PO. An open current limiting groove 210 can be set in one branch PO, and closed current limiting grooves 220 can be set in the other three branches PO. The closed current limiting grooves 220 can be distributed along the same rectangular track surrounding the center of the pad PA, and the pad PA within the range surrounded by the track is the welding part 10.

[0114] As shown in Figure 15 , if the light-emitting devices LD have a vertical structure, each light-emitting device LD is soldered to a pad PA. The light-emitting devices LD and the pads PA to which they are soldered can be arranged in a rectangular array along the row direction X and the column direction Y. The distance between two adjacent rows of pads PA is greater than the distance between two adjacent columns of pads PA. That is, the distance between two adjacent pads PA in the row direction X is greater than the distance between two adjacent pads PA in the column direction Y. Furthermore, the pad PA has two branches PO extending along the column direction Y and two branches PO extending along the row direction X. Each of the two branches PO extending along the column direction Y is equipped with an open current limiting slot 210, with the notches of the two open current limiting slots 210 facing opposite directions. The remaining branches PO can be equipped with closed current limiting slots 220.

[0115] As shown in FIG14 , if the light-emitting device LD is a flip-chip structure, one light-emitting device LD is soldered to two pads PA, that is, to one soldering unit PAU. Each light-emitting device LD and its soldered pads PA can be distributed in a rectangular array along the row direction X and the column direction Y. The spacing L1 between the two soldering pads PA of the soldering unit PAU is less than the distance L2 between the soldering units PAU. At the same time, the soldering pad PA has two branches PO extending along the column direction Y and two branches PO extending along the row direction X. Each of the two soldering pads PA of the same soldering unit PAU has one branch PO provided with an open current limiting groove 210, and the notches of the two open current limiting grooves 210 are oriented in opposite directions and are both open toward the other soldering unit PAU. The other branches PO can be provided with closed current limiting grooves 220.

[0116] If the pad PA is not the above-mentioned "cross" shape, but a polygon such as a circle, an ellipse or a rectangle, and the light-emitting device LD is the above-mentioned flip-chip structure, each pad PA may also be provided with only one current limiting groove 20, and the current limiting groove 20 is an open current limiting groove 210. The notches of the two current limiting grooves 20 of the two pads PA of the same welding unit PAU are in opposite directions. For example, as shown in Figure 16, the positive projection of the pad PA on the substrate SU is a rectangle, and the three light-emitting devices LD of the same pixel are distributed in a triangle. Correspondingly, the welding units PAU connected to these three light-emitting devices LD are also distributed in a triangle. The two pads PA of the same welding unit PAU are each provided with a current limiting groove 20, and the current limiting groove 20 is an open current limiting groove 210; the notches of the two open current limiting grooves 210 of the two pads PA of the same welding unit PAU are open in back to back directions.

[0117] It should be noted that the open flow limiting groove 210 and the closed flow limiting groove 220 are both provided in the flow limiting groove 20 . For the concentrically arranged multiple circles of flow limiting grooves 20 , the open flow limiting groove 210 is located in the outermost circle.

[0118] In addition, for the first and second ideas mentioned above, the area of ​​the positive projection of the current limiting groove 20 on the substrate SU can be made smaller than the area of ​​the positive projection of the welding part 10 on the substrate SU, ensuring that the pad PA has sufficient surface to contact the conductive solder SO and ensure the conductive performance.

[0119] The third approach

[0120] As shown in FIG17 , a blocking structure DA spaced apart from the pads PA may be provided between the pads PA, and the blocking structure DA is insulated from the pads PA, thereby blocking the conductive solder SO and reducing the risk of short circuits between adjacent pads PA.

[0121] At least part of the blocking structures DA can be connected into an integral structure, so that they can be formed simultaneously, which is beneficial to simplifying the process.

[0122] In some implementations of the third concept, as shown in FIG18 , all barrier structures DA can be connected into a single structure. In this case, the barrier structure DA can be considered a single layer structure with multiple openings DO. A pad PA can be positioned within each opening DO, so that each pad PA is surrounded by the barrier structure DA. The shape of the openings DO can be the same as the outline of the pad PA, and the distance between the sidewalls of the openings DO and the edges of the pad PA can be equal at all locations to ensure a uniform barrier effect. Of course, the distance between the pad PA and different areas of the sidewalls of the openings DO can also vary.

[0123] In some embodiments of the third concept, the barrier structures DA may be discontinuous and spaced apart. For example, a ring of barrier structures DA may be provided around each pad PA, spaced apart along a circular path, as long as they provide a certain degree of barrier to the conductive solder SO. A single barrier structure DA may extend along a straight line or a curve, depending on the shape of the pad PA. The path along which the barrier structures DA are distributed may be the same as or different from the shape of the pad PA. The outline of a single barrier structure DA may also be circular, elliptical, square, or the like, surrounding the pad PA in a lattice pattern.

[0124] In some embodiments of the third concept, the thickness of the blocking structure DA can be made smaller than the thickness of the pad PA, so that the blocking structure DA is located on the side of the pad PA that is closer to the substrate SU and away from the surface of the substrate SU. This prevents the blocking structure DA from contacting the light-emitting device LD and thus avoids interference with the soldering between the light-emitting device LD and the pad PA. Of course, the thickness of the blocking structure DA can also be equal to the thickness of the pad PA, but should not be greater than the thickness of the pad PA.

[0125] The blocking structure DA can be a single-layer or multi-layer structure, and the portion thereof in contact with the conductive solder SO is made of an insulating material. In some embodiments of the third concept, as shown in FIG17 , the blocking structure DA can include a blocking conductive layer DA1 and a blocking insulating layer DA2. The blocking conductive layer DA1 can be provided on the same surface of the driver backplane as the pad PA, and the blocking insulating layer DA2 can cover the blocking conductive layer DA1. The blocking insulating layer DA2 can extend from the sidewalls of the blocking conductive layer DA1 toward the driver backplane BP and contact the surface of the driver backplane BP, thereby encapsulating the blocking conductive layer DA1 and preventing the blocking conductive layer DA1 from contacting the outside world. The blocking conductive layer DA1 can be made of a metal or alloy, formed through processes such as sputtering and electroplating. The blocking insulating layer DA2 can be made of an inorganic insulating material such as silicon nitride or silicon oxide. The blocking conductive layer DA1 and the blocking insulating layer DA2 can increase the thickness of the blocking structure DA, thereby enhancing the effectiveness of blocking the conductive solder SO. The blocking insulating layer DA2 can also prevent short circuits.

[0126] In some embodiments, as shown in FIG17 , the pad PA includes a seed layer PA1 and a conductive layer PA2. The blocking conductive layer DA1 can be provided on the same layer as the seed layer PA1, thereby being formed simultaneously with the seed layer PA1 through the same process, thereby simplifying the process. Furthermore, after the seed layer PA1 and the blocking conductive layer DA1 are formed, the blocking insulating layer DA2 can be formed first, and then the conductive layer PA2 of the pad PA can be formed through a process such as electroplating.

[0127] In some embodiments of the present disclosure, the implementation methods of the first and second ideas mentioned above can be combined with the implementation method of the third idea in any feasible way. That is, as shown in Figure 19, while there is a current limiting groove 20 on the pad PA, a blocking structure DA can still be set between the pads PA to prevent short circuits between the pads PA due to overflow of the conductive solder SO to the greatest extent; as for the specific solutions of the current limiting groove 20 and the blocking structure DA, please refer to the above content about the current limiting groove 20 and the blocking structure DA, which will not be described in detail here.

[0128] When the light-emitting device LD is soldered to the pad PA via the conductive solder SO, the atomic mass ratio of the soldering product, i.e., the atomic mass ratio of the eutectic bonding product, can be restricted by controlling the thickness of the conductive solder SO and the pad PA, combined with the initial area of ​​the soldering portion 10 and the conductive solder SO, so as to ensure good conductivity and fixing performance.

[0129] In some embodiments of the present disclosure, taking a pad PA having a continuous annular current limiting groove 20 surrounding a soldering portion 10 as an example, the conductive layer PA2 of the pad PA is made of copper, and the conductive solder SO is made of tin. The area of ​​the orthographic projection of the boundary of the current limiting groove 20 on the surface of the pad PA away from the substrate SU can be defined as a first area, and the initial area of ​​the conductive solder SO when in contact with the pad PA can be defined as a second area. To limit the overflow range, the ratio of the first area to the second area can be greater than 1:3. At the same time, the ratio of the thickness of the conductive layer PA2 to the thickness of the conductive solder SO can be set to 3:1, thereby ensuring that the eutectic bonding product is primarily Cu3Sn, that is, the atomic weight ratio of copper to tin is 3:1.

[0130] In some embodiments of the present disclosure, the pad PA is made of gold and the solder is made of tin. In this case, the atomic weight ratio of gold to tin in the soldered product of the pad PA and the conductive solder SO can be controlled by controlling the area and thickness of the aforementioned embodiments. For example, the atomic weight ratio of gold to tin can be set to be no less than 2 and no greater than 3.5, and the ratio of the first area to the second area can be set to be no greater than 1:2 and no less than 1:7.

[0131] The present disclosure also provides a display device, which may include a display panel according to any of the aforementioned embodiments. The display panel is a display panel according to any of the aforementioned embodiments. Its specific structure and beneficial effects can be found in the embodiments of the display panel described above and will not be further described here. The display device of the present disclosure may be a mobile phone, tablet computer, television, or other electronic device with a display function, such as a smartwatch, smart bracelet, or in-vehicle display, which will not be listed here.

[0132] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A driving backplane, characterized in that, comprising: a substrate; a circuit layer disposed on one side of the substrate; a bonding layer disposed on the side of the circuit layer away from the substrate; the bonding layer includes a plurality of pads distributed in an array; the pad includes a welding portion and a current-limiting groove located outside the welding portion, and the boundary of the pad is located outside the current-limiting groove; and / or, a blocking structure spaced from the pad is provided between the pads, and the blocking structure is insulated from the pad.

2. The driving backplane according to claim 1, characterized in that, the current-limiting groove is a closed annular structure.

3. The driving backplane according to claim 1, characterized in that, the number of the current-limiting grooves is multiple, and they are spaced around the welding portion.

4. The driving backplane according to claim 1, characterized in that, the thickness of the blocking structure is less than the thickness of the pad.

5. The driving backplane according to claim 1, characterized in that, at least part of the blocking structure is connected into an integral structure.

6. The driving backplane according to claim 5, characterized in that, the blocking structure includes a blocking conductive layer and a blocking insulating layer covering the blocking conductive layer.

7. The driving backplane according to claim 2, characterized in that, the extension trajectory of the current-limiting groove is the same as the contour of the projection of the welding portion on the substrate.

8. The driving backplane according to claim 3, characterized in that, the current-limiting grooves on the same pad are distributed along a trajectory having the same shape as the contour of the projection of the welding portion on the substrate.

9. The driving backplane according to claim 1, characterized in that, the pad includes a seed layer and a conductive layer stacked in sequence in a direction away from the substrate; the depth of the current-limiting groove is less than or equal to the thickness of the conductive layer.

10. The driving backplane according to claim 6, characterized in that, the pad includes a seed layer and a conductive layer stacked in sequence in a direction away from the substrate; the blocking conductive layer is provided on the same layer as the seed layer.

11. The driving backplane according to claim 1, characterized in that, taking any one of the pads as a target pad; among the pads adjacent to the target pad, there are a first pad and a second pad; the distance between the first pad and the target pad is a first distance, and the distance between the second pad and the target pad is a second distance; the first distance is greater than the second distance; the current-limiting groove includes an open current-limiting groove, and the open current-limiting groove is a groove with a partially open side wall; the target pad is provided with the open current-limiting groove, and the open current-limiting groove of the target pad opens towards the first pad.

12. The driving backplane according to claim 11, characterized in that, the current-limiting groove further includes a closed current-limiting groove, and the closed current-limiting groove is a circumferentially closed groove; the pad includes a plurality of branches extending radially; at least one of the branches is provided with the closed current-limiting groove, and at least one of the branches is provided with the open current-limiting groove; and the closed current-limiting groove and the open current-limiting groove are located on different branches.

13. The driving backplane according to claim 11, characterized in that, The pad is divided into a plurality of welding units, and the welding units are distributed in an array; one welding unit includes two adjacent pads; the distance between the two pads of the same welding unit is greater than the distance between two adjacent welding units; One of the two pads of the same welding unit is respectively provided with an open current-limiting groove, and the open current-limiting grooves of the two pads open in opposite directions.

14. The driving backplane according to claim 11, characterized in that the area of the orthographic projection of the current-limiting groove on the substrate is smaller than the area of the orthographic projection of the welding part on the substrate.

15. The driving backplane according to claim 3, characterized in that the current-limiting grooves are divided into multiple groups, the current-limiting grooves of the same group are distributed along the same circular track around the welding part, and the current-limiting grooves of different groups are distributed along different circular tracks concentrically around the welding part.

16. A display panel, characterized in that it includes: the driving backplane according to any one of claims 1-15; a plurality of light-emitting devices, and any one of the light-emitting devices is welded to the welding part of at least one pad through a conductive solder.

17. The display panel according to claim 16, characterized in that the material of the pad includes copper, and the material of the solder includes tin; in the welding product formed by welding the pad and the conductive solder, the atomic weight ratio of copper to tin is 3.

18. The display panel according to claim 16, characterized in that the material of the pad includes gold, and the material of the solder includes tin; in the welding product formed by welding the pad and the conductive solder, the atomic weight ratio of gold to tin is 2 to 3.

5.

19. A display device, characterized in that it includes the display panel according to any one of claims 16-18.

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