Trench substrate lead-out structure, manufacturing method therefor and semiconductor device

Abstract

The present application relates to a trench substrate lead-out structure, a manufacturing method therefor and a semiconductor device. The method comprises: forming a main trench in a substrate; forming a heavily doped region in the substrate on a side surface of the main trench, the conductivity type of the heavily doped region being the same as that of the substrate; forming a metal-semiconductor structure, the metal-semiconductor structure extending from the top of the heavily doped region to the side surface of the main trench close to the heavily doped region and continuing to extend to the bottom of the main trench, and a metal-semiconductor structure being formed at partial positions at the bottom of the main trench, or no metal-semiconductor structure being formed at the bottom of the main trench; and filling the main trench with a first insulating material. The method has larger collection area for substrate carriers, thus more effectively collecting current formed by substrate carriers, and preventing occurrence of latch up.

Description

Trench substrate lead-out structure and manufacturing method thereof, and semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 27, 2023, with application number 2023115972715, and application name “Groove substrate lead-out structure and its manufacturing method, semiconductor device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor manufacturing, and in particular to a trench substrate lead-out structure, a method for manufacturing the trench substrate lead-out structure, and a method for manufacturing an isolation structure. Background Art

[0003] The lead-out of the substrate in a semiconductor is a very important structure, which can effectively collect hole current from the substrate and prevent latch-up (latch-up effect) from occurring, which may cause chip failure.

[0004] Summary of the Invention

[0005] Based on this, it is necessary to provide a trench substrate lead-out structure that has a better effect in preventing latch-up.

[0006] A trench substrate lead-out structure comprises: a heavily doped region located in a substrate and having the same conductivity type as the substrate, wherein the doping concentration of the heavily doped region is greater than the doping concentration of the substrate; a trench isolation structure located on a side of the heavily doped region; and a metal semiconductor structure extending from the top of the heavily doped region to a side of the trench isolation structure close to the heavily doped region, and continuing to extend toward the bottom of the trench isolation structure, wherein the bottom of the trench isolation structure is at least partially covered by the metal semiconductor structure, or the metal semiconductor structure is not provided at the bottom of the trench isolation structure.

[0007] The above-mentioned trench substrate lead-out structure has a metal semiconductor structure arranged on the side of the heavily doped region, which has a larger substrate carrier collection area and can more effectively collect the current formed by the substrate carriers to prevent latch up.

[0008] In one embodiment, the trench isolation structure includes a voltage-resistant portion and a metal semiconductor encapsulation portion located between the voltage-resistant portion and the heavily doped region, and the metal semiconductor structure is located on the side and bottom of the metal semiconductor encapsulation portion and the top of the heavily doped region.

[0009] In one embodiment, the depth of the voltage-resistant portion is greater than the depth of the metal semiconductor covering portion.

[0010] In one embodiment, the depth of the voltage-resistant portion is equal to the depth of the metal semiconductor covering portion.

[0011] In one embodiment, the depth of the pressure-resistant portion is less than the depth of the metal semiconductor covering portion, and the metal semiconductor structure is provided on the outer surface of a portion of the metal semiconductor covering portion that is deeper than the pressure-resistant portion.

[0012] In one embodiment, the metal semiconductor structure is made of metal silicide.

[0013] In one embodiment, the material of the trench isolation structure is silicon oxide.

[0014] In one embodiment, the conductivity type of the substrate and the heavily doped region is P-type.

[0015] There is also a need to provide a semiconductor device.

[0016] A semiconductor device comprises the trench substrate lead-out structure described in any of the preceding embodiments, further comprising a conductive structure in a contact hole on the heavily doped region, and a metal interconnection on the conductive structure; the bottom of the conductive structure is electrically connected to the metal semiconductor structure, and the top of the conductive structure is electrically connected to the metal interconnection.

[0017] The semiconductor device has a trench substrate lead-out structure with a metal semiconductor structure arranged on the side of the heavily doped region, which has a larger substrate carrier collection area and can more effectively collect the current formed by the substrate carriers to prevent latch up.

[0018] It is also necessary to provide a method for manufacturing a trench substrate lead-out structure.

[0019] A method for manufacturing a trench substrate lead-out structure, comprising:

[0020] A main trench is formed in a substrate; a heavily doped region is formed in the substrate on the side of the main trench, wherein the conductive type of the heavily doped region is the same as that of the substrate; a metal semiconductor structure is formed; the metal semiconductor structure extends from the top of the heavily doped region to the side of the main trench close to the heavily doped region, and continues to extend toward the bottom of the main trench, wherein the metal semiconductor structure is formed at a portion of the bottom of the main trench, or the metal semiconductor structure is not provided at the bottom of the main trench; and a first insulating material is filled in the main trench.

[0021] The above-mentioned method for manufacturing the trench substrate lead-out structure sets a metal semiconductor structure on the side of the heavily doped region, which has a larger substrate carrier collection area and can more effectively collect the current formed by the substrate carriers to prevent latch up.

[0022] In one embodiment, the total trench includes a first trench and a second trench, and forming the total trench in the substrate includes: forming a first trench in the substrate; filling the first trench with a second insulating material; forming a second trench connected to the first trench on the side of the first trench; forming a heavily doped region in the substrate on the side of the total trench includes forming a heavily doped region in the substrate on the side of the second trench; the metal semiconductor structure is formed on the top of the heavily doped region, the bottom of the second trench, and the side of the second trench close to the heavily doped region; filling the first insulating material in the total trench includes filling the first insulating material in the second trench.

[0023] In one embodiment, the heavily doped region is formed in the substrate on the side of the second trench by ion implantation at an inclined angle.

[0024] In one embodiment, it also includes: before forming the first trench in the substrate, forming a hard mask on the substrate; the forming of the first trench in the substrate is to etch the substrate using the hard mask as an etch barrier layer to form the first trench; the forming of the second trench connected to the first trench on the side of the first trench includes: photolithography and etching the hard mask to remove the hard mask directly above the position where the second trench is to be formed; etching the substrate using the remaining hard mask as an etch barrier layer to form the second trench; the manufacturing method also includes: after filling the second trench with a first insulating material, removing the hard mask; ion implanting the top of the heavily doped region to implant ions of the same conductivity type as the heavily doped region; wherein the metal semiconductor structure on the top of the heavily doped region is formed after the ion implantation is performed on the top of the heavily doped region.

[0025] In one embodiment, forming a hard mask on the substrate includes: forming a pad oxide layer on the upper surface of the substrate; and forming a hard mask on the pad oxide layer.

[0026] In one embodiment, the hard mask is a nitride layer.

[0027] In one embodiment, the material of the nitride layer is silicon nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0029] FIG1a is a schematic cross-sectional view of an exemplary polysilicon-filled trench substrate lead-out structure, and FIG1b is a schematic cross-sectional view of an exemplary tungsten-filled trench substrate lead-out structure;

[0030] FIG2a is a schematic cross-sectional view of a trench substrate lead-out structure in one embodiment of the present application, FIG2b is a schematic cross-sectional view of a trench substrate lead-out structure in another embodiment of the present application, and FIG2c is a schematic cross-sectional view of a trench substrate lead-out structure in yet another embodiment of the present application;

[0031] FIG3 is a flow chart of a method for manufacturing a trench substrate lead-out structure according to an embodiment of the present application;

[0032] 4 is a schematic diagram of forming a liner oxide layer and a hard mask layer on a substrate in a method for manufacturing a trench substrate lead-out structure according to an embodiment of the present application;

[0033] FIG5 is a schematic cross-sectional view of the semiconductor structure after step S310 is completed in one embodiment of the present application;

[0034] FIG6 is a schematic cross-sectional view of the semiconductor structure after step S320 is completed in one embodiment of the present application;

[0035] FIG7 is a schematic diagram of patterning a hard mask before etching a second trench in one embodiment of the present application;

[0036] FIG8a is a schematic diagram of the cross-sectional structure of the semiconductor structure after step S330 is completed in one embodiment of the present application. FIG8b is a schematic diagram of the cross-sectional structure of the semiconductor structure after step S330 is completed in another embodiment of the present application. FIG8c is a schematic diagram of the cross-sectional structure of the semiconductor structure after step S330 is completed in yet another embodiment of the present application.

[0037] FIG9a is a schematic cross-sectional view of a metal-semiconductor structure formed at the interface between the second trench and the silicon substrate in one embodiment of the present application; FIG9b is a schematic cross-sectional view of a metal-semiconductor structure formed at the interface between the second trench and the silicon substrate in another embodiment of the present application; and FIG9c is a schematic cross-sectional view of a metal-semiconductor structure formed at the interface between the second trench and the silicon substrate in yet another embodiment of the present application;

[0038] Figure 10a is a schematic diagram of the cross-sectional structure of the trench substrate lead-out structure after step S360 is completed in one embodiment of the present application, Figure 10b is a schematic diagram of the cross-sectional structure of the trench substrate lead-out structure after step S360 is completed in another embodiment of the present application, and Figure 10c is a schematic diagram of the cross-sectional structure of the trench substrate lead-out structure after step S360 is completed in yet another embodiment of the present application. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0045] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0046] An exemplary trench-substrate lead-out structure uses polysilicon filled in the trench. Referring to Figure 1a, a trench is formed in a P-type substrate (P-sub). The trench's sidewalls are formed by an oxide layer 12, and the trench is filled with polysilicon 14. The bottom of polysilicon 14 forms the substrate lead-out region P+. However, for devices with a P-type substrate, the trench must be filled with P-type polysilicon, which is incompatible with conventional gate polysilicon.

[0047] Another exemplary trench substrate lead-out structure involves filling the trench with metal tungsten. Referring to Figure 1b, a trench is formed in a P-type substrate (P-sub). The sidewalls of the trench are formed by an oxide layer 12, and the trench is filled with metal tungsten 16. The bottom of the metal tungsten 16 forms the substrate lead-out region P+. This process can only be performed in the back-end of line (BEOL) of chip manufacturing, and its portability is poor. Furthermore, whether the trench is filled with polysilicon or metal tungsten, significant stress is present, hindering process integration.

[0048] The present application proposes a novel trench substrate lead-out structure that can effectively collect hole current from the substrate and prevent latch-up effect from occurring.

[0049] Figure 2a is a schematic cross-sectional view of a trench substrate lead-out structure in one embodiment of the present application, comprising a substrate 210, a trench isolation structure 220, a heavily doped region 230, and a metal-semiconductor structure 240. The heavily doped region 230 is located in the substrate 210 and has the same conductivity type as the substrate 210. The doping concentration of the heavily doped region 230 is greater than that of the substrate 210. In the embodiment shown in Figure 2a, the substrate 210 is a P-type substrate (P-sub), and the heavily doped region 230 is a P+ region. The trench isolation structure 220 is located on the side of the heavily doped region 230. The trench isolation structure 220 is a structure formed by filling the trench with an insulating material. A metal semiconductor structure 240 is provided on top of the heavily doped region 230. The metal semiconductor structure 240 extends from the top of the heavily doped region 230 to the side of the trench isolation structure 220 adjacent to the heavily doped region 230. In one embodiment, the metal semiconductor structure 240 extends to the bottom of the trench isolation structure 220 so that it is partially or completely covered by the metal semiconductor structure 240. In another embodiment, the metal semiconductor structure 220 is not provided at the bottom of the trench isolation structure 240. A contact hole is provided on the top of the metal semiconductor structure 240 to extract the substrate potential. Therefore, the metal semiconductor structure 240 needs to be made of a material with good electrical contact properties so that the metal in the contact hole forms a good electrical contact with the heavily doped region 230 below (i.e., has a low contact resistance).

[0050] The above-mentioned trench substrate lead-out structure has a metal semiconductor structure 240 disposed on the side of the heavily doped region 230, which has a larger substrate carrier collection area and can more effectively collect the current formed by the substrate carriers to prevent latch-up.

[0051] In one embodiment of the present application, substrate 210 is a silicon substrate. The insulating material filling the trenches of trench isolation structure 220 is silicon oxide, such as silicon dioxide. Using silicon oxide instead of metal tungsten or polysilicon in the trenches reduces stress and facilitates process integration.

[0052] In one embodiment of the present application, the material of the metal semiconductor structure 240 is metal silicide. In one embodiment, the material of the metal silicide can be CoSi x 、NiSi x 、PtSi x or a combination of these compounds.

[0053] In the embodiment shown in Figure 2a, the trench isolation structure 220 includes a voltage-resistant portion 222 and a metal semiconductor cladding portion 224 located between the voltage-resistant portion 222 and the heavily doped region 230. The depth of the voltage-resistant portion 222 is represented by D1, and the depth of the metal semiconductor cladding portion 224 is represented by D2. The outer surface of the metal semiconductor cladding portion 224, except for the top, is covered by the metal semiconductor structure 240. The metal semiconductor structure 240 is not provided on the outer surface of the voltage-resistant portion 222. The voltage-resistant portion 222 is used to block the metal semiconductor structure 240 (and the heavily doped region 230) from other device structures to increase the breakdown voltage between the substrate lead and other device structures. The insulating materials filled in the voltage-resistant portion 222 and the metal semiconductor cladding portion 224 may be the same or different.

[0054] 2a , the depth D1 of the voltage-resistant portion 222 is greater than the depth D2 of the metal-semiconductor encapsulating portion 224 . Regarding the trench isolation structure 220 , the metal-semiconductor structure 240 is disposed on the bottom surface of the metal-semiconductor encapsulating portion 224 and on the side of the metal-semiconductor encapsulating portion 224 adjacent to the heavily doped region 230 .

[0055] Figure 2b is a schematic cross-sectional view of a trench substrate lead-out structure in another embodiment of the present application. The primary difference between this embodiment and that shown in Figure 2a is that the depth D1 of the voltage-resistant portion 222 (not labeled in Figure 2b ) is equal to the depth D2 of the metal-semiconductor encapsulation portion (not labeled in Figure 2b ). Similarly to the trench isolation structure 220 , the metal-semiconductor structure 240 is located on the bottom surface of the metal-semiconductor encapsulation portion 224 and on the side of the metal-semiconductor encapsulation portion 224 adjacent to the heavily doped region 230.

[0056] Figure 2c is a schematic cross-sectional view of a trench substrate lead-out structure in another embodiment of the present application. This embodiment differs from the embodiment shown in Figure 2a primarily in that the depth D1 of the voltage-resistant portion 222 (not labeled in Figure 2c ) is less than the depth D2 of the metal-semiconductor cladding portion (not labeled in Figure 2c ). Regarding the trench isolation structure 220 , the metal-semiconductor structure 240 is disposed on the outer surface of the portion of the metal-semiconductor cladding portion 224 that is deeper than the voltage-resistant portion 222, as well as on the side of the metal-semiconductor cladding portion 224 that is closer to the heavily doped region 230.

[0057] The present application accordingly provides a semiconductor device comprising the trench substrate lead-out structure described in any of the aforementioned embodiments, a conductive structure located in a contact hole above a heavily doped region 230, and a metal interconnect on the conductive structure. The bottom of the conductive structure is electrically connected to the metal-semiconductor structure 240, and the top of the conductive structure is electrically connected to the metal interconnect. The conductive structure can be made of a metal and / or alloy, such as a tungsten plug.

[0058] The semiconductor device has a trench substrate lead-out structure with a metal semiconductor structure 240 disposed on the side of the heavily doped region 230, which has a larger substrate carrier collection area and can more effectively collect the current formed by the substrate carriers to prevent latch-up.

[0059] The present application accordingly provides a method for manufacturing a trench substrate lead-out structure, comprising the following steps:

[0060] forming an overall trench in the substrate;

[0061] forming a heavily doped region in the substrate on the side of the main trench, wherein the heavily doped region has the same conductivity type as the substrate;

[0062] forming a metal semiconductor structure; the metal semiconductor structure extends from the top of the heavily doped region to the side of the main trench near the heavily doped region, and continues to extend toward the bottom of the main trench, with a portion of the bottom of the main trench being formed with the metal semiconductor structure, or the bottom of the main trench being free of the metal semiconductor structure;

[0063] The main trench is filled with a first insulating material.

[0064] In one embodiment of the present application, the total trench includes a first trench and a second trench, and the step of forming the total trench in the substrate includes: forming a first trench in the substrate; filling the first trench with a second insulating material; forming a second trench connected to the first trench on the side of the first trench; the step of forming a heavily doped region in the substrate on the side of the total trench includes forming a heavily doped region in the substrate on the side of the second trench; the metal semiconductor structure is formed on the top of the heavily doped region, the bottom of the second trench, and the side of the second trench close to the heavily doped region; the step of filling the first insulating material in the total trench includes filling the first insulating material in the second trench.

[0065] In one embodiment of the present application, the step of forming a heavily doped region in the substrate on the side of the second trench is to form the heavily doped region by ion implantation at an inclined angle.

[0066] In one embodiment of the present application, before the step of forming the first trench in the substrate, the step further includes forming a hard mask on the substrate; the step of forming the first trench in the substrate is etching the substrate with the hard mask as an etching barrier layer to form the first trench; the step of forming a second trench connected to the first trench on the side of the first trench includes: photolithography and etching the hard mask to remove the hard mask directly above the position where the second trench is to be formed; etching the substrate with the remaining hard mask as an etching barrier layer to form the second trench; after the step of filling the second trench with the first insulating material, the step further includes: removing the hard mask; performing ion implantation on the top of the heavily doped region to implant ions of the same conductivity type as the heavily doped region; wherein the metal semiconductor structure on the top of the heavily doped region is formed after the step of performing ion implantation on the top of the heavily doped region.

[0067] In one embodiment of the present application, the step of forming a hard mask on the substrate includes: forming a pad oxide layer on the upper surface of the substrate; and forming a hard mask on the pad oxide layer.

[0068] FIG3 is a flow chart of a method for manufacturing a trench substrate lead-out structure according to an embodiment of the present application, comprising the following steps:

[0069] S310 , forming a first trench in the substrate.

[0070] A wafer including a semiconductor substrate (substrate 410) is obtained, and a first trench 421 extending from the upper surface of substrate 410 toward the interior of substrate 410 is etched. In one embodiment of the present application, substrate 410 is etched to form first trench 421 using hard mask 460 as an etch barrier.

[0071] 4 , a hard mask 460 may be formed on a substrate 410 , and then patterned. The hard mask 460 may be removed from the portion of the substrate 410 directly above the location where the first trench 421 is to be formed. The substrate 410 may then be etched to form a first trench 421 having a depth D1 , as shown in FIG5 . Patterning the hard mask 460 may be performed using a photolithography and etching process. In one embodiment, a photoresist is applied to the hard mask 460 , and then the photoresist is exposed using a corresponding photomask. After development, an etching window having the same cross-section as the first trench 421 is obtained. The hard mask 460 is then etched to remove the portion of the hard mask 460 directly above the location of the first trench 421 . In one embodiment of the present application, the photoresist is removed before etching the substrate 410 to form the first trench 421 .

[0072] In one embodiment of the present application, before forming the hard mask 460, a step of forming a pad oxide layer (PAD Oxide) 450 on the upper surface of the substrate 410 is further included. After forming the pad oxide layer 450, the hard mask 460 is formed on the pad oxide layer 450. In one embodiment of the present application, the pad oxide layer 450 is formed by thermal oxidation.

[0073] In one embodiment of the present application, the hard mask 460 is a nitride layer, such as a silicon nitride layer. In one embodiment of the present application, the hard mask 460 is formed by depositing silicon nitride. In the embodiments shown in Figures 4 and 5, the substrate 410 is a P-type substrate (P-sub).

[0074] S320 , filling the first trench with an insulating material.

[0075] In one embodiment of the present application, filling the insulating material 422a includes depositing silicon oxide, such as silicon dioxide. In one embodiment of the present application, the step of grinding the upper surface of the wafer by chemical mechanical planarization (CMP) to remove excess insulating material 422a is also included, as shown in FIG6 .

[0076] S330 , forming a second trench on a side surface of the first trench and communicating with the first trench.

[0077] In one embodiment of the present application, the hard mask 460 is photolithographically and etched to remove the hard mask 460 directly above the location where the second trench 423 is to be formed. Then, the substrate 410 is etched using the remaining hard mask 460 as an etch barrier to form the second trench 423.

[0078] In one embodiment of the present application, a photoresist 492 is coated on the hard mask 460, and then exposed using a corresponding photomask. After development, an etching window having the same cross-section as the second trench 423 is obtained. The hard mask 460 is then etched to remove the portion of the hard mask 460 directly above the second trench 423, as shown in FIG7 . The photoresist 492 is then removed, and the substrate 410 is etched using the remaining hard mask 460 as an etch barrier to form a second trench 423 having a depth D2, as shown in FIG8 a.

[0079] Figures 8b and 8c are schematic diagrams of the semiconductor structure after step S330 is completed in two other embodiments. The main difference between these embodiments and the embodiment shown in Figure 8a is whether the first trench 421 or the second trench 423 is deeper. In the embodiment shown in Figure 8a, the depth D1 of the first trench 421 is greater than the depth D2 of the second trench 423. In the embodiment shown in Figure 8b, the depth D1 is equal to the depth D2; in the embodiment shown in Figure 8c, the depth D1 is less than the depth D2.

[0080] S340 , forming a heavily doped region in the substrate on a side of the second trench.

[0081] The heavily doped region 430 has the same conductivity type as the substrate 410. In one embodiment of the present application, the heavily doped region 430, i.e., the P+ region in FIG9a , is formed by ion implantation at an oblique angle. In the embodiment shown in FIG9a , the heavily doped region 430 is also formed in the substrate 410 below the second trench 423.

[0082] S350 , forming a metal semiconductor structure.

[0083] A metal semiconductor structure 440 is formed at the junction of the second trench 423 and the heavily doped region 430, and at the junction of the second trench 423 and the substrate 410. In one embodiment of the present application, the material of the metal semiconductor structure 440 is metal silicide. In one embodiment of the present application, the material of the metal silicide can be CoSi x 、NiSi x 、PtSi x or a combination of these compounds.

[0084] After executing steps S340 and S350, the structure shown in Figure 8b obtains the structure shown in Figure 9b. After executing steps S340 and S350, the structure shown in Figure 8c obtains the structure shown in Figure 9c.

[0085] S360 , filling the second trench with an insulating material.

[0086] In one embodiment of the present application, filling the insulating material includes depositing silicon oxide, such as silicon dioxide.

[0087] The above-mentioned method for manufacturing the trench substrate lead-out structure sets a metal semiconductor structure 440 on the side of the heavily doped region 430, which has a larger substrate carrier collection area and can more effectively collect the current formed by the substrate carriers to prevent latch-up.

[0088] In one embodiment of the present application, step S360 further includes a step of grinding the upper surface of the wafer by chemical mechanical planarization (CMP) to remove excess insulating material.

[0089] In one embodiment of the present application, step S360 is followed by a step of removing the hard mask 460 and excess insulating material. In one embodiment of the present application, the insulating material above the upper surface of the substrate 410 (the insulating material deposited in steps S320 and S360) is removed by wet etching, and then the hard mask 460 is removed.

[0090] Referring to Figure 10a, after removing the excess insulating material, the insulating material in the first groove 421 (not marked in Figure 10a) serves as the voltage-resistant portion 422, and the insulating material in the second groove 423 (not marked in Figure 10a) serves as the metal semiconductor encapsulation portion 424. The depth of the voltage-resistant portion 422 is the depth D1 of the groove 421, and the depth of the metal semiconductor encapsulation portion 424 is the depth D2 of the groove 423. The outer surface of the metal semiconductor encapsulation portion 424, except for the top, is covered by the metal semiconductor structure 440. The metal semiconductor structure 440 is not provided on the outer surface of the voltage-resistant portion 422. The voltage-resistant portion 422 is used to block the metal semiconductor structure 440 (and the heavily doped region 430) from other device structures to increase the breakdown voltage between the substrate lead and other device structures.

[0091] In one embodiment of the present application, after removing the hard mask 460, the step of ion implantation is further included into the top of the heavily doped region 430. Since step S340 is an inclined implantation, the impurity ion concentration at the top of the heavily doped region 430 is insufficient, requiring supplemental implantation. In one embodiment of the present application, after this supplemental implantation step, the step of removing the pad oxide layer 450 on the heavily doped region 430 and then forming the metal semiconductor structure 440 on the top of the heavily doped region 430 is further included, as shown in FIG. 10 a.

[0092] The structure shown in FIG9b is obtained by forming a metal semiconductor structure on top of the heavily doped region to obtain the structure shown in FIG10b, and the structure shown in FIG9c is obtained by forming a metal semiconductor structure on top of the heavily doped region to obtain the structure shown in FIG10c.

[0093] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0094] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0095] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A trench substrate lead-out structure, comprising: A heavily doped region, located in the substrate and having the same conductivity type as the substrate, wherein the doping concentration of the heavily doped region is greater than the doping concentration of the substrate; A trench isolation structure is located on a side of the heavily doped region; A metal semiconductor structure extends from the top of the heavily doped region to the side of the trench isolation structure close to the heavily doped region, and continues to extend toward the bottom of the trench isolation structure, the bottom of the trench isolation structure is at least partially covered by the metal semiconductor structure, or the metal semiconductor structure is not set at the bottom of the trench isolation structure.

2. The trench substrate lead-out structure according to claim 1, wherein: The trench isolation structure includes a voltage-resistant portion and a metal semiconductor encapsulating portion located between the voltage-resistant portion and the heavily doped region, and the metal semiconductor structure is located on the side surface and bottom surface of the metal semiconductor encapsulating portion and the top of the heavily doped region.

3. The trench substrate lead-out structure according to claim 2, wherein: The depth of the pressure-resistant portion is greater than the depth of the metal semiconductor covering portion; or The depth of the pressure-resistant portion is equal to the depth of the metal semiconductor covering portion; or The depth of the pressure-resistant portion is smaller than the depth of the metal semiconductor covering portion, and the metal semiconductor structure is disposed on an outer surface of a portion of the metal semiconductor covering portion that has a greater depth than the pressure-resistant portion.

4. The trench substrate lead-out structure according to claim 1, wherein: The material of the metal semiconductor structure is metal silicide.

5. The trench substrate lead-out structure according to claim 1, wherein: The material of the trench isolation structure is silicon oxide.

6. The trench substrate lead-out structure according to claim 1, wherein: The conductivity type of the substrate and the heavily doped region is P type.

7. The trench substrate lead-out structure according to claim 1, wherein: A contact hole for extracting the potential of the substrate is arranged on the top of the metal semiconductor structure.

8. A semiconductor device, comprising the trench substrate lead-out structure as described in claim 1, and also comprising a conductive structure in a contact hole located on the heavily doped region, and a metal interconnection on the conductive structure; the bottom of the conductive structure is electrically connected to the metal semiconductor structure, and the top of the conductive structure is electrically connected to the metal interconnection.

9. A method for manufacturing a trench substrate lead-out structure, comprising: forming an overall trench in a substrate; forming a heavily doped region in the substrate at the side of the main trench, wherein the heavily doped region has the same conductivity type as the substrate; forming a metal semiconductor structure; The metal semiconductor structure extends from the top of the heavily doped region to the side of the main trench close to the heavily doped region, and continues to extend toward the bottom of the main trench, and the metal semiconductor structure is formed at a portion of the bottom of the main trench, or the metal semiconductor structure is not provided at the bottom of the main trench; A first insulating material is filled in the main trench.

10. The method for manufacturing a trench substrate lead-out structure according to claim 9, wherein: The overall trench comprises a first trench and a second trench, and forming the overall trench in the substrate comprises: forming a first trench in a substrate; Filling a second insulating material in the first trench; forming a second groove communicating with the first groove on a side of the first groove; The forming of a heavily doped region in the substrate on the side of the total trench includes forming a heavily doped region in the substrate on the side of the second trench; the metal semiconductor structure is formed on the top of the heavily doped region, the bottom of the second trench and the side of the second trench close to the heavily doped region; and the filling of the first insulating material in the total trench includes filling the first insulating material in the second trench.

11. The method for manufacturing a trench substrate lead-out structure according to claim 10, wherein: The forming of the heavily doped region in the substrate at the side of the second trench is performed by ion implantation at an inclined angle.

12. The method for manufacturing a trench substrate lead-out structure according to claim 10, further comprising, before forming the first trench in the substrate, forming a hard mask on the substrate; The forming of the first trench in the substrate comprises etching the substrate using the hard mask as an etching barrier layer to form the first trench; The second groove formed on the side of the first groove and communicating with the first groove comprises: Photolithography and etching the hard mask to remove the hard mask directly above the position where the second trench is to be formed; Etching the substrate using the remaining hard mask as an etching barrier to form the second trench; The manufacturing method further comprises: after filling the second trench with the first insulating material, removing the hard mask; Performing ion implantation on the top of the heavily doped region, implanting ions of the same conductivity type as that of the heavily doped region; The metal semiconductor structure on the top of the heavily doped region is formed after ion implantation is performed on the top of the heavily doped region.

13. The method for manufacturing a trench substrate lead-out structure according to claim 12, wherein: The forming of a hard mask on the substrate comprises: forming a pad oxide layer on the upper surface of the substrate; The hard mask is formed on the pad oxide layer.

14. The method for manufacturing a trench substrate lead-out structure according to claim 12, wherein: The hard mask is a nitride layer.

15. The method for manufacturing a trench substrate lead-out structure according to claim 14, wherein: The material of the nitride layer is silicon nitride.

Images