Driving circuit, control apparatus, and driving system

Abstract

Disclosed in the present disclosure are a driving circuit, a control apparatus, and a driving system. The driving circuit comprises a driving control circuit and a plurality of half-bridge circuits, an output end of the driving control circuit being connected to the plurality of half-bridge circuits, wherein the driving control circuit is used for receiving a communication signal and outputting a plurality of control signals; and the plurality of half-bridge circuits are used for determining the operating states of the plurality of half-bridge circuits on the basis of the plurality of control signals, and providing a driving signal to at least one load circuit on the basis of the operating states of the plurality of half-bridge circuits, wherein the driving signal of each load circuit is provided by at least two of the plurality of half-bridge circuits. In this way, the resource occupancy of a GPIO interface of an MCU can be reduced, thereby improving the control efficiency of the circuit, and the complexity of the circuit is also reduced, thereby improving the anti-interference performance of the circuit.

Description

Drive circuit, control device and drive system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202323226637.6, application date November 27, 2023, and invention name “Drive circuit, control device and drive system”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this disclosure as a reference. Technical Field

[0003] The present disclosure relates to the technical field of relays, and in particular to a drive circuit, a control device, and a drive system. Background Art

[0004] High-side and low-side drivers are typically a combination of a high-side chip and a low-side chip. They are widely used in the battery management system (BMS) of new energy vehicles, for example, in relay control and lighting control. The terms "high-side" and "low-side" are used relative to the load. A high-side chip with a load on the ground side and a switch on the power supply side sends a high-side drive signal to the load; a low-side chip with a load on the power supply side and a switch on the ground side sends a low-side drive signal to the load.

[0005] At present, in related technologies, multiple sets of high-side and low-side drivers are generally used as load drivers. In this way, the microcontroller unit (MCU) needs to control multiple corresponding high-side chips and low-side chips to drive the load by outputting multiple hard-wired control signals. This not only occupies a large amount of resources of the MCU's general-purpose input / output (GPIO) interface, but also increases the circuit complexity of the BMS.

[0006] Summary of the Invention

[0007] The present disclosure proposes a drive circuit, a control device and a drive system. By using a drive circuit including multiple half-bridge circuits as the driver of the load circuit, it can not only reduce the resource occupation of the GPIO interface of the MCU and improve the control efficiency of the circuit, but also reduce the complexity of the circuit and improve the anti-interference ability of the circuit.

[0008] The technical solution of the present disclosure is achieved as follows:

[0009] In a first aspect, an embodiment of the present disclosure provides a drive circuit, which includes a drive control circuit and a multi-channel half-bridge circuit, wherein an output end of the drive control circuit is connected to the multi-channel half-bridge circuit, wherein:

[0010] Drive control circuit, used for receiving communication signals and outputting multi-channel control signals;

[0011] A multi-path half-bridge circuit is used to determine the operating state of the multi-path half-bridge circuit based on multiple control signals, and to provide a drive signal to at least one load circuit based on the operating state of the multi-path half-bridge circuit; wherein the drive signal of each load circuit is provided by at least two items in the multi-path half-bridge circuit.

[0012] Through the above-mentioned technical means, by using a driving circuit including a driving control circuit and a multi-channel half-bridge circuit as the driver of the load circuit, the communication signal is converted into a multi-channel control signal. Without the need for the MCU to output multiple hard-wired control signals, multiple load circuits can be driven, thereby reducing the resource occupation of the MCU's GPIO interface, improving the circuit's control efficiency, reducing the circuit's complexity, and improving the circuit's anti-interference ability.

[0013] In some embodiments, the driving circuit is provided with a plurality of output terminals, wherein:

[0014] Each half-bridge circuit corresponds to an output end, and at least two of the multiple output ends are connected to the load circuit, and the at least two output ends are used to provide corresponding driving signals to the load circuit.

[0015] Through the above technical means, the load circuit is connected to the high-side drive signal or the low-side drive signal through multiple output terminals of the drive circuit. The output of the drive signal only occupies the output pins of the drive circuit, reducing the GPIO resource occupation of the MCU.

[0016] In some embodiments, the driving circuit includes at least one first-type half-bridge circuit and at least one second-type half-bridge circuit, wherein:

[0017] At least one first-type half-bridge circuit, configured to provide a first-type driving signal to at least one load circuit;

[0018] At least one second-type half-bridge circuit is used to provide a second-type driving signal to at least one load circuit.

[0019] Through the above technical means, multiple half-bridge circuits are divided into first-type half-bridge circuits and second-type half-bridge circuits. According to the communication signal, high-side drive signals and low-side drive signals are respectively provided to at least one load circuit. Multiple drive signals are output through the drive circuit, reducing the GPIO resource occupation of the MCU.

[0020] In some embodiments, at least one first-type half-bridge circuit and at least one second-type half-bridge circuit are located on the same driver chip; or,

[0021] At least one first-type half-bridge circuit is located on at least one first driver chip, and at least one second-type half-bridge circuit is located on at least one second driver chip.

[0022] Through the above technical means, the first type of half-bridge circuit and the second type of half-bridge circuit can be set on the same driver chip or on different driver chips, which can meet the current requirements of different load circuits and improve the flexibility of the driver circuit.

[0023] In some embodiments, when at least one first-type half-bridge circuit and at least one second-type half-bridge circuit are located on the same driver chip, the at least one first-type half-bridge circuit includes a first half-bridge circuit, a second half-bridge circuit, and a third half-bridge circuit, and the at least one second-type half-bridge circuit includes a fourth half-bridge circuit, a fifth half-bridge circuit, and a sixth half-bridge circuit, wherein:

[0024] The first half-bridge circuit and the fourth half-bridge circuit constitute a first H-bridge circuit, which is used to provide a driving signal to the first load circuit;

[0025] The second half-bridge circuit and the fifth half-bridge circuit constitute a second H-bridge circuit, for providing a driving signal to the second load circuit;

[0026] The third half-bridge circuit and the sixth half-bridge circuit constitute a third H-bridge circuit, which is used to provide a driving signal to the third load circuit.

[0027] Through the above technical means, the first type of half-bridge circuit and the second type of half-bridge circuit are both arranged on the same driver chip to form multiple H-bridge circuits, providing drive signals to the load circuit. In this way, the MCU can drive multiple load circuits through one communication signal, reducing the GPIO resource occupation of the MCU.

[0028] In some embodiments, when at least one first-type half-bridge circuit is located on a first driver chip and at least one second-type half-bridge circuit is located on a second driver chip, the first driver chip includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, a fourth half-bridge circuit, a fifth half-bridge circuit, and a sixth half-bridge circuit, and at least one second driver chip includes a seventh half-bridge circuit, an eighth half-bridge circuit, a ninth half-bridge circuit, a tenth half-bridge circuit, an eleventh half-bridge circuit, and a twelfth half-bridge circuit, wherein:

[0029] The first half-bridge circuit and the second half-bridge circuit are connected as a first half-bridge circuit, the seventh half-bridge circuit and the eighth half-bridge circuit are connected as a fourth half-bridge circuit, and the first half-bridge circuit and the fourth half-bridge circuit constitute a first H-bridge circuit for providing a drive signal to the first load circuit;

[0030] The third half-bridge circuit and the fourth half-bridge circuit are connected to form a second half-bridge circuit, and the ninth half-bridge circuit and the tenth half-bridge circuit are connected to form a fifth half-bridge circuit. The second half-bridge circuit and the fifth half-bridge circuit constitute a second H-bridge circuit for providing a drive signal to the second load circuit.

[0031] The fifth half-bridge circuit is connected to the sixth half-bridge circuit as a third half-bridge circuit, the eleventh half-bridge circuit is connected to the twelfth half-bridge circuit as a sixth half-bridge circuit, and the third half-bridge circuit and the sixth half-bridge circuit constitute a third H-bridge circuit for providing a drive signal to the third load circuit.

[0032] Through this technical approach, when the current output by a single half-bridge circuit's drive signal fails to meet the load circuit's driving requirements, the arrangement of multiple half-bridge circuits is modified, increasing the upper limit of the current of the drive signal output by the driver control circuit to the load circuit. Furthermore, multiple driver chips are controlled via a single communication signal, reducing the MCU's GPIO resource usage.

[0033] In some embodiments, the driving circuit further includes a detection circuit, which is connected to the driving control circuit, wherein:

[0034] The detection circuit is used to detect the voltage and / or current of multiple output terminals on the driving circuit and send the obtained detection signals to the driving control circuit.

[0035] Through the above technical means, by integrating the detection circuit in the driver chip, the output drive signal is detected in voltage and / or current, and the detection process is automatically executed, thereby avoiding the impact of the abnormal output drive signal on the load circuit.

[0036] In some embodiments, the drive control circuit is further used to receive a detection signal, and when the detection signal indicates that an abnormality occurs at the output end of one of the half-bridge circuits, adjust the control signal corresponding to one of the half-bridge circuits to adjust the working state of one of the half-bridge circuits.

[0037] Through the above technical means, the detection signal is processed by the drive control circuit, and the abnormalities of multiple half-bridge circuits are automatically corrected, thereby reducing human intervention and lowering measurement costs.

[0038] In a second aspect, an embodiment of the present disclosure provides a control device, the control device comprising a controller and a drive circuit as in the first aspect, wherein:

[0039] A controller, configured to provide a communication signal to a drive circuit;

[0040] The drive circuit is used to receive a communication signal, control the operating state of the multiple half-bridge circuits according to the communication signal, and provide a drive signal to at least one load circuit according to the operating state of the multiple half-bridge circuits; wherein the drive signal of each load circuit is provided by at least two of the multiple half-bridge circuits.

[0041] Through the above technical means, the controller outputs one control signal, and the multiple half-bridge circuits in the drive circuit output multiple drive signals to drive the load circuit, thereby reducing the resource occupation of the controller's GPIO.

[0042] In some embodiments, when the multiple half-bridge circuits in the driving circuit are located on at least one driving chip, the communication terminals of the at least one driving chip are respectively connected to the communication terminals of the controller for receiving communication signals sent by the controller.

[0043] Through the above technical means, multiple driver chips reuse the communication signal and communication pin sent by the controller to drive multiple load circuits, reducing the GPIO resource occupation of the controller.

[0044] In a third aspect, an embodiment of the present disclosure provides a drive system, which includes a relay and a control device as in the second aspect, wherein the control device is used to control the switching state of the relay.

[0045] Through the above-mentioned technical means, the switching state of the relay is controlled by the control device. Compared with the control method of the combination of high-side chip and low-side chip in the related technology, the occupation of the controller GPIO resources in the control device is reduced, the complexity of the drive control circuit is reduced, and the control efficiency and anti-interference performance are improved.

[0046] The present disclosure provides a drive circuit, a control device, and a drive system. The drive control circuit converts communication signals input by an MCU into multiple control signals, which are then used to control multiple half-bridge circuits to output drive signals, thereby driving multiple load circuits. This eliminates the need for the MCU to output multiple hard-wired control signals, enabling the drive of multiple load circuits. This reduces resource usage on the MCU's GPIO interface, improves circuit control efficiency, reduces circuit complexity, and enhances circuit anti-interference capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram of a high-side and low-side driver workflow;

[0048] FIG2 is a schematic diagram of a structure of a driving circuit according to an embodiment of the present disclosure;

[0049] FIG3 is a second schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure;

[0050] FIG4 is a third structural diagram of a driving circuit provided in an embodiment of the present disclosure;

[0051] FIG5 is a fourth schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure;

[0052] FIG6 is a fifth structural diagram of a driving circuit provided in an embodiment of the present disclosure;

[0053] FIG7 is a sixth structural diagram of a driving circuit provided in an embodiment of the present disclosure;

[0054] FIG8 is a schematic diagram of the first structure of a control device provided by an embodiment of the present disclosure;

[0055] FIG9 is a second schematic diagram of the structure of a control device provided in an embodiment of the present disclosure;

[0056] FIG10 is a schematic diagram of the structural composition of a drive system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0059] In the following description, reference is made to "some embodiments," which describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. It should also be noted that the terms "first, second, and third" in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that the specific order or sequence of "first, second, and third" may be interchanged where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0060] In new energy vehicles, the BMS typically contains multiple load circuits, each driven by a set of high-side and low-side chips. A high-side driver typically consists of a high-side chip and a low-side chip. The high-side chip is a chip with a switching element located between the power supply and the load, while the low-side chip is a chip with a switching element located between the load and the common terminal. These chips can be used in scenarios such as relay driving, light-emitting diode (LED) driving, and optocoupler driving.

[0061] Figure 1 is a schematic diagram of the high-side and low-side driver workflow. For example, as shown in Figure 1, the high-side chipset 101 includes three high-side chips, and the low-side chipset 102 includes three low-side chips, forming three high-side and low-side driver groups to drive three load circuits in the load circuit group 103. The high-side and low-side driver workflow is described below. It will be appreciated that each high-side and low-side driver group is used to drive one load circuit in the load circuit group 103. Therefore, in actual use, the number of chips included in the high-side chipset 101 and the low-side chipset 102 can be set based on the number of load circuits to be driven in the load circuit group 103.

[0062] Referring to FIG1 , a high-side chipset 101 and a low-side chipset 102 jointly drive a load circuit group 103. The high-side chipset 101 and the low-side chipset 102 need to output multiple independent hard-wired control signals based on the MCU, including high-side drive signal 1, high-side drive signal 2, high-side drive signal 3, low-side drive signal 1, low-side drive signal 2, and low-side drive signal 3, to control the conduction and closure of multiple chips in the high-side chipset 101 and the low-side chipset 102. Each high-side chip in the high-side chipset 101 forms a high-side and low-side drive group with a low-side chip in the low-side chipset 102, respectively, for providing a high-side drive signal and a low-side drive signal to a load circuit in the load circuit group 103 to drive the load circuit.

[0063] As shown in Figure 1, the first high-side chip 1011 receives the high-side control signal 1, and the first low-side chip 1021 receives the low-side control signal 1, so that the first high-side chip 1011 sends a high-side drive signal 1 to the first load circuit 1031 according to the high-side control signal 1, and the first low-side chip 1021 sends the low-side drive signal 1 to the first load circuit 1031 to drive the first load circuit 1031; accordingly, the second high-side chip 1012 receives the high-side control signal 2 and outputs the high-side drive signal 2, and the second low-side chip 1022 receives the low-side control signal 2 and outputs the low-side drive signal 2 to drive the second load circuit 1032; the third high-side chip 1013 receives the high-side control signal 3 and outputs the high-side drive signal 3, and the third low-side chip 1023 receives the low-side control signal 3 and outputs the low-side drive signal 3 to drive the third load circuit 1033. It can be understood that when it is necessary to drive multiple load circuits in the load circuit group 103, it is necessary to control the high-side chipset 101 and the low-side chipset 102 to send multiple high-side drive signals and multiple low-side drive signals to drive the corresponding load circuits according to multiple hard-wired control signals. This way of driving the load circuits occupies a large amount of resources of the GPIO interface of the MCU.

[0064] Based on the above technical problems, the embodiments of the present disclosure provide a drive circuit, a control device, and a drive system. These drive control circuits can convert communication signals input from an MCU into multiple control signals, control multiple half-bridge circuits to output drive signals, and serve as drivers for multiple load circuits. This eliminates the need for the MCU to output multiple hard-wired control signals, enabling the drive of multiple load circuits. This reduces resource usage on the MCU's GPIO interface, improves circuit control efficiency, reduces circuit complexity, and enhances the circuit's anti-interference capabilities.

[0065] The present disclosure is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0066] FIG2 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure. As shown in FIG2 , the driving circuit 20 includes a driving control circuit 201 and a multi-way half-bridge circuit 202 , wherein the output end of the driving control circuit 201 is connected to the multi-way half-bridge circuit 202 .

[0067] The drive control circuit 201 is used to receive communication signals and output multiple control signals.

[0068] The drive control circuit 201 may be a unit with data processing function in the drive circuit 20 , and may also be called a control logic module, which is used to perform logic judgment according to the level state of the communication signal input by the MCU and output corresponding multiple control signals.

[0069] The MCU can connect to the drive circuit 20 via a synchronous serial communication interface (Serial Peripheral Interface, SPI) and output communication signals to the drive circuit. As shown in Figure 2, after the drive circuit 20 receives the communication signal sent by the MCU, the drive control circuit 201 processes the communication signal to generate multiple control signals, which are respectively input to the multiple half-bridge circuits 202 connected to the drive control circuit 201, including the first half-bridge circuit 2021, the second half-bridge circuit 2022, ..., and the Nth half-bridge circuit 2023, to control the operating state of each half-bridge circuit in the multiple half-bridge circuits 202.

[0070] The multiple half-bridge circuit 202 is configured to determine the operating state of the multiple half-bridge circuit 202 based on the multiple control signals, and to provide a drive signal to at least one load circuit 30 based on the operating state of the multiple half-bridge circuit 202; wherein the drive signal for each load circuit in the at least one load circuit 30 is provided by at least two items in the multiple half-bridge circuit 202.

[0071] As shown in FIG2 , the multiple half-bridge circuits 202 may include a first half-bridge circuit 2021, a second half-bridge circuit 2022, ..., an N-1th half-bridge circuit 2023, an Nth half-bridge circuit 2024, and other half-bridge circuits having the same structure, where N is an even number greater than 1. It will be appreciated that the specific number of half-bridge circuits can be determined based on the requirements of the load circuit and is not specifically limited herein.

[0072] A half-bridge circuit can be a structure composed of two power switching devices, capable of determining different operating states based on the control signal output by the drive control circuit 201, outputting a high-side drive signal or a low-side drive signal, and driving at least one load circuit 30. As in the above embodiment, the operating state of the half-bridge circuit can be determined based on the control signal, and different operating states can output different drive signals. For example, when the control signal is at a high level, the half-bridge circuit is in a first operating state and can provide multiple high-side drive signals to the at least one load circuit 30; when the control signal is at a low level, the half-bridge circuit is in a second operating state and can provide multiple low-side drive signals to the at least one load circuit 30.

[0073] For example, referring to FIG. 2 , based on the control signal from the drive control circuit 201, the first half-bridge circuit 2021 and the second half-bridge circuit 2022 can be in a first operating state, providing a high-side drive signal to at least one load circuit 30; the (N-1)th half-bridge circuit 2023 and the (N)th half-bridge circuit 2024 can be in a second operating state, providing a low-side drive signal to at least one load circuit 30. The first half-bridge circuit 2021 and the (N-1)th half-bridge circuit 2023 form a high-side and low-side drive pair, providing a high-side drive signal and a low-side drive signal to a corresponding load circuit in the at least one load circuit 30; the second half-bridge circuit 2022 and the (N)th half-bridge circuit 2024 form a high-side and low-side drive pair, providing a high-side drive signal and a low-side drive signal to a corresponding load circuit in the at least one load circuit 30. It can be understood that the multiple half-bridge circuits between the second half-bridge circuit 2022 and the N-1th half-bridge circuit 2023 can also form multiple groups of high and low side drivers in pairs to provide high side drive signals and low side drive signals to the corresponding load circuit in at least one load circuit 30.

[0074] It should be noted that FIG2 illustrates only one connection method between the drive circuit and the load circuit. As the number of half-bridge circuits in the drive circuit increases or decreases, the number of load circuits will also increase or decrease accordingly. Furthermore, depending on the relationship between the current drive requirements of the drive circuit and the load circuit, the same load circuit can be driven by two half-bridge circuits, i.e., a set of high-side and low-side drivers, or by multiple half-bridge circuits, i.e., multiple sets of high-side and low-side drivers, provided that at least one half-bridge circuit is used to generate a high-side drive signal and one half-bridge circuit is used to generate a low-side drive signal.

[0075] An embodiment of the present disclosure provides a driving circuit. By using a driving circuit including a driving control circuit and a multi-channel half-bridge circuit as a driver for a load circuit, a communication signal is converted into a multi-channel control signal. Multiple load circuits can be driven without the need for the MCU to output multiple hard-wired control signals, thereby reducing the resource occupation of the MCU's GPIO interface, improving the control efficiency of the circuit, reducing the complexity of the circuit, and improving the circuit's anti-interference ability.

[0076] In another embodiment of the present disclosure, FIG3 is a second schematic diagram of the structure of a driving circuit provided in the embodiment of the present disclosure. As shown in FIG2 , the driving circuit 20 is provided with a plurality of output terminals 203 , wherein:

[0077] Each half-bridge circuit corresponds to an output terminal, and at least two output terminals among the multiple output terminals 203 are connected to at least one load circuit 30 . The at least two output terminals are used to provide corresponding driving signals to the load circuit.

[0078] The driver circuit 20 may be a circuit composed of at least one driver chip, wherein the output terminal of the driver circuit 20 may refer to a connection terminal extending from the at least one driver chip to a peripheral circuit. It should be noted that the multiple output terminals 203 of the output circuit may be provided by a single driver chip or by multiple driver chips.

[0079] As shown in FIG3 , each half-bridge circuit is connected to a corresponding output terminal for outputting a high-side drive signal or a low-side drive signal to a load circuit via the corresponding output terminal. For example, the first half-bridge circuit 2051 is connected to the first output terminal 2031 for outputting a high-side drive signal, the (K+1)th half-bridge circuit 2061 is connected to the (K+1)th output terminal 2034 for outputting a low-side drive signal, and the first output terminal 2031 and the (K+1)th output terminal 2034 are connected to the first load circuit 301 for inputting the high-side drive signal and the low-side drive signal, respectively, to the first load circuit 301. Correspondingly, the second output terminal 2032 corresponds to the second half-bridge circuit 2052, and the K+2 output terminal 2035 corresponds to the K+2 half-bridge circuit 2062, which are respectively used to output a high-side drive signal and a low-side drive signal to the second load circuit 302; the Kth output terminal 2033 corresponds to the Kth half-bridge circuit 2053, and the K+Kth output terminal 2036 corresponds to the K+Kth half-bridge circuit 2063, which are respectively used to output a high-side drive signal to the Kth load circuit 303.

[0080] It is understood that multiple half-bridge circuits may be included between the second half-bridge circuit 2052 and the Kth half-bridge circuit 2053, corresponding to the multiple output terminals and outputting multiple high-side drive signals to the at least one load circuit 30. Multiple half-bridge circuits may be included between the K+2th half-bridge circuit 2062 and the K+Kth half-bridge circuit 2063, corresponding to the multiple output terminals and outputting multiple low-side drive signals to the at least one load circuit 30. K is an integer greater than 1, and its specific number can be set based on the number and requirements of the at least one load circuit 30.

[0081] It should be noted that, based on the current demand of at least one load circuit 30 for the driving signal, the same load circuit can be connected to more than two output terminals, and the driving signal can be provided by more than two half-bridge circuits corresponding to the more than two output terminals. It is not limited to the case where two output terminals are connected to the same load circuit as shown in Figure 3.

[0082] As in the above embodiment, the MCU provides a communication signal to the driving circuit 20 via an SPI. As shown in FIG3 , the driving circuit 20 may also be provided with an input terminal for receiving the communication signal provided by the MCU.

[0083] It should be noted that the driver circuit 20 may be a circuit composed of at least one driver chip. Therefore, the input terminals of the driver circuit 20 may refer to terminals provided on at least one driver chip for connection to the MCU. It should be noted that the input terminals on each driver chip are connected to communication pins of the MCU, thereby reducing the MCU's GPIO resource usage.

[0084] In some embodiments, referring to FIG. 3 , the driving circuit 20 includes at least one first-type half-bridge circuit 205 and at least one second-type half-bridge circuit 206 .

[0085] The at least one first-type half-bridge circuit 205 is used to provide a first-type driving signal to the at least one load circuit 30 ; and the at least one second-type half-bridge circuit 206 is used to provide a second-type driving signal to the at least one load circuit.

[0086] In the embodiment of the present disclosure, the first type of driving signal may be a high-side driving signal, and the second type of driving signal may be a low-side driving signal.

[0087] As shown in Figure 3, the multiple half-bridge circuits in the driving circuit 20 can be divided into a first type of half-bridge circuit and a second type of half-bridge circuit, wherein at least one first type of half-bridge circuit 205 can include a first half-bridge circuit 2051, a second half-bridge circuit 2052, ..., and a Kth half-bridge circuit 2053, all of which are used to output high-side drive signals; at least one second type of half-bridge circuit 206 can include a K+1th half-bridge circuit 2061, a K+2th half-bridge circuit 2062, ..., and a K+Kth half-bridge circuit 2063, all of which are used to output low-side drive signals.

[0088] Each half-bridge circuit in the first and second half-bridge circuits can have the same structure, exemplarily consisting of two gate drive modules and two NMOS transistors. Whether a half-bridge circuit belongs to the first or second half-bridge circuit can be determined by the control signal received and the drive signal output by the half-bridge circuit. For example, as shown in FIG3 , the control signal sent by the drive control circuit 201 to the first half-bridge circuit 2051 , the second half-bridge circuit 2052 , ..., and the Kth half-bridge circuit 2053 is high, causing the multiple first-class half-bridge circuits 205 to respectively send high-side drive signals to the first load circuit 301 , the second load circuit 302 , and the third load circuit 303 . The control signal sent by the drive control circuit 201 to the K+1th half-bridge circuit 2061 , the K+2th half-bridge circuit 2062 , ..., and the K+Kth half-bridge circuit 2063 is low, causing the aforementioned half-bridge circuits to respectively send low-side drive signals to the first load circuit 301 , the second load circuit 302 , and the third load circuit 303 . Therefore, in the embodiment of the present disclosure, the first half-bridge circuit 2051, the second half-bridge circuit 2052, ..., the Kth half-bridge circuit 2053 can be first-type half-bridge circuits, and the K+1th half-bridge circuit 2061, the K+2th half-bridge circuit 2062, ..., the K+Kth half-bridge circuit 2063 can be second-type half-bridge circuits.

[0089] In some embodiments, at least one first-type half-bridge circuit 205 and at least one second-type half-bridge circuit 206 are located on the same driver chip; or, at least one first-type half-bridge circuit 205 is located on at least one first driver chip, and at least one second-type half-bridge circuit 206 is located on at least one second driver chip.

[0090] As in the aforementioned embodiment, the drive circuit 20 may be composed of multiple driver chips, each of which may include multiple half-bridge circuits. It should be noted that the drive circuit 20 may include only one type of driver chip, wherein a portion of the multiple half-bridge circuits on each driver chip may be configured as first-type half-bridge circuits 205, and the remaining portion may be configured as second-type half-bridge circuits 206. The drive circuit 20 may also include two types of driver chips: first and second driver chips, wherein the multiple half-bridge circuits in each first driver chip may be configured as first-type half-bridge circuits 205, and the multiple half-bridge circuits in each second driver chip may be configured as second-type half-bridge circuits 206.

[0091] It can be understood that the number of half-bridge circuits included in the first type of half-bridge circuit 205 and the number of half-bridge circuits included in the second type of half-bridge circuit 206 can be the same.

[0092] An embodiment of the present disclosure provides a drive circuit, comprising at least one first-type half-bridge circuit and at least one second-type half-bridge circuit, which respectively provide a high-side drive signal and a low-side drive signal to a load circuit. In addition, the first-type half-bridge circuit and the second-type half-bridge circuit can be arranged on the same drive chip or on different drive chips, thereby being able to meet the current requirements of different load circuits and improving the flexibility of the drive circuit.

[0093] In another embodiment of the present disclosure, FIG4 is a third schematic diagram of the structure of a driver circuit provided in an embodiment of the present disclosure. As shown in FIG4 , when at least one first-type half-bridge circuit 205 and at least one second-type half-bridge circuit 206 are located on the same driver chip 207, the at least one first-type half-bridge circuit 205 includes a first half-bridge circuit 2051, a second half-bridge circuit 2052, and a third half-bridge circuit 2053, and the at least one second-type half-bridge circuit 206 includes a fourth half-bridge circuit 2061, a fifth half-bridge circuit 2062, and a sixth half-bridge circuit 2063.

[0094] As shown in FIG4 , in the embodiment of the present disclosure, a driver circuit 20 is described as including one driver chip 207, and the driver chip 207 includes six half-bridge circuits. It will be appreciated that the driver circuit 20 may include multiple driver chips 207 , each of which may include multiple half-bridge circuits, each of which may include at least one first-type half-bridge circuit and one second-type half-bridge circuit. The number of half-bridge circuits may be determined based on the number and requirements of the at least one load circuit 30 .

[0095] Among them, the first half-bridge circuit 2051 and the fourth half-bridge circuit 2061 constitute a first H-bridge circuit, which is used to provide a driving signal to the first load circuit 301; the second half-bridge circuit 2052 and the fifth half-bridge circuit 2062 constitute a second H-bridge circuit, which is used to provide a driving signal to the second load circuit 302; the third half-bridge circuit 2053 and the sixth half-bridge circuit 2063 constitute a third H-bridge circuit, which is used to provide a driving signal to the third load circuit 303.

[0096] As in the aforementioned embodiments, each half-bridge circuit can be composed of two gate drive modules and two NMOS transistors. As shown in FIG4 , taking the first half-bridge circuit 2051 as an example, one end of each of the two gate drive modules is connected to the drive control circuit 201, and the other ends of the two gate drive modules are respectively connected to the gate terminals of the two NMOS transistors. Furthermore, of the two NMOS transistors, the drain terminal of the first NMOS transistor is connected to the first power supply terminal 2081, the source terminal of the first NMOS transistor is connected to the drain terminal of the second NMOS transistor, and the source terminal of the second NMOS transistor is grounded. It should be noted that the internal connections of the second half-bridge circuit 2052, the third half-bridge circuit 2053, the fourth half-bridge circuit 2061, the fifth half-bridge circuit 2062, and the sixth half-bridge circuit 2063 are similar to those of the first half-bridge circuit 2051 and will not be described in detail here.

[0097] In the embodiment of the present disclosure, the first H-bridge circuit, the second H-bridge circuit, and the third H-bridge circuit can each be a set of high-side and low-side drivers, and each H-bridge circuit provides a high-side drive signal and a low-side drive signal to the same load circuit. For example, the first half-bridge circuit 2051 provides a high-side drive signal to the first load circuit 301, and the fourth half-bridge circuit 2061 provides a low-side drive signal to the first load circuit 301, for driving the first load circuit 301; the second half-bridge circuit 2052 provides a high-side drive signal to the second load circuit 302, and the fifth half-bridge circuit 2062 provides a low-side drive signal to the second load circuit 302, for driving the second load circuit 302; the third half-bridge circuit 2053 provides a high-side drive signal to the third load circuit 303, and the third load circuit 303 provides a low-side drive signal to the third load circuit 303, for driving the third load circuit 303.

[0098] It is understood that if the driver chip 207 includes more than six half-bridge circuits, multiple H-bridge circuits can be formed as shown in FIG4 to provide drive signals to at least one load circuit 30. In addition, the same H-bridge circuit can also include more than two half-bridge circuits.

[0099] As in the aforementioned embodiment, each driver chip may include multiple input terminals 204. As shown in FIG4 , the multiple input terminals 204 include: an SO input terminal 2041, an SI input terminal 2042, a CLK input terminal 2043, and a CS input terminal 2044. The SO input terminal 2041 is a host input / slave output interface for transmitting data related to the execution status of the driver circuit 20 back to the MCU; the SI input terminal 2042 is a host output / slave input interface for transmitting communication signals from the MCU to the driver circuit 20; the CLK input terminal 2043 is a clock synchronization interface for synchronizing the clocks of multiple driver chips in the driver circuit 20 via a clock signal; and the CS input terminal 2044 is a chip select interface for determining which driver chip in the driver circuit 20 is to be controlled via a chip select signal from the MCU.

[0100] It can be understood that FIG4 illustrates the connection method of multiple input terminals 204 by taking the driving circuit 20 including one driving chip as an example. If the driving circuit 20 includes multiple driving chips, each driving chip has multiple input terminals 204 as shown in FIG4 for receiving communication signals.

[0101] It should be noted that the drive circuit 20 may further include multiple power supply terminals, all of which are connected to an external power supply, so that the power supply supplies power to the multiple half-bridge circuits in the drive circuit 20 through the multiple power supply terminals. For example, as shown in FIG4 , the multiple power supply terminals may include a first power supply terminal 2081 and a second power supply terminal 2082. It is understood that each driver chip in the drive circuit 20 may be provided with at least one power supply terminal connected to the power supply. In addition, the power supply voltages connected to the first power supply terminal 2081 and the second power supply terminal 2082 may be the same or different, depending on the specific power supply voltage requirements of the driver chip.

[0102] An embodiment of the present disclosure provides a driving circuit, in which a first-type half-bridge circuit and a second-type half-bridge circuit are both arranged on the same driver chip to form multiple H-bridge circuits, which provide driving signals to the load circuit. In this way, the MCU can drive multiple load circuits through one communication signal, reducing the GPIO resource occupation of the MCU.

[0103] It is understood that the drive circuit includes a driver chip, with multiple half-bridge circuits on the driver chip forming multiple H-bridge circuits in pairs. Within each H-bridge circuit, one first-type half-bridge circuit outputs a high-side drive signal, while another second-type half-bridge circuit outputs a low-side drive signal to drive a load circuit. However, there may be situations where the current limit of the drive signal output by one half-bridge circuit does not meet the load circuit's drive requirements. This necessitates connecting the drive signals from multiple half-bridge circuits in parallel to provide a higher drive current to drive the same load circuit.

[0104] In another embodiment of the present disclosure, FIG5 is a fourth schematic diagram of the structure of a driver circuit provided in an embodiment of the present disclosure. As shown in FIG5 , when at least one first-type half-bridge circuit is located on a first driver chip 208 and at least one second-type half-bridge circuit is located on a second driver chip 209, the first driver chip 208 includes a first half-bridge circuit 2051, a second half-bridge circuit 2052, a third half-bridge circuit 2053, a fourth half-bridge circuit 2054, a fifth half-bridge circuit 2055, and a sixth half-bridge circuit 2056. The at least one second driver chip 209 includes a seventh half-bridge circuit 2061, an eighth half-bridge circuit 2062, a ninth half-bridge circuit 2063, a tenth half-bridge circuit 2064, an eleventh half-bridge circuit 2065, and a twelfth half-bridge circuit 2066.

[0105] As in the aforementioned embodiment, determining whether a half-bridge circuit belongs to the first or second category of half-bridge circuits can be determined by the control signals received and the drive signals output by the half-bridge circuit. The multiple half-bridge circuits on the first driver chip 208 can be configured as first category half-bridge circuits, configured to output multiple high-side drive signals to at least one load circuit 30 upon receiving a high-level control signal from the driver control circuit 201. The multiple half-bridge circuits on the second driver chip 209 can be configured as second category half-bridge circuits, configured to output multiple low-side drive signals to at least one load circuit 30 upon receiving a low-level control signal from the driver control circuit 201. It will be appreciated that the number of first driver chips 208 and second driver chips 209 in the driver circuit 20 can be determined based on the number and requirements of the load circuits.

[0106] Among them, the first half-bridge circuit 2051 and the second half-bridge circuit 2052 are connected as a first side half-bridge circuit, the seventh half-bridge circuit 2061 and the eighth half-bridge circuit 2062 are connected as a fourth side half-bridge circuit, and the first side half-bridge circuit and the fourth side half-bridge circuit constitute a first H-bridge circuit, which is used to provide a driving signal to the first load circuit 301.

[0107] In the disclosed embodiment, the first half-bridge circuit 2051 and the second half-bridge circuit 2052 are both first-type half-bridge circuits. They output high-side drive signals through the first output terminal 2031 and the second output terminal 2032, respectively, which are then connected in parallel to the first load circuit 301. The seventh half-bridge circuit 2061 and the eighth half-bridge circuit 2062 are both second-type half-bridge circuits. They output low-side drive signals through the seventh output terminal 2037 and the eighth output terminal 2038, respectively, which are then connected in parallel to the first load circuit 301. Thus, the four half-bridge circuits are connected in parallel, forming a first H-bridge circuit, i.e., a set of high-side and low-side drivers, for driving the first load circuit 301.

[0108] Among them, the third half-bridge circuit 2053 and the fourth half-bridge circuit 2054 are connected as the second half-bridge circuit, the ninth half-bridge circuit 2063 and the tenth half-bridge circuit 2064 are connected as the fifth half-bridge circuit, and the second half-bridge circuit and the fifth half-bridge circuit constitute a second H-bridge circuit, which is used to provide a driving signal to the second load circuit 302.

[0109] In the disclosed embodiment, the third half-bridge circuit 2053 and the fourth half-bridge circuit 2054 are both first-type half-bridge circuits. They output high-side drive signals through the third output terminal 2033 and the fourth output terminal 2034, respectively, which are then connected in parallel to the second load circuit 302. The ninth half-bridge circuit 2063 and the tenth half-bridge circuit 2064 are both second-type half-bridge circuits. They output low-side drive signals through the ninth output terminal 2039 and the tenth output terminal 20310, respectively, which are then connected in parallel to the second load circuit 302. Thus, the four half-bridge circuits are connected in parallel, forming a second H-bridge circuit, i.e., a set of high-side and low-side drivers, for driving the second load circuit 302.

[0110] Among them, the fifth half-bridge circuit 2055 and the sixth half-bridge circuit 2056 are connected as a third half-bridge circuit, the eleventh half-bridge circuit 2065 and the twelfth half-bridge circuit 2066 are connected as a sixth half-bridge circuit, and the third half-bridge circuit and the sixth half-bridge circuit constitute a third H-bridge circuit, which is used to provide a driving signal to the third load circuit 303.

[0111] In the disclosed embodiment, the fifth and sixth half-bridge circuits 2055 and 2056 are both first-type half-bridge circuits. They output high-side drive signals through their fifth and sixth output terminals 2035 and 2036, respectively, which are then connected in parallel to the third load circuit 303. The eleventh and twelfth half-bridge circuits 2065 and 2066 are both second-type half-bridge circuits. They output low-side drive signals through their eleventh and twelfth output terminals 20311 and 20312, respectively, which are then connected in parallel to the third load circuit 303. Thus, the four half-bridge circuits are connected in parallel, forming a third H-bridge circuit, i.e., a set of high-side and low-side drivers, for driving the third load circuit 303.

[0112] It can be understood that according to the changes in the current demand of the load circuit for the driving signal and the current upper limit of the driving signal output by each half-bridge circuit, the corresponding relationship between the number of half-bridge circuits and load circuits in the driving chip can be adjusted accordingly, and is not limited to the connection method in the above embodiment.

[0113] In addition, as shown in Figure 5, each first-type driver chip 208 and each second-type driver chip 209 in the driver circuit may include multiple input terminals 204, and the multiple input terminals 204 on different driver chips may be connected to the same group of communication interfaces of the MCU for receiving communication signals sent by the MCU.

[0114] The disclosed embodiments provide a driver circuit that, when the current output by a single half-bridge circuit fails to meet the load circuit's driving requirements, changes the layout of multiple half-bridge circuits to increase the upper current limit of the drive signal output by the driver control circuit to the load circuit. Furthermore, multiple driver chips are controlled via a single communication signal, reducing MCU GPIO resource usage.

[0115] In another embodiment of the present disclosure, as shown in FIG. 6 and FIG. 7 , the driving circuit 20 further includes a detection circuit 2010 , which is connected to the driving control circuit 20 .

[0116] In the embodiment of the present disclosure, FIG5 takes an example in which the driving circuit 20 includes a single driving chip 207, and FIG6 takes an example in which the driving circuit 20 includes a first driving chip 208 and a second driving chip 209, to illustrate the operating principle and connection method of the detection circuit 2010 in the driving circuit 20. It will be understood that when the driving circuit 20 includes multiple driving chips, a detection circuit 2010 can also be provided in each driving chip, and the operating principle and connection method of the detection circuit 2010 are the same as those of the detection circuit 2010 in FIG6 and FIG7 above.

[0117] The detection circuit 2010 is used to detect voltage and / or current on multiple output terminals of the driving circuit 20 and send the obtained detection signals to the driving control circuit 201 .

[0118] FIG6 is a fifth schematic diagram of the structure of a driver circuit provided by an embodiment of the present disclosure. Referring to FIG6 , when the driver circuit 20 includes a driver chip 207, the detection circuit 2010 can be disposed within the driver chip 207. By connecting to multiple output terminals on the driver chip 207 or directly connecting to the lines through which the multiple half-bridge circuits in the driver chip 207 output drive signals, the detection circuit 2010 obtains the high-side drive signals or low-side drive signals output by the multiple half-bridge circuits in the driver chip 207, performs voltage and / or current detection, and generates a detection signal based on the detection results.

[0119] FIG7 is a sixth schematic diagram of the structure of a drive circuit provided by an embodiment of the present disclosure. Referring to FIG7 , when the drive circuit 20 includes a first driver chip 208 and a second driver chip 209, a detection circuit 2010 may be provided in the first driver chip 208, and a detection circuit 2010 may be provided in the second driver chip 209. The detection circuit 2010 is connected to multiple output terminals provided on the first driver chip 208, and may also be connected to the circuits through which the multiple half-bridge circuits in the first driver chip 208 output drive signals. It performs voltage and / or current detection on the multiple output terminals of the first driver chip 208, determines the location and type of the fault, and generates a detection signal. Correspondingly, the detection circuit 2010 is connected to multiple output terminals provided on the second driver chip 209, and may also be connected to the circuits through which the multiple half-bridge circuits in the second driver chip 209 output drive signals. It performs voltage and / or current detection on the multiple output terminals of the second driver chip 209, determines the location and type of the fault, and generates a detection signal.

[0120] Exemplarily, the fault types that can be determined may include: overcurrent, open load, short circuit, undervoltage lockout, overvoltage lockout, thermal shutdown, etc.

[0121] The detection circuit 3010 can detect whether the voltage and / or current of the driving signal output from the output end of the driver chip is within a preset range, and based on the detection result, generate a normal detection signal or an abnormal detection signal and send it to the driver control circuit 201 in the driver chip for processing.

[0122] Furthermore, the drive control circuit 201 may also send the detection signal to the MCU through the SO output terminal 2041 , so that the MCU triggers a corresponding protection mechanism.

[0123] In some embodiments, the drive control circuit 201 is further used to receive a detection signal, and when the detection signal indicates that an abnormality occurs at the output end of one of the half-bridge circuits, adjust the control signal corresponding to one of the half-bridge circuits to adjust the working state of one of the half-bridge circuits.

[0124] In the disclosed embodiment, after the detection circuit 2010 in the driver chip performs voltage and / or current detection on the drive signal output by each output terminal, it can number the output terminal where the abnormality occurs and notify the driver control circuit 201 so that the driver control circuit 201 can make corresponding adjustments. For example, referring to FIG6 , if the first half-bridge circuit 2051 should output a high-side drive signal through the first output terminal 2031, but the detection circuit 3010 detects that the drive signal output by the first output terminal 2031 is not a high-side drive signal, the abnormality can be added to the detection signal and sent to the driver control circuit 201, causing the driver control circuit 201 to adjust the control signal sent to the first half-bridge circuit 2051, thereby adjusting the operating state of the first half-bridge circuit 2051 so that it outputs a high-side drive signal.

[0125] In related technologies, high-side and low-side driver modules often function solely as switches, lacking comprehensive real-time fault detection and judgment capabilities, requiring additional circuitry for detection and strategic protection. The disclosed embodiments provide a driver circuit that integrates detection circuitry within the driver chip to perform voltage and / or current detection on the output drive signal, automatically executing the detection process and providing an automatic correction function. This reduces human intervention, lowers measurement costs, and prevents the impact of abnormal output drive signals on the load circuit.

[0126] In another embodiment of the present disclosure, Figure 8 is a schematic diagram of the structure of a control device 4 provided in the embodiment of the present disclosure. As shown in Figure 8, the control device 4 includes a controller 40 and the drive circuit 20 in the above embodiment.

[0127] The controller 40 is used to provide a communication signal to the driving circuit 20 .

[0128] In the embodiment of the present disclosure, FIG8 illustrates the connection between the driver circuit 20 and the controller, using the example of a driver circuit 20 including a single driver chip. The controller 40 is connected to the multiple input terminals 204 of each driver chip in the driver circuit via an SPI interface, and outputs communication signals to the driver circuit 20 via a communication interface 401. The controller 40 inputs a clock signal to the CLK input terminal 2042 of the driver circuit 20 via a CLK communication interface 4012, inputs a chip select signal to the CS input terminal 2043 of the driver circuit 20 via a CS communication interface 4013, and inputs a control signal to the SI input terminal 2044 of the driver circuit 20 via an SI communication interface 4014.

[0129] The drive circuit 20 is used to receive communication signals, control the operating status of the multiple half-bridge circuits based on the communication signals, and provide a drive signal to at least one load circuit 30 based on the operating status of the multiple half-bridge circuits; wherein the drive signal for each load circuit 30 is provided by at least two of the multiple half-bridge circuits.

[0130] As in the previous embodiment, after the drive circuit 20 receives a communication signal, the drive control circuit 201 processes the communication signal to generate multiple control signals, which are then sent to each half-bridge circuit to control the operating state of the multiple half-bridge circuits. Furthermore, at least two of the multiple half-bridge circuits form an H-bridge circuit, which provides drive signals to the corresponding load circuits.

[0131] In some embodiments, FIG9 is a second schematic diagram of the structure of a control device 4 provided in an embodiment of the present disclosure. When the multiple half-bridge circuits in the driver circuit 20 are located on at least one driver chip, the communication terminals of at least one driver chip are respectively connected to the communication terminals of the controller for receiving communication signals sent by the controller.

[0132] In the embodiment of the present disclosure, FIG9 takes the example of a driver circuit 20 including two driver chips to illustrate the connection method between the driver circuit 20 and the controller. As shown in FIG8 , the multiple input terminals 204 of the driver chip 208 and the multiple input terminals 204 of the driver chip 209 are all connected to the same group of communication interfaces 401 of the controller 40. It will be understood that when the driver circuit includes multiple driver chips, the SO input terminal of each driver chip is connected to the SO communication interface 4011 of the controller 40, the CLK input terminal of each driver chip is connected to the CLK communication interface 4012 of the controller 40, the CS input terminal of each driver chip is connected to the CS communication interface 4013 of the controller 40, and the SI input terminal of each driver chip is connected to the SI communication interface 4014 of the controller 40.

[0133] An embodiment of the present disclosure provides a control device, in which a controller outputs a control signal, and multiple half-bridge circuits in a driving circuit output multiple drive signals to drive a load circuit, thereby achieving the effect of multiplexing one communication signal of the controller and reducing the resource occupation of the controller's GPIO.

[0134] In another embodiment of the present disclosure, FIG10 is a schematic diagram of the structure of a drive system 5 provided in an embodiment of the present disclosure. As shown in FIG10 , the drive system 5 includes a relay 50 and the control device 4 of the aforementioned embodiment, wherein the control device 4 is used to control the on / off state of the relay 50.

[0135] It should be noted that the relay 50 may be the load circuit in the aforementioned embodiment, and the control device 4 controls the on or off of the relay 50 by sending a high-side drive signal or a low-side drive signal to the relay 50 .

[0136] An embodiment of the present disclosure provides a drive system that controls the switching state of a relay through a control device. Compared with the control method of a combination of a high-side chip and a low-side chip in related technologies, it reduces the occupation of the controller GPIO resources in the control device, reduces the complexity of the drive control circuit, and improves the control efficiency and anti-interference performance.

[0137] It should be understood that "one embodiment" or "an embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other. For the sake of brevity, they will not be repeated here.

[0138] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0139] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0140] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0142] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0143] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. Industrial Applicability

[0144] The present disclosure provides a drive circuit, a control device, and a drive system. The drive control circuit converts communication signals input by an MCU into multiple control signals, which are then used to control multiple half-bridge circuits to output drive signals, thereby driving multiple load circuits. This eliminates the need for the MCU to output multiple hard-wired control signals, enabling the drive of multiple load circuits. This reduces resource usage on the MCU's GPIO interface, improves circuit control efficiency, reduces circuit complexity, and enhances circuit anti-interference capabilities.

Claims

1. A driving circuit, comprising a driving control circuit and a multi-channel half-bridge circuit, wherein an output end of the driving control circuit is connected to the multi-channel half-bridge circuit, wherein: The drive control circuit is used to receive communication signals and output multiple control signals; The multi-channel half-bridge circuit is used to determine the working state of the multi-channel half-bridge circuit according to the multi-channel control signal, and provide a driving signal to at least one load circuit according to the working state of the multi-channel half-bridge circuit; wherein the driving signal of each load circuit is provided by at least two items of the multi-channel half-bridge circuit.

2. The driving circuit according to claim 1, wherein: The driving circuit is provided with a plurality of output terminals, wherein: Each of the half-bridge circuits corresponds to one of the output ends, and at least two of the multiple output ends are connected to the load circuit, and the at least two output ends are used to provide corresponding driving signals to the load circuit.

3. The driving circuit according to claim 1 or 2, wherein: The driving circuit includes at least one first-type half-bridge circuit and at least one second-type half-bridge circuit, wherein: The at least one first-type half-bridge circuit is used to provide a first-type driving signal to the at least one load circuit; The at least one second type half-bridge circuit is used to provide a second type driving signal to the at least one load circuit.

4. The driving circuit according to claim 3, wherein: The first type of driving signal is a high-side driving signal, and the second type of driving signal is a low-side driving signal.

5. The driving circuit according to claim 3 or 4, wherein: The at least one first-type half-bridge circuit and the at least one second-type half-bridge circuit are located on the same driver chip; or, The at least one first-type half-bridge circuit is located on at least one first driving chip, and the at least one second-type half-bridge circuit is located on at least one second driving chip.

6. The driving circuit according to claim 5, wherein: When the at least one first-type half-bridge circuit and the at least one second-type half-bridge circuit are located on the same driver chip, the at least one first-type half-bridge circuit includes a first half-bridge circuit, a second half-bridge circuit, and a third half-bridge circuit, and the at least one second-type half-bridge circuit includes a fourth half-bridge circuit, a fifth half-bridge circuit, and a sixth half-bridge circuit, wherein: The first half-bridge circuit and the fourth half-bridge circuit constitute a first H-bridge circuit, which is used to provide a driving signal to a first load circuit; The second half-bridge circuit and the fifth half-bridge circuit constitute a second H-bridge circuit, which is used to provide a driving signal to a second load circuit; The third half-bridge circuit and the sixth half-bridge circuit constitute a third H-bridge circuit, which is used to provide a driving signal to a third load circuit.

7. The driving circuit according to claim 5, wherein: When the at least one first-type half-bridge circuit is located on a first driver chip, and the at least one second-type half-bridge circuit is located on a second driver chip, the first driver chip includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, a fourth half-bridge circuit, a fifth half-bridge circuit, and a sixth half-bridge circuit, and the at least one second driver chip includes a seventh half-bridge circuit, an eighth half-bridge circuit, a ninth half-bridge circuit, a tenth half-bridge circuit, an eleventh half-bridge circuit, and a twelfth half-bridge circuit, wherein: The first half-bridge circuit is connected to the second half-bridge circuit as a first half-bridge circuit, the seventh half-bridge circuit is connected to the eighth half-bridge circuit as a fourth half-bridge circuit, and the first half-bridge circuit and the fourth half-bridge circuit constitute a first H-bridge circuit for providing a driving signal to a first load circuit; The third half-bridge circuit is connected to the fourth half-bridge circuit as a second half-bridge circuit, the ninth half-bridge circuit is connected to the tenth half-bridge circuit as a fifth half-bridge circuit, and the second half-bridge circuit and the fifth half-bridge circuit constitute a second H-bridge circuit for providing a driving signal to a second load circuit; The fifth half-bridge circuit is connected to the sixth half-bridge circuit as a third side half-bridge circuit, the eleventh half-bridge circuit is connected to the twelfth half-bridge circuit as a sixth side half-bridge circuit, and the third side half-bridge circuit and the sixth side half-bridge circuit constitute a third H-bridge circuit for providing a driving signal to a third load circuit.

8. The driving circuit according to any one of claims 2 to 7, wherein: The driving circuit further includes a detection circuit, which is connected to the driving control circuit, wherein: The detection circuit is used to perform voltage and / or current detection on multiple output terminals of the drive circuit, and send the obtained detection signal to the drive control circuit.

9. The driving circuit according to claim 8, wherein: The drive control circuit is also used to receive the detection signal, and when the detection signal indicates that an abnormality occurs at the output end of one of the half-bridge circuits, adjust the control signal corresponding to one of the half-bridge circuits to adjust the working state of one of the half-bridge circuits. 10 . The driving circuit according to claim 1 , wherein each of the half-bridge circuits comprises a structure consisting of at least two power switching devices.

11. The driving circuit according to any one of claims 1 to 10, wherein: The driving circuit further includes a plurality of power supply terminals, and the plurality of power supply terminals are connected to a power supply, wherein: The power supply is used to supply power to multiple half-bridge circuits in the driving circuit through the multiple power supply terminals.

12. A control device, comprising a controller and a drive circuit according to any one of claims 1 to 11, wherein: The controller is used to provide a communication signal to the driving circuit; The driving circuit is used to receive the communication signal, control the working state of the multiple half-bridge circuits according to the communication signal, and provide a driving signal to at least one load circuit according to the working state of the multiple half-bridge circuits; wherein the driving signal of each load circuit is provided by at least two of the multiple half-bridge circuits.

13. The control device according to claim 12, wherein: When the multiple half-bridge circuits in the driving circuit are located on at least one driving chip, wherein: The communication terminals of the at least one driving chip are respectively connected to the communication terminals of the controller for receiving communication signals sent by the controller.

14. The control device according to claim 13, wherein: The communication terminal includes at least one of the following: a signal input terminal SI, a signal output terminal SO, a clock terminal CLK and a chip select terminal CS.

15. A driving system, comprising a relay and a control device according to any one of claims 12 to 14, wherein: The control device is used to control the switching state of the relay.

Images