Fault detection method and apparatus for detector, and computer device and storage medium

Abstract

A fault detection method and apparatus for a detector, and a computer device and a storage medium. The method comprises: on the basis of a feedback signal of each detector at a corresponding detection point, determining a hardware state corresponding to each detector, and determining that a detector corresponding to a hardware state that does not meet a first preset range condition is in a first failure state, wherein the hardware state is used for representing the condition of a hardware interface of a detector (S102); on the basis of an electrical signal of each detector at a corresponding detection point, determining a circuit state corresponding to each detector, taking as a candidate detector a detector corresponding to a circuit state that does not meet a second preset range condition, acquiring a checking result corresponding to the candidate detector, and when, on the basis of the checking result, it is determined that the circuit state of the candidate detector does not meet the second preset range condition, determining that the candidate detector is in a second failure state, wherein the circuit state is used for representing the operation condition of an electronic circuit of a detector (S104); and recording the number of detectors which are in a target failure state, and when the number of detectors which are in the target failure state is greater than a preset threshold value, triggering a reactor shutdown signal, wherein the target failure state comprises at least one of the first failure state and the second failure state (S106).

Description

Detector fault detection method, device, computer equipment and storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 29, 2023, with application number 202311614921.2, and entitled “Detector Fault Detection Method, Device, Computer Equipment and Storage Medium,” all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of nuclear power information technology, and in particular to a detector fault detection method, device, computer equipment, and storage medium. Background Art

[0003] In the field of nuclear power, neutron flux density is a key physical quantity for monitoring and controlling the operating status of nuclear reactors. To ensure the normal operation of nuclear reactors, neutron detectors are usually used to monitor the neutron flux inside the nuclear reactor.

[0004] However, due to the lack of comprehensive fault diagnosis methods, it is difficult to detect neutron detector faults efficiently and accurately, which affects the reliability of the neutron detector's detection results and the stability of the nuclear reactor's operating conditions.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a detector fault detection method, apparatus, computer equipment, and storage medium.

[0007] In a first aspect, the present application provides a detector fault detection method, which is executed by a computer device, and the method includes:

[0008] Determining the hardware status of each detector based on the feedback signal of each detector at the corresponding measuring point, and determining the detector corresponding to the hardware status that does not meet the first preset range condition as a first failure state; wherein the hardware status is used to represent the condition of the hardware interface of the detector;

[0009] Determining a circuit state corresponding to each detector based on an electrical signal of each detector at a corresponding measuring point, selecting detectors corresponding to circuit states that do not satisfy a second preset range condition as candidate detectors, obtaining verification results corresponding to the candidate detectors, and determining that the candidate detectors are in a second failure state when it is determined based on the verification results that the circuit state of the candidate detectors does not satisfy the second preset range condition; wherein the circuit state is used to characterize an operating condition of an electronic circuit of the detector;

[0010] The number of detectors in a target failure state is recorded, and when the number of detectors in the target failure state is greater than a preset threshold, a shutdown signal is triggered; wherein the target failure state includes at least one of the first failure state and the second failure state.

[0011] In one embodiment, the determining of the hardware status corresponding to each detector based on the feedback signal of each detector at the corresponding measuring point includes: determining the first preset range condition based on the reference signal of the detector, and when the feedback signal of the current detector at the corresponding measuring point does not satisfy the first preset range condition, determining that the hardware status of the current detector does not satisfy the first preset range condition; wherein the reference signal refers to the signal of the detector when it is in a known normal hardware state.

[0012] In one embodiment, determining the circuit state corresponding to each detector based on the electrical signal of each detector at the corresponding measuring point includes: determining the second preset range condition based on the working current range of the detector, and when the current value of the current detector at the corresponding measuring point that is not in the first failure state does not meet the second preset range condition, determining that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

[0013] In one embodiment, the circuit state corresponding to each detector is determined based on the electrical signal of each detector at the corresponding measuring point, including: determining the second preset range condition based on the reconstructed core line power density and the number of detectors currently in the target failure state; when the line power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0014] In one embodiment, the circuit state corresponding to each detector is determined based on the electrical signal of each detector at the corresponding measuring point, including: determining the second preset range condition based on the reconstructed core line power density and the average of the line power density corresponding to the detectors that are not currently in the target failure state; when the line power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0015] In one embodiment, the circuit state corresponding to each detector is determined based on the electrical signal of each detector at the corresponding measuring point, including: determining the second preset range condition based on the power deviation values ​​corresponding to a pair of detectors that are symmetrical about the measuring point and are neither in the first failure state; when the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0016] In one embodiment, before obtaining the verification result of the circuit state corresponding to the candidate detector, the method includes: triggering an alarm signal corresponding to the candidate detector, and triggering the verification result of the circuit state corresponding to the candidate detector according to the alarm signal.

[0017] In a second aspect, the present application further provides a detector fault detection device, comprising:

[0018] A first detection module is configured to determine a hardware status corresponding to each detector based on a feedback signal from each detector at a corresponding measuring point, and to determine a detector corresponding to a hardware status that does not meet a first preset range condition as being in a first failure state; wherein the hardware status is used to characterize a condition of a hardware interface of the detector;

[0019] a second detection module, configured to determine a circuit state corresponding to each detector based on an electrical signal of each detector at a corresponding measuring point, select detectors corresponding to circuit states that do not satisfy a second preset range condition as candidate detectors, obtain a verification result corresponding to the candidate detectors, and when it is determined based on the verification result that the circuit state of the candidate detectors does not satisfy the second preset range condition, determine the candidate detectors as being in a second failure state; wherein the circuit state is used to characterize an operating condition of an electronic circuit of the detector;

[0020] An analysis module is configured to record the number of detectors in a target failure state, and trigger a shutdown signal when the number of detectors in the target failure state is greater than a preset threshold; wherein the target failure state includes at least one of the first failure state and the second failure state.

[0021] In one embodiment, the first detection module includes a hardware judgment unit, which is used to: determine the first preset range condition based on the reference signal of the detector, and when the feedback signal of the current detector at the corresponding measuring point does not meet the first preset range condition, it is determined that the hardware state of the current detector does not meet the first preset range condition; wherein the reference signal refers to the signal of the detector when it is in a known normal hardware state.

[0022] In one embodiment, the second detection module includes a first circuit judgment unit, which is used to: determine the second preset range condition based on the working current range of the detector, and when the current value of the current detector at the corresponding measuring point that is not in the first failure state does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

[0023] In one embodiment, the second detection module includes a second circuit judgment unit, which is used to: determine the second preset range condition based on the reconstructed core line power density and the number of detectors currently in the target failure state; when the line power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0024] In one embodiment, the second detection module includes a third circuit judgment unit, which is used to: determine the second preset range condition based on the reconstructed core linear power density and the average linear power density corresponding to the detector that is not currently in the target failure state; when the linear power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0025] In one embodiment, the second detection module includes a fourth circuit judgment unit, which is used to: determine the second preset range condition based on the power deviation value corresponding to a pair of detectors that are symmetrical about the measurement point and are not in the first failure state; when the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0026] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores computer-readable instructions, and when the processor executes the computer-readable instructions, the following steps are implemented:

[0027] Determining the hardware status of each detector based on the feedback signal of each detector at the corresponding measuring point, and determining the detector corresponding to the hardware status that does not meet the first preset range condition as a first failure state; wherein the hardware status is used to represent the condition of the hardware interface of the detector;

[0028] Based on the electrical signal of each detector at the corresponding measuring point, the circuit state corresponding to each detector is determined, and the detector corresponding to the circuit state that does not meet the second preset range condition is used as a candidate detector. The verification result corresponding to the candidate detector is obtained, and when it is determined based on the verification result that the circuit state of the candidate detector does not meet the second preset range condition, the candidate detector is determined to be in the second failure state; wherein the circuit state is used to characterize the operating status of the electronic circuit of the detector; the number of detectors in the target failure state is recorded, and when the number of detectors in the target failure state is greater than a preset threshold, a shutdown signal is triggered; wherein the target failure state includes at least one of the first failure state and the second failure state.

[0029] In a fourth aspect, the present application further provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein the computer-readable instructions, when executed by a processor, implement the following steps:

[0030] Determining the hardware status of each detector based on the feedback signal of each detector at the corresponding measuring point, and determining the detector corresponding to the hardware status that does not meet the first preset range condition as a first failure state; wherein the hardware status is used to represent the condition of the hardware interface of the detector;

[0031] Based on the electrical signal of each detector at the corresponding measuring point, the circuit state corresponding to each detector is determined, and the detector corresponding to the circuit state that does not meet the second preset range condition is used as a candidate detector. The verification result corresponding to the candidate detector is obtained, and when it is determined based on the verification result that the circuit state of the candidate detector does not meet the second preset range condition, the candidate detector is determined to be in the second failure state; wherein the circuit state is used to characterize the operating status of the electronic circuit of the detector; the number of detectors in the target failure state is recorded, and when the number of detectors in the target failure state is greater than a preset threshold, a shutdown signal is triggered; wherein the target failure state includes at least one of the first failure state and the second failure state. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] FIG1 is a schematic flow chart of a detector fault detection method according to an embodiment;

[0034] FIG2 is a schematic flow chart of a detector fault detection method according to another embodiment;

[0035] FIG3 is a block diagram of a fault detection device for a detector according to an embodiment;

[0036] FIG4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0038] In one embodiment, as shown in FIG1 , a detector fault detection method is provided. This embodiment uses the method applied to a server as an example for illustration. It is understood that the method can also be applied to a terminal, or to a system including a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps S102 to S106. Among them:

[0039] In step S102, the hardware status of each detector is determined based on the feedback signal of each detector at the corresponding measuring point, and the detector corresponding to the hardware status that does not meet the first preset range condition is determined to be in the first failure state; wherein the hardware status is used to characterize the condition of the hardware interface of the detector.

[0040] The detector is a neutron detector used to detect the neutron flux density in a nuclear reactor core, and may include gas detectors, semiconductor detectors, scintillator detectors, and self-powered detectors. For example, due to the fact that self-powered detectors require no external bias, have a simple structure, are compact, are fully solid-state, and have simple electronics, they offer advantages in detecting neutron flux density. Therefore, this embodiment describes the method using a self-powered detector as an example.

[0041] Among them, feedback signals refer to signals that reflect the status, performance, or behavior of hardware devices; feedback signals can be expressed as signals used to detect and report on the hardware status and performance of the detector itself, and can be generated from the hardware components of the detector. Hardware status refers to the current performance status of the hardware device; hardware status can be expressed as the hardware integrity of the detector, that is, whether the detector has hardware-level damage, including hardware interface damage, contact failure, etc. Hardware interface refers to the physical connection point or electronic connection point used to connect or communicate between two or more hardware devices; hardware interfaces may include a power interface for connecting power to the detector, a data interface for transmitting data from the detector, and a control interface for controlling the working status of the detector.

[0042] Among them, converting the detector into a failure state means setting the output signal of the detector to zero or to the Non state; the first failure state can be represented as the state of the corresponding detector when the output signal of the corresponding detector is set to zero because the hardware state does not meet expectations.

[0043] Exemplarily, the server receives feedback signals from each detector and obtains the hardware status corresponding to each detector. At the same time, a first preset range condition is set as a judgment criterion for the hardware status. When the hardware status corresponding to the current detector does not meet the first preset range condition, the current detector is judged to be in the first failure state.

[0044] Optionally, the feedback signal can be expressed as a signal indicating whether the power interface of the detector is faulty, and the hardware status of the power interface is obtained accordingly; the feedback signal can also be expressed as a signal indicating whether an error or data loss occurs during data transmission through the data interface, and the hardware status of the data interface is obtained accordingly; the feedback signal can also be expressed as a signal indicating whether an abnormality occurs during the process of controlling the working condition of the detector through the control interface, and the hardware status of the control interface is obtained accordingly.

[0045] Optionally, the first preset range condition can be expressed as an objective evaluation criterion for the hardware status, which can be characterized as a condition for determining the stability of the power supply, and correspondingly determining the hardware status of the power supply interface; the first preset range condition can be characterized as a condition for determining the number of errors or error types occurring during data transmission, and correspondingly determining the hardware status of the data interface; the first preset range condition can also be characterized as a condition for determining anomalies occurring when controlling the working condition of the detector, and correspondingly determining the hardware status of the control interface.

[0046] In step S104, the circuit state corresponding to each detector is determined based on the electrical signal of each detector at the corresponding measuring point, and the detector corresponding to the circuit state that does not meet the second preset range condition is used as a candidate detector, and the verification result corresponding to the candidate detector is obtained. When it is determined based on the verification result that the circuit state of the candidate detector does not meet the second preset range condition, the candidate detector is determined to be in the second failure state; the circuit state is used to characterize the operating status of the electronic circuit of the detector.

[0047] An electrical signal refers to a signal transmitted in the form of voltage, current, or charge. An electrical signal can be represented by a signal detected by a detector at a corresponding measurement point, reflecting information such as current, linear power, and linear power density at that point. Circuit state refers to the operating conditions of individual components within an electronic circuit and the circuit as a whole. Circuit state can be expressed as the operating conditions of the detector's internal electronic circuitry, specifically the status of its electronic components, sensors, signal processing circuits, and so on.

[0048] Among them, converting the detector to a failure state means setting the output signal of the detector to zero; the second failure state can be represented as the state of the corresponding detector when the output signal of the corresponding detector is set to zero because the circuit state does not meet expectations.

[0049] Exemplarily, the server receives the electrical signal from each detector and obtains the circuit status corresponding to each detector. At the same time, a second preset range condition is set as a judgment criterion for the circuit status. When the circuit status corresponding to the current detector does not meet the second preset range condition, the circuit status corresponding to the current detector is verified and a verification result is obtained. When it is determined based on the verification result that the circuit status of the current detector does not meet the second preset range condition, the current detector is judged to be in the second failure state.

[0050] Optionally, the electrical signal can be represented by the current information measured by the detector at the corresponding measuring point, and the corresponding circuit state describing the current information is obtained; the electrical signal can also be represented by the line power information measured by the detector at the corresponding measuring point, and the corresponding circuit state describing the line power information is obtained.

[0051] Optionally, the second preset range condition can be expressed as an objective evaluation criterion for the circuit state, which can be characterized as a condition for determining the current size and its stability, and correspondingly determining the circuit state containing current information; the second preset range condition can also be characterized as a condition for determining the line power size and its stability, and correspondingly determining the circuit state containing line power information.

[0052] Optionally, the verification results can be obtained through manual verification to improve the accuracy and reliability of the verification results; further, corresponding computer-readable instructions or algorithms can be combined to implement automatic verification functions, thereby improving the efficiency of verification.

[0053] Step S106, recording the number of detectors in the target failure state, and triggering a shutdown signal when the number of detectors in the target failure state is greater than a preset threshold; wherein the target failure state includes at least one of a first failure state and a second failure state.

[0054] The shutdown signal refers to a signal indicating that the nuclear reaction of a nuclear reactor has stopped.

[0055] Exemplarily, the server records the number of detectors in a failed state, and when the number is greater than a preset threshold, a shutdown signal is triggered to stop the nuclear reaction of the nuclear reactor.

[0056] Optionally, the type of failure state of the detector can be recorded so that in the subsequent maintenance process, the detector in the first failure state can be repaired at the hardware level, and the detector in the second failure state can be repaired at the circuit level to improve maintenance efficiency.

[0057] Optionally, the first preset range conditions and the second preset range conditions corresponding to different detectors are consistent, so that there is a unified evaluation standard for the hardware status and circuit status of different detectors.

[0058] In the above-mentioned detector fault detection method, by setting a first preset range condition and a second preset range condition, the hardware status and circuit status of the detector are respectively determined in a targeted and comprehensive manner, and the determination result of the circuit status is further accurately verified to reduce the possibility of misjudgment, and whether to trigger the shutdown signal is accurately determined by the preset threshold, thereby accurately identifying the failure status of each detector, improving the efficiency and accuracy of detecting and processing detector faults, and thus ensuring the safe operation of the nuclear reactor.

[0059] In an exemplary embodiment, determining the hardware status of each detector according to the feedback signal of each detector at the corresponding measuring point includes step S1021.

[0060] Step S1021, determine the first preset range condition based on the reference signal of the detector. When the feedback signal of the current detector at the corresponding measuring point does not meet the first preset range condition, it is determined that the hardware state of the current detector does not meet the first preset range condition; wherein the reference signal refers to the signal of the detector when it is in a known normal hardware state.

[0061] The reference signal refers to a signal used as a reference or standard during the measurement process; the reference signal can be expressed as a signal used to describe the hardware status and performance of the detector itself when it is in normal working conditions, and can be generated from the hardware components of the detector.

[0062] Exemplarily, the server obtains a first preset range condition based on the reference signal of the detector. When the feedback signal of the current detector at the corresponding measuring point does not meet the first preset range condition, it is determined that the hardware state of the current detector does not meet the first preset range condition.

[0063] Optionally, the reference signal can represent a known normal state, and the reference signal can be compared with the feedback signal. When the reference signal and the feedback signal are highly matched, the hardware state of the detector is normal; when the difference in amplitude, frequency, waveform, etc. between the reference signal and the feedback signal exceeds a preset threshold, it indicates that the hardware state of the detector is abnormal.

[0064] Optionally, first, characteristic information is extracted from the reference signal, such as the signal's amplitude, frequency component, time domain characteristics, frequency domain characteristics, waveform shape, etc.; secondly, the corresponding characteristic information is used to establish a model to describe the signal characteristics of the detector under normal working conditions, such as a statistical model, a machine learning model, etc.; furthermore, based on the output and statistical information of the model, the criteria for judging the feedback signal are determined, such as a threshold, probability distribution, error range, etc.

[0065] In this embodiment, a standard for determining the feedback signal is obtained based on the reference signal, and then a standard for determining the hardware status is obtained, thereby improving the accuracy and efficiency of determining the detector hardware status.

[0066] In an exemplary embodiment, determining the circuit state corresponding to each detector based on the electrical signal of each detector at the corresponding measuring point includes step S1041.

[0067] Step S1041, determine the second preset range condition based on the working current range of the detector. When the current value of the current detector at the corresponding measuring point that is not in the first failure state does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

[0068] Exemplarily, a second preset range condition is obtained based on the working current range of the detector, and the second preset range condition is expressed as an objective evaluation standard for the circuit state of the detector; for a detector that is not in the first failure state, when the current value of the detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the detector does not meet the second preset range condition; for a detector that is in the first failure state, the output signal of the detector is zero, so there is no need to determine whether its current value meets the second preset range condition.

[0069] Optionally, when the operating current range of the detector is 4 to 20 mA, the circuit state corresponding to the detector with a current value lower than 3.7 mA or higher than 20.3 mA is determined to not meet the second preset range condition.

[0070] In this embodiment, the standard for determining the current value is obtained according to the operating current range, and then the standard for determining the circuit state is obtained, thereby improving the accuracy and efficiency of determining the detector circuit state.

[0071] In an exemplary embodiment, determining the circuit state corresponding to each detector based on the electrical signal of each detector at the corresponding measuring point includes step S1042.

[0072] Step S1042: Determine the second preset range condition based on the reconstructed core linear power density and the number of detectors currently in the target failure state. When the linear power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0073] Reconstruction refers to core power reconstruction, which can be expressed as real-time reconstruction of the power distribution of the entire core based on the power signals corresponding to the current signals measured by detectors that are not currently in a failed state. The power distribution can be expressed as the distribution of linear power density.

[0074] Exemplarily, based on the number of detector failures, the shutdown threshold of the linear power density under the reconstructed core linear power density distribution condition, that is, the second preset range condition, is determined; when the linear power density of the detector at the corresponding measuring point exceeds the shutdown threshold, it is determined that the circuit state of the detector does not meet the second preset range condition.

[0075] Optionally, the reconstructed power distribution state is the whole core power distribution state. Even if the output signal of the detector in the first failure state is zero, its circuit state can be determined by the corresponding reconstructed line power density.

[0076] Optionally, there is a correlation between the number of detector failures and the shutdown threshold. For example, as the number of detector failures increases, the shutdown threshold can be adjusted downward accordingly to ensure that the reactor can be shut down quickly when a large number of failed detectors occur, thereby ensuring the safety of the reactor.

[0077] Furthermore, different shutdown thresholds correspond to different numbers of failed detectors; or, different shutdown thresholds correspond to different number ranges of failed detectors. For example, when the number of failed detectors is between 1 and 5, the corresponding linear power density shutdown threshold is 600 W / cm; when the number of failed detectors is between 6 and 10, the corresponding linear power density shutdown threshold is lowered to 500 W / cm.

[0078] In this embodiment, based on the reconstructed core line power density status and the number of detector failures, a standard for determining the line power density is obtained, and then a standard for determining the circuit state is obtained, thereby improving the accuracy and efficiency of determining the detector circuit state.

[0079] In an exemplary embodiment, determining the circuit state corresponding to each detector based on the electrical signal of each detector at the corresponding measuring point includes step S1043.

[0080] Step S1043, determine the second preset range condition based on the reconstructed core linear power density and the average linear power density corresponding to the detector that is not currently in the target failure state. When the linear power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0081] Exemplarily, the linear power densities corresponding to the detectors that are not currently in a failed state are obtained, and the multiple linear power densities are summed and averaged to obtain the average linear power density corresponding to the detectors that are not currently in a failed state; the average linear power density is used as a reference value to determine the upper and lower thresholds of the linear power density under the reconstructed core linear power density distribution condition, that is, the second preset range condition; when the linear power density of the detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the detector does not meet the second preset range condition.

[0082] Optionally, the linear power density means corresponding to different numbers of detectors that are not in a failed state are roughly equivalent in value. Therefore, the different linear power density means corresponding to different numbers of detectors that are not in a failed state may correspond to the same upper and lower thresholds; or, based on the numerical differences between different linear power density means, the upper and lower thresholds corresponding to different linear power density means are adjusted accordingly. For example, when the numerical difference between the currently obtained linear power density mean and the historically obtained linear power density mean is too large, the upper threshold corresponding to the currently obtained linear power density mean is lowered and the lower threshold corresponding to the currently obtained linear power density mean is raised. Furthermore, the currently obtained linear power density mean can also be numerically compared with the linear power density mean of the standard specification.

[0083] Among them, the historical mean linear power density refers to the set of different linear power density means recorded at historical moments, and the standard specification linear power density mean refers to the standard linear power density mean corresponding to the reactor under normal working conditions.

[0084] In this embodiment, the standard for determining the linear power density is obtained based on the average linear power density corresponding to the detectors that are not in a failed state, and then the standard for determining the circuit state is obtained, thereby improving the accuracy and efficiency of determining the detector circuit state.

[0085] In an exemplary embodiment, determining the circuit state corresponding to each detector based on the electrical signal of each detector at the corresponding measuring point includes step S1044.

[0086] Step S1044, determine the second preset range condition based on the power deviation values ​​corresponding to a pair of detectors that are symmetrical about the measurement point center and are not in the first failure state. When the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0087] Among them, the measuring points in the core are arranged in a centrally symmetrical manner; when the core and the detectors are in normal working conditions, the deviation between the power values ​​measured by a pair of detectors with central symmetry at the measuring points is within the maximum allowable deviation range; under ideal working conditions, the deviation value is zero.

[0088] Exemplarily, the second preset range condition is obtained based on the maximum allowable deviation range between the power values ​​measured by a pair of detectors that are centrally symmetrical about the measuring points; for detectors that are not in the first failure state, the power values ​​measured by the detectors corresponding to a pair of centrally symmetrical measuring points are obtained respectively, and the deviation values ​​corresponding to the pair of power values ​​are obtained. When the deviation value does not meet the maximum allowable deviation range condition, it is determined that the circuit state corresponding to the current pair of detectors does not meet the second preset range condition; for the detector in the first failure state, the output signal of the detector is zero, so there is no need to determine whether its power value and deviation value meet the second preset range condition.

[0089] In this embodiment, based on the maximum allowable deviation range between the power values ​​measured by a pair of detectors symmetrically located about the measuring point, a standard for determining the power deviation value is obtained, and then a standard for determining the circuit state is obtained, thereby improving the accuracy and efficiency of determining the detector circuit state.

[0090] In an exemplary embodiment, before obtaining the verification result of the circuit state corresponding to the candidate detector, step S108 is included.

[0091] Step S108 , triggering an alarm signal corresponding to the candidate detector, and triggering a verification result of the circuit state corresponding to the candidate detector according to the alarm signal.

[0092] An alarm signal is a warning signal issued by a monitoring system or safety system to notify operators of an abnormal situation. Alarm signals can take the form of sound, light, text, or communication, depending on the application scenario.

[0093] For example, when the circuit state corresponding to the detector is determined to not meet the second preset range condition, the server triggers the alarm signal corresponding to the detector and sends it to the terminal corresponding to the operator. The operator verifies the judgment result of the detector to obtain the verification result, and then sends the verification result to the server through the terminal.

[0094] In this embodiment, an alarm signal is triggered to notify the operator to check the data, thereby reducing the possibility of missing data.

[0095] In an exemplary embodiment, as shown in FIG2 , a server obtains a feedback signal from a detector and determines the hardware status of the detector based on the feedback signal. Detectors corresponding to hardware statuses that do not meet a first preset range condition are determined to be in a first failure state. The upper and lower thresholds of the first preset range condition can be determined based on the reference signal of the detector.

[0096] The server obtains the electrical signal of the detector and determines the circuit state of the detector based on the electrical signal, wherein the determination method includes at least one of the following methods:

[0097] The first method is to determine that the circuit state of the current detector does not meet the second preset range condition when the current value corresponding to the current detector is higher than the upper threshold or lower than the lower threshold; wherein the upper threshold and the lower threshold of the second preset range condition can be determined according to the operating current range;

[0098] The second method is that when the deviation between the power value measured by the current detector at the corresponding measuring point and the power value measured by the detector corresponding to another centrally symmetrical measuring point is higher than a preset threshold, it is determined that the circuit state of the current detector does not meet the second preset range condition;

[0099] The third method is to determine that the circuit state of the current detector does not meet the second preset range condition when the reconstructed line power density corresponding to the current detector is higher than a preset upper threshold or lower than a preset lower threshold. The corresponding threshold can be determined based on the number of failed detectors.

[0100] The fourth method is that when the reconstructed line power density corresponding to the current detector is higher than the preset upper limit threshold or lower than the preset lower limit threshold, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein, the corresponding threshold can be determined based on the average line power density of the non-failed detectors.

[0101] Among them, the third and fourth methods can be applied to detectors in the first failure state as well as to detectors not in the first failure state; the first and second methods can only be applied to detectors not in the first failure state.

[0102] When the circuit state of the detector is determined to not meet the second preset range conditions, the server triggers an alarm signal and sends it to the terminal corresponding to the operator. The operator verifies the determination result and sends the verification result to the server through the terminal. When it is determined based on the verification result that the circuit state of the detector does not meet the second preset range conditions, the detector is determined to be in the second failure state.

[0103] The server records the number of detectors in a failed state, and when the number of detectors in a failed state exceeds a preset shutdown threshold, a shutdown signal is triggered.

[0104] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0105] Based on the same inventive concept, embodiments of the present application also provide a detector fault detection device for implementing the aforementioned detector fault detection method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of the following embodiments of one or more detector fault detection devices can be found in the above-described limitations of the detector fault detection method and will not be further elaborated here.

[0106] In an exemplary embodiment, as shown in FIG3 , a detector fault detection device is provided, comprising: a first detection module 302 , a second detection module 304 , and an analysis module 306 , wherein:

[0107] The first detection module 302 is used to determine the hardware status corresponding to each detector based on the feedback signal of each detector at the corresponding measuring point, and determine the detector corresponding to the hardware status that does not meet the first preset range conditions as a first failure state; wherein the hardware status is used to characterize the condition of the hardware interface of the detector.

[0108] The second detection module 304 is used to determine the circuit state corresponding to each detector based on the electrical signal of each detector at the corresponding measuring point, and to use the detectors corresponding to the circuit states that do not meet the second preset range conditions as candidate detectors, and to obtain the verification results corresponding to the candidate detectors. When it is determined based on the verification results that the circuit state of the candidate detector does not meet the second preset range conditions, the candidate detector is determined to be in the second failure state; wherein the circuit state is used to characterize the operating status of the electronic circuit of the detector.

[0109] The analysis module 306 is configured to record the number of detectors in a target failure state and trigger a shutdown signal when the number of detectors in the target failure state exceeds a preset threshold. The target failure state includes at least one of a first failure state and a second failure state.

[0110] In an exemplary embodiment, the first detection module 302 includes a hardware judgment unit, wherein: the hardware judgment unit is used to determine a first preset range condition based on a reference signal of the detector, and when the feedback signal of the current detector at the corresponding measuring point does not meet the first preset range condition, it is determined that the hardware state of the current detector does not meet the first preset range condition; wherein the reference signal refers to the signal of the detector when it is in a known normal hardware state.

[0111] In an exemplary embodiment, the second detection module 304 includes a first circuit judgment unit, wherein: the first circuit judgment unit is used to determine a second preset range condition based on the working current range of the detector, and when the current value of the current detector at the corresponding measuring point that is not in the first failure state does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

[0112] In an exemplary embodiment, the second detection module 304 includes a second circuit judgment unit, wherein: the second circuit judgment unit is used to determine the second preset range condition based on the reconstructed core line power density and the number of detectors currently in the target failure state; when the line power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0113] In an exemplary embodiment, the second detection module 304 includes a third circuit judgment unit, wherein: the third circuit judgment unit is used to determine the second preset range condition based on the reconstructed core line power density and the average line power density corresponding to the detector that is not currently in the target failure state; when the line power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0114] In an exemplary embodiment, the second detection module 304 includes a fourth circuit judgment unit, wherein: the fourth circuit judgment unit is used to determine the second preset range condition based on the power deviation value corresponding to a pair of detectors that are symmetrical about the measurement point center and are not in the first failure state; when the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0115] In an exemplary embodiment, the second detection module 304 includes an alarm unit, wherein the alarm unit is configured to trigger an alarm signal corresponding to the candidate detector, and trigger a verification result of the circuit state corresponding to the candidate detector according to the alarm signal.

[0116] Each module in the above-mentioned detector fault detection device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0117] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in Figure Y. The computer device includes a processor, a memory, an input / output interface (I / O), and a communication interface. The processor, the memory, and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer-readable instructions, and a database. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The database of the computer device is used to store signal data of the detector. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer-readable instructions are executed by the processor, a fault detection method for a detector is implemented.

[0118] Those skilled in the art will understand that the structure shown in FIG4 is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0119] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the processor executes the computer-readable instructions, the following steps are implemented:

[0120] Determining the hardware status of each detector based on the feedback signal of each detector at the corresponding measuring point, and determining the detector corresponding to the hardware status that does not meet the first preset range condition as a first failure state; wherein the hardware status is used to represent the condition of the hardware interface of the detector;

[0121] Based on the electrical signal of each detector at the corresponding measuring point, the circuit state corresponding to each detector is determined, and the detector corresponding to the circuit state that does not meet the second preset range condition is used as a candidate detector. The verification result corresponding to the candidate detector is obtained. When it is determined based on the verification result that the circuit state of the candidate detector does not meet the second preset range condition, the candidate detector is determined to be in the second failure state; the circuit state is used to characterize the operating status of the electronic circuit of the detector; the number of detectors in the target failure state is recorded, and when the number of detectors in the target failure state is greater than a preset threshold, a shutdown signal is triggered; the target failure state includes at least one of the first failure state and the second failure state.

[0122] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: determining a first preset range condition based on the reference signal of the detector, and when the feedback signal of the current detector at the corresponding measuring point does not meet the first preset range condition, it is determined that the hardware state of the current detector does not meet the first preset range condition; wherein the reference signal refers to the signal of the detector when it is in a known normal hardware state.

[0123] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: determining a second preset range condition based on the working current range of the detector, and when the current value of the current detector at the corresponding measuring point that is not in the first failure state does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

[0124] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: determining a second preset range condition based on the reconstructed core linear power density and the number of detectors currently in the target failure state; when the linear power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0125] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: determining a second preset range condition based on the reconstructed core linear power density and the average linear power density corresponding to the detectors that are not currently in the target failure state; when the linear power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0126] In one embodiment, when the processor executes the computer-readable instructions, it also implements the following steps: determining a second preset range condition based on the power deviation values ​​corresponding to a pair of detectors that are symmetrical about the measurement point center and are neither in the first failure state; when the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0127] In one embodiment, when the processor executes the computer-readable instructions, it further implements the following steps: triggering an alarm signal corresponding to the candidate detector, and triggering a verification result of the circuit state corresponding to the candidate detector according to the alarm signal.

[0128] In one embodiment, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the following steps are implemented:

[0129] Determining the hardware status of each detector based on the feedback signal of each detector at the corresponding measuring point, and determining the detector corresponding to the hardware status that does not meet the first preset range condition as a first failure state; wherein the hardware status is used to represent the condition of the hardware interface of the detector;

[0130] Based on the electrical signal of each detector at the corresponding measuring point, the circuit state corresponding to each detector is determined, and the detector corresponding to the circuit state that does not meet the second preset range condition is used as a candidate detector. The verification result corresponding to the candidate detector is obtained. When it is determined based on the verification result that the circuit state of the candidate detector does not meet the second preset range condition, the candidate detector is determined to be in the second failure state; the circuit state is used to characterize the operating status of the electronic circuit of the detector; the number of detectors in the target failure state is recorded, and when the number of detectors in the target failure state is greater than a preset threshold, a shutdown signal is triggered; the target failure state includes at least one of the first failure state and the second failure state.

[0131] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also implemented: determining a first preset range condition based on a reference signal of the detector, and when the feedback signal of the current detector at the corresponding measuring point does not meet the first preset range condition, determining that the hardware state of the current detector does not meet the first preset range condition; wherein the reference signal refers to the signal of the detector when it is in a known normal hardware state.

[0132] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also implemented: a second preset range condition is determined based on the working current range of the detector; when the current value of the current detector at the corresponding measuring point that is not in the first failure state does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

[0133] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also implemented: a second preset range condition is determined based on the reconstructed core linear power density and the number of detectors currently in the target failure state; when the linear power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0134] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also implemented: a second preset range condition is determined based on the reconstructed core linear power density and the average linear power density corresponding to the detectors that are not currently in the target failure state; when the linear power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0135] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also implemented: a second preset range condition is determined based on the power deviation values ​​corresponding to a pair of detectors that are symmetrical about the measurement point center and are neither in the first failure state; when the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

[0136] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are further implemented: triggering an alarm signal corresponding to the candidate detector, and triggering a verification result of the circuit state corresponding to the candidate detector according to the alarm signal.

[0137] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through computer-readable instructions. The computer-readable instructions can be stored in a non-volatile computer-readable storage medium. When the computer-readable instructions are executed, they can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0138] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A detector fault detection method, characterized in that: The method comprises: Determine the hardware state corresponding to each detector according to the feedback signal of each detector at the corresponding measuring point, and determine the detector corresponding to the hardware state that does not meet the first preset range condition as a first failure state; wherein the hardware state is used to characterize the condition of the hardware interface of the detector; Determine the circuit state corresponding to each detector according to the electrical signal of each detector at the corresponding measuring point, take the detector corresponding to the circuit state that does not meet the second preset range condition as a candidate detector, obtain the verification result corresponding to the candidate detector, and when it is determined based on the verification result that the circuit state of the candidate detector does not meet the second preset range condition, determine the candidate detector as a second failure state; wherein the circuit state is used to characterize the operating condition of the electronic circuit of the detector; and The number of detectors in a target failure state is recorded, and when the number of detectors in the target failure state is greater than a preset threshold, a shutdown signal is triggered; wherein the target failure state includes at least one of the first failure state and the second failure state.

2. The method according to claim 1, characterized in that Determining the hardware state corresponding to each detector according to the feedback signal of each detector at the corresponding measuring point includes: The first preset range condition is determined according to a reference signal of the detector. When the feedback signal of the current detector at the corresponding measuring point does not satisfy the first preset range condition, it is determined that the hardware state of the current detector does not satisfy the first preset range condition; wherein the reference signal refers to the signal of the detector when it is in a known normal hardware state.

3. The method according to claim 1, characterized in that The step of determining the circuit state corresponding to each detector according to the electrical signal of each detector at the corresponding measuring point includes: The second preset range condition is determined according to the working current range of the detector. When the current value of the current detector at the corresponding measuring point which is not in the first failure state does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

4. The method according to claim 1, characterized in that: The step of determining the circuit state corresponding to each detector according to the electrical signal of each detector at the corresponding measuring point includes: The second preset range condition is determined based on the reconstructed core line power density and the number of detectors currently in the target failure state. When the line power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

5. The method according to claim 1, characterized in that The step of determining the circuit state corresponding to each detector according to the electrical signal of each detector at the corresponding measuring point includes: The second preset range condition is determined based on the reconstructed core line power density and the average line power density corresponding to the detector that is not currently in the target failure state. When the line power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

6. The method according to claim 1, characterized in that The step of determining the circuit state corresponding to each detector according to the electrical signal of each detector at the corresponding measuring point includes: The second preset range condition is determined based on the power deviation values ​​corresponding to a pair of detectors that are symmetrical about the measuring point center and are neither in the first failure state. When the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

7. The method according to claim 1, characterized in that Before obtaining the verification result of the circuit state corresponding to the candidate detector, the method includes: An alarm signal corresponding to the candidate detector is triggered, and a verification result of a circuit state corresponding to the candidate detector is triggered according to the alarm signal.

8. A detector fault detection device, characterized in that: The device comprises: The first detection module is used to determine the corresponding position of each detector according to the feedback signal of each detector at the corresponding measurement point. Hardware status, determining the detector corresponding to the hardware status that does not meet the first preset range condition as a first failure state; wherein the hardware status is used to characterize the status of the hardware interface of the detector; A second detection module is used to determine the circuit state corresponding to each detector according to the electrical signal of each detector at the corresponding measuring point, and to use the detector corresponding to the circuit state that does not meet the second preset range condition as a candidate detector, and to obtain the verification result corresponding to the candidate detector. When it is determined based on the verification result that the circuit state of the candidate detector does not meet the second preset range condition, the candidate detector is determined to be in a second failure state; wherein the circuit state is used to characterize the operating condition of the electronic circuit of the detector; and An analysis module is used to record the number of detectors in a target failure state, and when the number of detectors in the target failure state is greater than a preset threshold, a shutdown signal is triggered; wherein the target failure state includes at least one of the first failure state and the second failure state.

9. The device according to claim 8, characterized in that The first detection module includes a hardware judgment unit, and the hardware judgment unit is used to: Determining the first preset range condition according to the reference signal of the detector, and when the feedback signal of the current detector at the corresponding measuring point does not meet the first preset range condition, determining that the hardware state of the current detector does not meet the first preset range condition; The reference signal refers to the signal of the detector when it is in a known normal hardware state.

10. The device according to claim 8, characterized in that The second detection module includes a first circuit judgment unit, and the first circuit judgment unit is used to: The second preset range condition is determined according to the working current range of the detector. When the current value of the current detector at the corresponding measuring point which is not in the first failure state does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition; wherein the working current range refers to the current range of the detector when it is in a known normal circuit state.

11. The device according to claim 8, characterized in that The second detection module includes a second circuit judgment unit, and the second circuit judgment unit is used to: The second preset range condition is determined based on the reconstructed core line power density and the number of detectors currently in the target failure state. When the line power density of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

12. The device according to claim 8, characterized in that The second detection module includes a third circuit judgment unit, and the third circuit judgment unit is used to: The second preset range condition is determined based on the reconstructed core line power density and the average line power density corresponding to the detector that is not currently in the target failure state. When the line power value of the current detector at the corresponding measuring point does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

13. The device according to claim 8, characterized in that The second detection module includes a fourth circuit judgment unit, and the fourth circuit judgment unit is used to: The second preset range condition is determined based on the power deviation values ​​corresponding to a pair of detectors that are symmetrical about the measuring point center and are neither in the first failure state. When the power value corresponding to the current detector does not meet the second preset range condition, it is determined that the circuit state of the current detector does not meet the second preset range condition.

14. A computer device comprising a memory and a processor, wherein the memory stores computer-readable instructions, characterized in that: When the processor executes the computer-readable instructions, the steps of the method according to any one of claims 1 to 7 are implemented.

15. A computer-readable storage medium having computer-readable instructions stored thereon, characterized in that: When the computer readable instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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