Display substrate and display apparatus

Abstract

A display substrate, comprising: a base, a plurality of sub-pixels and a plurality of first power lines which are located in a display area, and M first voltage supply groups which are located in a first frame area. The plurality of sub-pixels are divided into N sub-pixel groups, wherein each sub-pixel group comprises a plurality of sub-pixels emitting light of the same color, different sub-pixel groups are configured to emit light of different colors, and each first power line is connected to a plurality of sub-pixels emitting light of the same color. The M first voltage supply groups are configured to provide different first voltage signals; and each first voltage supply group is configured to provide a first voltage signal for a pixel circuit in at least one sub-pixel group by means of at least one first power line, wherein M and N are both integers greater than 1, and M is less than or equal to N.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 28, 2023, with application number 202311605913.1 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] In one aspect, this embodiment provides a display substrate comprising: a substrate, a plurality of subpixels, a plurality of first power lines, and M first voltage supply groups. The substrate comprises: a display area and a first frame area located to one side of the display area. The plurality of subpixels and the plurality of first power lines are located in the display area. The plurality of subpixels are divided into N subpixel groups, each subpixel group comprising a plurality of subpixels emitting light of the same color, with different subpixel groups configured to emit light of different colors. At least one of the plurality of subpixels comprises: a pixel circuit and a light-emitting element connected to the pixel circuit. Each first power line is connected to the pixel circuit of the plurality of subpixels emitting light of the same color. The M first voltage supply groups are located in the first frame area, the M first voltage supply groups being configured to provide different first voltage signals. Each first voltage supply group is configured to provide a first voltage signal to the pixel circuit in at least one subpixel group via at least one first power line. M and N are both integers greater than 1, and M is less than or equal to N.

[0008] In some exemplary embodiments, the first border region includes a first fan-out region and a first signal access region, which are sequentially arranged in a direction away from the display region. Each first voltage power supply group includes at least one first power supply line located in the first fan-out region and at least one first voltage contact pad located in the first signal access region; the at least one first power supply line is connected to the at least one first voltage contact pad.

[0009] In some exemplary embodiments, the first bezel region further includes: a second fan-out region and a bending region, the second fan-out region and the bending region being located on a side of the first fan-out region closer to the display region, the bending region connecting the first fan-out region and the second fan-out region. Each first voltage power supply group further includes: at least one second power supply line located in the second fan-out region, and at least one first power supply bending line located in the bending region; the at least one second power supply line is connected to multiple first power supply lines transmitting the same first voltage signal, and the at least one first power supply bending line connects the at least one first power supply line and the at least one second power supply line.

[0010] In some exemplary embodiments, the second power supply line extends at least along a first direction, the first power supply bending line extends at least along a second direction, the first power line extends at least along the second direction, and the first direction intersects the second direction; the at least one first power supply line is symmetrically arranged about the midline of the first border area along the first direction.

[0011] In some exemplary embodiments, the second power supply line is connected to multiple first power lines through a first type voltage transfer electrode, and the at least one first power supply bending line is connected to the second power supply line and multiple first power lines through a second type voltage transfer electrode; the first type voltage transfer electrode and the second type voltage transfer electrode are a same-layer structure.

[0012] In some exemplary embodiments, a distance between first power supply lines of at least two first voltage power supply groups among the M first voltage power supply groups and an orthographic projection of the substrate is greater than 0, and the first power supply line includes at least two interconnected traces.

[0013] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate. The first power supply line of at least one of the M first voltage power supply groups includes a trace located in at least two metal layers among the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

[0014] In some exemplary embodiments, the first power supply lines of different first voltage power supply groups are located in different conductive layers, and the first power supply lines of at least two first voltage power supply groups partially overlap in orthographic projection of the substrate.

[0015] In some exemplary embodiments, the first power supply lines of the M first voltage power supply groups have the same line width in the same extension direction.

[0016] In some exemplary embodiments, line widths of line segments of the first power supply lines of at least two adjacent first voltage power supply groups in the same extending direction are different.

[0017] In some exemplary embodiments, the N sub-pixel groups include: a first sub-pixel group emitting a first color of light, a second sub-pixel group emitting a second color of light, and a third sub-pixel group emitting a third color of light. The M first voltage supply groups include: a first first voltage supply group providing a first first voltage signal, a second first voltage supply group providing a second first voltage signal, and a third first voltage supply group providing a third first voltage signal. The first first voltage supply group is configured to provide the first first voltage signal to the first sub-pixel group; the second first voltage supply group is configured to provide the second first voltage signal to the second sub-pixel group; and the third first voltage supply group is configured to provide the third first voltage signal to the third sub-pixel group.

[0018] In some exemplary embodiments, the first color light is blue light, the second color light is red light, and the third color light is green light; the first first voltage signal is greater than the second first voltage signal, and the second first voltage signal is greater than the third first voltage signal.

[0019] In some exemplary embodiments, the display substrate further includes a bottom shielding layer connected to the first first voltage power supply group.

[0020] In some exemplary embodiments, the first border area includes: a first fan-out area and a first signal access area arranged in sequence along a direction away from the display area. Each first voltage power supply group includes at least: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; the at least one first power supply line is connected to the at least one first voltage contact pad. The average line width of the first power supply line of the first first voltage power supply group is greater than the average line width of the first power supply line of the second first voltage power supply group; the average line width of the first power supply line of the second first voltage power supply group is greater than the average line width of the first power supply line of the third first voltage power supply group.

[0021] In some exemplary embodiments, the first border region includes: a first fan-out region and a first signal access region, sequentially arranged in a direction away from the display region. Each first voltage power supply group includes at least: at least one first power supply line located in the first fan-out region and at least one first voltage contact pad located in the first signal access region; the at least one first power supply line is connected to the at least one first voltage contact pad. The first power supply line of the first first voltage power supply group, the first power supply line of the second first voltage power supply group, and the first power supply line of the third first voltage power supply group are single-layer traces and overlap in their orthographic projections on the substrate.

[0022] In some exemplary embodiments, the display substrate includes at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate in a direction perpendicular to the display substrate. The first power supply line of the first first-voltage power supply group is located in the first source-drain metal layer, the first power supply line of the second first-voltage power supply group is located in the second source-drain metal layer, and the first power supply line of the third first-voltage power supply group is located in the third source-drain metal layer.

[0023] In some exemplary embodiments, the display substrate further includes: L second voltage power supply groups located in the first border area, the L second voltage power supply groups being configured to provide different second voltage signals, each second voltage power supply group being configured to provide a second voltage signal to a light-emitting element in at least one sub-pixel group, wherein L is an integer greater than 1 and L is less than or equal to N; the second voltage signal is different from the first voltage signal.

[0024] In some exemplary embodiments, the N sub-pixel groups include: a first sub-pixel group emitting a first color of light, a second sub-pixel group emitting a second color of light, and a third sub-pixel group emitting a third color of light. The L second voltage supply groups include: a first second voltage supply group providing a first second voltage signal, a second second voltage supply group providing a second second voltage signal, and a third second voltage supply group providing a third second voltage signal. The first second voltage supply group is configured to provide the first second voltage signal to the first sub-pixel group; the second second voltage supply group is configured to provide the second second voltage signal to the second sub-pixel group; and the third second voltage supply group is configured to provide the third second voltage signal to the third sub-pixel group.

[0025] In some exemplary embodiments, the first color light is blue light, the second color light is red light, and the third color light is green light; the first second voltage signal is smaller than the second second voltage signal, and the second second voltage signal is smaller than the third second voltage signal.

[0026] In some exemplary embodiments, the light-emitting element includes an anode and a cathode; the cathodes of multiple light-emitting elements emitting light of the same color are connected to each other and connected to a second voltage power supply group through at least a third type voltage switching electrode.

[0027] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0028] On the other hand, this embodiment provides a display substrate comprising: a substrate, a plurality of sub-pixels, a plurality of second power lines, and L second voltage supply groups. The substrate comprises a display area and a first frame area located to one side of the display area. The plurality of sub-pixels and the plurality of second power lines are located in the display area. The plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group comprising a plurality of sub-pixels emitting light of the same color, with different sub-pixel groups configured to emit light of different colors. At least one of the plurality of sub-pixels comprises: a pixel circuit and a light-emitting element connected to the pixel circuit. Each second power line is connected to the light-emitting elements of the plurality of sub-pixels emitting light of the same color. The L second voltage supply groups are located in the first frame area. The L second voltage supply groups are configured to provide different second voltage signals, and each second voltage supply group is configured to provide a second voltage signal to the light-emitting element in at least one sub-pixel group via at least one second power line. Wherein, L and N are both integers greater than 1, and L is less than or equal to N.

[0029] In some exemplary embodiments, the N sub-pixel groups include: a first sub-pixel group that emits a first color of light, a second sub-pixel group that emits a second color of light, and a third sub-pixel group that emits a third color of light. The L second voltage power supply groups include: a first second voltage power supply group that provides a first second voltage signal, a second second voltage power supply group that provides a second second voltage signal, and a third second voltage power supply group that provides a third second voltage signal. The first second voltage power supply group is configured to provide the first second voltage signal to the first sub-pixel group. The second second voltage power supply group is configured to provide the second second voltage signal to the second sub-pixel group. The third second voltage power supply group is configured to provide the third second voltage signal to the third sub-pixel group.

[0030] In some exemplary embodiments, the first color light is blue light, the second color light is red light, and the third color light is green light; the first second voltage signal is smaller than the second second voltage signal, and the second second voltage signal is smaller than the third second voltage signal.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0032] Summary of the Figures

[0033] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0034] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0035] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] FIG3 is a timing diagram of the operation of the pixel circuit provided in FIG2 ;

[0037] FIG4 is a schematic diagram of transmission of a first voltage signal according to at least one embodiment of the present disclosure;

[0038] FIG5 is a schematic diagram of wiring in a first border area according to at least one embodiment of the present disclosure;

[0039] FIG6 is a partial enlarged schematic diagram of area C1 in FIG5 ;

[0040] FIG7 is a partial schematic diagram of the display substrate after the shielding layer is formed in FIG6 ;

[0041] FIG8 is a partial schematic diagram of the display substrate after the first semiconductor layer is formed in FIG6 ;

[0042] FIG9A is a partial schematic diagram of the display substrate after the first conductive layer is formed in FIG6 ;

[0043] FIG9B is a schematic diagram of the first conductive layer in FIG9A ;

[0044] FIG10A is a partial schematic diagram of the display substrate after the second conductive layer is formed in FIG6 ;

[0045] FIG10B is a schematic diagram of the second conductive layer in FIG10A ;

[0046] FIG11 is a partial schematic diagram of the display substrate after the second semiconductor layer is formed in FIG6 ;

[0047] FIG12A is a partial schematic diagram of the display substrate after the third conductive layer is formed in FIG6 ;

[0048] FIG12B is a schematic diagram of the third conductive layer in FIG12A;

[0049] FIG13 is a partial schematic diagram of the display substrate after the sixth insulating layer is formed in FIG6 ;

[0050] FIG14A is a partial schematic diagram of the display substrate after the fourth conductive layer is formed in FIG6 ;

[0051] FIG14B is a schematic diagram of the fourth conductive layer in FIG14A;

[0052] FIG15 is a partial schematic diagram of the display substrate after the eighth insulating layer is formed in FIG6;

[0053] FIG16A is a partial schematic diagram of the display substrate after the fifth conductive layer is formed in FIG6 ;

[0054] FIG16B is a schematic diagram of the fifth conductive layer in FIG16A;

[0055] FIG17 is a partial schematic diagram of the display substrate after the ninth insulating layer is formed in FIG6 ;

[0056] FIG18A is a partial schematic diagram of the display substrate after the sixth conductive layer is formed in FIG6 ;

[0057] FIG18B is a schematic diagram of the sixth conductive layer in FIG18A ;

[0058] FIG19 is a schematic diagram of the anode layer in FIG6 ;

[0059] FIG20A is a partial enlarged schematic diagram of area C2 in FIG5 ;

[0060] FIG20B is a schematic diagram of the fourth conductive layer in FIG20A ;

[0061] FIG20C is a schematic diagram of FIG20A after the eighth insulating layer is formed;

[0062] FIG20D is a schematic diagram of the fifth conductive layer in FIG20A;

[0063] FIG21A is a partial enlarged schematic diagram of area C2 in FIG5 ;

[0064] FIG21B is a schematic diagram of the fourth conductive layer in FIG21A ;

[0065] FIG21C is a schematic diagram of FIG21A after the eighth insulating layer is formed;

[0066] FIG21D is a schematic diagram of the fifth conductive layer in FIG21A ;

[0067] FIG22A is a partial enlarged schematic diagram of area C2 in FIG5 ;

[0068] FIG22B is a schematic diagram of the fourth conductive layer in FIG22A ;

[0069] FIG22C is a schematic diagram of FIG22A after forming an eighth insulating layer;

[0070] FIG22D is a schematic diagram of the fifth conductive layer in FIG22A ;

[0071] FIG23A is a partial enlarged schematic diagram of area C3 in FIG5 ;

[0072] FIG23B is a schematic diagram of the fourth conductive layer in FIG23A;

[0073] FIG23C is a schematic diagram of FIG23A after forming an eighth insulating layer;

[0074] FIG23D is a schematic diagram of the fifth conductive layer in FIG23A;

[0075] FIG23E is a schematic diagram of FIG23A after forming a ninth insulating layer;

[0076] FIG23F is a schematic diagram of the sixth conductive layer in FIG23A;

[0077] FIG24A is a partial enlarged schematic diagram of area C4 in FIG5 ;

[0078] FIG24B is a schematic diagram of the fourth conductive layer in FIG24A ;

[0079] FIG24C is a schematic diagram of FIG24A after forming an eighth insulating layer;

[0080] FIG24D is a schematic diagram of the fifth conductive layer in FIG24A;

[0081] FIG24E is a schematic diagram of the sixth conductive layer in FIG24A ;

[0082] FIG25 is a partial enlarged schematic diagram of area C5 in FIG24A ;

[0083] FIG26 is another schematic diagram of wiring in the first border area according to at least one embodiment of the present disclosure;

[0084] FIG27 is a partial enlarged schematic diagram of area C6 in FIG26 ;

[0085] FIG28 is another schematic diagram of wiring in the first border area according to at least one embodiment of the present disclosure;

[0086] FIG29 is a partial enlarged schematic diagram of area C7 in FIG28;

[0087] FIG30A is a partial enlarged schematic diagram of area C8 in FIG28;

[0088] FIG30B is a schematic diagram of the fourth conductive layer and the fifth conductive layer in FIG30A ;

[0089] FIG30C is a schematic diagram of the fifth conductive layer in FIG30A;

[0090] FIG31A is a partial enlarged schematic diagram of area C9 in FIG28;

[0091] FIG31B is a schematic diagram of the fourth conductive layer and the fifth conductive layer in FIG31A ;

[0092] FIG31C is a schematic diagram of the fifth conductive layer in FIG31A ;

[0093] FIG32 is a schematic diagram of transmission of a second voltage signal according to at least one embodiment of the present disclosure;

[0094] FIG33 is a schematic diagram of wiring in the first border area according to at least one embodiment of the present disclosure;

[0095] FIG34A is a partial enlarged schematic diagram of area C10 in FIG33 ;

[0096] FIG34B is a schematic diagram of the fourth conductive layer in FIG34A;

[0097] FIG34C is a schematic diagram of FIG34A after forming a fifth conductive layer;

[0098] FIG34D is a schematic diagram of FIG34A after the anode layer is formed;

[0099] FIG35 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0100] Details

[0101] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0102] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0103] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0104] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0105] In this specification, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0106] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0107] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0108] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. The functions of "source electrode" and "drain electrode" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0109] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0110] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0111] In this disclosure, "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" includes both completely identical and substantially the same, and "substantially the same" means that the difference in value is within 10%.

[0112] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0113] As used herein, "A and B are of the same layer structure" or "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B close to the substrate are in direct contact with the same film layer. "The same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. The "thickness" of a film layer is the dimension of the film layer in a direction perpendicular to the display substrate. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the range of the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0114] With the development of display technology, how to save power consumption of display substrates has become an issue that needs to be considered.

[0115] This embodiment provides a display substrate and a display device, which can save the overall power consumption of the display substrate.

[0116] This embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first power lines, and M first voltage supply groups. The substrate comprises: a display area and a first frame area located on one side of the display area. The plurality of sub-pixels and the plurality of first power lines are located in the display area. The plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group comprising a plurality of sub-pixels emitting light of the same color, and different sub-pixel groups are configured to emit light of different colors. At least one sub-pixel comprises: a pixel circuit and a light-emitting element connected to the pixel circuit. Each first power line is connected to the pixel circuit of the plurality of sub-pixels emitting light of the same color. The M first voltage supply groups are located in the first frame area, and the M first voltage supply groups are configured to provide different first voltage signals. Each first voltage supply group is configured to provide a first voltage signal to the pixel circuit in at least one sub-pixel group via at least one first power line. M and N are both integers greater than 1, and M is less than or equal to N.

[0117] In some examples, the number of sub-pixel groups may be the same as the number of first voltage power supply groups, that is, M may be equal to N. Each first voltage power supply group may provide a first voltage signal to a sub-pixel group. Different sub-pixel groups receive different first voltage signals. In other examples, M may be less than N, and at least one first voltage power supply group may provide a first voltage signal to at least two sub-pixel groups. The first voltage signals received by at least two sub-pixel groups may be the same. For example, one first voltage power supply group among the M first voltage power supply groups may be configured to provide the same first voltage signal to the pixel circuits in two sub-pixel groups. This embodiment is not limited to this.

[0118] In some examples, each of the M first voltage power supply groups can be configured to provide a first voltage signal that is different from the remaining first voltage power supply groups. In other words, the M first voltage power supply groups can provide M different first voltage signals. In other examples, at least two of the M first voltage power supply groups can be configured to provide different first voltage signals. For example, the M first voltage power supply groups can be configured to provide M-1 different first voltage signals, two of the M first voltage power supply groups can provide the same first voltage signal, and the remaining first voltage power supply groups can be configured to provide different first voltage signals. This embodiment is not limited to this.

[0119] In some examples, multiple pixel circuits in a subpixel group may be connected to multiple first power lines, and a first voltage supply group may be configured to provide a first voltage signal to the pixel circuits in the subpixel group via the multiple first power lines. In other examples, multiple pixel circuits in a subpixel group may be connected to one first power line, and a first voltage supply group may be configured to provide a first voltage signal to the pixel circuits in the subpixel group via the one first power line. This embodiment is not limited to this.

[0120] In some examples, the pixel circuit of a sub-pixel may include at least: a driving transistor, a first light emission control transistor, and a storage capacitor. The first electrode of the first light emission control transistor may be connected to a first power line, and the second electrode may be connected to the first electrode of the driving transistor. The first electrode of the storage capacitor may be connected to the gate of the driving transistor, and the second electrode may be connected to the first power line. The first power line may be electrically connected to the first electrode of the first light emission control transistor and the second electrode of the storage capacitor of the pixel circuits of multiple sub-pixels emitting light of the same color.

[0121] The display substrate provided in this embodiment provides first voltage signals to sub-pixels in groups, so that different sub-pixel groups in the display area receive different first voltage signals, which can help reduce power consumption of the display substrate.

[0122] In some exemplary embodiments, the first border area may include: a first fan-out area and a first signal access area, arranged sequentially in a direction away from the display area. Each first voltage power supply group may include at least: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; at least one first power supply line is connected to the at least one first voltage contact pad. In some examples, the first border area may further include: a second fan-out area and a bending area. The second fan-out area and the bending area may be located on the side of the first fan-out area closer to the display area, with the bending area connecting the first fan-out area and the second fan-out area. Each first voltage power supply group may further include: at least one second power supply line located in the second fan-out area and at least one first power supply bending line located in the bending area. The at least one second power supply line is connected to multiple first power supply lines transmitting the same first voltage signal, and the at least one first power supply bending line connects at least one first power supply line and at least one second power supply line. In this example, the routing of the first voltage power supply group can be arranged based on the structure of the first border area, which facilitates routing space arrangement.

[0123] In some exemplary embodiments, the second power supply line may extend at least along a first direction, the first power supply meander line may extend at least along a second direction, and the first power line may extend at least along the second direction, wherein the first direction intersects the second direction. At least one first power supply line may be symmetrically arranged about a midline of the first border region along the first direction. This exemplary wiring arrangement helps save layout space.

[0124] In some exemplary embodiments, the second power supply line can be connected to multiple first power supply lines via a first-type voltage transfer electrode, and at least one first power supply zigzag line can be connected to the second power supply line and multiple first power supply lines via a second-type voltage transfer electrode. The first-type voltage transfer electrode and the second-type voltage transfer electrode can be co-layered. The routing and connection method of the first voltage power supply group in this example can save layout space and facilitate the uniform design of the film layer pattern.

[0125] In some exemplary embodiments, the distance between the orthographic projections of the first power supply lines of at least two of the M first voltage power supply groups on the substrate may be greater than zero. In other words, the orthographic projections of the first power supply lines of the at least two first voltage power supply groups on the substrate may not overlap. The first power supply lines may include at least two interconnected traces. For example, the first power supply lines may have a double-layer trace structure, or a triple-layer trace structure. For example, in a direction perpendicular to the display substrate, the display substrate may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate; the first power supply line of at least one first voltage power supply group may include sub-traces located in at least two metal layers among the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer. For example, the first power supply lines of the multiple first voltage power supply groups may each include a double-layer trace or a triple-layer trace. In another example, the first power supply line of at least one first voltage power supply group may include a triple-layer trace, while the first power supply lines of the remaining first voltage power supply groups may include a double-layer trace, to meet the voltage drop requirements of the different first power supply lines. The first power supply line of this example adopts a multi-layer routing design, which can reduce the voltage drop of the first power supply line.

[0126] In some exemplary embodiments, the first power supply lines of different first voltage power supply groups may be located in different conductive layers, and the orthographic projections of the first power supply lines of at least two first voltage power supply groups on the substrate may partially overlap. For example, the first power supply line of at least one first voltage power supply group may be located in the first source / drain metal layer, the second source / drain metal layer, or the third source / drain metal layer. The first power supply lines of the multiple first voltage power supply groups in this example can be routed on a single layer, thereby reducing the need for via digging and overlapping connections and simplifying the manufacturing process.

[0127] In some exemplary embodiments, the first power supply lines of the M first voltage power supply groups may have the same line width in the same extension direction. This example employs a uniform width design for the first power supply lines of the multiple first voltage power supply groups, which not only helps reduce the impedance of the first power supply lines but also helps optimize the routing space.

[0128] In some exemplary embodiments, the line widths of the first power supply lines of at least two adjacent first voltage power supply groups along the same extension direction may be different. This example employs a unequal width design for the first power supply lines of multiple first voltage power supply groups, allowing for tailored voltage drops across different first power supply lines, thereby accommodating differentiated designs for the different first power supply lines.

[0129] In some exemplary embodiments, the N sub-pixel groups may include: a first sub-pixel group emitting a first color light, a second sub-pixel group emitting a second color light, and a third sub-pixel group emitting a third color light. The M first voltage supply groups may include: a first first voltage supply group providing a first first voltage signal, a second first voltage supply group providing a second first voltage signal, and a third first voltage supply group providing a third first voltage signal. The first first voltage supply group is configured to provide the first first voltage signal to the first sub-pixel group. The second first voltage supply group is configured to provide the second first voltage signal to the second sub-pixel group. The third first voltage supply group is configured to provide the third first voltage signal to the third sub-pixel group. In this example, M may be equal to N, and both are three. In some examples, the first color light may be blue light (B), the second color light may be red light (R), and the third color light may be green light (G); the first first voltage signal may be greater than the second first voltage signal, and the second first voltage signal may be greater than the third first voltage signal. However, this embodiment is not limited to this. In other examples, the number of sub-pixel groups can be three, the number of first voltage supply groups can be two, the first first voltage supply group can be configured to provide a first first voltage signal to a first sub-pixel group (e.g., including blue sub-pixels), and the second first voltage supply group can be configured to provide a second first voltage signal to a second sub-pixel group (e.g., including red sub-pixels) and a third sub-pixel group (e.g., including green sub-pixels). In this example, the grouping design of the first voltage signal can be used to implement RGB brightness grouping control, thereby achieving the purpose of saving power consumption of the first voltage signal.

[0130] In some exemplary embodiments, the display substrate may further include a bottom shielding layer, which may be connected to the first first voltage power supply group. In this example, by connecting the first first voltage power supply line group to the bottom shielding layer, the impedance of the first first voltage power supply group may be reduced.

[0131] In some exemplary embodiments, the average line width of the first power supply line of the first first voltage power supply group may be greater than the average line width of the first power supply line of the second first voltage power supply group, and the average line width of the first power supply line of the second first voltage power supply group may be greater than the average line width of the first power supply line of the third first voltage power supply group. The average line width of the first power supply line in this example refers to the average line width of multiple line segments of the first power supply line. In some examples, the first power supply line of each first voltage power supply group may adopt a non-uniform width design. This example can meet the differentiated design requirements of different first power supply lines by setting the average line width of the first power supply lines of multiple first voltage power supply groups.

[0132] In some exemplary embodiments, the display substrate may further include: L second voltage power supply groups located in the first border region, the L second voltage power supply groups may be configured to provide different second voltage signals, and each second voltage power supply group may be configured to provide a second voltage signal to the light-emitting element in at least one subpixel group, where L is an integer greater than 1 and L is less than or equal to N. The second voltage signal is different from the first voltage signal; for example, the second voltage signal may be less than the first voltage signal. In some examples, the start-up voltages of subpixels emitting different colors of light are different. By grouping the second voltage signals, precise control of the brightness of subpixels of different colors of light can be achieved, thereby reducing power consumption.

[0133] In some examples, the number of sub-pixel groups may be the same as the number of second voltage supply groups, that is, L may be equal to N. Each second voltage supply group may provide a second voltage signal to a sub-pixel group. Different sub-pixel groups receive different second voltage signals. In other examples, L may be less than N, and at least one second voltage supply group may provide a first voltage signal to at least two sub-pixel groups. The second voltage signals received by at least two sub-pixel groups may be the same. For example, one second voltage supply group among the L second voltage supply groups may be configured to provide the same second voltage signal to two sub-pixel groups. However, this embodiment is not limited to this.

[0134] In some examples, each of the L second voltage supply groups can be configured to provide a second voltage signal that is different from the remaining second voltage supply groups. In other words, the L second voltage supply groups can provide L different second voltage signals. In other examples, at least two of the L second voltage supply groups can be configured to provide different second voltage signals. For example, the L second voltage supply groups can be configured to provide L-1 different second voltage signals, two of the L second voltage supply groups can provide the same second voltage signal, and the remaining second voltage supply groups can be configured to provide different second voltage signals. This embodiment is not limited to this.

[0135] In some examples, the display area may include multiple second power lines, each of which may be connected to light-emitting elements of multiple sub-pixels that emit light of the same color. For example, the light-emitting elements of the sub-pixels may include an anode and a cathode. The cathode of the light-emitting element may be connected to the second power line.

[0136] In some examples, multiple light-emitting elements in a sub-pixel group can be connected to multiple second power lines, and a second voltage supply group can be configured to provide a second voltage signal to the light-emitting elements in the sub-pixel group through the multiple second power lines. In other examples, multiple light-emitting elements in a sub-pixel group can be connected to a single second power line, and a second voltage supply group can be configured to provide a second voltage signal to the light-emitting elements in the sub-pixel group through the single second power line. This embodiment is not limited to this.

[0137] The following examples illustrate the display substrate of this embodiment. The following exemplary embodiments are based on an OLED display substrate. Because the display area and first frame area typically have a large number of certain types of traces, the accompanying drawings only illustrate a few or a complete trace of a particular type, and do not limit the number of traces of a particular type.

[0138] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate of this example may include: a display area AA, a frame area located around the display area AA. The frame area may include: a first frame area B1 located on one side of the display area AA, and a second frame area B2 located on the other side of the display area AA. The first frame area B1 and the second frame area B2 may surround the display area AA after being connected. In some examples, the first frame area B1 may be the lower frame of the display substrate, and the second frame area B2 may include the upper frame, left frame, and right frame of the display substrate. However, this embodiment is not limited to this.

[0139] In some examples, as shown in FIG1 , a display area AA may include a plurality of sub-pixels PX forming a pixel array. The plurality of sub-pixels PX may be configured to display a dynamic image or a still image. The display area AA may be referred to as an active area. In some examples, a display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled.

[0140] In some examples, as shown in FIG1 , the display area AA may further include: a plurality of gate lines GL and a plurality of data lines DL. The gate lines GL may extend along a first direction X, and the data lines DL may extend along a second direction Y. The first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions, with a sub-pixel PX disposed in each sub-pixel region. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide scan signals to the plurality of sub-pixels PX.

[0141] In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may include one red (R) sub-pixel, one blue (B) sub-pixel, and two green (G) sub-pixels. Alternatively, a pixel unit may include three sub-pixels, and the three sub-pixels may be a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. However, this embodiment is not limited to this. In other examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0142] In some examples, at least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0143] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0144] In some examples, the shape of the light-emitting element can be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0145] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data write transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0146] In some examples, the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the multiple transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0147] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0148] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line VDD, a second power line VSS, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line VDD can be configured to provide a constant first voltage signal Vdd to the pixel circuit, and the second power line VSS can be configured to provide a constant second voltage signal Vss to the pixel circuit, where the first voltage signal Vdd can be greater than the second voltage signal Vss. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0149] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the second electrode of the second transistor T2 is electrically connected to the first node N1, and the first electrode of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line VDD. An anode of the light emitting element EL may be electrically connected to the fourth node N4 , and a cathode of the light emitting element EL may be electrically connected to the second power supply line VSS.

[0150] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0151] FIG3 is an operating timing diagram of the pixel circuit shown in FIG2. The operating process of the pixel circuit shown in FIG2 will be described below with reference to FIG3. In the pixel circuit, the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0152] In some examples, as shown in FIG. 2 and FIG. 3 , during a frame display period, the operation process of the pixel circuit may include at least: a first stage S11 , a second stage S12 , a third stage S13 , and a fourth stage S14 .

[0153] The first stage S11 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0154] The second stage S12 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The first transistor T1 and the second transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0155] The third stage S13 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0156] In the fourth stage S14, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal Vdd output by the first power line VDD can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0157] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0158] I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth]2 =K×[Vdd-Vdata] 2 ;

[0159] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0160] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0161] In some examples, sub-pixels emitting light of different colors require different data voltage ranges. Furthermore, according to the above drive current calculation formula, the drive current of a sub-pixel is related to the data voltage and the first voltage signal. Therefore, sub-pixels emitting light of different colors (e.g., red, blue, and green sub-pixels) have different requirements for the first voltage signal. This embodiment can achieve power savings by grouping the first voltage signals to provide sub-pixels emitting light of different colors with first voltage signals that meet their actual needs.

[0162] In some examples, as shown in Figure 1, the first frame area B1 may include: a second fan-out area B11, a bending area B12, a first fan-out area B13, a second signal access area B14, and a first signal access area B15, which are arranged in sequence along a direction away from the display area AA. The second fan-out area B11 may be connected to the second frame area B2 and located on one side of the display area AA. The bending area B12 may be connected to the second fan-out area B11 and the first fan-out area B13 and located on the side of the second fan-out area B11 away from the display area AA. The bending area B12 may cause the first fan-out area B13, the first signal access area B15, and the second signal access area B14 to bend to the back of the display area AA. The bending area B12 may include multiple bending connecting lines to connect the traces transmitting the same signal in the second fan-out area B11 and the first fan-out area B13. The first fan-out area B13 may be located on the side of the bending area B12 away from the display area AA.

[0163] In some examples, as shown in FIG1 , the second signal access area B14 can be located on a side of the first fan-out area B13 away from the display area AA. The second signal access area B14 can be configured to house a driver chip (IC). For example, the driver chip housed in the second signal access area B14 can be a touch and display driver integrated circuit (TDDI). The second signal access area B14 can also be referred to as a driver chip placement area. For example, the driver chip can be configured to generate data signals required to drive sub-pixels.

[0164] In some examples, as shown in FIG1 , the first signal access area B15 can be located on a side of the second signal access area B14 away from the display area AA. The first signal access area B15 can be provided with multiple contact pads, which can be configured to bind a flexible printed circuit (FPC) so that multiple signal lines (e.g., power lines, control signal lines, etc.) are connected to an external control device through the multiple contact pads. The first signal access area B15 can also be referred to as a circuit binding area.

[0165] Figure 4 is a schematic diagram illustrating the transmission of a first voltage signal according to at least one embodiment of the present disclosure. In some examples, the display area AA may include multiple subpixels and multiple first power lines. The multiple subpixels in the display area AA may be divided into N subpixel groups. Each subpixel group may include multiple subpixels emitting the same color light. Different subpixel groups may be configured to emit different colors of light. This example illustrates the division of the multiple subpixels in the display area AA into three subpixel groups. The display area AA may include a first subpixel group P1, a second subpixel group P2, and a third subpixel group P3. The first subpixel group P1 may include multiple subpixels PX1 emitting a first color light, the second subpixel group P2 may include multiple subpixels PX2 emitting a second color light, and the third subpixel group P3 may include multiple subpixels PX3 emitting a third color light. For example, the first color light may be blue light, the second color light may be red light, and the third color light may be green light. In other words, the first subpixel group P1 may be a blue subpixel group, the second subpixel group P2 may be a red subpixel group, and the third subpixel group P3 may be a green subpixel group. This embodiment is not limited to this.

[0166] In some examples, a sub-pixel may include: a pixel circuit and a connected light-emitting element. FIG4 shows the pixel circuit of a sub-pixel in display area AA as an example, and omits the light-emitting element of the sub-pixel. As shown in FIG4 , the multiple pixel circuits in display area AA can be arranged in an array into multiple rows and columns. A row of pixel circuits may include multiple pixel circuits arranged along a first direction X, and a column of pixel circuits may include multiple pixel circuits arranged along a second direction Y. The first sub-pixel group P1 may include multiple columns of pixel circuits, each column of pixel circuits may include multiple pixel circuits PX1-1; the second sub-pixel group P2 may include multiple columns of pixel circuits, each column of pixel circuits may include multiple pixel circuits PX2-1; the third sub-pixel group P3 may include multiple columns of pixel circuits, each column of pixel circuits may include multiple pixel circuits PX3-1.

[0167] In some examples, as shown in FIG4 , the plurality of first power lines in display area AA may include: a plurality of first power lines VDD1, a plurality of first power lines VDD2, and a plurality of first power lines VDD3. The first power line VDD1 may be configured to transmit a first voltage signal Vdd1, the first power line VDD2 may be configured to transmit a first voltage signal Vdd2, and the first power line VDD3 may be configured to transmit a first voltage signal Vdd3. The first voltage signals Vdd1, Vdd2, and Vdd3 may have different voltage values.

[0168] In some examples, as shown in FIG4 , each column of pixel circuits can be electrically connected to a first power line and configured to receive a first voltage signal. A column of pixel circuits PX1-1 in the first subpixel group P1 can be electrically connected to a first power line VDD1 and configured to receive a first voltage signal Vdd1. A column of pixel circuits PX2-1 in the second subpixel group P2 can be electrically connected to a first power line VDD2 and configured to receive a first voltage signal Vdd2. A column of pixel circuits PX3-1 in the third subpixel group P3 can be electrically connected to a first power line VDD3 and configured to receive a first voltage signal Vdd3. For example, the first subpixel group P1 includes blue subpixels, the second subpixel group P2 includes red subpixels, and the third pixel group P3 includes green subpixels. The first voltage signal Vdd1 provided to the first pixel group P1 can be greater than the first voltage signal Vdd2 provided to the second subpixel group P2, and the first voltage signal Vdd2 provided to the second subpixel group P2 can be greater than the first voltage signal Vdd3 provided to the third subpixel group P3. In this example, since the first voltage signal required by the blue sub-pixel is larger, power loss can be avoided by providing the blue sub-pixel, red sub-pixel and green sub-pixel with first voltage signals that meet their respective requirements, thereby achieving the purpose of saving power.

[0169] In some examples, as shown in FIG4 , the first border area B1 may include M first voltage power supply groups, for example, the value of M is 3, and the first border area B1 may include a first first voltage power supply group 11, a second first voltage power supply group 12, and a third first voltage power supply group 13. Each first voltage power supply group may be configured to provide a corresponding first voltage signal to at least one sub-pixel group. In this example, the first voltage power supply group 11 may be configured to provide a first voltage signal Vdd1 to the first sub-pixel group, the first voltage power supply group 12 may be configured to provide a first voltage signal Vdd2 to the second sub-pixel group, and the first voltage power supply group 13 may be configured to provide a first voltage signal Vdd3 to the third sub-pixel group.

[0170] In some examples, as shown in FIG4 , the first voltage supply group 11 may include: a second power supply line 111 located in the second fan-out area B11, a first power supply line 112 located in the first fan-out area B13, a first power supply bend line 113 located in the bend area B12, and first voltage contact pads 114a and 114b located in the first signal access area B15. The first voltage supply group 12 may include: a second power supply line 121 located in the second fan-out area B11, a first power supply line 122 located in the first fan-out area B13, a first power supply bend line 123 located in the bend area B12, and first voltage contact pads 124a and 124b located in the first signal access area B15. The first voltage supply group 13 may include: a second power supply line 131 located in the second fan-out area B11, a first power supply line 132 located in the first fan-out area B13, a first power supply bend line 133 located in the bend area B12, and first voltage contact pads 134a and 134b located in the first signal access area B15.

[0171] In some examples, as shown in FIG4 , the second power supply lines 111, 121, and 131 located in the second fan-out area B11 may be arranged sequentially along the opposite direction of the second direction Y. The second power supply lines 111, 121, and 131 may be at least traces extending along the first direction X. The second power supply line may be connected to the first power line through a first type voltage transfer electrode. For example, the first type voltage transfer electrode may include: a first voltage transfer electrode 141, a second voltage transfer electrode 142, and a third voltage transfer electrode 143. Among them, the second power supply line 111 may be connected to the first power line VDD1 through the first voltage transfer electrode 141, the second power supply line 121 may be connected to the first power line VDD2 through the second voltage transfer electrode 142, and the second power supply line 131 may be connected to the first power line VDD3 through the third voltage transfer electrode 143.

[0172] In some examples, the second power supply lines 111, 121, and 131 may be co-layered, the first voltage transfer electrode 141, the second voltage transfer electrode 142, and the third voltage transfer electrode 143 may be co-layered, and the first power supply lines VDD1, VDD2, and VDD3 may be co-layered. For example, the first power supply lines VDD1, VDD2, and VDD3 may be located on a side of the first voltage transfer electrode 141, the second voltage transfer electrode 142, and the third voltage transfer electrode 143 away from the substrate, and the second power supply lines 111, 121, and 131 may be located on a side of the first voltage transfer electrode 141, the second voltage transfer electrode 142, and the third voltage transfer electrode 143 away from the substrate. The first power supply lines VDD1, VDD2, and VDD3 may be located on a side of the second power supply lines 111, 121, and 131 away from the substrate. This embodiment is not limited to this.

[0173] In some examples, as shown in FIG4 , the first power supply bend lines 113, 123, and 133 located in the bending area B12 may be lines extending at least along the second direction Y. The first power supply bend lines 113, 123, and 133 may be structures on the same layer. The first power supply bend line 113 may connect the second power supply line 111 and the first power supply line 112, the first power supply bend line 123 may connect the second power supply line 121 and the first power supply line 122, and the first power supply bend line 133 may connect the second power supply line 131 and the first power supply line 132. For example, the first power supply bend line may be connected to the corresponding second power supply line through a second type voltage transfer electrode, and the first power supply bend line may be directly connected to the first power supply line. However, this embodiment is not limited to this. In other examples, the first power supply bend line may be directly connected to both the first power supply line and the second power supply line.

[0174] In some examples, as shown in FIG4 , the first power supply lines 112 , 122 , and 132 located in the first fan-out area B13 can be arranged sequentially along the opposite direction of the second direction Y. The two ends of the first power supply line 112 can be respectively connected to the first voltage contact pads 114 a and 114 b in the first signal access area B15. The two ends of the first power supply line 122 can be respectively connected to the first voltage contact pads 124 a and 124 b in the first signal access area B15. The two ends of the first power supply line 132 can be respectively connected to the first voltage contact pads 134 a and 134 b in the first signal access area B15. The first voltage contact pads 114 a, 124 a, and 134 a can be arranged adjacent to each other, and the first voltage contact pads 114 b, 124 b, and 124 b can be arranged adjacent to each other.

[0175] This example provides three different first voltage signals by setting three first voltage power supply groups in the first frame area, which can meet the different requirements of the three sub-pixel groups emitting different colors of light in the display area for the first voltage signal, thereby achieving the purpose of saving power consumption of the first voltage signal.

[0176] Figure 5 is a schematic diagram of the routing of the first border region of at least one embodiment of the present disclosure. Figure 5 primarily illustrates the three second power supply lines 111, 121, and 131 of the second fan-out region B11, the multiple curved connecting lines of the bending region B12, and some of the routing of the first fan-out region B13 (e.g., including first power supply lines 112a and 112b, 122a and 122b, and 132a and 132b). Furthermore, Figure 5 provides a schematic diagram of multiple adjacent routing lines of the same type.

[0177] In some examples, as shown in Figure 5, the second fan-out area B11 may include at least: three second power supply lines 111, 121 and 131, a second voltage fan-out line (not shown), a plurality of data fan-out lines (not shown), a plurality of drive fan-out lines (not shown) and a plurality of touch fan-out lines (not shown). The second voltage fan-out line can be configured to transmit a second voltage signal. The plurality of data fan-out lines can be connected to the plurality of data lines in the display area and configured to transmit data signals. The plurality of drive fan-out lines can be connected to the gate drive circuit provided in the second frame area and configured to transmit drive control signals (such as clock signals, start signals, etc.). The plurality of data fan-out lines may include a plurality of first data fan-out lines located in the first conductive layer and a plurality of second data fan-out lines located in the second conductive layer.

[0178] In some examples, as shown in FIG5 , the multiple bending connection lines of the bending area B12 may include: multiple data bending lines (for example, a first group of data bending lines 163a, a second group of data bending lines 163b, a third group of data bending lines 163c, a fourth group of data bending lines 163d, a fifth group of data bending lines 163e, and a sixth group of data bending lines 163f), multiple drive bending lines (for example, a first group of drive bending lines 173a, a second group of drive bending lines 173b), and multiple touch bending lines (for example, Including a first group of touch bending lines 183a, a second group of touch bending lines 183b, a third group of touch bending lines 183c and a fourth group of touch bending lines 183d), multiple first power supply bending lines (for example, including first power supply bending lines 113a, 113b, 113c and 113d, 123a, 123b, 123c and 123d, 133a, 133b and 133c), and multiple second power supply bending lines (for example, including second power supply bending lines 153a, 153b, 153c and 153d).

[0179] In some examples, as shown in FIG5 , within the bending region B12, the first group of driving bending lines 173a, the second power bending lines 153a, the first group of touch bending lines 183a, the first group of data bending lines 163a, the second group of touch bending lines 183b, the second power bending lines 153b, the second group of data bending lines 163b, the first power bending lines 113a, 123a, and 133a, the third group of data bending lines 163c, the first power bending lines 113 b, 123b, 133b, 123c and 113c, the fourth group of data bending lines 163d, the first power supply bending lines 113c, 123d and 113d, the fifth group of data bending lines 163c, the second power supply bending lines 153c, the third group of touch bending lines 183c, the sixth group of data bending lines 163f, the fourth group of touch bending lines 183d, the second power supply bending lines 153d and the second group of drive bending lines 173b can be arranged in sequence along the first direction X.

[0180] In some examples, as shown in FIG5 , the first fan-out area B13 may include: a plurality of first power supply lines (e.g., two first power supply lines 112 a and 112 b, two first power supply lines 122 a and 122 b, and two first power supply lines 132 a and 132 b), two second voltage lead lines (e.g., second voltage lead lines 151 and 152), a plurality of data lead lines (e.g., a first group of data lead lines 161 and a second group of data lead lines 162), a plurality of drive lead lines (e.g., a first group of drive lead lines 171 and a second group of drive lead lines 172), and a plurality of touch lead lines (e.g., a first group of touch lead lines 181 and a second group of touch lead lines 182). The first group of drive lead lines 171 and the second group of drive lead lines 172 may be located on both sides of the plurality of data lead lines in the first direction X. The first group of drive lead lines 171 can be connected to multiple drive fan-out lines in the second fan-out area B11 via a first group of drive bending lines 173a, and the second group of drive lead lines 172 can be connected to multiple drive fan-out lines in the second fan-out area B11 via a second group of drive bending lines 173b. The first group of touch lead lines 181 can be connected to multiple touch fan-out lines in the second fan-out area B11 via a first group of touch bending lines 183a and a second group of touch bending lines 183b. The second group of touch lead lines 182 can be connected to multiple touch fan-out lines in the second fan-out area B11 via a third group of touch bending lines 183c and a fourth group of touch bending lines 183d. The second voltage lead-out line 151 can be connected to the second voltage fan-out lines in the second fan-out area B11 via second voltage bending lines 153a and 153b, and the second voltage lead-out line 152 can be connected to the second voltage fan-out lines in the second fan-out area B11 via second voltage bending lines 153c and 153d. The second voltage lead-out lines 151 and 152 can be configured to transmit a second voltage signal.

[0181] In some examples, the two first power supply lines 112a and 112b can be arranged approximately symmetrically about the midline of the first border area in the first direction X, the two first power supply lines 122a and 122b can be arranged approximately symmetrically about the midline of the first border area in the first direction X, and the two first power supply lines 132a and 132b can be arranged approximately symmetrically about the midline of the first border area in the first direction X. The two first power supply lines 132a and 132b can be an integrated structure connected to each other.

[0182] In some examples, as shown in FIG5 , the line widths of the line segments of the plurality of first power lines extending in the same direction may be substantially the same. For example, the line widths of the line segments of the first power lines 112 a, 112 b, 122 a, 122 b, 132 a, and 132 b extending along the first direction X (i.e., the lengths along the second direction Y) may be substantially the same; and the line widths of the line segments of the first power lines 112 a, 112 b, 122 a, 122 b, 132 a, and 132 b extending along the second direction Y (i.e., the lengths along the first direction X) may be substantially the same.

[0183] In some examples, the first power line 112a can be connected to the second power line 111 via the first power-supply meandering lines 113a and 113b, and the first power line 112b can be connected to the second power line 111 via the first power-supply meandering lines 113c and 113d. The first power line 122a can be connected to the second power line 121 via the first power-supply meandering lines 123a and 123b, and the first power line 122b can be connected to the second power line 121 via the first power-supply meandering lines 123c and 123d. The first power line 132a can be connected to the second power line 131 via the first power-supply meandering lines 133a and 133b, and the first power line 132b can be connected to the second power line 131 via the first power-supply meandering lines 133b and 133c.

[0184] In some examples, as shown in FIG5 , the first signal access area B15 may include: a plurality of contact pads, such as a first group of power contact pads 31a and a second group of power contact pads 31b, and a group of intermediate contact pads 32. The first group of power contact pads 31a and the second group of power contact pads 31b are located on opposite sides of the group of intermediate contact pads 32 in the first direction X. The first group of power contact pads 31a may include: a plurality of first voltage contact pads (such as the first voltage contact pads 114a, 124a, and 134a shown in FIG4 ) and at least one second voltage contact pad, which may be located on one side of the plurality of first voltage contact pads in the opposite direction of the first direction X. The second group of power contact pads 21b may include: a plurality of first voltage contact pads (such as the first voltage contact pads 114b, 124b, and 134b shown in FIG4 ) and at least one second voltage contact pad, which may be located on one side of the plurality of first voltage contact pads in the first direction X.

[0185] In some examples, as shown in FIG5 , the second signal access region B14 may include: a plurality of input contact pads 34 and a plurality of output contact pads 33. The plurality of input contact pads 34 may be located on a side of the plurality of output contact pads 33 away from the bending region B12. The plurality of input contact pads 34 may be connected to a group of intermediate contact pads 32 via a plurality of contact pad leads. The plurality of output contact pads 33 may be connected to at least a first group of data lead lines 161 and a second group of data lead lines 162.

[0186] Figure 6 is a partially enlarged schematic diagram of area C1 in Figure 5. Figure 6 illustrates the boundary between the display area AA and the first border area B1, primarily illustrating two rows and eight columns (e.g., columns j to j+7, where j can be an integer greater than 0) of pixel circuits in the display area AA, some of the light-emitting elements connected to the pixel circuits, and a partial area of ​​the second fan-out area B11 of the first border area B1.

[0187] In some examples, as shown in FIG6 , the plurality of pixel circuits in the display area AA may be arranged in an array along a first direction X and a second direction Y. The plurality of light-emitting elements in the display area AA may include: a first light-emitting element PX1-2 emitting a first color light, a second light-emitting element PX2-2 emitting a second color light, a third light-emitting element PX3-2 emitting a third color light, and a fourth light-emitting element PX4-2 emitting a third color light. The first light-emitting element PX1-2 and the second light-emitting element PX2-2 may be arranged at intervals along the first direction X and the second direction Y, the third light-emitting element PX3-2 and the fourth light-emitting element PX4-2 may be arranged at intervals along the first direction X and the second direction Y, and the first light-emitting element PX1-2 and the second light-emitting element PX2-2 may be arranged in different rows and columns from the third light-emitting element PX3-2 and the fourth light-emitting element PX4-2. The pixel circuits connected to the plurality of first light-emitting elements PX1-2 may be arranged in the same column, the pixel circuits connected to the plurality of second light-emitting elements PX2-2 may be arranged in the same column, the pixel circuits connected to the plurality of third light-emitting elements PX3-2 and the pixel circuits connected to the plurality of fourth light-emitting elements PX4-3 may be arranged in the same column. For example, the pixel circuit in the jth column may be connected to the third light-emitting element PX3-2 and the fourth light-emitting element PX4-3 that emit light of the third color, the pixel circuit in the j+1th column may be connected to the first light-emitting element PX1-2, the pixel circuit in the j+2th column may be connected to the third light-emitting element and the fourth light-emitting element, the pixel circuit in the j+3th column may be connected to the second light-emitting element, the pixel circuit in the j+4th column may be connected to the third light-emitting element and the fourth light-emitting element, the pixel circuit in the j+5th column may be connected to the first light-emitting element, the pixel circuit in the j+6th column may be connected to the third light-emitting element and the fourth light-emitting element, and the pixel circuit in the j+7th column may be connected to the second light-emitting element.

[0188] In some examples, the first color light may be blue light, the second color light may be red light, and the third color light may be green light; the first light-emitting element may be a blue light-emitting element, the second light-emitting element may be a red light-emitting element, and the third and fourth light-emitting elements may be green light-emitting elements. In this example, every four columns of pixel circuits may be a group, and the four columns of pixel circuits within a group may be sequentially connected to a green light-emitting element, a blue light-emitting element, a green light-emitting element, and a red light-emitting element. For example, the pixel circuits in columns j to j+3 may form a group, and the pixel circuits in columns j+4 to j+7 may form a group.

[0189] In some examples, subpixel PX1 includes a first light-emitting element PX1-2, subpixel PX2 includes a second light-emitting element PX2-2, subpixel PX3 includes a third light-emitting element PX3-2, and subpixel PX4 includes a fourth light-emitting element PX4-2. Subpixel PX1 belongs to a first subpixel group PX1, subpixel PX2 belongs to a second subpixel group P2, and subpixels PX3 and PX4 belong to a third subpixel group P3.

[0190] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a bottom shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the bottom shielding layer and the first semiconductor layer, a second insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a third insulating layer may be disposed between the first conductive layer and the second conductive layer, a fourth insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fifth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a sixth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a seventh insulating layer and an eighth insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, a ninth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a tenth insulating layer may be disposed on the side of the sixth conductive layer away from the substrate. In some examples, the first to seventh insulating layers may be inorganic insulating layers, and the eighth, ninth, and tenth insulating layers may be organic insulating layers. However, this embodiment is not limited to this.

[0191] The following illustrates the film structure of the display substrate of this example through the preparation process of the display substrate. The "patterning process" referred to in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials. For organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be achieved by any one or more of spraying, spin coating, and inkjet printing; and etching can be achieved by any one or more of dry etching and wet etching, which are not limited in this disclosure. A "thin film" refers to a thin film produced by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire production process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The shape of A can refer to the shape of the orthographic projection of A on the substrate.

[0192] In some examples, the preparation process of the display substrate may include the following operations: In the following examples, a film layer of a pixel circuit in the display area (eg, a pixel circuit located in the last row and column j) is used as an example for description.

[0193] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., to improve the substrate's resistance to water and oxygen.

[0194] (2) Forming a bottom blocking layer. In some examples, a blocking metal film is deposited on a substrate, and the blocking metal film is patterned through a patterning process to form a bottom blocking layer disposed on the substrate.

[0195] Figure 7 is a partial schematic diagram of the display substrate after the shielding layer is formed in Figure 6. In some examples, as shown in Figure 7, the bottom shielding layer may include: a first bottom structure 411 located in the display area AA and a second bottom structure 412 located in the second fan-out area B11. The bottom shielding layer may have a generally mesh structure. The first bottom structure 411 and the second bottom structure 412 may be interconnected, integral structures. The first bottom structure 411 may have a generally mesh structure, and the second bottom structure 412 may have a generally strip-like structure extending along the first direction X.

[0196] (3) Forming a first semiconductor layer. In some examples, a first insulating film and a first semiconductor film are sequentially deposited on the substrate forming the aforementioned structure, and the first semiconductor film is patterned by a patterning process to form a first insulating layer. The first semiconductor layer is disposed on the first insulating layer. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0197] FIG8 is a partial schematic diagram of the display substrate after the first semiconductor layer is formed in FIG6. In some examples, as shown in FIG8, the first semiconductor layer of the display area AA may include at least active layers of multiple first-type transistors of multiple pixel circuits (e.g., active layer T10 of the first transistor T1, active layer T30 of the third transistor T3, active layer T40 of the fourth transistor T4, active layer T50 of the fifth transistor T5, active layer T60 of the sixth transistor T6, active layer T70 of the seventh transistor T7, and active layer T80 of the eighth transistor T8).

[0198] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0199] In some examples, as shown in FIG8 , the active layer T10 of the first transistor T1 and the active layer T40 of the fourth transistor T4 of the pixel circuit may be located on one side of the active layer T30 of the third transistor T3 in the second direction Y, and the active layer T50 of the fifth transistor T5, the active layer T60 of the sixth transistor T6, the active layer T70 of the seventh transistor T7, and the active layer T80 of the eighth transistor T8 may be located on a side of the active layer T30 of the third transistor T3 in a direction opposite to the second direction Y. The active layer T30 of the third transistor T3, the active layer T40 of the fourth transistor T4, the active layer T50 of the fifth transistor T5, the active layer T60 of the sixth transistor T6, and the active layer T70 of the eighth transistor T7 of a single pixel circuit may be an interconnected integral structure. The first region of the active layer T30 of the third transistor T3 can simultaneously serve as the second region of the active layer T40 of the fourth transistor T4 and the second region of the active layer T50 of the fifth transistor T5. The second region of the active layer T30 of the third transistor T3 can simultaneously serve as the first region of the active layer T60 of the sixth transistor T6. The second region of the active layer T60 of the sixth transistor T6 can simultaneously serve as the second region of the active layer T70 of the seventh transistor T7.

[0200] In some examples, the active layer T10 of the first transistor T1, the active layer T40 of the fourth transistor T4, and the active layer T70 of the seventh transistor T7 may be approximately I-shaped, the active layer T30 of the third transistor T3 may be approximately U-shaped, the active layer T60 of the sixth transistor T6 and the active layer T80 of the eighth transistor T8 may be approximately L-shaped, and the active layer T50 of the fifth transistor T5 may be approximately F-shaped.

[0201] In some examples, as shown in FIG8 , the display area AA may include multiple pixel circuit groups, each pixel circuit group may include two pixel circuits adjacently arranged in a first direction X. Each pixel circuit group may be substantially symmetrically arranged about a center line of the pixel circuit group in the first direction X. The active layers T80 of the eighth transistors of the two pixel circuits in each pixel circuit group may be an integrated structure connected to each other.

[0202] In some examples, the orthographic projection of the first base structure 411 on the substrate may at least partially overlap the orthographic projection of the active layer T30 of the third transistor T3 of the pixel circuit on the substrate. For example, the orthographic projection of the first base structure 411 on the substrate may cover the orthographic projection of the channel region of the active layer T30 on the substrate. In this example, the first base structure 411 can shield the channel region of the active layer T30 of the third transistor T3, thereby reducing the impact of external light on the third transistor, thereby ensuring the performance of the third transistor.

[0203] (4) Forming a first conductive layer. In some examples, a second insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure. The first conductive film is patterned by a patterning process to form a second insulating layer and a first conductive layer disposed on the second insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the second insulating layer may also be referred to as a first gate insulating layer.

[0204] FIG9A is a partial schematic diagram of the display substrate after the first conductive layer is formed in FIG6 . FIG9B is a schematic diagram of the first conductive layer in FIG9A . In some examples, as shown in FIG9A and FIG9B , the first conductive layer of the display area AA may include at least: first electrodes of storage capacitors of multiple pixel circuits (e.g., first electrode Cst-1), multiple first scan lines (e.g., including first scan line GL1(m)), multiple first reset control lines (e.g., including first reset control line RST1(m)), multiple second reset control lines (e.g., including second reset control line RST2(m)), and multiple emission control lines (e.g., including emission control line EML(m)).

[0205] In some examples, as shown in Figures 9A and 9B, the overlapping region between the first electrode Cst-1 of the storage capacitor and the active layer T30 of the third pixel circuit T3 can serve as the gate of the third transistor T3. The overlapping region between the first scan line GL1(m) and the active layer T40 of the fourth transistor T4 can serve as the gate of the fourth transistor T4. The overlapping region between the first reset control line RST1(m) and the active layer T10 of the first transistor T1 can serve as the gate of the first transistor T1. The overlapping region between the second reset control line RST2(m) and the active layer T70 of the seventh transistor T7 can serve as the gate of the seventh transistor T7, and the overlapping region between the second reset control line RST2(m) and the active layer T80 of the eighth transistor T8 can serve as the gate of the eighth transistor T8. The overlapping region between the emission control line EML(m) and the active layer T50 of the fifth transistor T5 can serve as the gate of the fifth transistor T5, and the overlapping region between the emission control line EML(m) and the active layer T60 of the sixth transistor T6 can serve as the gate of the sixth transistor T6.

[0206] 9A and 9B , the first conductive layer of the second fan-out region B11 may include at least a plurality of first data fan-out lines 401. The plurality of first data fan-out lines 401 may be sequentially arranged along the first direction X and extend toward one side of the bending region.

[0207] (5) Forming a second conductive layer. In some examples, a third insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned by a patterning process to form a third insulating layer and a second conductive layer disposed on the third insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the third insulating layer may also be referred to as a second gate insulating layer.

[0208] Figure 10A is a partial schematic diagram of the display substrate after the second conductive layer is formed in Figure 6. Figure 10B is a schematic diagram of the second conductive layer in Figure 10A. In some examples, as shown in Figures 10A and 10B, the second conductive layer in the display area AA may include at least: second electrodes of storage capacitors of multiple pixel circuits (e.g., second electrode Cst-2), and multiple second auxiliary scanning lines (e.g., including second auxiliary scanning lines GL2a(m)). The second auxiliary scanning lines GL2a(m) may be located on one side of the second electrode Cst-2 of the storage capacitor of the corresponding pixel circuit in the second direction Y.

[0209] In some examples, as shown in Figures 10A and 10B, the second conductive layer of the second fan-out region B11 may include at least a plurality of second data fan-out lines 402. The plurality of second data fan-out lines 402 may be arranged sequentially along the first direction X and extend toward one side of the bending region. The plurality of second data fan-out lines 402 and the plurality of first data fan-out lines 401 may be arranged alternately along the first direction X, and the orthographic projections of the first data fan-out lines 401 and the second data fan-out lines 402 on the substrate may not overlap.

[0210] (6) Forming a second semiconductor layer. In some examples, a fourth insulating film and a second semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second semiconductor film is patterned by a patterning process to form a fourth insulating layer and a second semiconductor layer disposed on the fourth insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the fourth insulating layer may also be referred to as a third gate insulating layer.

[0211] Figure 11 is a partial schematic diagram of the display substrate after the second semiconductor layer is formed in Figure 6. In some examples, as shown in Figure 11, the second semiconductor layer in the display area AA may include at least active layers of the second-type transistors of the plurality of pixel circuits, such as the active layer T20 of the second transistor T2. The active layer T20 of the second transistor T2 may be substantially L-shaped. The orthographic projection of the active layer T20 of the second transistor T2 onto the substrate may be located between the active layer T10 of the first transistor T1 and the active layer T50 of the fifth transistor T5 in the second direction Y.

[0212] (7) Forming a third conductive layer. In some examples, a fifth insulating film and a third conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The third conductive film is patterned by a patterning process to form a fifth insulating layer and a third conductive layer disposed on the fifth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fifth insulating layer may also be referred to as a fourth gate insulating layer.

[0213] FIG12A is a partial schematic diagram of the display substrate after the third conductive layer is formed in FIG6 . FIG12B is a schematic diagram of the third conductive layer in FIG12A . In some examples, as shown in FIG12A and FIG12B , the third conductive layer of the display area AA may include at least: a plurality of first initial signal lines (e.g., including the first initial signal line INIT1(m)), a plurality of second initial signal lines (e.g., including the second initial signal line INIT2(m)), a plurality of third initial signal lines (e.g., including the third initial signal line INIT3(m)), and a plurality of second scan lines (e.g., including the second scan line GL2(m)).

[0214] In some examples, the first initial signal line INIT1(m), the second initial signal line INIT2(m), the third initial signal line INIT3(m), and the second scan line GL2(m) may be substantially in the shape of a zigzag line extending along the first direction X. The first initial signal line INIT1(m), the second scan line GL2(m), the second initial signal line INIT2(m), and the third initial signal line INIT3(m) may be sequentially arranged in a direction opposite to the second direction X. An inactive first initial signal line may further be provided between the second initial signal line INIT2(m) and the third initial signal line INIT3(m).

[0215] In some examples, the overlapping region between the second scan line GL2(m) and the active layer T20 of the second transistor T2 can serve as the gate of the second transistor T2. The overlapping region between the second scan auxiliary line GL2a(m) and the active layer T20 of the second transistor T2 can serve as the bottom gate of the second transistor T2. The second scan auxiliary line GL2a(m) and the second scan line GL2(m) can be connected in the second border region to transmit the same second scan signal. However, this embodiment is not limited to this.

[0216] (8) Forming a sixth insulating layer. In some examples, a sixth insulating film is deposited on the substrate having the aforementioned pattern, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. In some examples, the sixth insulating layer may also be referred to as an interlayer insulating layer. The sixth insulating layer may have a plurality of vias.

[0217] Figure 13 is a partial schematic diagram of the display substrate after the sixth insulating layer is formed in Figure 6. In some examples, as shown in Figure 13, the multiple vias defined in the sixth insulating layer in display area AA may include: first through tenth vias V1 through V10, an eleventh through V11, a twelfth through V12, a thirteenth through V13, a fourteenth through V14, and fifteenth through seventeenth vias V15 through V17. The sixth, fifth, fourth, third, and second insulating layers within the first through tenth vias V1 through V10 may be removed, exposing a portion of the surface of the first semiconductor layer. The sixth, fifth, fourth, and third insulating layers within the eleventh through V11 may be removed, exposing a portion of the surface of the first conductive layer. The sixth, fifth, and fourth insulating layers within the twelfth through V12 may be removed, exposing a portion of the surface of the second conductive layer. The sixth and fifth insulating layers in the thirteenth and fourteenth via holes V13 and V14 can be removed to expose a portion of the surface of the second semiconductor layer. The sixth insulating layer in the fifteenth to seventeenth via holes V15 to V17 can be removed to expose a portion of the surface of the third conductive layer.

[0218] In some examples, as shown in FIG13 , the plurality of vias opened in the sixth insulating layer of the second fan-out area B11 may include: a plurality of twenty-first vias V21, a plurality of twenty-second vias V22, and a plurality of twenty-third vias V23. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the plurality of twenty-first vias V21 may be removed to expose a portion of the surface of the bottom blocking layer. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer within the plurality of twenty-second vias V22 may be removed to expose a portion of the surface of the first conductive layer. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the plurality of twenty-third vias V23 may be removed to expose a portion of the surface of the second conductive layer.

[0219] (9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the sixth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0220] FIG14A is a partial schematic diagram of the display substrate after the fourth conductive layer is formed in FIG6 . FIG14B is a schematic diagram of the fourth conductive layer in FIG14A . In some examples, as shown in FIG14A and FIG14B , the fourth conductive layer in the display area AA may include at least: a plurality of pixel connection electrodes (e.g., including first to ninth pixel connection electrodes 301 to 309 ), and a plurality of initial transmission lines (e.g., including first initial transmission line 41 , second initial transmission line 42 , and third initial transmission line 43 ).

[0221] In some examples, the first pixel connection electrode 301 can be connected to the first region of the active layer T10 of the first transistor T1 through a first via hole V1, and can also be connected to the first initial signal line INIT1(m) through a fifteenth via hole V15. The second pixel connection electrode 302 can be connected to the second region of the active layer T10 of the first transistor T1 through a second via hole V2, can also be connected to the second region of the active layer T30 of the third transistor T3 through a fourth via hole V4, and can also be connected to the first region of the active layer T20 of the second transistor T2 through a fourteenth via hole V14. The second pixel connection electrode 302 can electrically connect the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6, and the second pixel connection electrode 302 can serve as the third node N3 of the pixel circuit. The third pixel connection electrode 303 can be connected to the second region of the active layer T20 of the second transistor T2 through a thirteenth via hole V13, and can also be connected to the first electrode Cst-1 of the storage capacitor through an eleventh via hole V11. The third pixel connection electrode 303 can electrically connect the second transistor T2, the storage capacitor, and the third transistor T3, and can serve as the first node N1 of the pixel circuit. The fourth pixel connection electrode 304 can be connected to the first area of ​​the active layer T40 of the fourth transistor T4 through the third via hole V3. The fifth pixel connection electrode 305 can be connected to the second electrode Cst-2 of the storage capacitor through the twelfth via hole V12, and can also be connected to the first area of ​​the fifth active layer T50 of the fifth transistor T5 through the sixth via hole V6. The sixth pixel connection electrode 306 can be connected to the second area of ​​the active layer T60 of the sixth transistor T6 through the seventh via hole V7. The seventh pixel connection electrode 307 can be connected to the third initial signal line INIT3(m) through the sixteenth via hole V16, and can also be connected to the first area of ​​the active layer T80 of the eighth transistor T8 through the tenth via hole V10. The eighth pixel connection electrode 308 can be connected to the first area of ​​the active layer T70 of the seventh transistor T7 through the eighth via hole V8, and can also be connected to the second initial signal line INIT2(m) through the seventeenth via hole V17. The ninth pixel connection electrode 309 can be connected to the second area of ​​the active layer T80 of the eighth transistor T8 through the ninth via hole V9, and can also be connected to the second area of ​​the active layer T50 of the fifth transistor T5 through the fifth via hole V5.

[0222] In some examples, the first initial transmission line 41, the second initial transmission line 42, and the third initial transmission line 43 may be strips extending along the second direction Y. The first initial transmission line 41 may be connected to the first initial signal line INIT1(m). For example, the first initial transmission line 41 and two adjacent first pixel connection electrodes may be an integrated structure connected to each other, thereby achieving connection to the first initial signal line INIT1(m). The second initial transmission line 41 extending along the second direction Y is connected to the first initial signal line extending along the first direction X, and a grid structure for transmitting the first initial signal may be formed in the display area AA, which is beneficial to the transmission stability and uniformity of the first initial signal. The second initial transmission line 42 extending along the second direction Y is connected to the second initial signal line extending along the first direction X, and a grid structure for transmitting the second initial signal may be formed in the display area AA, which is beneficial to the transmission stability and uniformity of the second initial signal. The third initial transmission line 43 extending along the second direction Y is connected to the third initial signal line (for example, the third initial signal line INIT3(m)) extending along the first direction X, and a grid structure for transmitting the third initial signal can be formed in the display area AA, which is beneficial to the transmission stability and uniformity of the third initial signal.

[0223] In some examples, the first initial transmission line 41 can be located between two adjacent pixel circuit groups, such as between the j+3th column pixel circuit and the j+4th column pixel circuit; the second initial transmission line 42 can be located between two adjacent pixel circuit groups, such as between the j+5th column pixel circuit and the j+6th column pixel circuit; the third initial transmission line 43 can be located between two adjacent pixel circuit groups, such as between the j+1th column pixel circuit and the j+2th column pixel circuit.

[0224] In some examples, as shown in Figures 14A and 14B, the fourth conductive layer of the second fan-out area B11 may include at least: a plurality of frame transfer electrodes (for example, including a first frame transfer electrode 311, a second frame transfer electrode 312, a third frame transfer electrode 313, a fourth frame transfer electrode 314, a fifth frame transfer electrode 315 and a sixth frame transfer electrode 316), a plurality of first-type voltage transfer electrodes (for example, including a plurality of first voltage transfer electrodes 141, a plurality of second voltage transfer electrodes 142 and a plurality of third voltage transfer electrodes 143), and a plurality of auxiliary electrodes (for example, including a first auxiliary electrode 361 and a second auxiliary electrode 362).

[0225] In some examples, a plurality of frame transfer electrodes may be arranged along a first direction X and located on a side of the first type voltage connection electrode and the plurality of auxiliary electrodes close to the display area AA. The first frame transfer electrode 311 may be connected to a second data fan-out line 402 through two twenty-second vias V22 arranged vertically. The second frame transfer electrode 312 may be connected to a first data fan-out line 401 through two twenty-third vias V23 arranged vertically. The fifth frame transfer electrode 315 may be connected to a second data fan-out line 402, and the sixth frame transfer electrode 316 may be connected to a first data fan-out line 401. The third frame transfer electrode 313 may be connected to a second data fan-out line 402 located on the second conductive layer. The fourth frame transfer electrode 314 may be connected to a first data fan-out line 401 located on the first conductive layer.

[0226] In some examples, the first voltage conversion electrode 141 may have a first main body and a first protrusion, and the first main body and the first protrusion are an integral structure connected to each other. The shape of the first main body may be roughly rectangular, and the shape of the first protrusion may be roughly dumbbell-shaped extending along the second direction Y. The first main body may be located on the side of the first frame conversion electrode 311, the second frame conversion electrode 312, and the third frame conversion electrode 313 away from the display area AA, and the first protrusion may be located on the side of the third frame conversion electrode 313 in the first direction X. The first protrusion of the first voltage conversion electrode 141 can be connected to the second bottom structure 412 of the bottom shielding layer through the twenty-first via V21.

[0227] In some examples, the second voltage conversion electrode 142 may have a second main portion and a second protruding portion. The second main portion and the second protruding portion are interconnected as an integral structure. The second main portion may be substantially rectangular, and the second protruding portion may be substantially strip-shaped extending along the second direction Y. The second protruding portion may be located on one side of the sixth frame conversion electrode 316 in the first direction X. The second main portion may be located on a side of the fourth frame conversion electrode 314, the fifth frame conversion electrode 315, and the sixth frame conversion electrode 316 away from the display area AA.

[0228] In some examples, the third voltage conversion electrode 143 may include a third main portion 143-1 and multiple third protrusions 143-2. ​​The third main portion 143-1 and the multiple third protrusions 143-2 may be interconnected, integral structures. The third main portion 143-1 may be generally strip-shaped, extending along the first direction X. The third protrusions 143-2 may be generally strip-shaped, extending along the second direction Y. The multiple third protrusions 143-2 may be located on a side of the third main portion 143-1 that is close to the display area AA. The multiple third protrusions 143-2 and the third main portion 143-1 may be connected to form multiple accommodating areas, and the first voltage conversion electrodes 141 and the second voltage conversion electrodes 142 may be arranged at intervals within the multiple accommodating areas. In other words, a first voltage conversion electrode 141 or a second voltage conversion electrode 142 may be disposed between two adjacent third protrusions 143-2. In the first direction X, the third protrusions 143 - 2 , the first voltage conversion electrodes 141 , the third protrusions 143 - 2 , and the second voltage conversion electrodes 142 may be periodically arranged.

[0229] In some examples, the first auxiliary electrode 361 can be located on a side of the first voltage switching electrode 141 away from the display area AA, and on a side of the third main portion 143-1 of the third voltage switching electrode 143 closer to the display area AA. The first auxiliary electrode 361 can be roughly rectangular. The second auxiliary electrode 362 can be located on a side of the second main portion of the second voltage switching electrode 142 closer to the display area AA. The second auxiliary electrode 362 can be roughly rectangular. The provision of the first auxiliary electrode 361 and the second auxiliary electrode 362 in this example helps ensure uniformity of the film pattern.

[0230] (10) Forming a seventh insulating layer and an eighth insulating layer. In some examples, a seventh insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer; then, an eighth insulating film is applied, and the eighth insulating film is patterned by a patterning process to form an eighth insulating layer. In some examples, the seventh insulating layer may also be referred to as a passivation layer, and the eighth insulating layer may also be referred to as a first planarization layer.

[0231] Figure 15 is a partial schematic diagram of the display substrate after the eighth insulating layer is formed in Figure 6. In some examples, as shown in Figure 15, the multiple vias defined in the eighth insulating layer in display area AA may include: vias 31 to 33 (V31 to V33). The seventh and eighth insulating layers within vias 31 to 33 (V31 to V33) may be removed, exposing a portion of the surface of the fourth conductive layer.

[0232] In some examples, as shown in FIG15 , the plurality of vias defined in the eighth insulating layer of the second fan-out region B11 may include: a thirty-fourth via V34 to a forty-seventh via V47. The seventh insulating layer and the eighth insulating layer within the thirty-fourth via V34 to the forty-seventh via V47 may be removed to expose a portion of the surface of the fourth conductive layer.

[0233] (11) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the eighth insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0234] FIG16A is a partial schematic diagram of the display substrate after the fifth conductive layer is formed in FIG6 . FIG16B is a schematic diagram of the fifth conductive layer in FIG16A . In some examples, as shown in FIG16A and FIG16B , the fifth conductive layer in display area AA may include at least: a plurality of first anode connection electrodes 321, a plurality of data connection electrodes 323, a plurality of first power connection blocks 322, a plurality of first power transverse transmission lines (such as first power transverse transmission lines 34a and 34b), and a plurality of first data transfer lines (such as first data transfer lines 35a and 35b).

[0235] In some examples, the first anode connection electrode 321 can be connected to the sixth pixel connection electrode 306 through the thirty-first via hole V31 to achieve electrical connection with the second electrode of the sixth transistor T6 of the pixel circuit. The data connection electrode 323 can be connected to the fourth pixel connection electrode 304 through the thirty-third via hole V33 to achieve electrical connection with the first electrode of the fourth transistor T4 of the pixel circuit. The first power connection block 322 can be connected to the fifth pixel connection electrode 305 through the thirty-second via hole V32 to achieve electrical connection with the fifth transistor T5 of the pixel circuit and the second electrode of the storage capacitor.

[0236] In some examples, the first power transverse transmission lines 34a and 34b can be shaped as a generally zigzag line extending along the first direction X. The first power transverse transmission line 34a and the first power connection blocks 322 of the pixel circuits in the last row, columns j, j+2, j+4, and j+6 can be interconnected as an integral structure. The first power transverse transmission line 34a can be connected to a subsequently formed first power line VDD3 in the display area AA to form a mesh structure and be configured to transmit the first voltage signal Vdd3, thereby ensuring uniform and stable transmission of the first voltage signal Vdd3. The first power transverse transmission line 34b and the first power connection lines of the pixel circuits in the penultimate row, columns j+1, and columns j+5 can be interconnected as an integral structure. The first power transverse transmission line 34b can be connected to a subsequently formed first power line VDD1 in the display area AA to form a mesh structure and be configured to transmit the first voltage signal Vdd1, thereby ensuring uniform and stable transmission of the first voltage signal Vdd1. Similarly, the display area may further include a first power transverse transmission line connected to the first power line VDD2. The first power horizontal transmission lines transmitting different first voltage signals may be arranged in the second direction Y at intervals.

[0237] In some examples, the first data transfer lines 35a and 35b may be shaped substantially like a broken line extending along the first direction X. In this example, by providing the first data transfer lines, centralized fan-out of the data fan-out lines can be facilitated, which is beneficial to a narrow frame design.

[0238] In some examples, as shown in Figures 16A and 16B, the fifth conductive layer of the second fan-out area B11 may include at least: a plurality of frame transfer electrodes (for example, including a seventh frame transfer electrode 341, an eighth frame transfer electrode 342, a ninth frame transfer electrode 343, a tenth frame transfer electrode 344, an eleventh frame transfer electrode 345 and a twelfth frame transfer electrode 346), a plurality of frame power connection electrodes (for example, including a first frame power connection electrode 331, a second frame power connection electrode 332, a third frame power connection electrode 333, a fourth frame power connection electrode 334), and a plurality of second power supply lines (for example, including second power supply lines 111, 121 and 131).

[0239] In some examples, the seventh frame transition electrode 341, the eighth frame transition electrode 342, the tenth frame transition electrode 344, and the eleventh frame transition electrode 345 can be substantially rectangular in shape; and the ninth frame transition electrode 343 and the twelfth frame transition electrode 346 can be substantially L-shaped. The seventh frame transition electrode 341 can be connected to the first frame transition electrode 311 via the thirty-fifth via hole V35. The eighth frame transition electrode 342 can be connected to the second frame transition electrode 312 via the thirty-sixth via hole V36. The ninth frame transition electrode 343 can be connected to the third frame transition electrode 313 via the thirty-seventh via hole V37. The tenth frame transition electrode 344 can be connected to the fourth frame transition electrode 314 via the thirty-ninth via hole V39. The eleventh frame transition electrode 345 can be connected to the fifth frame transition electrode 315 via the fortieth via hole V40. The twelfth frame transition electrode 346 can be connected to the sixth frame transition electrode 316 via the forty-first via hole V41.

[0240] In some examples, the first frame power connection electrode 331, the second frame power connection electrode 332, the third frame power connection electrode 333, and the fourth frame power connection electrode 334 can be roughly rectangular in shape. The first frame power connection electrode 331 can be connected to a third protrusion 143-2 of the third voltage transfer electrode 143 through the thirty-fourth via V34. The second frame power connection electrode 332 can be connected to the first voltage transfer electrode 141 through the thirty-eighth via V38. The third frame power connection electrode 333 can be connected to another third protrusion 143-2 of the third voltage transfer electrode 143. The fourth frame power connection electrode 334 can be connected to the second voltage transfer electrode 142 through the forty-second via V42.

[0241] In some examples, the second power supply lines 111, 121, and 131 can be substantially strip-shaped and extend along the first direction X. The second power supply line 111 can be connected to the first main body of the first voltage conversion electrode 141 through a plurality of forty-third vias V43, and can also be connected to the second auxiliary electrode 362 through a plurality of forty-fourth vias V44. The second power supply line 121 can be connected to the first auxiliary electrode 361 through a plurality of forty-fifth vias V45, and can also be connected to the second main body of the second voltage conversion electrode 142 through a plurality of forty-sixth vias V46. The second power supply line 131 can be connected to the third main body of the third voltage conversion electrode 143 through a plurality of forty-seventh vias V47.

[0242] (12) Forming a ninth insulating layer. In some examples, a ninth insulating film is coated on the substrate having the aforementioned pattern, and the ninth insulating film is patterned by a patterning process to form a ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as a second planar layer.

[0243] Figure 17 is a partial schematic diagram of the display substrate after the ninth insulating layer is formed in Figure 6. In some examples, as shown in Figure 17, the plurality of vias defined in the ninth insulating layer in the display area AA may include: a fifty-first via V51 to a fifty-third via V53. The plurality of vias defined in the ninth insulating layer in the second fan-out area B11 may include: a fifty-fifth via V55 to a sixty-fourth via V64. The ninth insulating layer within the fifty-first via V51 to the fifty-third via V53 and the fifty-fifth via V55 to the sixty-fourth via V64 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0244] (13) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate having the aforementioned pattern, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the ninth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0245] FIG18A is a partial schematic diagram of the display substrate after the sixth conductive layer is formed in FIG6 . FIG18B is a schematic diagram of the sixth conductive layer in FIG18A . In some examples, as shown in FIG18A and FIG18B , the sixth conductive layer of the display area AA may include at least: a plurality of second anode connection electrodes 324 , a plurality of data lines (e.g., including data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4)), a plurality of first power lines (e.g., including first power lines VDD1, VDD2, and VDD3), and a plurality of second data transfer lines (e.g., including second data transfer lines 36 a and 36 b ).

[0246] In some examples, the second anode connection electrode 324 can be connected to the first anode connection electrode 321 through the fifty-first via V51 to achieve electrical connection with the sixth transistor T6 of the pixel circuit. The multiple data lines can be in the shape of a broken line extending along the second direction Y. For example, the data line DL(j) can be connected to the data connection electrode 323 through the fifty-third via V53 to achieve electrical connection with the fourth transistor T4 of the pixel circuit. The second data transfer lines 36a and 36b can be in the shape of a straight line extending along the second direction Y. For example, the second data transfer line 36b can be connected to the first data transfer line 35a, and the second data transfer line 36a can be connected to the first data transfer line 35b.

[0247] In some examples, the first power lines VDD1, VDD2, and VDD3 can be substantially zigzag-line shaped and extend along the second direction Y, and the first power lines VDD1, VDD2, and VDD3 can be lines of varying widths. The first power line VDD3 located in the jth column can be electrically connected to the first power connection block 322 through the fifty-second via V52, thereby achieving electrical connection to the first power transverse transmission line 34a, the fifth transistor T5, and the storage capacitor of the pixel circuit.

[0248] In some examples, as shown in Figures 18A and 18B, the sixth conductive layer of the second fan-out region B11 may include at least a second sub-route 512 of a second voltage fan-out line. The second voltage fan-out line may be a dual-layer route, for example, including a first sub-route located in the fifth conductive layer and a second sub-route 512 located in the sixth conductive layer. The second sub-route 512 may have multiple first hollow portions, and the orthographic projection of the first hollow portions on the substrate may be substantially rectangular. In this example, by providing multiple first hollow portions in the second sub-route 512, degassing of the ninth insulating layer beneath the large metal block can be facilitated.

[0249] In some examples, the data line DL(j) connected to the pixel circuit in the jth column can extend to the second fan-out area B11 and be connected to the seventh frame transfer electrode 341 through the fifty-ninth via hole V59. The data line DL(j+1) connected to the pixel circuit in the j+1th column can extend to the second fan-out area B11 and be connected to the eighth frame transfer electrode 342 through the sixtieth via hole V60. The second data transfer line 36a located between the data lines DL(j) and DL(j+1) can be connected to the ninth frame transfer electrode 343 through the sixty-first via hole V61. The data line DL(j+2) connected to the pixel circuit in the j+2th column can extend to the second fan-out area B11 and be connected to the eleventh frame transfer electrode 345 through the sixty-third via hole V63. The data line DL(j+3) connected to the pixel circuit in the j+3th column can extend to the second fan-out area B11 and be connected to the twelfth frame transfer electrode 346 through the sixty-fourth via hole V64. The second data transfer line 36b located between the data lines DL(j+2) and DL(j+3) can be connected to the tenth frame transfer electrode 344 through the sixty-second via V62. In this example, the data line and the second data transfer line can be connected to the first data fan-out line located on the first conductive layer or the second data fan-out line located on the second conductive layer through the frame transfer electrodes located on the fifth conductive layer and the fourth conductive layer.

[0250] In some examples, the first power line VDD3 connected to the pixel circuit in the jth column can extend to the second fan-out area B11 and connect to the first frame power connection electrode 331 through the fifty-fifth via V55, thereby connecting to a third protrusion 143-2 of the third voltage transfer electrode 143. The first power line VDD1 connected to the pixel circuit in the j+1th column can extend to the second fan-out area B11 and connect to the second frame power connection electrode 332 through the fifty-sixth via V56, thereby connecting to the first protrusion of the first voltage transfer electrode 141. The first power line VDD3 connected to the pixel circuit in the j+2th column can extend to the second fan-out area B11 and connect to the third frame power connection electrode 333 through the fifty-seventh via V57, thereby connecting to another third protrusion 143-2 of the third voltage transfer electrode 143. The first power line VDD2 connected to the pixel circuit of the j+3th column can extend to the second fan-out area B11 and be connected to the fourth frame power connection electrode 333 through the fifty-eighth via V58 to achieve connection with the second protrusion of the second voltage transfer electrode 142.

[0251] In some examples, the first power line VDD3 connected to the pixel circuits in the jth column can be connected to the second power supply line 131 in the fifth conductive layer, sequentially through the first frame power connection electrode 331 in the fifth conductive layer and the third voltage transfer electrode 143 in the fourth conductive layer. The first power line VDD1 connected to the pixel circuits in the j+1th column can be connected to the second power supply line 111 in the fifth conductive layer, sequentially through the second frame power connection electrode 332 in the fifth conductive layer and the first voltage transfer electrode 141 in the fourth conductive layer. The first power line VDD3 connected to the pixel circuits in the j+2th column can be connected to the second power supply line 131 in the fifth conductive layer, sequentially through the third frame power connection electrode 333 in the fifth conductive layer and the third voltage transfer electrode 143 in the fourth conductive layer. The first power line VDD2 connected to the pixel circuits in the j+3th column can be connected to the second power supply line 121 in the fifth conductive layer, sequentially through the fourth frame power connection electrode 334 in the fifth conductive layer and the second voltage transfer electrode 142 in the fourth conductive layer.

[0252] (14) Forming a tenth insulating layer and an anode layer. In some examples, a tenth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the tenth insulating film is patterned by a patterning process to form a tenth insulating layer. The tenth insulating layer may have a plurality of vias. Subsequently, an anode film is deposited, and the anode film is patterned by a patterning process to form an anode layer. In some examples, the tenth insulating layer may also be referred to as a third planar layer.

[0253] FIG19 is a schematic diagram of the anode layer in FIG6. In some examples, as shown in FIG19, the anode layer may include anodes of multiple light-emitting elements (e.g., the anode 351 of the first light-emitting element PX1-2 in the first sub-pixel group P1, the anode 352 of the second light-emitting element PX2-2 in the second sub-pixel group P2, the anode 353 of the third light-emitting element PX3-2 in the third sub-pixel group P3, and the anode 354 of the fourth light-emitting element PX4-2). The anode 353 of the third light-emitting element PX3-2 may be connected to the pixel circuit in the jth column of the second-to-last row through a via hole provided in the tenth insulating layer. The anode 354 of the fourth light-emitting element PX4-2 may be connected to the pixel circuit in the jth column of the last row through a via hole provided in the tenth insulating layer. The anode 351 of the first light-emitting element PX1-2 may be connected to the pixel circuit in the j+1th column of the second-to-last row. The anode 352 of the second light-emitting element PX2-2 may be connected to the pixel circuit in the j-1th column of the last row. In this example, the anodes of the first light-emitting element and the second light-emitting element may be connected to the corresponding pixel circuits via a winding wire. For example, the winding wire and the connected anode may form an integrated structure connected to each other.

[0254] In some examples, the same column of pixel circuits can be connected to light-emitting elements that emit the same color light, so that different first power lines can provide first voltage signals to light-emitting elements that emit different colors of light. For example, the pixel circuits in the jth column are connected to the first power line VDD3 and are connected to multiple light-emitting elements that emit a third color light (e.g., green light); the pixel circuits in the j+1th column are connected to the first power line VDD1 and are connected to multiple light-emitting elements that emit a first color light (e.g., blue light); the pixel circuits in the j+2th column are connected to the first power line VDD3 and are connected to multiple light-emitting elements that emit a third color light (e.g., green light); and the pixel circuits in the j+3th column are connected to the first power line VDD2 and are connected to multiple light-emitting elements that emit a second color light (e.g., red light).

[0255] In some examples, after the anode layer is formed, a pixel definition layer, an organic light emitting layer, and a cathode layer may be sequentially disposed.

[0256] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The eighth to tenth insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited to this.

[0257] The structure of the display substrate and its preparation process in this embodiment are merely illustrative. In some examples, the corresponding structure can be modified and patterning processes can be added or reduced according to actual needs. For example, the fifth or sixth conductive layer can be omitted. In another example, the bottom shielding layer can be omitted. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to implement, easy to implement, and has high production efficiency, low production cost, and high yield rate.

[0258] Figures 20A, 21A, and 22A are partially enlarged schematic diagrams of region C2 in Figure 5. Figures 20A, 21A, and 22A primarily illustrate the structures of the fourth and fifth conductive layers in region C2. Figure 20A primarily illustrates the transition region between the second power supply line 111 and the first power supply meander line 113a in the second fan-out region; Figure 21A primarily illustrates the transition region between the second power supply line 121 and the first power supply meander line 123a in the second fan-out region; and Figure 22A primarily illustrates the transition region between the second power supply line 131 and the first power supply meander line 133a in the second fan-out region.

[0259] Figure 20B is a schematic diagram of the fourth conductive layer in Figure 20A. Figure 20C is a schematic diagram of Figure 20A after the eighth insulating layer is formed. Figure 20D is a schematic diagram of the fifth conductive layer in Figure 20A. Figure 21B is a schematic diagram of the fourth conductive layer in Figure 21A. Figure 21C is a schematic diagram of Figure 21A after the eighth insulating layer is formed. Figure 21D is a schematic diagram of the fifth conductive layer in Figure 21A. Figure 22B is a schematic diagram of the fourth conductive layer in Figure 22A. Figure 22C is a schematic diagram of Figure 22A after the eighth insulating layer is formed. Figure 22D is a schematic diagram of the fifth conductive layer in Figure 22A.

[0260] In some examples, as shown in Figures 20B, 21B, and 22B, the fourth conductive layer of the second fan-out region may include at least: a plurality of first-type voltage transfer electrodes (for example, a first voltage transfer electrode 141, a second voltage transfer electrode 142, and a third voltage transfer electrode 143), a plurality of second-type voltage transfer electrodes (for example, a fourth voltage transfer electrode 144, a fifth voltage transfer electrode 145, and a sixth voltage transfer electrode 146), and a plurality of auxiliary connection electrodes (for example, a first auxiliary connection electrode 147 and a second auxiliary connection electrode 148). In this example, the first-type voltage transfer electrodes can realize the connection between the first power line and the second power line, and the second-type voltage transfer electrodes can realize the connection between the first power line, the second power line, and the first power supply zigzag line.

[0261] In some examples, the first voltage conversion electrode 141 can be connected to the first power line VDD1 of the display area, the second voltage conversion electrode 142 can be connected to the first power line VDD2 of the display area, and the third voltage conversion electrode 143 can be connected to the first power line VDD3 of the display area.

[0262] In some examples, the first auxiliary connection electrode 147 and the second auxiliary connection electrode 148 may be substantially strip-shaped extending along the second direction Y, and the length of the second auxiliary connection electrode 148 along the second direction Y may be greater than the length of the first auxiliary connection electrode 147 along the second direction Y. One first auxiliary connection electrode 147 may be connected to one first power line VDD2 of the display area, and one second auxiliary connection electrode 148 may be connected to one second power line VDD3 of the display area.

[0263] In some examples, as shown in FIG20B , the fourth voltage conversion electrode 144 can include a fourth main portion 144-1, a plurality of fourth protrusions 144-2, and a plurality of fifth protrusions 144-3. The fourth main portion 144-1, the plurality of fourth protrusions 144-2, and the plurality of fifth protrusions 144-3 can be interconnected and integrally formed. The fourth main portion 144-1 can be substantially rectangular, the fourth protrusion 144-2 can be substantially L-shaped, and the fifth protrusion 144-3 can be substantially rectangular. The fourth protrusion 144-2 and the fifth protrusion 144-3 can be located on a side of the fourth main portion 144-1 closer to the display area, and the fourth protrusion 144-2 and the fifth protrusion 144-3 can be spaced apart along the first direction X. A second auxiliary connection electrode 148 may be disposed between the fourth protrusion 144-2 and the fifth protrusion 144-3 adjacent to the fourth protrusion 144-2 in the first direction X. A first auxiliary connection electrode 147 and a second auxiliary connection electrode 148 arranged along the first direction X may be disposed between the fifth protrusion 144-3 and the fourth protrusion 144-2 adjacent to the first direction X. The fourth protrusion 144-2 may be configured to be connected to the first power line VDD1 of the display area, and the fifth protrusion 144-3 may be configured not to be directly connected to the first power line.

[0264] In some examples, as shown in FIG21B , the fifth voltage conversion electrode 145 may include a fifth main portion 145-1, multiple sixth protruding portions 145-2, and multiple seventh protruding portions 145-3. The fifth main portion 145-1, multiple sixth protruding portions 145-2, and multiple seventh protruding portions 145-3 may be interconnected and integrally formed. The fifth main portion 145-1 may be generally rectangular, the sixth protruding portion 145-2 may be generally L-shaped, and the seventh protruding portion 145-3 may be generally rectangular. The sixth and seventh protruding portions 145-2, 145-3 may be located on the side of the fifth main portion 145-1 closest to the display area. A second auxiliary electrode 362 may be provided on the side of the sixth protruding portion 145-2 closest to the display area, and a first voltage conversion electrode 141 may be provided on the side of the seventh protruding portion 145-3 closest to the display area. The sixth protrusion 145-2 and the seventh protrusion 145-3 may be spaced apart along the first direction X, and a second auxiliary connection electrode 148 may be disposed between adjacent sixth protrusions 145-2 and seventh protrusions 145-3. One sixth protrusion 145-2 may be configured to be connected to a first power line VDD2 of the display area, while the seventh protrusion 145-3 may be configured not to be directly connected to the first power line.

[0265] In some examples, as shown in FIG22B , the sixth voltage conversion electrode 146 may include a sixth main portion 146-1 and a plurality of eighth protruding portions 146-2. The sixth main portion 146-1 and the plurality of eighth protruding portions 146-2 may be interconnected integral structures. The sixth main portion 146-1 may be substantially rectangular, and the eighth protruding portions 146-2 may be substantially strip-shaped extending along the second direction Y. The eighth protruding portions 146-2 may be located on a side of the sixth main portion 146-1 closer to the display area. Between two adjacent eighth protruding portions 146-2, the first voltage conversion electrode 141 and the first auxiliary electrode 361 may be arranged along the second direction Y, or the second voltage conversion electrode 142 and the second auxiliary electrode 362 may be arranged along the second direction Y.

[0266] In some examples, as shown in Figures 20D, 21D, and 22D, the fifth conductive layer of the first border area may include at least: second power supply lines 111, 121, and 131, a first sub-line 511 of the second voltage fan-out line, and first power supply bending lines 113a, 123a, and 133a. The first power supply bending line 113a may extend from the bending area to the second fan-out area and be connected to the fourth voltage transfer electrode 144 in the second fan-out area, the first power supply bending line 123a may extend from the bending area to the second fan-out area and be connected to the fifth voltage transfer electrode 145 in the second fan-out area, and the first power supply bending line 133a may extend from the bending area to the second fan-out area and be connected to the sixth voltage transfer electrode 146 in the second fan-out area.

[0267] In some examples, as shown in Figures 20C, 21C, and 22C, the first border region may be provided with at least a first opening K1, a second opening K2, a third opening K3, and a first groove K4. The eighth insulating layer and the seventh insulating layer within the first opening K1, the second opening K2, and the third opening K3 may be removed to expose a portion of the surface of the fourth conductive layer. The eighth insulating layer within the first groove K4 may be removed, while retaining the seventh insulating layer.

[0268] In some examples, the second power supply lines 111, 121, and 131 may be substantially straight lines extending along the first direction X. The second power supply lines 111, 121, and 131 may be arranged sequentially in the opposite direction of the second direction Y. The first sub-line 511 of the second voltage fan-out line may be located on a side of the second power supply line 131 away from the display area. The orthographic projection of the first sub-line 511 of the second voltage fan-out line on the substrate may cover the orthographic projection of the first groove K4 on the substrate. By retaining the seventh insulating layer in the first groove K4, an insulation setting between the first sub-line 511 of the second voltage fan-out line and the voltage transfer electrode may be achieved.

[0269] In some examples, the second power supply line 111 can be connected to the first voltage transfer electrode 141, the second auxiliary electrode 362, and the fourth protrusion 144-2 and the fifth protrusion 144-3 of the fourth voltage transfer electrode 144. The second power supply line 121 can be connected to the second voltage transfer electrode 142, the first auxiliary electrode 361, the first auxiliary connection electrode 147, and the sixth protrusion 145-2 and the seventh protrusion 145-3 of the fifth voltage transfer electrode 145. The second power supply line 131 can be connected to the third voltage transfer electrode 143, the second auxiliary connection electrode 148, and the sixth body portion 146-1 of the sixth voltage transfer electrode 146.

[0270] In some examples, as shown in Figures 20A and 20D, the first power supply meander line 113a may include at least a first connection portion 113a-1, a bend portion 113a-2, and a second connection portion 113a-3 (as shown in Figure 23A). The first connection portion 113a-1, the bend portion 113a-2, and the second connection portion 113a-3 may be interconnected as an integral structure. The first connection portion 113a-1 may be substantially rectangular in shape. The first connection portion 113a-1 may be located on a side of the first sub-trace 511 of the second voltage fan-out line away from the display area. The first connection portion 113a-1 may be connected to the fourth main portion 144-1 of the fourth voltage conversion electrode 144 through a first opening K1. The bend portion 113a-2 may include multiple bends arranged sequentially along the first direction X. In this example, the fourth voltage conversion electrode 144 may be used to achieve electrical connection between the second power supply line 111 and the first power supply meander line 113a.

[0271] In some examples, as shown in Figures 21A and 21D, the first power supply meander line 123a may include: a first connection portion 123a-1, a bend portion 123a-2, and a second connection portion 123a-3 (as shown in Figure 23A). The first connection portion 123a-1, the bend portion 123a-2, and the second connection portion 123a-3 may be an interconnected, integral structure. The first connection portion 123a-1 may be substantially rectangular in shape. The first connection portion 123a-1 may be located on a side of the first sub-trace 511 of the second voltage fan-out line away from the display area. The first connection portion 123a-1 may be connected to the fifth main portion 145-1 of the fifth voltage conversion electrode 145 through the second opening K2. The bend portion 113a-2 may include multiple bends arranged sequentially along the first direction X. In this example, the fifth voltage conversion electrode 145 may be used to achieve electrical connection between the second power supply line 121 and the first power supply meander line 123a.

[0272] In some examples, as shown in Figures 22A and 22D, the first power supply meander line 133a may include at least a first connection portion 133a-1, a bend portion 133a-2, and a second connection portion 133a-3 (as shown in Figure 23A). The first connection portion 133a-1, the bend portion 133a-2, and the second connection portion 133a-3 may be interconnected as an integral structure. The first connection portion 133a-1 may be substantially rectangular in shape. The first connection portion 133a-1 may be located on a side of the first sub-trace 511 of the second voltage fan-out line away from the display area. The first connection portion 133a-1 may be connected to the sixth main portion 146-1 of the sixth voltage conversion electrode 146 through a third opening K3. The bend portion 133a-2 may include multiple bends arranged sequentially along the first direction X. In this example, the sixth voltage conversion electrode 146 may be used to achieve electrical connection between the second power supply line 131 and the first power supply meander line 133a.

[0273] Regarding the connection method between the first power line and the second power line in this example, reference can be made to the description of the aforementioned embodiment, and therefore no further details will be given here.

[0274] Figure 23A is a partially enlarged schematic diagram of region C3 in Figure 5 . Figure 23A illustrates the structures of the fourth, fifth, and sixth conductive layers in region C3. Figure 23B is a schematic diagram of the fourth conductive layer in Figure 23A . Figure 23C is a schematic diagram of Figure 23A after the eighth insulating layer is formed. Figure 23D is a schematic diagram of the fifth conductive layer in Figure 23A . Figure 23E is a schematic diagram of Figure 23A after the ninth insulating layer is formed. Figure 23F is a schematic diagram of the sixth conductive layer in Figure 23A .

[0275] In some examples, as shown in Figures 23A to 23F, the first power supply lines 112a, 122a, and 132a in the first fan-out region can be a three-layer routing structure. Each first power supply line may include: a first routing line located on the fourth conductive layer, a second routing line located on the fifth conductive layer, and a third routing line located on the sixth conductive layer. For example, the first power supply line 112a may include: a first routing line 112a-1 located on the fourth conductive layer, a second routing line 112a-2 located on the fifth conductive layer, and a third routing line 112a-3 located on the sixth conductive layer; the first power supply line 122a may include: a first routing line 122a-1 located on the fourth conductive layer, a second routing line 122a-2 located on the fifth conductive layer, and a third routing line 122a-3 located on the sixth conductive layer; and the first power supply line 132a may include: a first routing line 132a-1 located on the fourth conductive layer, a second routing line 132a-2 located on the fifth conductive layer, and a third routing line 132a-3 located on the sixth conductive layer.

[0276] In some examples, as shown in FIG23C , the eighth insulating layer in the first fan-out region may be provided with a fifth opening K5, a sixth opening K6, and a seventh opening K7. The eighth insulating layer and the seventh insulating layer within the fifth opening K5, the sixth opening K6, and the seventh opening K7 may be removed, exposing a portion of the surface of the fourth conductive layer. As shown in FIG23E , the ninth insulating layer in the first fan-out region may be provided with an eighth opening K8, a ninth opening K9, and a tenth opening K10. The ninth insulating layer within the eighth opening K8, the ninth opening K9, and the tenth opening K10 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0277] In some examples, as shown in Figures 23A to 23F, the second connection portion 113a-3 of the first power supply meander line 113a can extend to the first fan-out region and connect to the first power supply line 112a in the first fan-out region. The second connection portion 113a-3 located on the fifth conductive layer and the second trace 112a-2 of the first power supply line 112a can be interconnected as an integral structure. The second trace 112a-2 can be connected to the first trace 112a-1 located on the fourth conductive layer via a fifth opening K5. The third trace 112a-3 located on the sixth conductive layer can be connected to the second trace 112a-2 located on the fifth conductive layer via an eighth opening K8. The orthographic projection of the third trace 112a-3 on the substrate can partially overlap with the orthographic projections of the second connection portion 123a-3 of the first power supply meander line 123a and the second connection portion 133a-3 of the first power supply meander line 133a on the substrate.

[0278] In some examples, as shown in Figures 23A to 23F, the second connection portion 123a-3 of the first power supply meander line 123a can extend to the first fan-out region and connect to the first power supply line 122a in the first fan-out region. The second connection portion 123a-3 located on the fifth conductive layer and the second trace 122a-2 of the first power supply line 122a can be interconnected as an integral structure. The second trace 122a-2 can be connected to the first sub-trace 122a-1 located on the fourth conductive layer via a sixth opening K6. The third trace 122a-3 located on the sixth conductive layer can be connected to the second trace 122a-2 located on the fifth conductive layer via a ninth opening K9. The orthographic projection of the third trace 122a-3 on the substrate can partially overlap with the orthographic projection of the second connection portion 133a-3 of the first power supply meander line 133a on the substrate.

[0279] In some examples, as shown in Figures 23A to 23F, the second connection portion 133a-3 of the first power supply meander line 133a can extend to the first fan-out region and connect to the first power supply line 132a in the first fan-out region. The second connection portion 123a-3 located in the fifth conductive layer and the second trace 132a-2 of the first power supply line 132a can be interconnected as an integrated structure. The second trace 132a-2 can be connected to the first trace 132a-1 located in the fourth conductive layer via the seventh opening K7. The third sub-trace 132a-3 located in the sixth conductive layer can be connected to the second trace 132a-2 located in the fifth conductive layer via the tenth opening K10.

[0280] In some examples, as shown in FIG23D , a plurality of hollow portions may be provided in the areas where the second connection portion 113a-3 of the first power supply bending line 113a, the second connection portion 123a-3 of the first power supply bending line 123a, and the second connection portion 133a-3 of the first power supply bending line 133a overlap with the eighth insulating layer to facilitate exhaust of the eighth insulating layer.

[0281] Figure 24A is a partially enlarged schematic diagram of region C4 in Figure 5 . Figure 24B is a schematic diagram of the fourth conductive layer in Figure 24A . Figure 24C is a schematic diagram of Figure 24A after the eighth insulating layer is formed. Figure 24D is a schematic diagram of the fifth conductive layer in Figure 24A . Figure 24E is a schematic diagram of the sixth conductive layer in Figure 24A .

[0282] In some examples, as shown in Figures 24A to 24E, the first power supply lines 112a and 112b of the first fan-out area can be arranged roughly symmetrically about the center line of the first fan-out area in the first direction X; the first power supply lines 122a and 122b can be arranged roughly symmetrically about the center line of the first fan-out area in the first direction X; and the first power supply lines 132a and 132b can be arranged roughly symmetrically about the center line of the first fan-out area in the first direction X.

[0283] In some examples, the first power supply lines 132a and 132b can be interconnected as an integrated structure. As shown in FIG24B , the first trace 132a-1 of the first power supply line 132a located on the fourth conductive layer and the first trace 132b-1 of the first power supply line 132b located on the fourth conductive layer can be interconnected as an integrated structure. As shown in FIG24D , the second trace 132a-2 of the first power supply line 132a located on the fifth conductive layer and the second trace 132b-2 of the first power supply line 132b located on the fifth conductive layer, as well as the first power supply meandering line 133b can be interconnected as an integrated structure. As shown in FIG24E , the third trace 132a-3 of the first power supply line 132a located on the sixth conductive layer and the third trace 132b-3 of the first power supply line 132b located on the sixth conductive layer can be interconnected as an integrated structure.

[0284] In some examples, as shown in Figure 24D, the second route 112a-2 of the first power supply line 112a and the first power supply bend line 113b can be an integrated structure connected to each other; the second route 122a-2 of the first power supply line 122a and the first power supply bend line 123b can be an integrated structure connected to each other; the second route 112b-2 of the first power supply line 112b and the first power supply bend line 113c can be an integrated structure connected to each other; the second route 122b-2 of the first power supply line 122b and the first power supply bend line 123c can be an integrated structure connected to each other.

[0285] In some examples, as shown in FIG24C , the eighth insulating layer in the first fan-out region may be provided with an eleventh opening K11, a twelfth opening K12, a thirteenth opening K13, a fourteenth opening K14, and a fifteenth opening K15. The eighth insulating layer and the seventh insulating layer within the eleventh opening K11, the twelfth opening K12, the thirteenth opening K13, the fourteenth opening K14, and the fifteenth opening K15 may be removed to expose a portion of the surface of the fourth conductive layer. The ninth insulating layer may be provided with an opening that exposes a portion of the surface of the fifth conductive layer.

[0286] In some examples, as shown in Figures 24A to 24E, the second route 112a-2 of the first power supply line 112a can be connected to the first route 112a-1 through the eleventh opening K11; the second route 122a-2 of the first power supply line 122a can be connected to the first route 122a-1 through the twelfth opening K12; the second route 132a-2 of the first power supply line 132a can be connected to the first route 132a-1 through the thirteenth opening K13; the second route 11ba-2 of the first power supply line 112b can be connected to the first route 112b-1 through the fourteenth opening K14; the second route 122b-2 of the first power supply line 122b can be connected to the first route 122b-1 through the fifteenth opening K15. The third route 112a-3 of the first power supply line 112a can be connected to the second route 112a-2 through the opening of the ninth insulating layer; the third route 122a-3 of the first power supply line 122a can be connected to the second route 122a-2 through the opening of the ninth insulating layer; the third route 132a-3 of the first power supply line 132a can be connected to the second route 132a-2 through the opening of the ninth insulating layer; the third route 112b-3 of the first power supply line 112b can be connected to the second route 112b-2 through the opening of the ninth insulating layer; the third route 122b-3 of the first power supply line 122b can be connected to the second route 122b-2 through the opening of the ninth insulating layer.

[0287] Figure 25 is a partially enlarged schematic diagram of area C5 in Figure 24A. In some examples, the third trace of the sixth conductive layer of the first power supply line may have a fifth edge F5, the second trace of the fifth conductive layer may have a fourth edge F4, the first trace of the fourth conductive layer may have a third edge F3, the opening of the seventh insulating layer may have a first edge F1, and the opening of the eighth insulating layer may have a second edge F2. The orthographic projection of the opening of the seventh insulating layer on the substrate may overlap the orthographic projection of the corresponding opening of the eighth insulating layer on the substrate. The orthographic projection of the third trace on the substrate may overlap the orthographic projection of the corresponding second trace on the substrate, and the orthographic projection of the second trace on the substrate may overlap the orthographic projection of the corresponding first trace on the substrate.

[0288] The display substrate provided in this embodiment has three first voltage power supply groups arranged in the first border area, and the first voltage signals required by the blue sub-pixel, the red sub-pixel and the green sub-pixel can be designed separately, so as to provide different first voltage signals to the blue sub-pixel, the red sub-pixel and the green sub-pixel, thereby reducing power consumption.

[0289] Figure 26 is another routing diagram of the first border area of ​​at least one embodiment of the present disclosure. Figure 27 is a partially enlarged schematic diagram of area C6 in Figure 26. In some examples, as shown in Figures 26 and 27, the first fan-out area B14 may include: multiple first power supply lines (for example, including first power supply lines 112a and 112b, 122a and 122b, 132a and 132b). The line widths of the line segments of the multiple first power supply lines in the same extension direction can be different, that is, the multiple first power supply lines can adopt a non-equal width design. For example, the line width of the line segment of the first power lines 112a and 112b extending along the first direction X (that is, the length along the second direction Y) may be greater than the line width of the line segment of the first power lines 122a and 122b extending along the first direction X, and the line width of the line segment of the first power lines 122a and 122b extending along the first direction X may be greater than the line width of the line segment of the first power lines 132a and 132b extending along the first direction X; the line width of the line segment of the first power lines 112a and 112b extending along the second direction Y (that is, the length along the first direction X) may be greater than the line width of the line segment of the first power lines 122a and 122b extending along the second direction Y, and the line width of the line segment of the first power lines 122a and 122b extending along the second direction Y may be greater than the line width of the line segment of the first power lines 132a and 132b extending along the second direction Y.

[0290] In some examples, the first power supply lines 112a and 112b can be configured to transmit a first first voltage signal Vdd1, the first power supply lines 122a and 122b can be configured to transmit a second first voltage signal Vdd2, and the first power supply lines 132a and 132b can be configured to transmit a third first voltage signal Vdd3. The first voltage signal Vdd1 is configured to be provided to the first sub-pixel group (including multiple blue sub-pixels), the first voltage signal Vdd2 is configured to be provided to the second sub-pixel group (including multiple red sub-pixels), and the first voltage signal Vdd3 is configured to be provided to the third sub-pixel group (including multiple green sub-pixels). Since the current of the blue sub-pixels is relatively large, the impedance can be reduced by reducing the IR drop of the first voltage signal Vdd1. In this example, by setting the line width of the first power supply lines 112a and 112b to be larger than the line width of the other first power supply lines, it is beneficial to reduce the impedance of the first voltage signal Vdd1, thereby ensuring the display effect of the first sub-pixel group.

[0291] In other examples, in order to avoid increasing the size of the first border area, the arrangement space of multiple first power supply lines providing different first voltage signals is limited, and the transmission voltage drop of the first voltage signal can be reduced by wiring on the same layer. For example, since the pixel current of the blue sub-pixel is relatively large, the voltage drop of the first voltage signal caused by the blue sub-pixel is relatively large, which easily affects the display uniformity of the blue sub-pixel. By adopting a multi-layer metal routing design for the first power supply lines 112a and 112b, the transmission voltage drop of the first voltage signal Vdd1 can be reduced, thereby improving the display uniformity of the blue sub-pixel. For example, the number of routing layers included in the first power supply lines 112a and 112b can be greater than the number of routing layers included in the first power supply lines 122a and 122b and 132a and 132b. In some examples, the first power supply lines 122a, 122b, 132a, and 132b can be a three-layer routing structure including a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer; the first power supply lines 112a and 112b can be a four-layer routing structure including a bottom shielding layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The routing portion located in the bottom shielding layer can be set in an area within the first fan-out region that is not blocked by the first conductive layer and the second conductive layer, for example, it can be located below the first routing of the fourth conductive layer within region 6. However, this embodiment is not limited to this. In other examples, the routing portion of the first power supply lines 112a and 112b located in the bottom shielding layer can be located in an area on one side of the laterally extending drive lead line close to the second fan-out region B11.

[0292] The remaining structures of the display substrate of this example can be referred to the description of the aforementioned embodiment, and thus will not be described again here.

[0293] Figure 28 is another schematic diagram of the routing of the first border area of ​​at least one embodiment of the present disclosure. Figure 29 is a partially enlarged schematic diagram of area C7 in Figure 28. In some examples, as shown in Figures 28 and 29, the first fan-out area B14 may include multiple first power supply lines 112, 122, and 132. The first power supply line 112 is configured to transmit a first voltage signal Vdd1, the first power supply line 122 is configured to transmit a first voltage signal Vdd2, and the first power supply line 132 is configured to transmit a first voltage signal Vdd3. The line widths of the first power supply lines 112, 122, and 132 in the same extension direction can be substantially the same.

[0294] In some examples, as shown in Figures 28 and 29, the first power supply lines 112, 122, and 132 may be located in different conductive layers. For example, the first power supply line 112 may be located in the fourth conductive layer, the first power supply line 122 may be located in the fifth conductive layer, and the first power supply line 132 may be located in the sixth conductive layer. A seventh insulating layer and an eighth insulating layer may be provided between the first power supply line 112 and the first power supply line 122, and a ninth insulating layer may be provided between the first power supply lines 122 and 132. The first power supply lines 122 and 132 may be provided with a plurality of hollow portions to facilitate the exhaust of the organic insulating layer (including the eighth insulating layer and the ninth insulating layer). The plurality of hollow portions on the first power supply lines 122 and 132 are omitted in Figures 28 and 29.

[0295] Figure 30A is a partially enlarged schematic diagram of region C8 in Figure 28. Figure 30A illustrates the structures of the fourth, fifth, and sixth conductive layers in region C8. Figure 30B is a schematic diagram of the fourth and fifth conductive layers in Figure 30A. Figure 30C is a schematic diagram of the fifth conductive layer in Figure 30A. Figure 31A is a partially enlarged schematic diagram of region C9 in Figure 28. Figure 31A illustrates the structures of the fourth, fifth, and sixth conductive layers in region C9. Figure 31B is a schematic diagram of the fourth and fifth conductive layers in Figure 31A. Figure 31C is a schematic diagram of the fifth conductive layer in Figure 31A.

[0296] In some examples, as shown in Figures 30A to 31C , the first power supply line 122 located in the fifth conductive layer may have multiple notches on the side near the bending region, such as a first notch Q1, a second notch Q2, a third notch Q3, a fourth notch Q4, and a fifth notch Q5. The first power supply line 122 and the first power supply bending lines 123a, 123b, and 123c may be interconnected and integrally formed. The first notch Q1 and the second notch Q2 may be located on either side of the first power supply bending line 123a in the first direction X, the third notch Q3 and the fourth notch Q4 may be located on either side of the first power supply bending line 123b in the first direction X, and the fourth notch Q4 may be located between the first power supply bending lines 123b and 123c. The fifth notch Q5 may be located on the side of the first power supply bending line 123c away from the fourth notch Q4.

[0297] In some examples, as shown in FIG30B , the first power supply meandering line 113a located in the fifth conductive layer can extend into the first notch Q1 and connect to the first power supply line 112 located in the fourth conductive layer through the openings in the eighth and seventh insulating layers. As shown in FIG31B , the first power supply meandering line 113b located in the fifth conductive layer can extend into the third notch Q3 and connect to the first power supply line 112 located in the fourth conductive layer through the openings in the eighth and seventh insulating layers. The first power supply meandering line 113c located in the fifth conductive layer can extend into the fifth notch Q5 and connect to the first power supply line 112 located in the fourth conductive layer through the openings in the eighth and seventh insulating layers.

[0298] In some examples, as shown in FIG30A , the first power supply meandering line 133a located in the fifth conductive layer can extend into the second notch Q2, and the first power supply line 132 located in the sixth conductive layer can be connected to the first power supply meandering line 133a through an opening in the ninth insulating layer. As shown in FIG31A , the first power supply meandering line 133b located in the fifth conductive layer can extend into the fourth notch Q4, and the first power supply line 132 located in the sixth conductive layer can be connected to the first power supply meandering line 133b through an opening in the ninth insulating layer.

[0299] In some examples, the orthographic projections of the first power supply lines 112, 122, and 132 on the substrate may partially overlap. For example, the orthographic projection of the first power supply line 132 located in the sixth conductive layer extending along the first direction X on the substrate may overlap the orthographic projection of the first power supply line 122 located in the fifth conductive layer extending along the first direction X on the substrate. Furthermore, the orthographic projection of the first power supply line 122 located in the fifth conductive layer extending along the first direction X on the substrate may overlap the orthographic projection of the first power supply line 112 located in the fourth conductive layer extending along the first direction X on the substrate.

[0300] In this example, by arranging multiple first power supply lines in different conductive layers, the routing width of the first power supply lines does not need to be reduced, which is beneficial for reducing the impedance of the first power supply lines and ensuring display uniformity of sub-pixels.

[0301] In some examples, the brightness of sub-pixels emitting light of different colors (e.g., blue sub-pixels, red sub-pixels, and green sub-pixels) can be controlled by the magnitude of a second voltage signal. For example, by providing different second voltage signals to the RGB sub-pixels based on the different turn-on voltages of the RGB sub-pixels, the pixel circuit can output the same voltage to the anodes of the light-emitting elements emitting light of different colors to illuminate the light-emitting elements emitting light of different colors. This allows the maximum value of the data signal range of the RGB sub-pixels to remain the same, thereby achieving fine control of the brightness of the RGB sub-pixels in groups and saving power with the second voltage signal.

[0302] FIG32 is a schematic diagram illustrating the transmission of a second voltage signal according to at least one embodiment of the present disclosure. In some examples, as shown in FIG32 , the multiple subpixels in display area AA can be divided into three subpixel groups. For example, the first subpixel group can include multiple first subpixels PX1 that emit a first color light (e.g., blue light), the second subpixel group can include multiple second subpixels PX2 that emit a second color light (e.g., red light), and the third subpixel group can include multiple third subpixels PX3 that emit a third color light (e.g., green light). The first subpixel group can be connected to a second power line VSS1, the second subpixel group can be connected to a second power line VSS2, and the third subpixel group can be connected to a second power line VSS3. The second power line VSS1 can be configured to transmit a first second voltage signal Vss1, the second power line VSS2 can be configured to transmit a second second voltage signal Vss2, and the second power line VSS3 can be configured to transmit a third second voltage signal Vss3. The second voltage signals Vss1, Vss2, and Vss3 can be second voltage signals with different voltage values. For example, the second voltage signal Vss1 may be lower than the second voltage signal Vss2 , and the second voltage signal Vss2 may be lower than the second voltage signal Vss3 .

[0303] In some examples, the cathodes of the light-emitting elements of a column of first sub-pixels PX1 in the first sub-pixel group can be an integrated structure connected to each other, serving as a second power line VSS1; the cathodes of the light-emitting elements of a column of second sub-pixels PX2 in the second sub-pixel group can be an integrated structure connected to each other, serving as a second power line VSS2; and the cathodes of the light-emitting elements of a column of third sub-pixels PX3 in the third sub-pixel group can be an integrated structure connected to each other, serving as a second power line VSS3.

[0304] In some examples, as shown in FIG32 , the first border area B1 may include L second voltage power supply groups, such as a first second voltage power supply group 21, a second second voltage power supply group 22, and a third second voltage power supply group 23. Each second voltage power supply group may be configured to provide a corresponding second voltage signal to at least one sub-pixel group. In this example, the second voltage power supply group 21 may be configured to provide a second voltage signal Vss1 to the first sub-pixel group, the second voltage power supply group 22 may be configured to provide a second voltage signal Vss2 to the second sub-pixel group, and the second voltage power supply group 23 may be configured to provide a second voltage signal Vss3 to the third sub-pixel group.

[0305] In some examples, as shown in FIG32 , the second voltage supply group 21 may include: a third power supply line 211 located in the second fan-out area B11, a fourth power supply line 212 located in the first fan-out area B13, a second power supply meander line 213 located in the bend area B12, and second voltage contact pads 214a and 214b located in the first signal access area B15. The second voltage supply group 22 may include: a third power supply line 221 located in the second fan-out area B11, a fourth power supply line 222 located in the first fan-out area B13, a second power supply meander line 223 located in the bend area B12, and second voltage contact pads 224a and 224b located in the first signal access area B15. The second voltage supply group 23 may include: a third power supply line 231 located in the second fan-out area B11, a fourth power supply line 232 located in the first fan-out area B13, a second power supply meander line 233 located in the bend area B12, and second voltage contact pads 234a and 234b located in the first signal access area B15.

[0306] In some examples, as shown in FIG32 , the third power supply lines 211, 221, and 231 located in the second fan-out area B11 may be arranged sequentially along a direction opposite to the second direction Y. The third power supply lines 211, 221, and 231 may be at least traces extending along the first direction X. The third power supply line may be connected to the second power line via a third-type voltage transfer electrode, and the third-type voltage transfer electrode may include: a seventh voltage transfer electrode 241, an eighth voltage transfer electrode 242, and a ninth voltage transfer electrode 243. The third power supply line 211 may be connected to the second power line VSS1 via the seventh voltage transfer electrode 241, the third power supply line 221 may be connected to the second power line VSS2 via the eighth voltage transfer electrode 242, and the third power supply line 231 may be connected to the second power line VSS3 via the ninth voltage transfer electrode 243.

[0307] This example provides three different second voltage signals by setting three second voltage power supply groups in the first frame area, which can meet the different requirements of the three sub-pixel groups emitting different colors of light in the display area for the second voltage signal, thereby achieving the purpose of saving power consumption of the second voltage signal.

[0308] Figure 33 is a schematic diagram of the routing of the first border region of at least one embodiment of the present disclosure. Figure 33 primarily illustrates the three third power supply lines 211, 221, and 231 of the second fan-out region B11, the multiple curved connecting lines of the bending region B12, and some of the routing of the first fan-out region B13 (e.g., including first power supply lines 212a and 212b, 222a and 222b, and 232a and 232b). Furthermore, Figure 33 also provides an overall diagram of multiple adjacent routing lines of the same type.

[0309] In some examples, as shown in FIG33 , the second fan-out area B11 may include at least three third power supply lines 211, 221, and 231, a first voltage fan-out line (not shown), multiple data fan-out lines (not shown), multiple drive fan-out lines (not shown), and multiple touch fan-out lines (not shown). The first voltage fan-out line may be configured to transmit a first voltage signal.

[0310] In some examples, as shown in FIG33 , the multiple bending connection lines of the bending area B12 may include: multiple data bending lines (for example, a first group of data bending lines 163a, a second group of data bending lines 163b, a third group of data bending lines 163c, a fourth group of data bending lines 163d, a fifth group of data bending lines 163e, and a sixth group of data bending lines 163f), multiple drive bending lines (for example, a first group of drive bending lines 173a, a second group of drive bending lines 173b), and multiple touch bending lines (for example, a first group of drive bending lines 173a, a second group of drive bending lines 173b). Including a first group of touch bending lines 183a, a second group of touch bending lines 183b, a third group of touch bending lines 183c and a fourth group of touch bending lines 183d), multiple first power supply bending lines (for example, including first power supply bending lines 193a, 193b, 193c and 193d), and multiple second power supply bending lines (for example, including second power supply bending lines 213a, 213b, 213c and 213d, 223a, 223b, 223c and 223d, 233a, 233b and 233c).

[0311] In some examples, as shown in FIG33 , within the bending region B12, the first group of driving bending lines 173a, the first power bending lines 193a, the first group of touch bending lines 183a, the first group of data bending lines 163a, the second group of touch bending lines 183b, the first power bending lines 193b, the second group of data bending lines 163b, the second power bending lines 213a, 223a, and 233a, the third group of data bending lines 163c, and the second power bending lines 213 b, 223b, 233b, 223c and 213c, the fourth group of data bending lines 163d, the second power supply bending lines 213c, 223d and 213d, the fifth group of data bending lines 163c, the first power supply bending lines 193c, the third group of touch bending lines 183c, the sixth group of data bending lines 163f, the fourth group of touch bending lines 183d, the first power supply bending lines 193d and the second group of drive bending lines 173b can be arranged in sequence along the first direction X.

[0312] In some examples, as shown in Figure 33, the first fan-out area B13 may include: multiple fourth power supply lines (for example, two fourth power supply lines 212a and 212b, two fourth power supply lines 222a and 222b, and two fourth power supply lines 232a and 232b), two first voltage lead lines (for example, first voltage lead lines 191 and 192), multiple data lead lines (including a first group of data lead lines 161 and a second group of data lead lines 162), multiple drive lead lines (including a first group of drive lead lines 171 and a second group of drive lead lines 172), and multiple touch lead lines (including a first group of touch lead lines 181 and a second group of touch lead lines 182). First voltage lead-out line 191 can be connected to the first voltage fan-out line in the second fan-out area B11 via first voltage bending lines 193a and 193b, and first voltage lead-out line 192 can be connected to the first voltage fan-out line in the second fan-out area B11 via first voltage bending lines 193c and 193d. First voltage lead-out lines 191 and 192 can be configured to transmit a first voltage signal.

[0313] Figure 34A is a partially enlarged schematic diagram of area C10 in Figure 33. Figure 34A illustrates a portion of the film layers at the junction of display area AA and first border area B1. Figure 34B is a schematic diagram of the fourth conductive layer in Figure 34A. Figure 34C is a schematic diagram of Figure 34A after the fifth conductive layer is formed. Figure 34D is a schematic diagram of Figure 34A after the anode layer is formed.

[0314] In some examples, as shown in Figure 34B, the fourth conductive layer of the first border area may include at least: a third type of voltage conversion electrode (for example, including a seventh voltage conversion electrode 241, an eighth voltage conversion electrode 242 and a ninth voltage conversion electrode 243), and multiple auxiliary electrodes (for example, including a third auxiliary electrode 363 and a fourth auxiliary electrode 364).

[0315] In some examples, the seventh voltage conversion electrode 241 may include a seventh main portion 241-1 and a ninth protruding portion 241-2. The seventh main portion 241-1 and the ninth protruding portion 241-2 may be interconnected as a single unit. The seventh main portion 241-1 may be substantially rectangular, and the ninth protruding portion 241-2 may be substantially L-shaped. The ninth protruding portion 241-2 is located on the side of the seventh main portion 241-1 closer to the display area. The eighth voltage conversion electrode 242 may include an eighth main portion 242-1 and a tenth protruding portion 242-2. The eighth main portion 242-1 may be substantially rectangular, and the tenth protruding portion 242-2 may be substantially L-shaped. The eighth main portion 242-1 and the tenth protruding portion 242-2 may be interconnected as a single unit. The ninth voltage conversion electrode 243 may include a ninth main portion 243-1 and a plurality of eleventh protruding portions 243-2. The ninth main portion 243 - 1 may be substantially rectangular, and the eleventh protrusion 243 - 2 may be substantially strip-shaped extending along the second direction Y. The ninth main portion 243 - 1 and the plurality of eleventh protrusions 243 - 2 may be an integrated structure connected to each other.

[0316] In some examples, the third auxiliary electrode 363 and the fourth auxiliary electrode 364 can be substantially rectangular in shape. The seventh voltage conversion electrode 241 is aligned with the third auxiliary electrode 363 in the second direction Y. The third auxiliary electrode 363 is located on a side of the seventh voltage conversion electrode 241 away from the display area and between the two eleventh protrusions 243-2 of the ninth voltage conversion electrode 243. The eighth voltage conversion electrode 242 is aligned with the fourth auxiliary electrode 364 in the second direction Y. The fourth auxiliary electrode 364 can be located on a side of the eighth voltage conversion electrode 242 closer to the display area and between the two eleventh protrusions 243-2 of the ninth voltage conversion electrode 243.

[0317] In some examples, as shown in FIG34C , the fifth conductive layer in the first frame region may include at least: third power supply lines 211, 221, and 231, and a plurality of frame power connection electrodes (for example, a fifth frame power connection electrode 335, a sixth frame power connection electrode 336, a seventh frame power connection electrode 337, and an eighth frame power connection electrode 338). The fifth frame power connection electrode 335, the sixth frame power connection electrode 336, the seventh frame power connection electrode 337, and the eighth frame power connection electrode 338 may be arranged along the first direction X and located on a side of the third power supply line 211 close to the display area. The fifth frame power connection electrode 335 can be connected to the ninth protrusion 241-2 of the seventh voltage conversion electrode 241 through the via holes opened in the eighth insulating layer and the seventh insulating layer, the sixth frame power connection electrode 336 can be connected to an eleventh protrusion 243-2 of the ninth voltage conversion electrode 243, the seventh frame power connection electrode 337 can be connected to the tenth protrusion 242-2 of the eighth voltage conversion electrode 242, and the eighth frame power connection electrode 338 can be connected to another eleventh protrusion 243-2 of the ninth voltage conversion electrode 243.

[0318] In some examples, as shown in FIG34D , the anode layer in the first frame region includes at least: a plurality of frame power connection electrodes (e.g., a ninth frame power connection electrode 371 , a tenth frame power connection electrode 372 , an eleventh frame power connection electrode 373 , and a twelfth frame power connection electrode 374 ). The ninth frame power connection electrode 371 , the tenth frame power connection electrode 372 , the eleventh frame power connection electrode 373 , and the twelfth frame power connection electrode 374 can be arranged along the first direction X and located on a side of the third power supply line 211 close to the display area. The ninth frame power connection electrode 371 can be connected to the fifth frame power connection electrode 335 , the tenth frame power connection electrode 372 can be connected to the sixth frame power connection electrode 336 , the eleventh frame power connection electrode 373 can be connected to the seventh frame power connection electrode 337 , and the twelfth frame power connection electrode 374 can be connected to the eighth frame power connection electrode 338 .

[0319] In some examples, as shown in FIG34A , the cathode layer of the display substrate may include multiple second power lines (e.g., second power lines VSS1, VSS2, and VSS3). The cathode of the display area may be patterned as multiple stripes extending along the second direction Y, each stripe serving as a second power line. The second power line VSS1 may be connected to the ninth frame power connection electrode 371 of the anode layer through a via in the pixel definition layer, thereby connecting to the third power line 211 through the seventh voltage transfer electrode 241 to receive the second voltage signal Vss1. A second power line VSS3 may be connected to the tenth frame power connection electrode 372 of the anode layer through a via in the pixel definition layer, thereby connecting to the third power line 231 through the ninth voltage transfer electrode 243 to receive the second voltage signal Vss3. Another second power line VSS3 may be connected to the twelfth frame power connection electrode 374 of the anode layer through a via in the pixel definition layer, thereby connecting to the third power line 231 through the ninth voltage transfer electrode 243 to receive the second voltage signal Vss3. The second power line VSS2 can be connected to the eleventh frame power connection electrode 373 of the anode layer through a via hole opened in the pixel definition layer, and then connected to the third power supply line 221 through the eighth voltage transfer electrode 242 to receive the second voltage signal Vss2.

[0320] This example utilizes the frame power connection electrodes located in the anode layer and the fifth conductive layer and the third type voltage transfer electrodes located in the fourth conductive layer to achieve electrical connection between the second power line located in the cathode layer and the third power line located in the fifth conductive layer. In other examples, when the cathode of the display area is patterned as a plurality of strip patterns extending along the first direction X, and each strip pattern serves as a second power line (in other words, when the second power line extends along the first direction X), the structure shown in FIG34A can be rotated 90 degrees, and the third power line can be adjusted to extend along the second direction Y, so as to achieve electrical connection between the second power line and the third power line in the second frame area. This embodiment is not limited to this.

[0321] Regarding the routing arrangement, width and cross-line method within the second voltage power supply group of this example, reference can be made to the relevant contents of the first voltage power supply group in the aforementioned embodiment, so they will not be repeated here.

[0322] In other examples, the line segments of the fourth power supply lines of the three second voltage power supply groups arranged in the first frame area along the same extension direction may be different. For example, reference may be made to the embodiment shown in FIG. 26 , so it will not be repeated here.

[0323] In other examples, the fourth power supply lines of the three second voltage power supply groups set in the first border area can be arranged in different conductive layers. For example, reference can be made to the embodiment shown in Figure 28 above, so it will not be repeated here.

[0324] In other examples, three first voltage power supply groups and three second voltage power supply groups can be set in the first border area to provide three different first voltage signals and three different second voltage signals to meet the different requirements of the three sub-pixel groups emitting different colors of light in the display area for the first voltage signal and the second voltage signal, thereby achieving the purpose of saving power consumption of the first voltage signal and the second voltage signal.

[0325] This embodiment also provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of second power lines, and L second voltage supply groups. The substrate includes a display area and a first frame area located on one side of the display area. The plurality of sub-pixels and the plurality of second power lines are located in the display area. The plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group includes a plurality of sub-pixels that emit light of the same color, and different sub-pixel groups are configured to emit light of different colors. At least one sub-pixel includes: a pixel circuit and a light-emitting element connected to the pixel circuit. Each second power line is connected to the light-emitting elements of the plurality of sub-pixels that emit light of the same color. The L second voltage supply groups are located in the first frame area. The L second voltage supply groups are configured to provide different second voltage signals. Each second voltage supply group is configured to provide a second voltage signal to the light-emitting element in at least one sub-pixel group via at least one second power line. Wherein, L and N are both integers greater than 1, and L is less than or equal to N.

[0326] In some examples, the number of sub-pixel groups may be the same as the number of second voltage supply groups, that is, L may be equal to N. Each second voltage supply group may provide a second voltage signal to a sub-pixel group. Different sub-pixel groups receive different second voltage signals. In other examples, L may be less than N, and at least one second voltage supply group may provide a first voltage signal to at least two sub-pixel groups. The second voltage signals received by at least two sub-pixel groups may be the same. For example, one second voltage supply group among the L second voltage supply groups may be configured to provide the same second voltage signal to two sub-pixel groups. However, this embodiment is not limited to this.

[0327] In some examples, each of the L second voltage supply groups can be configured to provide a second voltage signal that is different from the remaining second voltage supply groups. In other words, the L second voltage supply groups can provide L different second voltage signals. In other examples, at least two of the L second voltage supply groups can be configured to provide different second voltage signals. For example, the L second voltage supply groups can be configured to provide L-1 different second voltage signals, two of the L second voltage supply groups can provide the same second voltage signal, and the remaining second voltage supply groups can be configured to provide different second voltage signals. This embodiment is not limited to this.

[0328] In some examples, the display area may include multiple second power lines, and each second power line may be connected to the light-emitting elements of multiple sub-pixels that emit light of the same color. For example, the light-emitting element of the sub-pixel may include an anode and a cathode. The cathode of the light-emitting element may be connected to the second power line. Multiple light-emitting elements in a sub-pixel group may be connected to multiple second power lines, and a second voltage supply group may be configured to provide a second voltage signal to the light-emitting elements in the sub-pixel group through the multiple second power lines. In other examples, multiple light-emitting elements in a sub-pixel group may be connected to a second power line, and a second voltage supply group may be configured to provide a second voltage signal to the light-emitting elements in the sub-pixel group through the one second power line. This embodiment is not limited to this.

[0329] This embodiment provides three different second voltage signals by setting three second voltage power supply groups in the first frame area, which can meet the different requirements of the three sub-pixel groups emitting different colors of light in the display area for the second voltage signal, thereby achieving the purpose of saving power consumption of the second voltage signal.

[0330] In some exemplary embodiments, the N subpixel groups may include: a first subpixel group that emits light of a first color, a second subpixel group that emits light of a second color, and a third subpixel group that emits light of a third color. The L second voltage supply groups may include: a first second voltage supply group that provides a first second voltage signal, a second second voltage supply group that provides a second second voltage signal, and a third second voltage supply group that provides a third second voltage signal. The first second voltage supply group is configured to provide the first second voltage signal to the first subpixel group. The second second voltage supply group is configured to provide the second second voltage signal to the second subpixel group. The third second voltage supply group is configured to provide the third second voltage signal to the third subpixel group. However, this embodiment is not limited to this. In other examples, the number of subpixel groups may be three, and the number of second voltage supply groups may be two. The first second voltage supply group may be configured to provide the first second voltage signal to the first subpixel group (e.g., including blue subpixels), and the second first voltage supply group may be configured to provide the second second voltage signal to the second subpixel group (e.g., including red subpixels) and the third subpixel group (e.g., including green subpixels). In this example, the grouping design of the second voltage signal can be used to implement RGB brightness grouping control, thereby achieving the purpose of saving power consumption of the second voltage signal.

[0331] In some exemplary embodiments, the first color light may be blue light, the second color light may be red light, and the third color light may be green light. The first second voltage signal may be smaller than the second second voltage signal, and the second second voltage signal may be smaller than the third second voltage signal.

[0332] The rest of the description about the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0333] FIG35 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG35 , this embodiment provides a display device 91 comprising a display panel 910 according to the aforementioned embodiment. In some examples, the display panel 910 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be any of the following products: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a picture screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as a business query device for e-government, banks, hospitals, power departments, etc.), a monitor, etc. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, etc.

[0334] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising: a display area and a first frame area located on one side of the display area; A plurality of sub-pixels and a plurality of first power lines are located in the display area, the plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group includes a plurality of sub-pixels emitting light of the same color, and different sub-pixel groups are configured to emit light of different colors, at least one sub-pixel of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit, and each first power line is connected to the pixel circuit of the plurality of sub-pixels emitting light of the same color; M first voltage power supply groups are located in the first border area, and the M first voltage power supply groups are configured to provide different first voltage signals; each first voltage power supply group is configured to provide a first voltage signal to a pixel circuit in at least one sub-pixel group through at least one first power line, wherein M and N are both integers greater than 1, and M is less than or equal to N.

2. The display substrate according to claim 1, wherein: The first frame area includes: a first fan-out area and a first signal access area which are sequentially arranged in a direction away from the display area; Each first voltage power supply group includes at least: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; the at least one first power supply line is connected to the at least one first voltage contact pad.

3. The display substrate according to claim 2, wherein: The first frame area further includes: a second fan-out area and a bending area, the second fan-out area and the bending area are located on a side of the first fan-out area close to the display area, and the bending area connects the first fan-out area and the second fan-out area; Each first voltage power supply group also includes: at least one second power supply line located in the second fan-out area and at least one first power supply bending line located in the bending area; the at least one second power supply line is connected to multiple first power lines transmitting the same first voltage signal, and the at least one first power supply bending line connects the at least one first power supply line and the at least one second power supply line.

4. The display substrate according to claim 3, wherein: The second power supply line extends at least along the first direction, the first power supply bending line extends at least along the second direction, the first power line extends at least along the second direction, and the first direction intersects with the second direction; the at least one first power supply line is symmetrically arranged about the midline of the first border area along the first direction.

5. The display substrate according to claim 3, wherein: The second power supply line is connected to multiple first power supply lines through a first type voltage conversion electrode, and the at least one first power supply bending line is connected to the second power supply line and multiple first power supply lines through a second type voltage conversion electrode; the first type voltage conversion electrode and the second type voltage conversion electrode are a same-layer structure.

6. The display substrate according to claim 2, wherein: A distance between the first power supply lines of at least two first voltage power supply groups among the M first voltage power supply groups and the orthographic projections of the substrate is greater than 0, and the first power supply lines include at least two interconnected routing lines.

7. The display substrate according to claim 6, wherein: In a direction perpendicular to the display substrate, the display substrate comprises: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate; The first power supply line of at least one first voltage power supply group among the M first voltage power supply groups includes a routing line located in at least two metal layers among the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer.

8. The display substrate according to claim 2, wherein: The first power supply lines of different first voltage power supply groups are located in different conductive layers, and the first power supply lines of at least two first voltage power supply groups overlap in the orthographic projection portion of the substrate.

9. The display substrate according to claim 2, wherein: The line widths of the first power supply lines of the M first voltage power supply groups in the same extending direction are the same.

10. The display substrate according to claim 2, wherein: The line widths of the first power supply lines of at least two adjacent first voltage power supply groups in the same extending direction are different.

11. The display substrate according to claim 1, wherein: The N sub-pixel groups include: a first sub-pixel group emitting a first color light, a second sub-pixel group emitting a second color light, and a third sub-pixel group emitting a third color light; The M first voltage power supply groups include: a first first voltage power supply group providing a first first voltage signal, a second first voltage power supply group providing a second first voltage signal, and a third first voltage power supply group providing a third first voltage signal; The first first voltage supply group is configured to provide a first first voltage signal to the first sub-pixel group; The second first voltage supply group is configured to provide a second first voltage signal to the second sub-pixel group; The third first voltage supply group is configured to provide a third first voltage signal to the third sub-pixel group.

12. The display substrate according to claim 11, wherein: The first color light is blue light, the second color light is red light, and the third color light is green light; the first first voltage signal is greater than the second first voltage signal, and the second first voltage signal is greater than the third first voltage signal.

13. The display substrate according to claim 11, further comprising: A bottom shielding layer, wherein the bottom shielding layer is connected to the first first voltage power supply group.

14. The display substrate according to claim 11, wherein: The first frame area includes: a first fan-out area and a first signal access area which are sequentially arranged in a direction away from the display area; Each first voltage power supply group includes at least: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; the at least one first power supply line is connected to the at least one first voltage contact pad; The average line width of the first power supply line of the first first voltage power supply group is greater than the average line width of the first power supply line of the second first voltage power supply group; the average line width of the first power supply line of the second first voltage power supply group is greater than the average line width of the first power supply line of the third first voltage power supply group.

15. The display substrate according to claim 11, wherein: The first frame area includes: a first fan-out area and a first signal access area which are sequentially arranged in a direction away from the display area; Each first voltage power supply group includes at least: at least one first power supply line located in the first fan-out area and at least one first voltage contact pad located in the first signal access area; the at least one first power supply line is connected to the at least one first voltage contact pad; The first power supply line of the first first voltage power supply group, the first power supply line of the second first voltage power supply group and the first power supply line of the third first voltage power supply group are single-layer routing lines and overlap in the orthographic projection part of the substrate.

16. The display substrate according to claim 15, wherein: In a direction perpendicular to the display substrate, the display substrate includes at least: a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged on the substrate; the first power supply line of the first first voltage power supply group is located in the first source-drain metal layer, the first power supply line of the second first voltage power supply group is located in the second source-drain metal layer, and the first power supply line of the third first voltage power supply group is located in the third source-drain metal layer.

17. The display substrate according to any one of claims 1 to 16, further comprising: L second voltage power supply groups are located in the first border area, and the L second voltage power supply groups are configured to provide different second voltage signals. Each second voltage power supply group is configured to provide a second voltage signal to the light-emitting element in at least one sub-pixel group, wherein L is an integer greater than 1 and L is less than or equal to N; and the second voltage signal is different from the first voltage signal.

18. The display substrate according to claim 17, wherein: The N sub-pixel groups include: a first sub-pixel group emitting a first color light, a second sub-pixel group emitting a second color light, and a third sub-pixel group emitting a third color light; The L second voltage power supply groups include: a first second voltage power supply group providing a first second voltage signal, a second second voltage power supply group providing a second second voltage signal, and a third second voltage power supply group providing a third second voltage signal; The first second voltage supply group is configured to provide a first second voltage signal to the first sub-pixel group; The second second voltage supply group is configured to provide a second second voltage signal to the second sub-pixel group; The third second voltage supply group is configured to provide a third second voltage signal to the third sub-pixel group.

19. The display substrate according to claim 18, wherein: The first color light is blue light, the second color light is red light, and the third color light is green light; the first second voltage signal is smaller than the second second voltage signal, and the second second voltage signal is smaller than the third second voltage signal.

20. The display substrate according to claim 17, wherein: The light emitting element comprises an anode and a cathode; the cathodes of a plurality of light emitting elements emitting light of the same color are connected to each other and are connected to a second voltage power supply group via at least a third type voltage switching electrode.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

22. A display substrate, comprising: A substrate, comprising a display area and a first frame area located on one side of the display area; A plurality of sub-pixels and a plurality of second power lines are located in the display area, the plurality of sub-pixels are divided into N sub-pixel groups, each sub-pixel group includes a plurality of sub-pixels emitting light of the same color, and different sub-pixel groups are configured to emit light of different colors, at least one sub-pixel of the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit, and each second power line is connected to the light-emitting elements of the plurality of sub-pixels emitting light of the same color; L second voltage power supply groups are located in the first border area, and the L second voltage power supply groups are configured to provide different second voltage signals, and each second voltage power supply group is configured to provide a second voltage signal to the light-emitting element in at least one sub-pixel group through at least one second power line; wherein L and N are both integers greater than 1, and L is less than or equal to N.

23. The display substrate according to claim 22, wherein: The N sub-pixel groups include: a first sub-pixel group emitting a first color light, a second sub-pixel group emitting a second color light, and a third sub-pixel group emitting a third color light; The L second voltage power supply groups include: a first second voltage power supply group providing a first second voltage signal, a second second voltage power supply group providing a second second voltage signal, and a third second voltage power supply group providing a third second voltage signal; The first second voltage supply group is configured to provide a first second voltage signal to the first sub-pixel group; The second second voltage supply group is configured to provide a second second voltage signal to the second sub-pixel group; The third second voltage supply group is configured to provide a third second voltage signal to the third sub-pixel group.

24. The display substrate according to claim 23, wherein: The first color light is blue light, the second color light is red light, and the third color light is green light; the first second voltage signal is smaller than the second second voltage signal, and the second second voltage signal is smaller than the third second voltage signal.

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