Multi-gate transistor pixel circuit, display apparatus and control method thereof

Abstract

A pixel circuit is disclosed, comprising at least a first transistor, a light emitting component and a driving circuit. The first transistor is a multiple-gate transistor, for example a multimodal transistor (MMT). The first transistor comprises a current control gate for controlling a magnitude of current supplied by a source region of the first transistor in dependence on a first voltage applied to the current control gate, the current control gate being disposed opposite a source electrode of the first transistor, and a switching gate for blocking or permitting a flow of current in a channel region of the first transistor in dependence on a second voltage applied to the switching gate. The light emitting component is connected to the source or drain of the first transistor such that, in use, a current flowing through the light emitting component is controlled by the current control gate of the first transistor, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the first transistor. The driving circuit is configured to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component. Corresponding methods of controlling such pixel circuits are also disclosed, together with a display apparatus comprising a plurality of the pixel circuits.

Description

[0001] Multi-Gate Transistor Pixel Circuit, Display Apparatus and Control

[0002] Method Thereof

[0003] Field

[0004] The present invention relates to a pixel circuit. More particularly, the present invention relates to a pixel circuit comprising a multi-gate (multiple-gate) transistor, a display apparatus comprising the same, and control methods thereof.

[0005] Background

[0006] Emissive electronic information displays comprise an array of (millions of) pixels, which in turn are composed of a light emitting device (LED) and an electronic circuit which controls the LED's brightness. The pixel circuit is largely composed of transistors (which act as current sources or switches, where conventional transistors provide both functions simultaneously through biasing a gated channel region) and capacitors. Aside from the LED, the simple pixel circuit has two transistors and one capacitor (2T1C), but due to the non-idealities in all electronic components, these simple circuits cannot provide uniformity across a large area, which results in intolerable non-uniformities in the image or flickering. For this reason, more complex pixel architectures (power-inefficient pixel-driving / programming techniques) are used (e.g. seven transistors and two capacitors, 7T2C), at the expense of pixel size and complexity of the electronic driving scheme. It would therefore be desirable to have small pixel circuits for increased density and thus higher image resolution, preferably with improved uniformity and power efficiency compared to existing solutions.

[0007] Summary

[0008] According to a first aspect of the present invention, there is provided a pixel circuit comprising: a first transistor comprising a current control gate for controlling a magnitude of current supplied by a source region (e.g. a source-gate overlap region) of the first transistor in dependence on a first voltage applied to the current control gate, and a switching gate for blocking or permitting a flow of current in a channel region of the first transistor in dependence on a second voltage applied to the switching gate; a light emitting component connected to a source or drain of the first transistor such that, in use, a current flowing through the light emitting component is controlled by the current set by the current control gate of the first transistor, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the first transistor; and a driving circuit configured to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component.

[0009] In some embodiments according to the first aspect, the first transistor comprises: a source; a drain spaced apart from the source; a semiconductor region disposed between the source and the drain; and an insulating region disposed over the semiconductor region; wherein the current control gate is configured to control the magnitude of current flowing between the source and the drain through the semiconductor region in dependence on the first voltage applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and wherein the switching gate is configured to block or permit the flow of said current between the source and the drain through the semiconductor region in dependence on the second voltage applied to the switching gate.

[0010] In some embodiments according to the first aspect, the driving circuit comprises: a first capacitor connected to the current control gate such that, in use, a voltage on the first capacitor can be applied to the current control gate as the first voltage; and a second capacitor connected to the switching gate such that, in use, a voltage on the second capacitor can be applied to the switching gate as the second voltage.

[0011] In some embodiments according to the first aspect, the driving circuit further comprises: a second transistor connected between the second capacitor and a first reference voltage node such that, in use, when the second transistor is in an ON state said voltage on the second capacitor can be reset to a voltage at the first reference voltage node.

[0012] In some embodiments according to the first aspect, the driving circuit further comprises: a third transistor connected between the current control gate and the switching gate such that, in use, when the third transistor is in an ON state a voltage at the current control gate is the same as a voltage at the switching gate.

[0013] In some embodiments according to the first aspect, the third transistor is further connected in series with the second transistor.

[0014] In some embodiments according to the first aspect, the driving circuit further comprises: a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to a data signal input. In some embodiments according to the first aspect, the source of the first transistor is connected to the data signal input via the source and the drain of the first transistor such that, in use, when the third and fourth transistors are both in the ON state the first and second capacitors can be charged to a voltage equal to VDATA + Vth, where VDATA is a voltage at the data signal input and Vth is a threshold voltage of the first transistor.

[0015] In some embodiments according to the first aspect, the driving circuit further comprises: a fifth transistor connected between the source of the first transistor and the data signal input.

[0016] In some embodiments according to the first aspect, respective gates of the fourth transistor and the fifth transistor are connected to a first control input for receiving a first control signal.

[0017] In some embodiments according to the first aspect, the driving circuit further comprises: a sixth transistor connected between the source of the first transistor and a ground plane such that, in use, the sixth transistor can be switched to an ON state to allow current to flow through the first transistor and the light emitting component, and can be switched to an OFF state to isolate the data signal input from the ground plane.

[0018] In some embodiments according to the first aspect, the driving circuit further comprises: a seventh transistor connected in series between the first transistor and the light emitting component such that, in use, when the seventh transistor is in an ON state current can flow through the first transistor and the light emitting component.

[0019] In some embodiments according to the first aspect, the driving circuit further comprises: an eighth transistor connected between the first capacitor and a second reference voltage node such that, in use, when the eighth transistor is in an ON state the first capacitor can be charged to a voltage at the second reference voltage node.

[0020] In some embodiments according to the first aspect, respective gates of the second transistor and the eighth transistor are connected to a second control input for receiving a second control signal, and respective gates of the third transistor and the fourth transistor are connected to a third control input for receiving a third control signal.

[0021] In some embodiments according to the first aspect, the driving circuit comprises: a capacitor connected between the source of the first transistor and the current control gate; and a second transistor connected between the current control gate and a data signal input, wherein the switching gate and the drain of the first transistor are connected to a ground plane.

[0022] According to a second aspect of the present invention, there is provided a display apparatus comprising a plurality of pixel circuits according to the first aspect.

[0023] In some embodiments according to the second aspect, the display apparatus comprises control circuitry configured to provide control signals to the plurality of pixel circuits to control the switching of one or more transistors within each pixel circuit.

[0024] According to a third aspect of the present invention, there is provided a method of controlling a pixel circuit comprising a first transistor, the first transistor comprising a current control gate for controlling a magnitude of current supplied by a source region of the first transistor in dependence on a first voltage applied to the current control gate, and a switching gate for blocking or permitting a flow of current in a channel region of the first transistor in dependence on a second voltage applied to the switching gate, the pixel circuit further comprising a light emitting component connected to a source or drain of the first transistor such that, in use, a current flowing through the light emitting component is controlled by the current control gate of the first transistor, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the first transistor, and a driving circuit, the method comprising: during an emission phase, using the driving circuit to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component.

[0025] In some embodiments according to the third aspect, the driving circuit comprises a first capacitor connected to the current control gate and a second capacitor connected to the switching gate, wherein during the emission phase, a voltage on the first capacitor is applied to the current control gate as the first voltage, and a voltage on the second capacitor is applied to the switching gate as the second voltage. In some embodiments according to the third aspect, the method comprises: during a reset phase, setting the first capacitor to a first voltage level and setting the second capacitor to a second voltage level.

[0026] In some embodiments according to the third aspect, the driving circuit further comprises a second transistor connected between the second capacitor and a first reference voltage node such that, in use, when the second transistor is in an ON state said voltage on the second capacitor can be reset to a voltage at the first reference voltage node, and wherein the driving circuit further comprises a third transistor connected between the current control gate and the switching gate such that, in use, when the third transistor is in an ON state a voltage at the current control gate is the same as a voltage at the switching gate, wherein setting the first capacitor to the first voltage level and setting the second capacitor to the second voltage level comprises: switching the second transistor and the third transistor to an ON state, so as to set the first and second voltage levels of the first capacitor and the second capacitor, respectively, to the voltage at the first reference voltage node.

[0027] In some embodiments according to the third aspect, during the reset phase the voltage at the first reference voltage node is held at a voltage level higher than a maximum level of the first or second voltages to be applied to the current control gate and the switching gate, respectively, during the emission phase.

[0028] In some embodiments according to the third aspect, the driving circuit further comprises a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to a data signal input, the method comprising: during a first stage of a programming phase, switching the third and fourth transistors to an ON state to connect both the first and second capacitors to the data signal input so as to set respective charge levels of the first and second capacitors in dependence on a voltage at the data signal input during said first stage, during a second stage of a programming phase, switching the third transistor to an OFF state while the fourth transistor is in the ON state, so as to further set the charge level of the second capacitor in dependence on a voltage at the data signal input during said second stage.

[0029] In some embodiments according to the third aspect, the driving circuit further comprises a fifth transistor connected between the source of the first transistor and the data signal input, and a sixth transistor connected between the source of the first transistor and a ground plane, wherein during the first and second stages of the programming phase, the fifth transistor is switched to an ON state to connect the fourth transistor to the data signal input via the source and drain of the first transistor, and the sixth transistor is switched to an OFF state to isolate the data signal input from the ground plane and wherein during the emission phase, the sixth transistor is switched to an ON state to allow current to flow through the first transistor and the light emitting component, and the fifth transistor is switched to an OFF state.

[0030] In some embodiments according to the third aspect, the driving circuit further comprises a seventh transistor connected in series between the first transistor and the light emitting component, wherein during the emission phase, the seventh transistor is switched to an ON state such that current can flow through the first transistor and the light emitting component.

[0031] In some embodiments according to the third aspect, the driving circuit further comprises a second transistor connected between the second capacitor and a first reference voltage node such that, in use, when the second transistor is in an ON state said voltage on the second capacitor can be reset to a voltage at the first reference voltage node, and wherein the driving circuit further comprises an eighth transistor connected between the first capacitor and a second reference voltage node such that, in use, when the eighth transistor is in an ON state the first capacitor can be charged to a voltage at the second reference voltage node, wherein setting the first capacitor to the first voltage level and setting the second capacitor to the second voltage level comprises: switching the second transistor to an ON state, so as to set the second voltage level of the second capacitor to the voltage at the first reference voltage node; and switching the eighth transistor to an ON state, so as to set the first voltage level of the first capacitor to the voltage at the second reference voltage node.

[0032] In some embodiments according to the third aspect, the first reference voltage node comprises a ground plane, such that the voltage at the first reference voltage node is a ground voltage.

[0033] In some embodiments according to the third aspect, the driving circuit further comprises a third transistor connected between the current control gate and the source control gate such that, in use, when the third transistor is in an ON state a voltage at the current control gate is the same as a voltage at the source control gate, and comprises a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to a data signal input, the method comprising: during a programming phase, switching the third transistor and the fourth transistor to an ON state to connect both the first and second capacitors to the data signal input so as to set respective charge levels of the first and second capacitors in dependence on a voltage at the data signal input during said programming stage.

[0034] Brief Description of Drawings

[0035] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0036] Figure 1 illustrates a multiple-gate transistor comprising a current control gate and a switching gate, according to an embodiment of the present invention;

[0037] Figure 2 illustrates a first pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0038] Figure 3 is a flowchart showing a method of controlling a pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0039] Figure 4 is a timing diagram showing reset, programming, hold and emission phases during operation of the first pixel circuit;

[0040] Figure 5 illustrates a flow of current in the first pixel circuit during the reset phase;

[0041] Figure 6 illustrates a flow of current in the first pixel circuit during a first stage of the programming phase for pulse amplitude modulation;

[0042] Figure 7 illustrates a flow of current in the first pixel circuit during a second stage of the programming phase for pulse width modulation;

[0043] Figure 8 illustrates the first pixel circuit during the hold phase;

[0044] Figure 9 illustrates a flow of current in the first pixel circuit during the emission phase; Figure 10 illustrates transfer characteristics of a conventional thin-film transistor (TFT), in linear scale (left-hand diagram) and semilogarithmic scale (middle diagram), as well as output characteristics in linear scale (right-hand diagram);

[0045] Figure 11 illustrates multiple-gate multimodal transistor (MMT) transfer characteristics for the current control gate in linear scale (left-hand diagram) and semilogarithmic scale (right-hand diagram);

[0046] Figure 12 illustrates multiple-gate MMT transfer characteristics for the switching gate in linear scale (left-hand diagram) and semilogarithmic scale (right-hand diagram); Figure 13 illustrates output characteristics in linear scale for the multiple-gate MMT in the first pixel circuit;

[0047] Figure 14 illustrates node voltages in the first pixel circuit during the reset and programming phases;

[0048] Figure 15 illustrates node voltages and drain current during operation of the first pixel circuit; Figure 16 illustrates node voltages and drain current providing pulse amplitude modulation (PAM) operation of the first pixel circuit;

[0049] Figure 17 illustrates node voltages and drain current providing pulse width modulation (PWM) operation of the first pixel circuit;

[0050] Figure 18 illustrates a second pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0051] Figure 19 is a timing diagram showing reset and programming phases during operation of the second pixel circuit;

[0052] Figure 20 illustrates a flow of current in the second pixel circuit during the reset phase;

[0053] Figure 21 illustrates a flow of current in the second pixel circuit during the programming phase;

[0054] Figure 22 illustrates a flow of current in the second pixel circuit during the emission phase;

[0055] Figure 23 illustrates transfer characteristics for the current control gate (CGI) in linear scale (left-hand diagram) and transfer characteristics in semilogarithmic scale for the switching gate in semilogarithmic scale (right-hand diagram) for the multiple-gate transistor in the second pixel circuit;

[0056] Figure 24 illustrates output characteristics for the multiple-gate transistor in the second pixel circuit, in linear scale (left-hand diagram) and semilogarithmic scale (right-hand diagram);

[0057] Figure 25 illustrates switching gate transfer characteristics of the multiple-gate transistor in the second pixel circuit for various interfacial charge values Qi;

[0058] Figure 26 illustrates node voltages in the second pixel circuit during the reset, programming, and emission phases for two values of a data signal (left-hand diagram), and a close-up of node voltages for the data signal value equal to 3 V (right-hand diagram);

[0059] Figure 27 illustrates the drain current of the multiple-gate transistor across a frame duration of the second pixel circuit for three values of the data signal;

[0060] Figure 28 illustrates a third pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0061] Figure 29 illustrates a fourth pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0062] Figure 30 is a timing diagram showing hold, programming, and emission phases during operation of the fourth pixel circuit;

[0063] Figure 31 illustrates a flow of current in the fourth pixel circuit during the programming phase; Figure 32 illustrates a flow of current in the fourth pixel circuit during the emission phase;

[0064] Figure 33 illustrates a fifth pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0065] Figure 34 illustrates a display apparatus comprising a plurality of pixel circuits, according to an embodiment of the present invention;

[0066] Figure 35 illustrates a sixth pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0067] Figure 36 is a timing diagram showing programming, hold, and emission phases during operation of the sixth pixel circuit;

[0068] Figure 37 illustrates a flow of current in the sixth pixel circuit during the programming phase;

[0069] Figure 38 illustrates charge stored within the respective capacitors in the sixth pixel circuit during the hold phase;

[0070] Figure 39 illustrates a flow of current in the sixth pixel circuit during the emission phase;

[0071] Figure 40 illustrates a seventh pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention;

[0072] Figure 41 is a timing diagram showing reset, programming, and emission phases during operation of the seventh pixel circuit;

[0073] Figure 42 illustrates a flow of current in the seventh pixel circuit during the reset phase;

[0074] Figure 43 illustrates a flow of current in the seventh pixel circuit during a first programming phase;

[0075] Figure 44 illustrates a flow of current and charge stored in the capacitor connected to the source control gate in the seventh pixel circuit during a second programming phase; and

[0076] Figure 45 illustrates a flow of current in the seventh pixel circuit during the emission phase.

[0077] Detailed description

[0078] In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. For convenience, in the following description various device geometries according to embodiments of the invention are described in relation to devices in the orientations shown in the drawings. Where terms such as "over", "above", "lateral", "vertical" and so on are used in the description, these should not be construed as meaning that such embodiments are restricted to the specific orientations shown in the drawings. It should be readily appreciated that the devices described herein will be capable of functioning correctly regardless of the physical orientation of the device, or of an apparatus in which the device is included, and as such the following description should be interpreted accordingly.

[0079] As noted above, existing pixel circuits typically have complex architectures at the expense of pixel size and complexity of the electronic driving scheme. To address such issues, embodiments of the present invention provide pixel circuits based on highly functional and robust multi-gate transistors, which consequently benefit from improvements in efficiency of both operation and layout. The multimodal transistor (MMT) is one type of multiple-gate transistor that uses two gate electrodes for controlling the magnitude of drain current separate from on / off channel switching. The function and properties of this type of device is unique, and making use of the unique device behaviour requires bespoke circuits that can leverage the separation of current generation from channel switching for creating compact and highly functional circuits.

[0080] In the following description, various pixel circuits according to embodiments of the invention will be described in more detail. It should be understood that in this context, the term "pixel circuit" refers to the circuit that controls the emission of each physical pixel in a display comprising an array of such pixels (e.g. red, green or blue pixels in an RGB display). When considering the image that is formed by the display, the term "pixel" can also be used to describe the light components from which the image is formed. In practice, each image pixel is formed by light emitted from a number of physical pixels in the display (e.g. a pixel group comprising one red, one green and one blue light emitting component, each of which has an associated pixel circuit to control the emission of that component). Hence, the physical pixels (and pixel circuits) may sometimes be referred to as "sub-pixels".

[0081] Referring now to Fig. 1, a multiple-gate transistor comprising a current control gate and a switching gate is illustrated, according to an embodiment of the present invention. The multiple-gate transistor 100 comprises a source 101, a drain 102, a first gate 103 and a second gate 104. The source 101 and drain 102 are spaced apart from each other and separated by a semiconductor region 105. In other words, the source 101 and the drain 102 are separated by the semiconductor region 105. The contact between the source 101 and the semiconductor 105 comprises a potential barrier. For example, a potential barrier between the source 101 and the semiconductor 105 may be provided by selecting suitable materials for the source 101 and the semiconductor region 105, by doping the material of the source 101 and / or the semiconductor region 105, or by forming a heterojunction contact between two or more semiconductor materials.

[0082] The source 101, drain 102, first gate 103, second gate 104, and semiconductor region

[0083] 105 may each be formed from any suitable material or combinations of materials. Examples of materials that may be used for the source 101, drain 102, first gate 103 and / or second gate 104 include, but are not limited to: metals; conductive or semiconducting metal oxides; conductive or semiconducting polymers; doped semiconductors; graphene; and two-dimensional (2D) materials. Examples of materials that may be used for the semiconductor region 105 include, but are not limited to: crystalline, polycrystalline or amorphous silicon; crystalline membranes, semiconducting metal oxides; transition metal dichalcogenides; graphene; carbon nanotubes; semiconducting nanowires; organic semiconductors; and 2D- semiconductors.

[0084] The first gate 103 is disposed over at least part of the source 101, and is separated from the source 101 by the semiconductor region 105 and by an electrical insulator

[0085] 106 disposed over the semiconductor region 105. The electrical insulator 106 may generally be referred to as an 'insulating region', and may comprise the same material throughout or may comprise different insulating materials in different parts of the device. The region (e.g. a source-gate overlap region) of semiconductor material 105 that is above the source 101 may be referred to as the 'source region' of the semiconductor 105. When a potential difference greater than a certain threshold is applied to the first gate 103, an accumulation layer is formed in the source region at the interface between the semiconductor 105 and the insulator 106. Similarly, the second gate 104 is disposed over a gap 107 between the source 101 and the drain 102, and is separated from the source 101 and the drain 102 by the semiconductor region 105 and by the electrical insulator 106. Depending on the embodiment, the second gate 104 may or may not overlap vertically with the drain 102. When a potential difference greater than a certain threshold is applied to the second gate 104, an accumulation layer is formed in the gap 107 between the source 101 and drain 102 (also referred to as the 'source-drain gap' 107), at the interface between the semiconductor 105 and the insulator 106.

[0086] In some embodiments, the multiple-gate transistor 100 can comprise an interfacial layer between the source 101 and the semiconductor region 105 for controlling the properties of the potential barrier. For example, an interfacial layer may be formed by depositing a different material over the source 101 before depositing the semiconductor region 105, or by doping a surface region of the source 101. As a further example, in some embodiments an interfacial layer may be formed by processing the source material before the depositing the semiconductor region 105, for instance by oxidising a surface of the source 101 before depositing the semiconductor region 105, or applying a suitable chemical treatment to alter the surface chemistry of the source material.

[0087] In some embodiments, the source 101 may not directly overlap the first gate 103, but instead a region of the semiconductor 105 to one side of the source 101 may be doped to provide a region of overlap with the first gate 103. As a further alternative, in some embodiments a different material may be deposited to one side of the source metallisation 101 in the direction of the drain 102, for example another metal, and the first gate 103 may be formed above, and overlap with, this region of other material adjacent to the source 101.

[0088] In the present embodiment, the source 101 and drain 102 are arranged such that when a potential difference greater than a certain threshold is applied across the source 101 and drain 102, a depletion layer is formed in the semiconductor region 105 adjacent to the source 101 across the whole cross-section of the semiconductor layer 105 at the edge of the source 101 closest to the drain 102. In the present embodiment the source 101 comprises a single continuous layer, but in other embodiments the source 101 may comprise a plurality of separate parts electrically connected in parallel to the semiconductor region 105. In some embodiments the depletion layer may not be formed across the whole cross-section of the semiconductor layer 105, although device performance may be compromised as a result due to an increase in saturation voltage and a reduction in intrinsic gain.

[0089] Together, the first gate 103 and the second gate 104 are configured to cause creation of a continuous conductive layer at the interface between the semiconductor region 105 and the insulator 106. In the present embodiment the conductive layer is an accumulation layer, but in other embodiments an inversion layer may be formed as the conductive layer. In this context, 'continuous' means that the conductive layer extends from the drain 102, across the gap 107 between the source 101 and drain 102, and over at least part of the source 101. The conductive layer therefore provides a path for current to flow between the source 101 and the drain 102 in the semiconductor region 105. In this way, when the correct voltage is applied to both the first and second gates 103, 104, the multiple-gate transistor 100 functions in a similar manner to a conventional source-gated transistor (SGT).

[0090] The operation of the multiple-gate transistor 100 can be understood with reference to Mode I and Mode II currents, as shown in Fig. 1. The diagram in Fig. 1 illustrates an example of the multiple-gate transistor 100 when operating in a similar mode to an SGT, according to an embodiment of the present invention. This mode of operation of the multiple-gate transistor 100 may be referred to as an 'SGT-like' mode. In the SGT-like operating mode, two distinct modes of current exist as a consequence of the source pinch-off effect. The Mode I current, II, is determined by the electric field in the depletion region 105a at the tip of the source 101. This can be referred to as the high field mode. Mode I current has a high temperature coefficient and high electric field dependence.

[0091] The Mode II current, 12, is injected along the remaining length of the source 101, i.e. away from the source-drain gap, and encounters resistance in the horizontal accumulation layer 105b as it travels through the semiconductor 105 along the length of the source 101. The Mode II current also encounters resistance vertically as it is injected from the source contact 101 and traverses the semiconductor 105, and hence the Mode II current is ohmic in nature. The Mode II current is therefore linearly proportional to the voltage applied to the first gate 103. The total current flowing into the drain 102, ID, is equal to the sum of the Mode I and Mode II currents, i.e. ID = (Il + 12).

[0092] As described above, in the present embodiment the multiple-gate transistor 100 functions in a similar manner to a conventional SGT when the correct voltage is applied to both the first and second gates 103, 104. However, unlike a conventional SGT, the multiple-gate transistor 100 of the present embodiment comprises a plurality of gates 103, 104. The magnitude of the Mode I and Mode II currents can be controlled by varying the voltage applied to the first gate 103. By providing first and second gates 103, 104 as shown in Fig. 1, the first gate 103 can be used to control the charge injection from the source electrode 101, while the second gate 104 can be used to control the conductive channel between the source 101 and the drain 102 without influencing charge injection. Consequently, the first gate 103 is hereinafter referred to as a "current control gate", and the second gate 104 is hereinafter referred to as a "switching gate".

[0093] Additionally, by appropriately designing the current control gate 103 to shield the source 101 from the electric field generated by the switching gate 104, coupling of the switching gate 104 to the source 101 can be reduced. For example, in the present embodiment the current control gate 103 comprises an extending portion 103a which overhangs a gap between the current control gate 103 and the switching gate 104. The extending portion 103a serves to shield the source 101 from the influence of the switching gate 104. Since the current control gate 103 is separated from the switching gate 104 by an insulator 106, different voltages can be applied to the current control gate 103 and the switching gate 104, and the current control gate 103 can electrically shield the source 101 from a potential difference applied to the switching gate 104. In this way, the device operation can be improved since the drain 102 voltage and switching gate 104 voltage will not influence the amount of current that is injected. When voltage is applied to the switching gate 104, current is permitted to flow within the semiconductor region 105 in the gap 107 between the source 101 and the drain 102. This can be considered as switching the transistor from 'off' to 'on', hence the second gate 104 can be referred to as the "switching gate". At the same time, the magnitude of the current flowing between the source 101 and drain 102 is determined by the potential applied to the current control gate 103.

[0094] Since the current flowing between the source 101 and the drain 102 can scale linearly with the current control gate 103 voltage, the multiple-gate transistor 100 can be considered to behave as a linear variable resistor, or a linear voltage-controlled current source, with an integrated switch, in a single device. If the switching gate 104 is 'on', meaning that the voltage applied to the switching gate 104 is above a certain threshold, and the voltage on the current control gate 103 is also below a corresponding threshold for the current control gate 103, the device remains 'off' and no current will flow between the source 101 and drain 102. Therefore, the switching gate 104 controls the switching on / off behaviour, and the current control gate 103 controls the device as a current source while the transistor 100 is in the 'on' state.

[0095] Therefore by providing separate current control and switching gates 103, 104, the conduction state of the device (on / off) can be controlled in one part of the device, i.e. by varying the voltage that is applied to the switching gate 104, whilst the magnitude of the current through the multiple-gate transistor 100 can be set in a separate part of the device, i.e. by varying the voltage that is applied to the current control gate 103.

[0096] In the embodiment shown in Fig. 1, the drain 102 is laterally spaced apart from the source 101, the semiconductor region 105 is disposed over the source 101 and the drain 102, and the current control 103 and switching gates 104 are disposed on an opposite side of the semiconductor region 105 to the source 101 and the drain 102. However, in other embodiments different device geometries are possible. For example, in some embodiments the drain may be disposed above the source, and the control and switching gates may be disposed to one side of the source and drain. The example of the multiple-gate device cross-section does not necessarily pertain to a rectangular device from a top-view perspective but may refer to a rectangular device, or a round design (e.g. Corbino), or a cylindrical device with the shown cross section as the slice which gets rotated around one the vertical edges to create the cylindrical structure.

[0097] In the present embodiment, the current control gate 103 and the switching gate 104 are disposed at the same height above the source 101 and drain 102. To keep the two gates separate, the current control gate 103 and the switching gate 104 are spaced apart from one another and separated by an electrical insulator 106. Also, to achieve a continuous electric field across the source 101 and the source-drain gap 107, the current control gate 103 comprises a portion 103a that extends above a gap separating the current control gate 103 from the switching gate 104. In other embodiments a similar extending portion may be formed from the switching gate 104 instead of the current control gate 103. However, it can be advantageous to form the extending portion 103a as part of the current control gate 103 as opposed to the switching gate 104, as an extending portion 103a formed from the current control gate 103 can assist in shielding the source 101 from the switching gate 104, as explained above.

[0098] As shown in Fig. 1, the portion of the current control gate 103 or the switching gate 104 may extend to at least the same lateral position as an adjacent edge of the other one of the current control gate 103 and the switching gate 104, so that a continuous electric field can be maintained over the source 101 and the source-drain gap 107. In some embodiments the extending portion 103a may overlap the switching gate 104, meaning that part of the extending portion 103a lies directly above part of the switching gate 104. Also, the extending portion 103a is vertically separated from the edge of the other one of the current control gate 103 and the switching gate 104, to ensure that the current control gate 103 and the switching gate 104 are electrically isolated from each other within the device.

[0099] The multiple-gate transistor 100 is therefore an example of a type of transistor in which one gate (i.e. the current control gate, CGI) can be used to independently control a magnitude of current supplied by a source region of the multiple-gate transistor in dependence on a first voltage applied to the current control gate, the current control gate being disposed opposite a source electrode of the multiple-gate transistor, and in which another gate (i.e. the switching gate, CG2) can be used to block or permit a flow of current in a channel region of the multiple-gate transistor in dependence on a second voltage applied to the switching gate. Here, the term "independently control" is used to mean that variations in a voltage applied to one of the gates has little or no measurable effect on the property controlled by the other gate(s). For example, the current control gate CGI "independently controlling" the magnitude of the current can be understood as meaning that the voltage applied to the switching gate CG2 has little or no effect on the magnitude of the current. In other words, the channel region (i.e. the part of the semiconductor region that is influenced by the voltage on the switching gate CG2) does not control the magnitude of current in the multiple-gate transistor, which is distinctly different from conventional transistors where the gate in the channel regions simultaneously controls current and switching.

[0100] In multiple-gate transistors where the current control gate CGI can be used to independently control a magnitude of current supplied by a source region of the multiple-gate transistor in dependence on a first voltage applied to the current control gate, the current control gate being disposed opposite a source electrode of the multiple-gate transistor, the source electrode can comprise an energy barrier. The energy barrier may be configured to provide a reduced transconductance in comparison to an Ohmic or quasi-Ohmic source. In such embodiments, the energy barrier can control the magnitude of current over a wider range of current control gate voltages (e.g. for improved linearity of drain current for grey levels in a display based on the pixel circuit, for supralinear dependence of drain current, and for low leakage), and is inherently controlled by the current control gate in dependence on a first voltage applied to the current control gate.

[0101] In some embodiments of the present invention, when using certain high-mobility semiconductors in a multiple-gate MMT, a field plate structure may be included on the source (and optionally also on the drain) in order to provide shielding from the lateral drain electric field, which can influence the height of the energy barrier at the source edge and result in an unwanted increase in drain current. In some cases, the field plate can be implemented as a separate electrode rather than a metal extension. It can be appreciated that the addition of supplementary or auxiliary electrodes that promote or improve device performance in this way, in addition to those illustrated in Fig. 1, do not depart form the scope of this invention.

[0102] In embodiments of the present invention, a multiple-gate transistor can be used in a pixel circuit to control the flow of current through a light emitting component connected to the source or drain of the multiple-gate transistor such that, in use, the current flowing through the light emitting component is controlled by the current control gate of the multiple-gate transistor, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the multiple-gate transistor. Such pixel circuits can also comprise a driving circuit configured to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component. Examples of such pixel circuits are described in more detail below.

[0103] Figure 2 illustrates a first pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention. The first pixel circuit comprises a first transistor, Ml, which is a multiple-gate transistor comprising separate current control gates and switching gates for controlling the magnitude of the current flowing between the source and drain independently of switching the flow of current on / off. In the present embodiment the first transistor Ml has a similar structure to the transistor 100 shown in Fig. 1, and comprises a source, a drain spaced apart from the source, a semiconductor region disposed between the source and the drain, an insulating region disposed over the semiconductor region, a current control gate CGI in the source region and a switching gate CG2 in the channel (source-drain gap) region. The current control gate CGI can be used to control a magnitude of current flowing between the source and the drain through the semiconductor region in dependence on a first voltage applied to the current control gate, and is separated from the source by the semiconductor region and the insulating region. The switching gate CG2 can be used to permit current to flow between the source and the drain through the semiconductor region in dependence on a second voltage applied to the switching gate, in other words, to switch the transistor Ml between ON and OFF states. The first pixel circuit further comprises a light emitting component (e.g. a light emitting diode LED, or an organic light emitting diode OLED) connected to the source or drain of the first transistor such that, in use, a current flowing through the light emitting component is controlled by the first transistor, and a driving circuit configured to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component.

[0104] In the present embodiment, the driving circuit of the first pixel circuit comprises a first capacitor Cl and a second capacitor C2. The first capacitor Cl is connected to the current control gate CGI such that, in use, a voltage on the first capacitor Cl can be applied to the current control gate CGI as the first voltage. The second capacitor C2 is connected to the switching gate CG2 such that, in use, a voltage on the second capacitor C2 can be applied to the switching gate CG2 as the second voltage. By providing a separate capacitor Cl, C2 for each of the current control gate CGI and the switching gate CG2, the driving circuit is capable of independently controlling the voltage that is applied to the respective gates CGI, CG2 during an emission phase, by charging each capacitor Cl, C2 to an appropriate level before the start of the emission phase.

[0105] Continuing with reference to Fig. 2, in the present embodiment the driving circuit of the first pixel circuit further comprises a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. As will become apparent from the following description, in some embodiments of a pixel circuit comprising a multiple-gate transistor the driving circuit may omit some or all of the second to seventh transistors M2-M7, depending on whether the functionality associated with each such transistor is required in any given implementation.

[0106] The second transistor M2 is connected between the second capacitor C2 and a first reference voltage node. In other words, the second transistor M2 is configured to block or permit the flow of current between the second capacitor C2 and the first reference voltage node, depending on whether the second transistor M2 is in an ON state or an OFF state. Here, the term "ON state" refers to the state in which a transistor is able to conduct and produce current between its source and drain, whereas the "OFF state" refers to the state in which substantially no current is able to flow between the source and drain. A transistor may be switched between its ON and OFF states by applying an appropriate voltage to its gate electrode. The skilled person will be familiar with the operating principles of conventional transistors (e.g. thin film transistors, TFTs), and a detailed description will not be provided here. During operation of the first pixel circuit, the second transistor M2 can therefore be switched into an ON state to reset a voltage on the second capacitor C2 to a voltage (VREF) at the first reference voltage node. The second transistor M2 is further connected to the switching gate CG2 of Ml. In some embodiments, the second transistor M2 may be connected to the current control gate CGI instead of the switching gate CG2.

[0107] The third transistor M3 is connected between the current control gate CGI and the switching gate CG2. In other words, the third transistor M3 is configured to block or permit the flow of current between the electrical nodes represented by the current control gate CGI and the switching gate CG2, depending on whether the third transistor M3 is in an ON state or an OFF state. During operation of the first pixel circuit, the third transistor M3 can therefore be switched into an ON state to allow the voltages at the current control gate CGI and the switching gate CG2 to be equalised. The third transistor M3 may be further connected in series with the second transistor M2, such that when the second and third transistors M2, M3 are both in the ON state the reference voltage VREF is applied to both the first and second capacitors Cl, C2, given that the first and second capacitors Cl, C2 are connected respectively to the current control gate CGI and the switching gate CG2.

[0108] The fourth transistor M4 is connected in series with the third transistor M3, and is further connected between a data signal input, DATA, and the second capacitor C2. In this way, when the fourth transistor M4 is in the ON state, current can flow between the second capacitor C2 and the data signal input. Additionally, since the fourth transistor M4 is connected in series with the third transistor M3, when both the third and fourth transistors M3, M4 are in the ON state, current can flow between the first capacitor Cl and the data signal input. It should be appreciated that in the context of the present disclosure, the term "connected" does not necessarily imply "directly connected", and can allow for the possibility that other components may be connected between the two components / nodes in question. For example, in relation to the discussion of M4 above, it will be appreciated that in the first pixel circuit the fourth transistor M4 is connected to the data signal input DATA via the first transistor Ml and the fifth transistor M5, both of which must therefore also be switched into the ON state to connect M4 to the data signal input DATA. By virtue of being connected as shown in Fig. 2, the fourth transistor M4 is thereby configured to connect the second capacitor C2 to the data signal input DATA when the fourth transistor M4 is switched to the ON state by signal SEL 1. In other embodiments, however, the fourth transistor M4 could be connected directly to the data signal input so as to apply the DATA signal directly to the first and second capacitors Cl, C2.

[0109] In the present embodiment, the source of the first transistor Ml is connected to the data signal input DATA via the source and the drain of the first transistor Ml such that, in use, when the third and fourth transistors M3, M4 are both in the ON state the first and second capacitors Cl, C2 can be discharged to a voltage equal to VDATA + Vth, where VDATA is a voltage at the data signal input and Vth is a threshold voltage of the first transistor Ml with respect to CGI. This is achieved through the diode-connection of the first transistor Ml made through the fourth transistor M4. The contact- controlled (source energy barrier controlled) nature of the first transistor Ml ensures that it is always in saturation when its drain to source voltage is equal to, or higher than, its CGI gate to source voltage. This voltage programming method compensates for the device-to-device variability of the threshold voltage.

[0110] In the present embodiment, the driving circuit further comprises the fifth and sixth transistors M5, M6, to allow the source of the first transistor Ml to be interchangeably connected to either a ground plane, GND, or to the data signal input DATA. The fifth transistor M5 is connected between the source of the first transistor Ml and the data signal input DATA. The sixth transistor M6 is connected between the source of the first transistor Ml and a ground plane, GND. In use, the sixth transistor M6 can be switched to an ON state to allow current to flow through the first transistor Ml and the light emitting component DI, and can be switched to an OFF state to isolate the source of the first transistor Ml from the ground plane GND (e.g. when the fifth transistor M5 is switched ON to connect the source of the first transistor Ml to the data signal input DATA).

[0111] In some embodiments, as is the case in the first pixel circuit of Fig. 2, respective gates of the fourth transistor M4 and the fifth transistor M5 may be connected to a first control input for receiving a first control signal SEL1. In this way, the fourth and fifth transistors M4, M5 can be switched ON or OFF in tandem using a single control signal SEL1, simplifying control of the driving circuit.

[0112] In other embodiments the fifth and sixth transistors M5, M6 may be omitted, such that the source of the first transistor Ml is permanently connected to the data signal input DATA. For example, in such embodiments the supply voltage ELVDD may be temporarily lowered below the threshold voltage of the light emitting component DI whilst the data signal DATA is used to program pixels on other rows of the display, to avoid emission by the light emitting component DI whilst the other pixels are being programmed.

[0113] In the present embodiment the driving circuit further comprises the seventh transistor M7, which is connected in series between the first transistor Ml and the light emitting component DI. In use, the seventh transistor M7 may be switched into an ON state to allow current to flow through the first transistor Ml and the light emitting component DI. In some embodiments, respective gates of the sixth and seventh transistors M6, M7 may be connected to an emission control input for receiving an emission control signal EM. In this way, the sixth and seventh transistors M6, M7 can be switched ON or OFF in tandem using a single emission control signal EM, simplifying control of the driving circuit.

[0114] Figure 3 is a flowchart showing a method of controlling a pixel circuit comprising a multiple-gate transistor, according to an embodiment of the present invention. The method can be used to control the first pixel circuit shown in Fig. 2, or similar such methods may be used to control other types of pixel circuits as disclosed herein.

[0115] The method starts by performing a reset phase in step S301. During the reset phase, the first capacitor Cl is set to a first voltage level and the second capacitor C2 is set to a second voltage level. In the pixel circuit of Fig. 2, the first and second voltage levels are the same, in other words the first and second capacitors Cl, C2 are charged to the same voltage (VREF) during the reset phase. However, in other embodiments the first and second capacitors Cl, C2 may be charged to different respective voltages during the reset phase.

[0116] Next, the method proceeds to a programming phase in step S302. During the programming phase, respective charge levels of the first and second capacitors Cl, C2 are set to the desired levels, in other words the voltage levels that are to be applied respectively to the current control gate CGI and the switching gate CG2 during the emission phase.

[0117] In the present embodiment, the method then proceeds to a hold phase S303, in which the charge levels on the first and second capacitors Cl, C2 are maintained while other pixels in the display are programmed (e.g. pixels in other rows of the display). The timing of the hold phase S303 relative to the programming phase S302 may vary depending on the position of the current row of pixels in the pixel array. For example, for the first row (row 1) in an array comprising n rows the method may proceed straight from the reset phase S301 to the programming phase S302, followed by a hold phase S303 while rows 2 to n are programmed. On the other hand, for the nthrow the hold phase S303 occurs before the programming phase S302, since the nthrow is held while all other rows (1 to n-l) are programmed. For the intervening rows (rows 2 to n-l) there will be two hold phases, one before and one after the programming phase for that row, with the relative durations of the two hold phases varying from one row to another depending on the position of each row in the pixel array. In general, one or more hold phases are applied to any given pixel row, such that the pixels in that row are held (i.e. the charges are maintained on the first and second capacitors Cl, C2) while pixels in other rows are being programmed.

[0118] Then, in the present embodiment the method proceeds to the emission phase in step S304 once said other pixels have been programmed. In this way, all pixels of the display emit light simultaneously during the emission phase S304. Alternatively, in other embodiments each pixel row could enter the emission phase S304 immediately after that row has been programmed, without waiting for other rows of the display to be programmed. During the emission phase, the driving circuit is used to apply the first and second voltages stored on the first and second capacitors Cl, C2, respectively, to the current control gate CGI and the switching gate CG2, so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component DI.

[0119] The operation of the pixel circuit during each of the reset, programming, hold and emission phases will now be described with reference to Figs. 4 to 9. Figure 4 is a timing diagram showing reset, programming, hold, and emission phases during operation of the first pixel circuit. Specifically, Fig. 4 shows the relative states (e.g. LOW or HIGH or a specified analogue voltage level) of the various control signals used in the operation of the first pixel circuit, namely DATA, RESET, SEL1, SEL2, EM and RAMP.

[0120] Figure 5 illustrates a flow of current in the first pixel circuit during the reset phase S301. During the reset phase S301, the potential on the gates of the first transistor Ml, specifically the current control gate CGI and the switching gate CG2, is raised to a level higher than a maximum level of the first or second voltages that could ever be required to be applied to the current control gate CGI and the switching gate CG2, respectively, during the emission phase S304. This is achieved by setting control signals reset and SEL2 in a high logic state and keeping the ramp signal to the ground potential (GND). This has the effect of connecting nodes CGI and CG2 by closing the third transistor M3 (e.g. such that the third transistor M3 is in an ON state and conducting), and simultaneously connecting capacitors Cl and C2 to the potential VREF via the second transistor M2, which is also now closed (e.g. such that the second transistor M2 is in an ON state and conducting). Ml, M2, Cl, and C2 may be sized so that the potential at nodes CGI and CG2 can reach a value reasonably close to the reference VREF within a short period of time, typically on the order of one or a few microseconds (ps). In the reset phase S301, it is not necessary for the current control gate CGI and the switching gate CG2 to reach the same potential or a particular value of potential, as long as they are suitably high. In this phase, the signals EM, SEL1 are kept low such that transistors M4, M5, M6, and M7 are turned off and, since there is no current flowing through the light emitting component DI, the pixel is entirely dark.

[0121] Figure 6 illustrates a flow of current in the first pixel circuit during a first stage of the programming phase S302. In the first stage of the programming phase S302, which may be referred to as a pulse amplitude modulation (PAM) programming phase, the desired magnitude of the current, which will flow through the light emitting component DI when in the emission phase S304, is set. This current will be governed by the potential on the current control gate CGI of the first transistor Ml. The emission control signal EM continues to be set low so that the sixth and seventh transistors M6 and M7 are in the OFF state, not allowing any current through the light emitting component DI or from the source node to ground (GND). The ramp voltage is maintained at zero volts (off-state) and the reset signal is driven low to turn off the second transistor M2 and disconnect VREF from the rest of the pixel circuit. The voltage on the data line is stable at the desired level VDATA1, which is correlated with the required voltage at the current control gate CGI, for which the co rrect / d esired current would be passed through the light emitting component DI during the emission phase S304. Signal SEL1 is driven high to turn on the fourth and fifth transistors M4 and M5.

[0122] Since the current control gate CGI and switching gate CG2 are connected together through the third transistor M3, which remains closed, we write the voltage significantly higher than VDATA1. The first and second capacitors Cl, C2 will discharge over a period on the order of one or a few ps, until the potential at the current control gate CGI and switching gate CG2 reaches the value of VDATAI + Vthi, the latter being the threshold voltage of the first transistor Ml with respect to its current control gate CGI region. This is achieved through the diode-connection of the first transistor Ml made through the fourth transistor M4, and it is possible because the contact-controlled nature of the first transistor Ml ensures that it is always in saturation when its drain to source voltage is equal to, or higher than, its CGI gate to source voltage. This voltage programming method compensates for the device-to- device variability of the threshold voltage.

[0123] However, in other embodiments the data signal DATA may not be applied through the first transistor Ml. For example, in some embodiments the data signal input may be connected to the first capacitor Cl, the second capacitor C2, the current control gate CGI or the switching gate CG2, such that current can flow from the data signal input to the first and second capacitors Cl, C2 without passing through the first transistor Ml.

[0124] Figure 7 illustrates a flow of current in the first pixel circuit during a second stage of the programming phase, which may be referred to as a pulse width modulation (PWM) programming phase. In the PWM programming phase, the timing of the signals remains unchanged except for SEL2, which is driven low, switching the third transistor M3 into the OFF state and electrically disconnecting the previously shorted current control gate CGI and the switching gate CG2. Now the current control gate CGI is disconnected from the rest of the pixel circuit, and its potential with respect to ground is maintained by the charge stored in the first capacitor Cl, which for a typical implementation may be on the order of a fraction of a picofarad (pF). The voltage on the data line is now reduced to the value VDATA2.

[0125] This approach exploits the fact that the first transistor Ml can operate with a constant drain current when its switching gate CG2 voltage is lower than its current control gate CGI voltage, as the switching gate CG2 does not significantly influence the magnitude of drain current over a given range of voltages. At the start of this phase, the voltage at the switching gate CG2 was VDATAI + Vthi. The second capacitor C2, again typically sized to fractions of a pF, discharges through the fourth transistor M4, the first transistor Ml and the fifth transistor M5 until the potential at the switching gate CG2 reaches VDATA2 + Vth2 (where Vth2 is the threshold voltage with respect to the channel region controlled by the switching gate CG2), again in a typical time interval on the order of one or a few ps, and again compensating for threshold shift variations between the first transistors Ml in adjacent pixels.

[0126] Figure 8 illustrates the first pixel circuit during the hold phase S303, in which the fourth and fifth transistors M4, M5 are turned off by driving signal SEL1 low. The respective voltages are stored on the current control gate CGI and the switching gate CG2 by the first and second capacitors Cl, C2. The hold phase continues while all the pixels are sequentially programmed, as described above. In some embodiments a display may be configured to enable all pixels to be programmed simultaneously, for example by providing dedicated data signal inputs for each pixel, in which case the hold phase may be omitted completely.

[0127] Figure 9 illustrates a flow of current in the first pixel circuit during the emission phase S304, in which the sixth and seventh transistor M6, M7 are turned on by driving the signal EM high. This drives the SOURCE node of the first transistor Ml close to GND, and the node DRAIN toward supply voltage ELVDD, turning on the first transistor Ml. A current with the magnitude controlled by the potential at the current control gate CGI flows through the light emitting component DI, the sixth and seventh transistors M6, M7, and the first transistor Ml, and the light emitting component DI emits light with a brightness proportional to the drain current of the first transistor Ml, set by the potential on the current control gate CGI.

[0128] The emission phase S304 may be relatively long compared to durations of the other phases. For example, depending on the implementation, the emission phase S304 could range from a few milliseconds to a few seconds. Over this time, the voltage on node RAMP is reduced linearly to a negative value, which reduces the potential at the switching gate CG2 through capacitive coupling via the second capacitor C2. When the voltage at the switching gate CG2 reaches a low enough value, the first transistor Ml turns off, thereby turning off the current through the light emitting component DI and stopping light emission. The interval over which the light emitting component DI is allowed to emit is dictated by the value of the potential programmed on the switching gate CG2 during the PWM programming phase. The off-state current of transistors M2, M3, M4, and M5, along with the parasitic coupling between nodes CGI, CG2, DRAIN, and SOURCE may lead to deviations from ideal behaviour. Hence, the relative sizing of the capacitors and transistors can be determined in accordance to their electrical characteristics and to the desired frame time.

[0129] The results of computer simulation of the behaviour of the first pixel circuit during the phases described above will now be briefly described with reference to Figs. 10 to 17. The electrical characteristics of the transistors used in the simulation are given in Figs. 10 to 13, and the main parameters of the simulation are given in Table 1.

[0130] TABLE 1

[0131] The control transistors M2 to M7, i.e. the second to seventh transistors, are assumed to have transfer characteristics of a conventional TFT, as shown in Fig. 10 in linear and semilogarithmic scales. The output characteristics illustrated in Fig. 10 show poor saturation behaviour, but the high currents make these devices particular suited for fast switching. It should be appreciated that it is not essential for the components (e.g. transistors) in the circuit to behave precisely as shown in Fig. 10, and the pixel circuit may still be capable of operating correctly even if the behaviour of some or all of the transistors differs from that shown in the curves in Fig. 10.

[0132] Figure 11 illustrates transfer characteristics for the current control gate CGI in semilogarithmic and linear scales, Fig. 12 illustrates transfer characteristics for the switching gate CG2 in semilogarithmic and linear scales, and Fig. 13 illustrates output characteristics for the multiple-gate transistor in the first pixel circuit. As switching gate CG2 does not modulate the drain current, the characteristics flatten. This means that higher CG2 voltage does not affect the drain current and is exploited in the circuit. The output characteristics show low voltage saturation with flat curves, which is desirable in analogue circuit design.

[0133] Figure 14 illustrates node voltages in the first pixel circuit during the reset and programming phases, Fig. 15 illustrates node voltages and drain current during operation of the first pixel circuit, Fig. 16 illustrates node voltages and drain current as a result of the PAM capability of the circuit, and Fig. 17 illustrates node voltages and drain current as a result of the PWM capability of the circuit. It can be seen from Fig. 16 that the different CGI voltage increases the current and thereby the amplitude for PAM, whilst it can be seen from Fig. 17 that the different CG2 voltage translates to varying the width of the pulse for PWM.

[0134] A second pixel circuit according to an embodiment of the present invention will now be described, with reference to Figs. 18 to 27. As shown in Fig. 18, the second pixel circuit comprises a first transistor Ml, which is a multiple-gate transistor similar to the one shown in Fig. 1. Like the first pixel circuit of Fig. 2, the second pixel circuit comprises second, third and fourth transistors M2, M3 and M4 connected in a similar manner to the second, third and fourth transistors M2, M3 and M4 of the first pixel circuit, and comprises first and second capacitors Cl, C2 and a light emitting component DI similar to those of the first pixel circuit. For the sake of brevity, a detailed description of such features that are common to both the first and second pixel circuits (and which have therefore already been described above) will not be repeated here.

[0135] In the present embodiment, the driving circuit of the second pixel circuit comprises an eighth transistor M8 connected between the first capacitor Cl and a second reference voltage node. During operation of the second pixel circuit, the eighth transistor M8 can be switched into an ON state to charge the first capacitor Cl to a voltage (REF) at the second reference voltage node. In some embodiments, as shown in Fig. 18, respective gates of the second transistor M2 and the eighth transistor M8 may be connected to a second control input for receiving a second control signal (SEL n-1), where the second control input is the previous row's select signal. Similarly, respective gates of the third transistor M3 and the fourth transistor M4 may be connected to a third control input for receiving a third control signal (SEL n). In this way, the second and eighth transistors M2, M8, and the third and fourth transistors M3, M4 can be switched ON or OFF in tandem using a single respective control signal SEL n-1 or SEL n, thereby simplifying control of the driving circuit. For example, rows n of an array of such pixels in a display can be programmed via signals SEL n and the previous row's selection signal SEL n-1. The columns m of the pixel array can be programmed via the data m (DATA m) signal.

[0136] The operation of the pixel circuit during each of the reset S301, programming S302, hold S303 and emission phases S304 will now be described with reference to Figs. 19 to 22. Figure 19 is a timing diagram showing reset, programming, hold and emission phases during operation of the second pixel circuit. Specifically, Fig. 19 shows the relative states (e.g. LOW or HIGH or an analogue level of voltage) of the various control signals used in the operation of the first pixel circuit, namely DATA m, SEL n-1, and SEL n. The reset and programming phases are repeated until all rows have been programmed, before proceeding to the emission phase in which the programmed pixels across all rows emit light simultaneously. Alternatively, as described above, in some embodiments the emission signal EM(n) may be generated suitably for each row, so that once reset and programming has been completed for a given row, the emission phase can start for that row (i.e. as opposed to entering a hold phase for that row while other rows are programmed).

[0137] Figure 20 illustrates a flow of current in the second pixel circuit during the reset phase S301. The eighth transistor M8 performs a similar function to the second and third transistors M2, M3 in the first pixel circuit during the reset phase, by connecting the first capacitor Cl to a second reference node (REF). The reset phase in the second pixel circuit differs from the reset phase in the first pixel circuit in that the second capacitor C2 is discharged to ground (GND) via the second transistor M2, whereas in the first pixel circuit the second capacitor C2 is charged to the same high voltage VREF as the first capacitor Cl during the reset phase S301.

[0138] In more detail, in the reset phase S301 in the second pixel circuit two elements of circuit functionality are achieved. First, light emission is suppressed by blocking the current through the light emitting component DI by means of grounding the switching gate CG2 input of the first transistor Ml. This is achieved by turning on the second transistor M2 and thus draining the charge stored in the second capacitor C2 to ground GND. In some embodiments, the voltage at the first reference node may be a voltage other than ground, for example a relatively low reference voltage.

[0139] Secondly and simultaneously, the first capacitor Cl is charged to a relatively high potential by connecting the current control gate CGI terminal of the first transistor Ml to a common and constant reference potential REF, through the eighth transistor M8 which is closed by the same control signal as the second transistor M2. This control signal denoted select n-1 (SEL n-1) is the same signal which performs the function of select n (SEL n) in the previous row of pixels. For this reason, the time duration over which signal select n-1 and select n are asserted may be identical in practice, and, to allow the programming of all of the rows on the display within a reasonable time, this duration should be on the order of a few microseconds in a typical display. The third and fourth transistors M3, M4 remain open in this phase, being gated by signal SEL n, which is kept low. The magnitude of the final voltage stored on the first capacitor Cl at the end of the reset phase S301 may be set to any level that is significantly higher than the final value required at that node at the end of the programming phase S302. As will become clear from the explanation below, the charge that is stored on the first capacitor Cl during the reset phase should be sufficient that, when the first capacitor Cl subsequently shares charge with the second capacitor C2 during the PAM programming phase, their combined charge is still higher than that which will be required at the common node CG1 / CG2 (via the third transistor M3) at the end of the PAM programming phase. In other words, the two capacitors together should have more charge than needed at the end of the PAM programming phase, so that the excess can discharge via the data signal input DATA, thereby simultaneously programming the capacitors with the correct charges whilst also compensating for the threshold voltage of the first transistor Ml.

[0140] Figure 21 illustrates a flow of current in the second pixel circuit during the programming phase S302. Unlike the programming phase in the first pixel circuit, which comprises two distinct stages (the PAM and PWM programming phases), in the present embodiment the programming phase of the second pixel circuit comprises a single stage. During the programming phase in the second pixel circuit, the third transistor (M3) and the fourth transistor (M4) are switched to an ON state to connect both the first and second capacitors Cl, C2 to the data signal input DATA m, so as to set respective charge levels of the first and second capacitors Cl, C2 in dependence on a voltage at the data signal input.

[0141] In more detail, in the programming phase S302 of the second pixel circuit, the desired magnitude of the current which will flow through the light emitting component DI when in the emission phase S304, is set. This current will be governed by the potential on the current control gate CGI of the first transistor Ml. In some embodiments, the current may be governed by the potential on the switching gate CG2 if low current levels are desired. In this phase, the signal SEL n is active and SEL n-1 is inactive, therefore the third and fourth transistors M3, M4 are closed and the second and eighth transistors M2, M8 are open (e.g. in an OFF state and not conducting). Accordingly, the following simultaneous effects occur.

[0142] Firstly, the first and second capacitors Cl, C2 now each have one terminal connected to ground and the other terminal connected together via the third transistor M3. At the start of this phase, the first capacitor Cl has a relatively large amount of charge while the second capacitor C2 was completely discharged to ground. As the third transistor M3 begins conducting, the two capacitors Cl, C2 share charge, aiming for a common resultant potential to be established over the first and second capacitors Cl, C2. This resultant potential should be higher than the final potential required at the current control gate CGI at the end of the programming phase S302. For example, this can be achieved through a combination of magnitude of REF voltage, the timing of the reset S301 and programming S302 phases, and the relative sizes of the first and second capacitors Cl, C2.

[0143] Secondly, as capacitor C2 begins to charge, the first transistor Ml closes and begins conducting. Since the fourth transistor M4 is also conducting, nodes DRAIN, the current control gate CGI, and the switching gate CG2 are now effectively short- circuited. This arrangement also means that the first transistor Ml is connected in diode configuration, with both of its gates CGI, CG2 shorted to the drain. The charge shared between the first and second capacitors Cl, C2 flows through the fourth transistor M4 and the first transistor Ml to DATA m, until the potential at the current control gate and switching gate CGI, CG2 equals the DATA m voltage plus the threshold voltage of the first transistor Ml (in principle, with respect to the current control gate CGI).

[0144] The programming phase S302 in the second pixel circuit therefore follows a similar approach to that of the first pixel circuit in terms of connecting the data signal DATA m to the first and second capacitors Cl, C2 through the first transistor Ml (and via the third and fourth transistors M3, M4). This voltage programming method compensates for the device-to-device variability of the threshold voltage. However, as described above with reference to the first pixel circuit, in other embodiments based on the second pixel circuit the data signal DATA m may not be applied through the first transistor Ml.

[0145] In the programming phase S302 in the second pixel circuit, there is no emission from the light emitting component DI since it is reverse biased by the relatively large voltage at node DRAIN compared to the supply voltage VDD. For this reason, the first transistor Ml should have a relatively high threshold voltage compared to the light emitting component DI, to allow node DRAIN to reach a relatively high voltage during programming even when the value of the DATA m input is low.

[0146] When signal SEL n is applied, the first and second capacitors Cl, C2 share charge and the resultant potential is higher than the maximum required voltage on the current control gate CGI during the emission phase S304. Simultaneously, the first transistor Ml is turned on and is biased in diode configuration. The light emitting component DI does not conduct, as it is reverse biased by the potential at DRAIN. The first and second capacitors Cl, C2 discharge through the third and fourth transistors M3, M4 and the first transistor Ml and conduction stops when the current control gate and switching gate CGI, CG2 equals DATA m plus the threshold voltage of the first transistor Ml (with respect to the current control gate CGI).

[0147] Once both signals SEL n and SEL n-1 have been lowered, after the programming phase S302 in the second pixel circuit, the current row n of pixels will enter the emission phase S304. However, there may be still other rows to be programmed, in which case if the data signal DATA m is common (i.e. shared between pixels) the data that will be presented to the common DATA m signal may lead to unwanted emission from already-programmed rows in short durations equivalent to the programming time. Even though these may be imperceptibly fast to the human eye, they may lead to image degradation through deviations from the desired local image brightness. In some embodiments, this problem can be addressed by lowering of the supply voltage VDD below the threshold voltage of the light emitting component DI for the duration of the sequence denoted "All rows programmed" in Fig. 19. From the point of view of a given pixel, the period of time in which the supply voltage VDD is lowered below the threshold voltage of the light emitting component DI can be considered to be equivalent to the hold phase S303 of the first pixel circuit.

[0148] Figure 22 illustrates a flow of current in the second pixel circuit during the emission phase S304, in which all transistors except the first transistor Ml are turned off. The DATA m signal is driven to a specific low potential and emission occurs because the supply voltage VDD is set so that the light emitting component DI is in forward bias and the first transistor Ml is in saturation. This phase continues for the duration of the frame time. In comparison to the first pixel circuit, the second pixel circuit does not include the fifth, sixth and seventh transistors M5, M6, M7, and therefore the component count (and hence the physical size) of the second pixel circuit is reduced compared to the first pixel circuit.

[0149] The relatively small size of the first capacitor Cl and the second capacitor C2 may mean that the parasitic capacitances of the first to fourth and eighth transistors Ml- M4, M8 play a role in charge sharing, especially when the various switches (transistors) in the second pixel circuit are turned on and off. In some embodiments, the data signal DATA m may be pre-processed to compensate for any kickback effect of setting the potential on the current control gate CGI. In certain situations, the precise potential at the switching gate CG2 may not be of particular significance, should the first transistor Ml operate in a source- controlled rather than channel- controlled mode, such as at high drain currents. The second pixel circuit can be tuned for low linear sensitivity of the drain current to the current control gate CGI potential, meaning that the small variations at the input of the transistor which occur as a result of the first capacitor Cl discharging will produce only small, and potentially imperceptible, ultimate variations of the brightness of emitted light. Conversely, the first transistor Ml can be designed with a supra- linear / exponential dependence of drain current, in which case a much higher dynamic range can be achieved by solely relying on the current control gate CGl / source control, making the precise programming of the switching gate CG2 voltage far less stringent. This in turn allows the reduction of the layout area allocated to the second capacitor C2.

[0150] In some embodiments, the first transistor Ml can be configured such that the current control gate CGI transfer characteristic is exponential, meaning that the threshold voltage of the multimodal transistor can be kept close to zero. Accordingly, the values presented on the DATA m bus may be quite high compared to VDD minus the threshold voltage of the light emitting component DI, which would significantly reduce the problem described in relation to the hold phase S303, as all data presented would be significantly higher than the potential assigned to the DATA m line during the emission phase S304.

[0151] The thresholds of the light emitting component DI and multimodal transistor Ml, as well as supply voltage VDD, can be configured so that during the programming phase S302 when the light emitting component DI is in reverse bias its photo-generated current does not significantly affect operation. However, in principle, this may not be an issue in practice, as the photocurrent would discharge to VDD and DATA m.

[0152] As an alternative to configuring the first transistor Ml to have a high threshold voltage, the potential on the ground line GND could be raised to a certain value corresponding to the threshold of the light emitting component DI for the whole duration of the "All rows programmed" Phase in Fig. 19, and then restored to the zero potential during the common emission phase S304.

[0153] The electrical characteristics of the transistors used in the simulation are given in Figs. 23 to 25, and the main parameters of the simulation are given in Table 2. As with the simulation for the first pixel circuit, in the present simulation of the second pixel circuit the electrical characteristics of the control transistors, M2-M4 and M8, are based on those of a conventional TFT as illustrated in Fig. 10.

[0154] TABLE 2

[0155] Figure 23 illustrates transfer characteristics for the current control gate CGI in linear scale (left-hand diagram) and transfer characteristics for the switching gate in log scale (right-hand diagram), showing that the switching gate CG2 does not influence drain current above a certain bias. The transfer characteristics for the switching gate CG2 show that this gate does not modulate current, hence the characteristics flatten. The first transistor Ml here is implemented with interfacial charge to ensure a specific threshold voltage for circuit operation.

[0156] Figure 24 illustrates output characteristics for the multiple-gate transistor in the second pixel circuit, in linear scale (left-hand diagram) and log scale (right-hand diagram). The output characteristics (left: linear scale, right: log scale) show low voltage saturation (below 1 V) with predominantly flat curves, which is desirable in analogue circuit design. The first transistor Ml here has its threshold voltage changed, with respect to the current control gate CGI, so that it remains in the off- state for low CGl-source voltage VCGIS. Here, ~100 nanoamps (nA) is shown as a typical drain current corresponding to close-to-maximum brightness of the light emitting component DI. The output characteristics remain flat over a range of several volts, sufficient for all operating conditions (e.g., 1.5 to 2.5 V to account for temperature and ageing effects of the light emitting component DI).

[0157] Figure 25 illustrates switching gate transfer characteristics of the first transistor Ml in the second pixel circuit for various interfacial charge values Qi. At moderate and very low values of VCGIS, the device operating state can be altered by shifting the threshold voltage in the current control gate CGI region. Here, varying the interfacial charge values is shown merely as one example of a mechanism by which the desired functionality may be achieved. In other embodiments, other approaches may be used to change the threshold voltage of the first transistor Ml as required relative to the light emitting component DI, to enable correct operation of the pixel circuit.

[0158] Figure 26 illustrates node voltages in the second pixel circuit during the reset, programming, and emission phases for two values of a data signal (left-hand diagram), and a close-up of node voltages for the data signal value equal to 3 V (right-hand diagram), whilst Fig. 27 illustrates the drain current of the multiple-gate transistor across a frame duration of the second pixel circuit. The drain current of the multimodal transistor does not vary for the frame duration of the pixel circuit, indicating that variations in rail supply VDD are well tolerated.

[0159] Referring now to Fig. 28, a third pixel circuit comprising a multiple-gate transistor is illustrated according to an embodiment of the present invention. The third pixel circuit can be understood as a simplified representation showing a common structure to both the first and second pixel circuits. The third pixel circuit comprises a first transistor Ml, which is a multiple-gate transistor of the type described above. The third pixel circuit also comprises a light emitting component DI connected to the source or drain of the first transistor Ml such that, in use, a current flowing through the light emitting component is controlled by the first transistor Ml, and comprises a driving circuit 110 configured to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component.

[0160] Referring now to Fig. 29, a fourth pixel circuit comprising a multiple-gate transistor is illustrated according to an embodiment of the present invention. The fourth pixel circuit comprises a first transistor Ml, which is a multiple-gate transistor of the type described above, and comprises a light emitting component DI and driving circuit. The driving circuit of the fourth pixel circuit comprises a capacitor C connected between the source of the first transistor Ml and the current control gate CGI, and comprises a second transistor M2 connected between the current control gate CGI and a data signal input, DATA. The switching gate CG2 and the drain of the first transistor Ml are both connected to a ground plane, GND. The fourth pixel circuit therefore comprises two transistors and one capacitor in total, and may be referred to as a "2T1C" pixel circuit.

[0161] In a programming phase S302 in the fourth pixel circuit, rows n of the pixel array are programmed via signals select n (SEL n). The columns m are programmed via the data m (DATA m) signal. The switching gate CG2 and drain terminals of the first transistor Ml are connected to a reference potential (e.g. a ground plane, GND). Although the reference potential is ground (GND) in the present embodiment, in other embodiments a different potential may be used as the reference potential. For example, the circuit operation will remain identical to that described below with reference to Figs. 30 to 32 if all potentials are translated up or down by notionally identical amounts.

[0162] Figure 30 is a timing diagram showing hold, programming, and emission phases during operation of the fourth pixel circuit. The hold phase occurs first in this embodiment, and is somewhat trivial. The hold phase occurs for all the pixels in the array while the other rows and columns are being programmed. In the hold phase, the emission signal EM is brought to a suitably high potential (e.g. same potential as GND, for convenience). This reverse-biases the light emitting component DI, allowing no current flow and thus no light to be emitted. In the hold phase the SEL (n) signal is low, so the second transistor M2 is off and not conducting. The capacitor C holds its charge. The source node S is connected to the drain potential (GND) through the source-drain leakage path of the first transistor Ml. No current flows in the circuit, as the potential difference between the source and the switching gate CG2 of the first transistor Ml is nil, as its drain-source potential difference, and hence the first transistor Ml remains switched off during the hold phase.

[0163] Figure 31 illustrates a flow of current in the fourth pixel circuit during the programming phase, which follows the hold phase in this embodiment. In the programming phase, the desired magnitude of the current which will flow through the light emitting component DI in the emission phase is set. This current will be governed by the potential on the current control gate CGI gate of the first transistor Ml.

[0164] When signal SEL n is applied, the second transistor M2 is turned on and the voltage across capacitor C becomes DATA(m) i.e. increases or decreases as the capacitor C charges or discharges through the second transistor M2. The source of the first transistor Ml, node S, is held close to GND potential (save for minimal parasitic capacitive coupling between the devices). DATA(m) is chosen in the usual fashion, to control the first transistor Ml into allowing a certain current flow through the light emitting component DI in the emission phase. Once the desired voltage has been stored in capacitor C, the SEL(n) signal is grounded and the DATA(m) signal will change to a value that is irrelevant to the current pixel. Therefore, the pixel will revert to the hold phase. Figure 32 illustrates a flow of current in the fourth pixel circuit during the emission phase, which occurs once all pixels have undergone programming via the hold and programming phases described above. The second transistor M2 is off, therefore the charge stored on C will keep a potential difference between the current control gate CGI and the source of the first transistor Ml as programmed.

[0165] When the emission signal EM (which may be a common signal applied to all pixels) is brought to a suitable negative potential with respect to GND, the following effects occur:

[0166] The light emitting component DI is forward biased and can emit light;

[0167] The drain-source voltage of the first transistor Ml is positive and thus the first transistor Ml can pass current;

[0168] The CG2-source voltage of the first transistor Ml is positive and thus the channel of the first transistor Ml is on, enabling conduction without influencing the magnitude of drain current;

[0169] The CGl-source voltage of the first transistor Ml remains as programmed, allowing the magnitude of the current through the first transistor Ml to be controlled. This magnitude, will, to a first order, not depend on the CG2-source and drain-source voltages of the first transistor Ml, nor on the absolute magnitude of the emission signal EM potential with respect to GND.

[0170] In comparison to the first and second pixel circuits, the fourth pixel circuit is more compact on account of fewer transistors being used, which enables increased display resolution. Additionally, using a multiple-gate transistor as the first transistor Ml in the fourth pixel circuit offers a number of advantages compared to using a conventional thin film transistor (TFT), including:

[0171] 1. Better discretization between grey levels. The multiple-gate transistor requires larger voltages on CGI than a conventional TFT. This may come with a minor energy penalty, but increases the available range over which e.g. the 256 or 1024 brightness tones are assigned, resulting in superior image quality and potentially lower flickering.

[0172] 2. Diminished effect of charge leakage from C via Ml, making either C smaller for increased display resolution, or reducing minimum refresh rate for improved energy efficiency. Because of the relative electrical potentials between nodes S, CGI, SEL(n) = 0 in the emission phase and {the range of DATA(m)}, reverse leakage through Ml is reduced, allowing the correct voltage to be retained on C for longer, or conversely maintaining the same performance but with a reduced C area. 3. Reduced or eliminated influence of I x R supply voltage drop. Conventional TFTs need to be driven in subthreshold to allow reduced drain-source voltage for superior energy efficiency, as well as to reduce the influence of the drain-source voltage variations on the current. The latter variation is likely different for different pixels in the array due to the supply current being drawn via wiring of varying resistance. Conventional transistors would saturate poorly, however MMTs allow early and flat saturation. Therefore, even for large values of CG1-S voltage, the drainsource voltage drop of the MMT will be small, and variations in current with drainsource voltage will be minimal. Therefore, image uniformity can be improved across the display area. Similarly, changes in LED forward voltage with current and / or ageing do not affect the magnitude of the current sourced by the MMT.

[0173] 4. Reduced complexity of wiring. The pixel only requires DATA, SEL and two supply rail signals, as a conventional 2T1C circuit would. The functionality comes at no extra expense of wiring or timing complexity.

[0174] 5. Compact pixel size for increased resolution, minimal feature sizes and overlap of CGI. The MMT allows a small drive transistor to be used, including staggering S and CGI, effectively resulting in the same footprint of a conventional TFT.

[0175] 6. Maintaining the channel of the transistor at fairly similar voltage via CG2-S potential being constant, thus being able to further improve the metrics discussed at point 3 above.

[0176] Referring now to Fig. 33, a fifth pixel circuit is illustrated according to an embodiment of the present invention. As with the fourth pixel circuit, the fifth pixel circuit is an example of a pixel circuit design in which the data signal DATA m is applied directly to the capacitor C, as opposed to being applied to the capacitor(s) via the driving transistor (Ml) as in the first and second pixel circuits. The fifth pixel circuit is similar to the fourth pixel circuit, except that the switching gate CG2 of the first transistor Ml is connected to an emission signal input as opposed to ground. This approach therefore uses the switching gate CG2 of the first transistor (which is an MMT in this embodiment) as an emission-enable input, allowing the programming of the voltage on capacitor C while the light emitting component DI is turned off. This can help to increase image contrast and energy efficiency, whilst providing a more compact implementation compared to alternative circuit designs that employ an additional switching transistor (e.g. M2, M3 etc.) in series with the driving transistor (the first transistor Ml). The lateral structure of the MMT staggers the switching gate CGI and the source contact S, reducing the overall footprint of the first transistor Ml compared to the alternative of having two transistors in series. Pixel circuits have therefore been described according to embodiments of the invention, such as the first, second, third and fourth pixel circuits, which exploit the ability of a multiple-gate transistor to perform functions that previously would have required multiple conventional transistors. In this way, the number of components (e.g. transistors) required in the pixel circuit can be reduced compared to conventional solutions.

[0177] A plurality of such pixel circuits can be included in a display apparatus, as shown in Fig. 34. The display apparatus 3400 comprises a display panel 3420 comprising a plurality of pixel circuits 3421, each of which comprises a pixel circuit according to an embodiment of the present invention (e.g. any of the pixel circuits disclosed herein). The pixel circuits may be arranged into a plurality of rows 1 to n. The display apparatus 3400 may further comprise control circuitry 3410 configured to provide control signals (e.g. EM, DATA, RESET, SEL etc.) to the plurality of pixel circuits to control the switching of one or more transistors within each pixel circuit 3421. The control signals may be applied to the pixel circuits 3421 via one or more transmission lines 3411. In some embodiments the control circuitry 3410 may be omitted, for example the display panel 3420 may be configured to receive control signals from an external source outside the display apparatus 3400.

[0178] Additionally, since the multiple-gate transistor can independently control the switching behaviour (i.e. ON / OFF) and the magnitude of current flowing through the light emitting component in the emission phase, pixel circuits according to embodiments of the invention can allow the setting of both the magnitude of the quasi-constant current through the light emitting component and the desired emission time. This in turn can enable the realisation of high-resolution, high-brightness and high-efficiency display screens (e.g. based on micro-LED emitters as the light emitting component), with superior image quality. The ability to independently control the switching and magnitude of current can also enable implementation of PAM and PWM control schemes, either separately or combined (PWAM).

[0179] The low saturation voltage of the multiple-gate transistor allows the following advantages: a reduction in the power supply voltage ELVDD and proportional energy saving during the emission phase; the ability to set the high precision of the output or drain current of the multiple-gate transistor (e.g. by choosing the potential at the current control gate CGI), due to the low transconductance possible in such devices; the ability to maintain a constant output current as long as the potential at the current control gate CGI is maintained constant, even during large variations of the switching gate CG2 voltage. This is central to the way that the combined PAM and PWM functionality is realised, maintaining a constant current set by means of the current control gate CGI as long as the switching gate CG2 is above a certain value; the low sensitivity of the output current of the multiple-gate transistor to variations in CG1-S voltage, meaning that small variations at the input of the transistor will result in small and potentially imperceptible ultimate variations of the brightness of emitted light.

[0180] A sixth pixel circuit according to an embodiment of the present invention will now be described, with reference to Figs. 35 to 39. As shown in Fig. 35, the sixth pixel circuit comprises a first transistor Ml, which is a multiple-gate transistor similar to the one shown in Fig. 1. As with the fourth and fifth pixel circuits, the sixth pixel circuit is an example of a pixel circuit design in which a data signal is applied directly to a capacitor, as opposed to being applied to the capacitor(s) via the driving transistor (Ml) as in the first and second pixel circuits. Like the first pixel circuit of Fig. 2 and the second pixel circuit of Fig. 18, the sixth pixel circuit comprises first and second capacitors Cl, C2 connected respectively to the current control gate CGI and switching gate CG2 of the first transistor Ml, and a light emitting component DI. Also like the first pixel circuit of Fig. 2 and the second pixel circuit of Fig. 18, the sixth pixel circuit comprises a second transistor M2 connected to the switching gate CG2, and comprises a third transistor M3 connected to the current control gate CGI. For the sake of brevity, a detailed description of such features that are common to the first, second, and sixth pixel circuits (and which have therefore already been described above) will not be repeated here.

[0181] The sixth pixel circuit differs from the first and second pixel circuits in several respects. Firstly, whereas the third transistor M3 is connected between the current control gate CGI and the switching gate CG2 in the first and second pixel circuits, such that the third transistor M3 can be controlled to open or close an electrical connection between the current control gate CGI and the switching gate CG2, in the sixth pixel circuit the third transistor M3 is connected between the current control gate CGI and a first data signal input. The first data signal input is configured, in use, to receive a first data signal DATA1. In this way, the current control gate CGI can be electrically connected or disconnected from the first data signal input by switching the third transistor M3 between the ON and OFF states. During operation of the sixth pixel circuit, the third transistor M3 can therefore be switched ON to charge the first capacitor Cl to the voltage of the first data signal DATA1. Secondly, whereas the second transistor M2 is connected between the switching gate CG2 and a reference node in the first and pixel circuits (VREF in the first pixel circuit; GND in the second pixel circuit), in the sixth pixel circuit the second transistor M2 is connected between the switching gate CG2 and a second data signal input. The second data signal input is configured, in use, to receive a second data signal DATA2. In this way, the switching gate CGI can be electrically connected or disconnected from the second data signal input by switching the second transistor M2 between the ON and OFF states. During operation of the sixth pixel circuit, the second transistor M2 can therefore be switched ON to charge the second capacitor C2 to the voltage of the second data signal DATA2.

[0182] Thirdly, whereas different control signals are applied to respective gates of the second and third transistors M2, M3 in the first and second pixel circuits (RESET and SEL2 in the first pixel circuit; SEL n-l and SEL n in the second pixel circuit), in the sixth pixel circuit the gates of the second and third transistors M2, M3 are both connected to a common input. Accordingly, in use, the same control signal (SEL n) is applied to the gates of both the second and third transistors M2, M3 in the sixth pixel circuit. Therefore, in the sixth pixel circuit the second and third transistors M2, M3 are configured to be switched concurrently (i.e. at the same time).

[0183] The sixth pixel circuit also comprises first and second emission (Em.) control components 3501, 3502. The first emission control component 3501 is connected to the drain of the first transistor Ml. In the present embodiment, the first emission control component 3501 is connected between the drain of the first transistor Ml and the light emitting component DI. In other embodiments the first emission control component 3501 may be connected between the light emitting component DI and the supply voltage line (VDD). As yet another alternative, in some embodiments the light emitting component DI may be connected between the source of the first transistor Ml and ground (GND), in which case the first emission control component 3501 may be connected between the drain of the first transistor Ml and the supply voltage line VDD.

[0184] The second emission control component 3502 is connected to the source of the first transistor Ml. In the present embodiment, the second emission control component 3502 is connected between the source of the first transistor Ml and GND. Furthermore, as described above, in some embodiments the light emitting component DI may be connected between the source of the first transistor Ml and GND. In such embodiments, the second emission control component 3502 may be connected between the source of the first transistor Ml and the light emitting component DI, or the second emission control component 3502 may be connected between the light emitting component DI and GND.

[0185] The first and second emission control components 3501, 3502 may be switched ON or OFF under the control of a suitable control signal, which may be referred to as the emission control signal. For example, the first and second emission control components 3501, 3502 may comprise transistors controlled by an emission control signal, similar to the sixth and seventh transistors M6, M7 described above with reference to the first pixel circuit of Fig. 2. When the first and second emission control components 3501, 3502 are both in the ON state (i.e. conducting), current is permitted to flow through the light emitting component DI from the voltage supply line VDD and GND via the first transistor Ml.

[0186] In an example embodiment, first and second emission control components 3501, 3502 may be optional, such that one or both of the first and second emission control components 3501, 3502 may be omitted. For example, the first transistor DI may be connected to the light emitting component DI directly, and may also be connected to GND directly. The emission control components 3501 and 3502 may, for example, be used for improving LED off-state performance, and may not be essential for the operation of the circuit.

[0187] The operation of the sixth pixel circuit during each of the programming S302, hold S303 and emission phases S304 (e.g. as described with reference to Fig. 3) will now be described with reference to Figs. 36 to 39. Figure 36 is a timing diagram showing programming, hold and emission phases during operation of the sixth pixel circuit. Specifically, Fig. 36 shows the relative states (e.g. LOW or HIGH or an analogue level of voltage) of the various control signals used in the operation of the first pixel circuit, namely DATA1 m, DATA2 m, and SEL n. The programming and hold phases are repeated until all rows have been programmed, before proceeding to the emission phase in which the programmed pixels across all rows start emitting light simultaneously. Alternatively, as described above, in some embodiments a separate emission signal EM(n) may be generated for each row in the display, so that once programming has been completed for a given row, the emission phase can start for that row whilst other rows are being programmed (in which case the hold phase may be omitted). In one example, length and / or positioning of the hold phase S303 within the timing diagram may vary, as every row of the display may be programmed sequentially, such that the row duration (Fig. 36) of one row may follow the row duration of the previous row within the "All rows programmed" time.

[0188] In one example, for the pixel being programmed i.e. row n and column m, DATAlm and DATA2m values may only be relevant while SEL(n) is high. Outside of this time, DATAlm and DATA2m may have values relevant to rows other than row n, such that their value may be irrelevant for the pixels on row n.

[0189] In one example, the length of the hold phase and the positioning of the hold phase within the timing diagram of Fig. 36 may vary for different sequences, as every row of the display may be programmed sequentially. Thus, for example, the row duration (e.g. shown in Fig. 36) of one timing diagram may follow the row duration of a previous timing diagram within the "All rows programmed" time.

[0190] Figure 37 illustrates a flow of current in the sixth pixel circuit during the programming phase S302. Unlike the programming phase in the first pixel circuit, which comprises two distinct stages (the PAM and PWM programming phases), in the present embodiment the programming phase of the sixth pixel circuit comprises a single stage. During the programming phase in the sixth pixel circuit, the second and third transistors M2, M3 are both switched to an ON state by the control signal SEL n. In this way, the first and second capacitors Cl, C2 are simultaneously connected and charged, respectively, to the first and second data signal inputs.

[0191] Hence, when the control signal SEL n is driven to a high level during the programming phase, as shown in Fig. 36, the voltage of the first data signal DATA1 m is applied to the first capacitor Cl, whilst the voltage of the second data signal DATA2 m is applied to the second capacitor C2. Since the first and second data signals DATA1 m, DATA2 m can be independently generated to have different instantaneous voltages, as illustrated in the exemplary programming phase shown in Fig. 36, the first and second capacitors Cl, C2 can therefore be independently charged to any arbitrary voltage during the programming phase (i.e. depending on the voltage of the respective first or second data signal DATA1 m, DATA2 m).

[0192] In this way, the desired magnitude of the current which will flow through the light emitting component DI when in the emission phase S304, is set during the programming phase S302. This current will be governed by the potential on the current control gate CGI of the first transistor Ml. In some embodiments, the current being controlled by CGI may be restricted by the potential on the switching gate CG2 if low current levels are desired, as CG2 cannot otherwise control current, but merely limit it. In this phase, the signal SEL n is active (i.e. at a high level), therefore the second and third transistors M2, M3 are closed.

[0193] Figure 38 illustrates a charge stored in the sixth pixel circuit during the hold phase S303. In this phase, the control signal SEL n is driven to a low level, such that the second and third transistors M2, M3 are both switched into the OFF (i.e. nonconducting) state. Also, the first and second emission control components 3501, 3502 are both in the OFF state, and accordingly no current flows between the source and drain of the first transistor Ml, or through the light emitting component DI. The sixth pixel circuit can be kept in the hold phase until all rows of the display have been programmed.

[0194] Figure 39 illustrates a flow of current in the sixth pixel circuit during the emission phase S304, in which the control signal SEL n is kept low such that the second and third transistors M2, M3 remain in the OFF state. In the emission phase S304, the first and / or second emission control components 3501, 3502 (if included in the circuit) are both switched into the ON state (i.e. conducting), such that current generated by CGI is permitted to flow by CG2 through the light emitting component DI from the voltage supply line VDD and GND via the first transistor Ml. Consequently, emission occurs because the light emitting component DI is in forward bias and the first transistor Ml is in saturation. This phase continues for the duration of the frame time.

[0195] The sixth pixel circuit can be tuned for low linear sensitivity of the drain current to the current control gate CGI potential, meaning that the small variations at the input of the first transistor Ml which occur as a result of the first capacitor Cl discharging will produce only small, and potentially imperceptible, ultimate variations of the brightness of emitted light. Conversely, the first transistor Ml can be designed with a supra- linear / exponential dependence of drain current, in which case a much higher dynamic range can be achieved by solely relying on the current control gate CGl / source control, making the precise programming of the switching gate CG2 voltage far less stringent. This in turn allows the reduction of the layout area allocated to the second capacitor C2.

[0196] A seventh pixel circuit according to an embodiment of the present invention will now be described, with reference to Figs. 40 to 45. As shown in Fig. 40, the seventh pixel circuit comprises a first transistor Ml, which is a multiple-gate transistor similar to the one shown in Fig. 1. As with the fourth, fifth and sixth pixel circuits, the seventh pixel circuit is an example of a pixel circuit design in which a data signal is applied directly to a capacitor, as opposed to being applied to the capacitor(s) via the driving transistor (Ml) as in the first and second pixel circuits. Like the first pixel circuit of Fig. 2 and the second pixel circuit of Fig. 18, the seventh pixel circuit comprises first and second capacitors Cl, C2 connected respectively to the current control gate CGI and switching gate CG2 of the first transistor Ml, and a light emitting component DI. Also like the first pixel circuit of Fig. 2 and the second pixel circuit of Fig. 18, the seventh pixel circuit comprises a second transistor M2 connected to the switching gate CG2, and comprises a third transistor M3 connected to the current control gate CGI and switching gate CG2.

[0197] Additionally, like the sixth pixel circuit, the seventh pixel circuit may optionally comprise first and / or second emission control components 4001, 4002. As with the sixth pixel circuit, the first and second emission control components 4001, 4002 may for example be similar to the sixth and seventh transistors M6, M7 described above with reference to the first pixel circuit of Fig. 2.

[0198] In many respects therefore, the seventh pixel circuit is similar to the sixth pixel circuit. For the sake of brevity, a detailed description of such features that are common to the first, second, sixth and seventh pixel circuits (and which have therefore already been described above) will not be repeated here.

[0199] The seventh pixel circuit differs from the sixth pixel circuit in that instead of respective first and second data signal inputs being provided for programming the first and second capacitors, as is the case in the sixth pixel circuit, the third transistor M3 in the seventh pixel circuit is connected between the current control gate CGI and the switching gate CG2. Hence, the third transistor M3 is connected in a similar arrangement to the third transistor M3 in the second pixel circuit. As with the second pixel circuit, in the seventh pixel circuit the respective gates of the second and third transistors M2, M3 are configured to receive different control signals, here labelled as SEL n and SEL n-l respectively. Accordingly, in the seventh pixel circuit the second and third transistors M2, M3 can be switched independently of one another.

[0200] The operation of the seventh pixel circuit during each of the reset S301, programming S302, hold S303 and emission phases S304 will now be described with reference to Figs. 42 to 45. Figure 41 is a timing diagram showing reset, programming, and emission phases during operation of the seventh pixel circuit. Specifically, Fig. 41 shows the relative states (e.g. LOW or HIGH or an analogue level of voltage) of the various control signals used in the operation of the first pixel circuit, namely DATA m, SEL n and SEL n-l, where SEL n-l may be the previous row's SEL signal. Figure 41 also plots the voltage at the current control gate (VCG1) and the voltage at the switching gate (VCG2) during each phase of operation of the seventh pixel circuit.

[0201] As shown in Fig. 41, the programming and hold phases are repeated until all rows have been programmed, before proceeding to the emission phase in which the programmed pixels across all rows emit light simultaneously. Alternatively, as described above, in some embodiments a separate emission signal EM(n) may be generated for each row in the display, so that once programming has been completed for a given row, the emission phase can start for that row whilst other rows are being programmed (in which case the hold phase may be omitted).

[0202] Figure 42 illustrates a flow of current in the seventh pixel circuit during the reset phase S301. In the reset phase S301, the signal SEL n-l is driven to a high level whilst the signal SEL n is driven to a low level. Since the signal SEL n is applied to the gate of the second transistor M2, the second transistor M2 is therefore in the OFF state in the reset phase S301. At the same time, since the signal SEL n-l is applied to the gate of the third transistor M3, the third transistor M3 is therefore in the ON state in the reset phase S301. Accordingly, charge can flow between the first and second capacitors Cl, C2 via the third transistor M3, and the capacitors Cl and C2 may share charge such that they store the same potential with respect to ground GND, during the reset phase S301.

[0203] Figure 43 illustrates a flow of current in the seventh pixel circuit during a first programming phase. In the first programming phase, the signal SEL n-l is kept at a high level whilst the signal SEL n is also driven to a high level. Since the signal SEL n is applied to the gate of the second transistor M2, the second transistor M2 is therefore in the ON state in the first programming phase. At the same time, since the signal SEL n-l is applied to the gate of the third transistor M3, the third transistor M3 is also in the ON state in the first programming phase. Therefore, during the first programming phase the first and second capacitors Cl, C2 are both connected to the same data signal input, to which a data signal DATA m is applied. In the case of the first capacitor Cl, the first capacitor Cl is connected to the data signal input via the third transistor M3 as well as the second transistor M2, as shown in Fig. 43. The data signal DATA m is set to a suitable value to charge (or discharge) the first capacitor Cl to the required voltage for operation of the first transistor Ml during the emission phase. Since the second capacitor C2 is also connected to the data signal input, the second capacitor is therefore also charged to the same voltage as the first capacitor Cl during the first programming phase (or to substantially the same voltage, disregarding minor variations due to the threshold voltage across the third transistor M3). Accordingly, the method of operation for the seventh pixel circuit then proceeds to a second programming phase to charge the second capacitor C2 to a desired voltage level.

[0204] Figure 44 illustrates a flow of current in the seventh pixel circuit during the second programming phase. In this phase, the signal SEL n remains at a high level such that the second transistor M2 remains in the ON state, and hence the second capacitor C2 remains connected to the data signal input in the second programming phase. However, in the second programming phase the signal SEL n-l is driven to a low level, switching the third transistor M3 OFF and therefore disconnecting the first capacitor Cl from the data signal input. In this state, the data signal DATA m is then set to an appropriate value to charge the second capacitor C2 to its desired voltage level. Meanwhile, the first capacitor Cl remains charged to the voltage that was set during the first programming phase, based on the previous value of the data signal DATA m (i.e. the value of DATA m during the first programming phase).

[0205] Figure 45 illustrates a flow of current in the seventh pixel circuit during the emission phase S304, in which the control signals SEL n and SEL n-l are both kept low such that the second and third transistors M2, M3 remain in the OFF state. In the emission phase S304, the first and second emission control components (if included in the circuit design) 4001, 4002 are both switched into the ON state (i.e. conducting), such that current is permitted to flow through the light emitting component DI from the voltage supply line VDD and GND via the first transistor Ml. Consequently, emission occurs because the light emitting component DI is in forward bias and the first transistor Ml is in saturation. This phase continues for the duration of the frame time.

[0206] Comparing the sixth and seventh pixel circuits, the sixth pixel circuit can therefore be understood as an example of a pixel circuit in which two capacitors Cl, C2 are independently charged at the same time by simultaneously providing each capacitor Cl, C2 with its own data signal, the value of which can be set independently from the other data signal. In that case, the ability to independently set the voltages of the first and second capacitors Cl, C2, and hence to independently control the switching and current characteristics of the first transistor Ml during the emission phase, is achieved via independent control of the respective data signals DATA1 m, DATA2 m.

[0207] In comparison, the seventh pixel circuit can be understood as an example of a pixel circuit in which the two capacitors Cl, C2 are programmed using the same data signal DATA m, but in which data signal DATA m can be applied independently to one capacitor without being applied to the other capacitor (i.e. in the second programming phase). In this way, the ability to independently set the voltages of the first and second capacitors Cl, C2, and hence to independently control the switching and current characteristics of the first transistor Ml during the emission phase, is achieved by applying different values of the data signal DATA m to the first and second capacitors Cl, C2 at different points in time.

[0208] Embodiments of the invention have been described in which a light emitting component is connected to the source or drain of a multiple-gate transistor, e.g. an MMT, such that, in use, a current flowing through the light emitting component is controlled by the current control gate of the first transistor, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the first transistor. In some embodiments, the multiple-gate transistor may comprise one or more auxiliary gates in addition to the current control gate and switching gate.

[0209] The one or more auxiliary gates may provide additional functionality, for example by allowing the threshold voltage (Vth) of one or both of the current control and switching gates to be adjusted. For example, an auxiliary gate can supplement the function of the current control gate by shifting the threshold voltage of the charge injection region (VthCGi) and an additional auxiliary gate can supplement the function of the switching gate (VthCG2) in the channel region by shifting its respective threshold voltage. Such additional auxiliary gates would supplement the function of a multimodal transistor so long as each individual auxiliary gate maintains the ability of the device to separately control charge injection and switching. Another example of supplementing transistor function would be an auxiliary gate disposed adjacent to the source region (e.g. laterally adjacent to the current control gate) can be used to screen the electric field of the drain from influencing the source region, further improving the contact- controlled operation of the device. As another example, an auxiliary gate at the drain can be used to mitigate unwanted charge carrier generation at the drain when the device is in the off-state (off-state leakage). Furthermore, embodiments of the invention have been described in which a pixel circuit comprises a number of transistors (e.g. Ml, M2, M3 etc.) that are individually switched on / off as required. It should be appreciated that in all of the above- described embodiments, any given transistor may in practice be implemented as a single device (e.g. a single TFT) or as a plurality of devices (e.g. two TFTs) connected in series.

[0210] Whilst certain embodiments of the invention have been described herein with reference to the drawings, it will be understood that many variations and modifications will be possible without departing from the scope of the invention as defined in the accompanying claims.

Claims

Claims1. A pixel circuit comprising: a first transistor comprising: a current control gate for controlling a magnitude of current supplied by a source region of the first transistor in dependence on a first voltage applied to the current control gate; and a switching gate for blocking or permitting a flow of current in a channel region of the first transistor in dependence on a second voltage applied to the switching gate; a light emitting component connected to the source or drain of the first transistor such that, in use, a current flowing through the light emitting component is controlled by the current control gate of the first transistor, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the first transistor; and a driving circuit configured to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component.

2. The pixel circuit according to claim 1, wherein the first transistor comprises: a source; a drain spaced apart from the source; a semiconductor region disposed between the source and the drain; and an insulating region disposed over the semiconductor region; wherein the current control gate is configured to control the magnitude of current flowing between the source and the drain through the semiconductor region in dependence on the first voltage applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region; and wherein the switching gate is configured to block or permit the flow of said current between the source and the drain through the semiconductor region in dependence on the second voltage applied to the switching gate.

3. The pixel circuit according to claim 1 or 2, wherein the driving circuit comprises: a first capacitor connected to the current control gate such that, in use, a voltage on the first capacitor can be applied to the current control gate as the first voltage; anda second capacitor connected to the switching gate such that, in use, a voltage on the second capacitor can be applied to the switching gate as the second voltage.

4. The pixel circuit according to claim 3, wherein the driving circuit further comprises: a second transistor connected between the second capacitor and a first reference voltage node such that, in use, when the second transistor is in an ON state said voltage on the second capacitor can be reset to a voltage at the first reference voltage node.

5. The pixel circuit according to claim 3 or 4, wherein the driving circuit further comprises: a third transistor connected between the current control gate and the switching gate such that, in use, when the third transistor is in an ON state a voltage at the current control gate is the same as a voltage at the switching gate.

6. The pixel circuit according to claim 5, wherein the third transistor is further connected in series with the second transistor.

7. The pixel circuit according to claim 5 or 6, wherein the driving circuit further comprises: a fourth transistor connected in series with the third transistor, the fourth transistor being further connected between a data signal input and the second capacitor.

8. The pixel circuit according to claim 7, wherein the source of the first transistor is connected to the data signal input via the source and the drain of the first transistor such that, in use, when the third and fourth transistors are both in the ON state the first and second capacitors can be charged to a voltage equal to VDATA + Vth, where VDATA is a voltage at the data signal input and Vth is a threshold voltage of the first transistor.

9. The pixel circuit according to claim 8, wherein the driving circuit further comprises: a fifth transistor connected between the source of the first transistor and the data signal input.

10. The pixel circuit according to claim 9, wherein respective gates of the fourth transistor and the fifth transistor are connected to a first control input for receiving a first control signal.

11. The pixel circuit according to claim 8, 9 or 10, wherein the driving circuit further comprises: a sixth transistor connected between the source of the first transistor and a ground plane such that, in use, the sixth transistor can be switched to an ON state to allow current to flow through the first transistor and the light emitting component, and can be switched to an OFF state to isolate the data signal input from the ground plane.

12. The pixel circuit according to any one of the preceding claims, wherein the driving circuit further comprises: a seventh transistor connected in series between the first transistor and the light emitting component such that, in use, when the seventh transistor is in an ON state current can flow through the first transistor and the light emitting component.

13. The pixel circuit according to claim 8, wherein the driving circuit further comprises: an eighth transistor connected between the first capacitor and a second reference voltage node such that, in use, when the eighth transistor is in an ON state the first capacitor can be charged to a voltage at the second reference voltage node.

14. The pixel circuit according to claim 13, wherein respective gates of the second transistor and the eighth transistor are connected to a second control input for receiving a second control signal, and respective gates of the third transistor and the fourth transistor are connected to a third control input for receiving a third control signal.

15. The pixel circuit according to claim 1 or 2, wherein the driving circuit comprises: a capacitor connected between the source of the first transistor and the current control gate; and a second transistor connected between the current control gate and a data signal input, wherein the switching gate and the drain of the first transistor are connected to a ground plane.

16. A display apparatus comprising: a plurality of pixel circuits, each comprising a pixel circuit according to any one of claims 1 to 15.

17. The display apparatus according to claim 16, further comprising: control circuitry configured to provide control signals to the plurality of pixel circuits to control the switching of one or more transistors within each pixel circuit.

18. A method of controlling a pixel circuit comprising a first transistor, the first transistor comprising a current control gate for controlling a magnitude of current supplied by a source region of the first transistor in dependence on a first voltage applied to the current control gate, and a switching gate for blocking or permitting a flow of current in a channel region of the first transistor in dependence on a second voltage applied to the switching gate, the pixel circuit further comprising a light emitting component connected to a source or drain of the first transistor such that, in use, a current flowing through the light emitting component is controlled by the current control gate of the first transistor, and is blocked or permitted to flow through the light emitting component under the control of the switching gate of the first transistor, and a driving circuit, the method comprising: during an emission phase, using the driving circuit to independently control said first and second voltages so as to independently control a magnitude of said current and a time at which said current flows through the light emitting component.

19. The method according to claim 18, wherein the driving circuit comprises a first capacitor connected to the current control gate and a second capacitor connected to the switching gate, wherein during the emission phase, a voltage on the first capacitor is applied to the current control gate as the first voltage, and a voltage on the second capacitor is applied to the switching gate as the second voltage.

20. The method according to claim 19, comprising: during a reset phase, setting the first capacitor to a first voltage level and setting the second capacitor to a second voltage level.

21. The method according to claim 20, wherein the driving circuit further comprises a second transistor connected between the second capacitor and a first reference voltage node such that, in use, when the second transistor is in an ON state said voltage on the second capacitor can be reset to a voltage at the first reference voltagenode, and wherein the driving circuit further comprises a third transistor connected between the current control gate and the switching gate such that, in use, when the third transistor is in an ON state a voltage at the current control gate is the same as a voltage at the switching gate, wherein setting the first capacitor to the first voltage level and setting the second capacitor to the second voltage level comprises: switching the second transistor and the third transistor to an ON state, so as to set the first and second voltage levels of the first capacitor and the second capacitor, respectively, to the voltage at the first reference voltage node.

22. The method according to claim 21, wherein during the reset phase the voltage at the first reference voltage node is held at a voltage level higher than a maximum level of the first or second voltages to be applied to the current control gate and the switching gate, respectively, during the emission phase.

23. The method according to claim 21 or 22, wherein the driving circuit further comprises a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to a data signal input, the method comprising: during a first stage of a programming phase, switching the third and fourth transistors to an ON state to connect both the first and second capacitors to the data signal input so as to set respective charge levels of the first and second capacitors in dependence on a voltage at the data signal input during said first stage, during a second stage of a programming phase, switching the third transistor to an OFF state while the fourth transistor is in the ON state, so as to further set the charge level of the second capacitor in dependence on a voltage at the data signal input during said second stage.

24. The method according to claim 23, wherein the driving circuit further comprises a fifth transistor connected between the source of the first transistor and the data signal input, and a sixth transistor connected between the source of the first transistor and a ground plane, wherein during the first and second stages of the programming phase, the fifth transistor is switched to an ON state to connect the fourth transistor to the data signal input via the source and drain of the first transistor, and the sixth transistor is switched to an OFF state to isolate the data signal input from the ground plane and wherein during the emission phase, the sixth transistor is switched to an ON state to allow current to flow through the first transistor and the light emitting component, and the fifth transistor is switched to an OFF state.

25. The method according to any one of claims 18 to 24, wherein the driving circuit further comprises a seventh transistor connected in series between the first transistor and the light emitting component, wherein during the emission phase, the seventh transistor is switched to an ON state such that current can flow through the first transistor and the light emitting component.

26. The method according to claim 20, wherein the driving circuit further comprises a second transistor connected between the second capacitor and a first reference voltage node such that, in use, when the second transistor is in an ON state said voltage on the second capacitor can be reset to a voltage at the first reference voltage node, and wherein the driving circuit further comprises an eighth transistor connected between the first capacitor and a second reference voltage node such that, in use, when the eighth transistor is in an ON state the first capacitor can be charged to a voltage at the second reference voltage node, wherein setting the first capacitor to the first voltage level and setting the second capacitor to the second voltage level comprises: switching the second transistor to an ON state, so as to set the second voltage level of the second capacitor to the voltage at the first reference voltage node; and switching the eighth transistor to an ON state, so as to set the first voltage level of the first capacitor to the voltage at the second reference voltage node.

27. The method according to claim 26, wherein the first reference voltage node comprises a ground plane, such that the voltage at the first reference voltage node is a ground voltage.

28. The method according to claim 26 or 27 , wherein the driving circuit further comprises a third transistor connected between the current control gate and the source control gate such that, in use, when the third transistor is in an ON state a voltage at the current control gate is the same as a voltage at the source control gate, and comprises a fourth transistor connected in series with the third transistor, the fourth transistor being configured to connect the second capacitor to a data signal input, the method comprising: during a programming phase, switching the third transistor and the fourth transistor to an ON state to connect both the first and second capacitors to the data signal input so as to set respective charge levels of the first and second capacitors in dependence on a voltage at the data signal input during said programming stage.

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