Wafer processing method and wafer processing system

Abstract

This wafer processing method comprises: a step for performing a plurality of processes on a wafer (We) in which a plurality of semiconductor chips (Ch) and a plurality of streets (St) are disposed; a step for performing a plurality of inspections on the plurality of processes; and a step for analyzing the results of the plurality of inspections in association with street portion identifiers (60) for identifying wafer portions defined by the plurality of streets.

Description

Wafer processing method and wafer processing system

[0001] The present invention relates to a wafer processing method and a wafer processing system.

[0002] 2. Description of the Related Art Conventionally, there has been known a wafer processing system that inspects wafer processing. Such a wafer processing system is disclosed, for example, in Japanese Patent Laid-Open Publication No. 2023-18740.

[0003] The above-mentioned Japanese Patent Application Laid-Open No. 2023-18740 discloses a wafer processing system for inspecting wafer processing. This wafer processing system includes a processing device that performs cutting processing along the parting lines (streets) of the wafer, and an inspection device that inspects the wafer after cutting processing. The inspection device inspects the shape, size, distribution, etc. of chips that occur on the wafer due to the cutting processing. This allows the quality of the cutting processing to be evaluated.

[0004] JP 2023-18740 A

[0005] Although not explicitly stated in the above-mentioned Japanese Patent Application Laid-Open No. 2023-18740, a wafer is typically subjected to multiple processes, such as cutting along parting lines (streets), in sequence. Furthermore, the impact on the quality of the processes may extend to downstream processes. Therefore, as in the conventional wafer processing system described in the above-mentioned Japanese Patent Application Laid-Open No. 2023-18740, even if an abnormality is detected in a certain process, the cause of the abnormality may be present in a process upstream of the certain process. Therefore, a wafer processing method and a wafer processing system that can easily grasp the influence between multiple processes are desired.

[0006] The present invention has been made to solve the above-mentioned problems, and one object of the present invention is to provide a wafer processing method and a wafer processing system that make it possible to easily grasp the influence between multiple processes.

[0007] A wafer processing method according to a first aspect of the present invention includes a step of performing a plurality of processes on a wafer having a plurality of semiconductor chips and a plurality of streets arranged thereon, a step of performing a plurality of inspections for the plurality of processes, and a step of analyzing the results of the plurality of inspections by linking the results to street portion identifiers for identifying portions of the wafer defined by the plurality of streets.

[0008] As described above, the wafer processing method according to the first aspect of the present invention includes a step of analyzing the results of multiple inspections by linking them to street site identifiers for identifying wafer sites defined by multiple streets. This allows the results of multiple inspections resulting from multiple processes to be analyzed by linking them to the street site identifiers, making it possible to easily understand the influence between the multiple processes. Furthermore, by linking the results of multiple inspections to the street site identifiers, the results of the inspections can be easily compared. As a result, the results of the multiple inspections can be easily analyzed.

[0009] In the wafer processing method according to the first aspect, the step of analyzing the results of the plurality of inspections preferably includes the step of determining, for each street portion identifier, whether the inspection result is a failure or a pass (not a failure). With this configuration, it is possible to easily determine whether the inspection result is a failure or a pass, and therefore, if the inspection result is a failure, it is possible to quickly implement countermeasures.

[0010] In this case, the step of analyzing the results of the multiple inspections preferably includes a step of determining, for each street portion identifier, whether the inspection result is a failure, a warning (not a failure but close to a failure), or a pass. With this configuration, warnings can be used to identify signs of a failure, allowing for prompt implementation of countermeasures at the stage when the signs of a failure are identified. As a result, the occurrence of defects can be suppressed.

[0011] In the configuration for determining whether the test results are "fail," "warning," or "pass," the step of analyzing the test results preferably includes a step of estimating the cause of the warning or failure based on a correlation coefficient between the test results. With this configuration, the cause of the warning or failure can be accurately estimated, and appropriate countermeasures can be implemented based on the estimated cause.

[0012] In this case, the step of analyzing the results of the multiple tests preferably includes a step of estimating the cause of the warning or failure based on a correlation coefficient between the result of a first test that has been determined to be a warning or failure and the result of a second test that is theoretically correlated with the first test. With this configuration, the cause of the warning or failure can be estimated more accurately, and countermeasures can be more appropriately implemented based on the estimated cause.

[0013] The above-described configuration for estimating the cause of a warning or failure preferably includes a step of confirming the effectiveness of the countermeasure based on a change in the correlation coefficient before and after the countermeasure for the estimated cause of the warning or failure is taken. This configuration allows the effectiveness of the countermeasure to be confirmed, making it possible to determine whether the cause has been corrected. Furthermore, if the countermeasure is not effective, other causes can be investigated or other countermeasures can be taken.

[0014] In this case, the step of confirming the effectiveness of the countermeasure preferably includes a step of determining whether or not there is a cause of the warning or failure other than the estimated cause of the warning or failure, based on a change in the correlation coefficient before and after the countermeasure is taken for the estimated cause of the warning or failure. With this configuration, if there is a cause of the other warning or failure, it is possible to quickly implement a countermeasure for the cause of the other warning or failure.

[0015] In the wafer processing method according to the first aspect, the plurality of processes preferably include at least one of a stress relief process for removing processing distortion by polishing the wafer, a grooving process, a dicing process, and an expanding process. With this configuration, when at least one of the stress relief process, the grooving process, the dicing process, and the expanding process is performed, the results of the plurality of tests can be easily analyzed.

[0016] In the wafer processing method according to the first aspect, the step of analyzing the results of the multiple inspections preferably includes a step of determining, for each street portion identifier, that an inspection value resulting from the current inspection exceeds the inspection value resulting from the previous inspection by a predetermined value or more, indicating that the inspection is not a failure but is a warning indicating a near-failure. With this configuration, if a sign of a failure is observed because the inspection value resulting from the current inspection exceeds the inspection value resulting from the previous inspection by a predetermined value or more, the sign of a failure can be identified by issuing a warning. As a result, countermeasures can be implemented promptly at the stage when a sign of a failure is identified, thereby effectively suppressing the occurrence of a failure.

[0017] In the configuration for determining whether the test result is a fail, warning, or pass, the step of analyzing the results of the multiple tests preferably includes a step of estimating the cause of the warning or fail based on the layout state of the warning or fail street site identifier. With this configuration, the layout state (pattern) of the warning or fail street site identifier differs depending on the cause of the warning or fail, so the cause of the warning or fail can be accurately estimated.

[0018] In this case, the layout state of the warning or failure street site identifier preferably includes at least one of a dotted shape, a lined shape, an area shape, and the entire wafer. With this configuration, the layout state (pattern) of the warning or failure street site identifier will be at least one of a dotted shape, a lined shape, an area shape, and the entire wafer depending on the cause of the warning or failure, so that the cause of the warning or failure can be more accurately estimated.

[0019] In the configuration for determining whether the test result is a failure, a warning, or a pass, the step of analyzing the results of the multiple tests preferably includes a step of estimating the cause of the warning or failure based on whether the warning or failure occurs suddenly or continuously. With this configuration, the cause of the warning or failure differs depending on whether the warning or failure occurs suddenly or continuously, so the cause of the warning or failure can be accurately estimated.

[0020] A wafer processing system according to a second aspect of the present invention includes a plurality of wafer processing devices that perform a plurality of processes on a wafer having a plurality of semiconductor chips and a plurality of streets arranged thereon; a plurality of wafer inspection devices that perform a plurality of inspections for the plurality of processes; and an analysis device that analyzes the results of the plurality of inspections by linking them to street portion identifiers that identify portions of the wafer defined by the plurality of streets.

[0021] In a wafer processing system according to a second aspect of the present invention, as described above, an analysis device is provided that analyzes the results of multiple inspections by linking them to street site identifiers that identify wafer sites defined by multiple streets. This allows the results of multiple inspections resulting from multiple processes to be analyzed by linking them to the street site identifiers, thereby providing a wafer processing system that can easily grasp the influence between multiple processes. Furthermore, by linking the results of multiple inspections to the street site identifiers, the results of the inspections can be easily compared. As a result, the results of the multiple inspections can be easily analyzed.

[0022] According to the present invention, as described above, the influence between a plurality of processes can be easily grasped.

[0023] FIG. 1 is a block diagram showing a wafer processing system according to an embodiment. FIG. 2 is a plan view showing a stress relief processing apparatus according to an embodiment. FIG. 3 is a plan view showing a dicing processing apparatus according to an embodiment. FIG. 4 is a plan view showing an expanding processing apparatus according to an embodiment. FIG. 5 is a flowchart for explaining a wafer processing method according to an embodiment. FIG. 6 is a diagram for explaining street site identifiers according to an embodiment. FIG. 7 is a diagram for explaining results of an inspection for stress relief processing according to an embodiment. FIG. 8 is a diagram for explaining (1) results of an inspection for grooving processing according to an embodiment. FIG. 9 is a diagram for explaining (2) results of an inspection for grooving processing according to an embodiment. FIG. 10 is a diagram for explaining results of an inspection for dicing processing according to an embodiment. FIG. 11 is a diagram for explaining results of an inspection for dicing processing according to an embodiment. FIG. 12 is a diagram for explaining results of an inspection for dicing processing according to an embodiment. FIG. 13 is a diagram for explaining results of an inspection for dicing processing according to an embodiment. FIG. 14 is a diagram for explaining results of an inspection for dicing processing according to an embodiment. FIG. 15 is a diagram for explaining results of an inspection for warning or fail street site identifiers according to an embodiment. FIG. 16 is a diagram for explaining the relationship between the arrangement of warning or fail street site identifiers and the cause of a failure according to an embodiment. FIG. 17 is a diagram for explaining theoretically correlated inspection results according to an embodiment. FIG. 1 is a diagram (1) for explaining an example of estimating the cause of a warning or failure according to an embodiment; FIG. 2 is a diagram (2) for explaining an example of estimating the cause of a warning or failure according to an embodiment; FIG. 3 is a diagram (3) for explaining an example of estimating the cause of a warning or failure according to an embodiment; FIG. 1 is a diagram (1) for explaining a change in correlation coefficient after taking measures according to an embodiment; FIG. 2 is a diagram (2) for explaining a change in correlation coefficient after taking measures according to an embodiment.

[0024] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

[0025] The configuration of a wafer processing system 100 according to one embodiment of the present invention will be described with reference to FIGS.

[0026] 1, the wafer processing system 100 includes a stress relief processing device 10, a grooving processing device 20, a dicing processing device 30, an expanding processing device 40, and an analyzing device 50. The stress relief processing device 10, the grooving processing device 20, the dicing processing device 30, and the expanding processing device 40 process the wafer We in this order. The stress relief processing device 10, the grooving processing device 20, the dicing processing device 30, and the expanding processing device 40 are all examples of the "wafer processing device" defined in the claims.

[0027] 2, the stress relief processing apparatus 10 is a grinding and stress relief processing apparatus. The stress relief processing apparatus 10 performs grinding on the wafer We to adjust the thickness of the wafer We, and stress relief processing, polishing the wafer We to remove processing strain. The stress relief processing apparatus 10 includes cassette mounting units 11a and 11b, a transfer robot 12, multiple wafer holding units 13, multiple grinding units 14, a finish polishing unit 15, a plasma processing unit 16, and a turntable 17.

[0028] A cassette containing a plurality of unprocessed wafers We is placed on the cassette placement section 11a. A cassette containing processed wafers We is placed on the cassette placement section 11b. A protective tape Tb is attached to the circuit surface of the wafer We. The transfer robot 12 removes the unprocessed wafer We from the cassette placed on the cassette placement section 11a and transfers it to the wafer holding section 13 closest to the cassette placement section 11a among the plurality of wafer holding sections 13. The transfer robot 12 also transfers the processed wafer We placed on the wafer holding section 13 closest to the cassette placement section 11b among the plurality of wafer holding sections 13 to the cassette placed on the cassette placement section 11b.

[0029] The plurality of wafer holders 13 hold the wafer We by suction. The plurality of grinding units 14 grind the back surface of the wafer We opposite the circuit surface in stages. The plurality of grinding units 14 include a rough grinding unit 14a, a finish grinding unit 14b, and a fine grinding unit 14c. The rough grinding unit 14a grinds the back surface of the wafer We with a first abrasive having a first particle diameter. The finish grinding unit 14b grinds the back surface of the wafer We with a second abrasive having a second particle diameter smaller than the first particle diameter. The fine grinding unit 14c grinds the back surface of the wafer We with a third abrasive having a third particle diameter smaller than the second particle diameter.

[0030] The finish polishing unit 15 polishes the backside of the wafer We that has been ground by the plurality of grinding units 14. The plasma processing unit 16 performs plasma processing on the backside of the wafer We that has been polished by the finish polishing unit 15. The transfer robot 12 transfers the wafer We between the plasma processing unit 16 and the wafer holding unit 13. The turntable 18 rotates and moves each of the plurality of wafer holding units 13 to positions corresponding to the cassette mounting unit 11a, the cassette mounting unit 11b, the plurality of grinding units 14, the finish polishing unit 15, and the plasma processing unit 16, respectively.

[0031] 3, the grooving processing apparatus 20 performs grooving processing on the wafer We processed by the stress relief processing apparatus 10 to divide the insulating film provided on the wafer We. The grooving processing apparatus 20 includes a wafer storage unit 21, a wafer transport unit 22, a plurality of wafer transfer units 23, a wafer coating unit 24, a wafer holding unit 25, a laser irradiation unit 26, and a wafer cleaning unit 27.

[0032] The wafer storage section 21 houses cassettes each containing a plurality of wafers We. Expandable tape Te is attached to the back surface of each wafer We. A ring frame Rf is attached to the expandable tape Te together with the wafer We. Before the wafer We processed by the stress relief processing device 10 is transported into the grooving processing device 20, the protective tape Tb is replaced with the expandable tape Te in a tape replacement device.

[0033] The wafer transport unit 22 takes out wafers We from cassettes stored in the wafer storage unit 21 and transports them on the transport rails 22a. The plurality of wafer transfer units 23 transfer the wafers We on the transport rails 22a. The plurality of wafer transfer units 23 includes wafer transfer units 23a, 23b, and 23c. The wafer transfer unit 23a transfers the wafers We between the transport rails 22a and the wafer holder 25. The wafer transfer unit 23b transfers the wafers We between the transport rails 22a and the wafer coating unit 24. The wafer transfer unit 23c transfers the wafers We between the transport rails 22a and the wafer cleaning unit 27.

[0034] The wafer coating unit 24 coats the circuit surface of the wafer We before laser irradiation by the laser irradiation unit 26. The wafer coating unit 24 supplies a protective film liquid to protect the circuit surface of the wafer We, forming a protective film. The wafer coating unit 24 is provided with an inspection unit 24a that inspects the stress relief processing (processing for polishing the wafer We) performed by the stress relief processing apparatus 10. The inspection unit 24a includes a height measurement unit such as a laser displacement meter, and inspects the height of the wafer We by measuring the height of the wafer We. Analysis of the inspection results will be described later. The inspection unit 24a is an example of a "wafer inspection device" in the claims.

[0035] The wafer holding unit 25 holds the wafer We when the laser irradiation unit 26 irradiates the wafer We with a laser. The wafer holding unit 25 is movable horizontally and rotatable around a vertical axis of rotation. The laser irradiation unit 26 irradiates the wafer We held by the wafer holding unit 25 with a laser to divide the insulating film formed on the wafer We. The wafer cleaning unit 27 cleans the circuit surface of the wafer We after the laser irradiation by the laser irradiation unit 26. The wafer cleaning unit 27 supplies a cleaning liquid for cleaning the circuit surface of the wafer We to clean the circuit surface of the wafer We. The wafer cleaning unit 27 is provided with an inspection unit 27a that inspects the grooving process (processing for dividing the insulating film) performed by the grooving processing device 20. The inspection unit 27a includes a camera with an image sensor and inspects the wafer We for processing marks caused by the grooving process by capturing an image of the wafer We. Analysis of the inspection results will be described later. The inspection unit 27a is an example of a "wafer inspection device" in the claims.

[0036] 4, the dicing device 30 performs dicing on the wafer We processed by the grooving device 20 to form a modified layer inside the wafer We along the streets St (see FIG. 7). The dicing device 30 includes a wafer storage unit 31, a wafer transport unit 32, a wafer transfer unit 33, a wafer holder 34, and a laser irradiation unit 35.

[0037] A cassette containing a plurality of wafers We is housed in the wafer storage section 31. Expandable tape Te is attached to the back surface of the wafer We. A ring frame Rf is attached to the expandable tape Te together with the wafer We.

[0038] The wafer transport unit 32 removes a wafer We from a cassette stored in the wafer storage unit 31 and transports it on the transport rails 32a. The wafer transfer unit 33 transfers the wafer We on the transport rails 32a. The wafer transfer unit 33 transfers the wafer We between the transport rails 32a and the wafer holding unit 34. The wafer holding unit 34 holds the wafer We when the laser irradiation unit 35 irradiates the wafer We with laser light. The wafer holding unit 34 is movable horizontally and rotatable about an axis of rotation in the vertical direction. The laser irradiation unit 35 irradiates the wafer We held by the wafer holding unit 34 with laser light to form a modified layer inside the wafer We for dividing the wafer We. An inspection unit 35a is provided near the laser irradiation unit 35 to inspect the dicing process (process for forming a modified layer) performed by the dicing device 30. The inspection unit 35a includes a camera with an image sensor, and inspects the modified layer caused by the dicing process of the wafer We by capturing an image of the wafer We. Analysis of the inspection results will be described later. The inspection unit 35a is an example of a "wafer inspection device" in the claims.

[0039] 5 , the expanding processing device 40 performs an expanding process in which the wafer We processed by the dicing processing device 30 is divided by expanding the expanding tape Te. The expanding processing device 40 includes a wafer storage unit 41, a wafer removal unit 42, a wafer transfer unit 43, a wafer holding unit 44, a tape cooling unit 45, an expanding unit 46, and a wafer cleaning unit 47.

[0040] A cassette containing a plurality of wafers We is housed in the wafer storage section 41. Expandable tape Te is attached to the back surface of the wafer We. A ring frame Rf is attached to the expandable tape Te together with the wafer We.

[0041] The wafer unloading unit 42 unloads the wafer We from the cassette stored in the wafer storage unit 31. The wafer transfer unit 43 transfers the wafer We before being expanded by the expanding unit 46 from the wafer unloading unit 42 to the wafer holding unit 44. The wafer transfer unit 43 transfers the wafer We after being expanded by the expanding unit 46 from the wafer holding unit 44 to the wafer cleaning unit 47. The wafer transfer unit 43 transfers the wafer We after being cleaned by the wafer cleaning unit 47 from the wafer cleaning unit 47 to the wafer unloading unit 42.

[0042] The wafer holding unit 44 holds the wafer We via the ring frame Rf when cooling is performed by the tape cooling unit 45 and when expanding is performed by the expanding unit 46. The wafer holding unit 44 is movable in the horizontal direction. The tape cooling unit 45 cools the expanding tape Te of the wafer We held by the wafer holding unit 44 from above and below before expanding is performed by the expanding unit 46. After cooling is performed by the tape cooling unit 45, the expanding unit 46 expands the expanding tape Te of the wafer We held by the wafer holding unit 44 and divides the wafer We. When expanding the expanding tape Te by the expanding unit 46, heat shrinking of the expanding tape Te is performed by heating by the heat shrink unit.

[0043] The wafer cleaning unit 47 cleans the wafer We after the expanding unit 46 has performed the expanding. The wafer cleaning unit 47 supplies a cleaning liquid for cleaning the wafer We to clean the wafer We. The wafer cleaning unit 47 is provided with an inspection unit 47a that inspects the expanding process (the process of dividing the wafer We) performed by the expanding processing device 40. The inspection unit 47a includes a camera with an image sensor, and inspects the division portions of the wafer We caused by the expanding process by capturing an image of the wafer We. Analysis of the inspection results will be described later. The inspection unit 47a is an example of a "wafer inspection device" in the claims.

[0044] As shown in FIG. 1 , the analysis device 50 analyzes the results of multiple inspections performed on multiple processes. The analysis device 50 is configured, for example, by a personal computer. The analysis device 50 includes a control unit 51. The control unit 51 includes a central processing unit (CPU) and a storage unit having a read-only memory (ROM), a random access memory (RAM), an SSD (solid state drive), etc. The storage unit stores an analysis program for analyzing the results of multiple inspections performed on multiple processes.

[0045] (Wafer Processing Method) With reference to FIG. 6, a wafer processing method using the wafer processing system 100 of this embodiment will be described based on a flowchart.

[0046] In step S1, a plurality of wafer processing devices (stress relief processing device 10, grooving processing device 20, dicing processing device 30, and expanding processing device 40) perform a plurality of processes on a wafer We on which a plurality of semiconductor chips Ch and a plurality of streets St are arranged. Furthermore, a plurality of wafer inspection devices (inspection units 24a, 27a, 35a, and 47a) perform a plurality of inspections on the plurality of processes. Then, in step S2, a control unit 51 of analysis device 50 analyzes the results of the plurality of inspections.

[0047] 7, the control unit 51 of the analysis device 50 analyzes the results of multiple inspections by linking the results to street site identifiers 60 for identifying sites on the wafer We defined by multiple streets St. In the example shown in FIG. 7, there is a semiconductor chip Ch indicated by U** that is separated by seven vertical and seven horizontal streets St, and street site identifiers 60 are assigned to each site on the streets St indicated by R** and C**. R** and C** indicate sites on the streets St adjacent to the semiconductor chip Ch and indicate the street site identifiers 60 of those sites.

[0048] For stress relief processing, the inspection unit 24a measures the height of each position on the wafer We. The height measurement results are grouped into R** and C**. That is, the inspection results by the inspection unit 24a are linked to the street site identifier 60. Depending on the height measurement method, only one height measurement result or multiple height measurement results may be linked to one street site identifier 60. Height measurement results that cannot be grouped into R** and C** are discarded. Height measurement results that deviate by more than a predetermined percentage (e.g., 5% or more) from the average value are discarded as noise. As shown in FIG. 8 , the average height measurement results Ha and the difference Hr between the maximum and minimum height measurement results are obtained for each R** and C**. That is, the inspection results by the inspection unit 24a include the results Ha and Hr.

[0049] For grooving, the inspection unit 27a captures images of the processing marks along each street St on the wafer We. Based on the results of capturing the processing marks, the widths of the processing marks and the horizontal positional deviations of the processing marks are acquired. The widths of the processing marks and the horizontal positional deviations of the processing marks are grouped into R** and C**. That is, the inspection results by the inspection unit 27a are linked to the street site identifier 60. Depending on the imaging method, only one processing mark width (horizontal positional deviation of the processing mark) may be linked to one street site identifier 60, or multiple processing mark widths (horizontal positional deviations of the processing mark) may be linked to one street site identifier 60. Furthermore, as shown in FIG. 9 , the average processing mark width Wa and the difference Wr between the maximum and minimum processing mark widths are acquired for each R** and C**. That is, the inspection results by the inspection unit 27a include the results Wa and Wr. 10, the average value Pa of the horizontal positional deviation of the processing marks and the difference Pr between the maximum and minimum values ​​of the horizontal positional deviation of the processing marks are acquired for each R** and C**. That is, the result of the inspection by the inspection unit 27a includes the results Pa and Pr.

[0050] During the dicing process, the inspection unit 35a captures images of the modified layer at each position of each street St created by the dicing process of the wafer We. Based on the results of capturing the modified layer images, the inspection unit 35a acquires a first distance between the expanding tape Te and the modified layer closest to the expanding tape Te, a second distance between the surface of the wafer We opposite the expanding tape Te and the modified layer closest to this surface, and the horizontal positional deviation of the modified layer. The first distance, the second distance, and the horizontal positional deviation of the modified layer are grouped into R** and C**. That is, the inspection results by the inspection unit 35a are linked to the street site identifier 60. Depending on the imaging method, only one first distance (second distance, horizontal positional deviation of the modified layer) may be linked to one street site identifier 60, or multiple first distances (second distance, horizontal positional deviation of the modified layer) may be linked to one street site identifier 60. 11, the inspection unit 35a acquires the average value Ta of the first distance and the difference Tr between the maximum and minimum values ​​of the first distance for each of R** and C**. That is, the inspection results by the inspection unit 35a include the results Ta and Tr. As shown in FIG. 12, the inspection unit 35a acquires the average value Oa of the second distance and the difference Or between the maximum and minimum values ​​of the second distance for each of R** and C**. That is, the inspection results by the inspection unit 35a include the results Oa and Or. As shown in FIG. 13, the inspection unit 35a acquires the average value Sa of the horizontal positional deviation of the modified layer and the difference Sr between the maximum and minimum values ​​of the horizontal positional deviation of the modified layer for each of R** and C**. That is, the inspection results by the inspection unit 35a include the results Sa and Sr.

[0051] During the expanding process, the inspection unit 47a captures images of the divisions (i.e., the edge portions of the semiconductor chips Ch) at each position of each street St due to the expanding process of the wafer We. Based on the image capture results of the divisions, the size Ra of the gap between the edges of adjacent semiconductor chips Ch, the length Rs of one edge of the semiconductor chips Ch, and the magnitude Rr of the meandering of one edge of the semiconductor chips Ch are acquired. The size Ra of the gap, the length Rs of one edge, and the magnitude Rr of the meandering are grouped into R** and C**. That is, the results of the inspection by the inspection unit 35a are linked to the street portion identifier 60. The results of the inspection by the inspection unit 47a include the results Ra, Rs, and Rr.

[0052] In this embodiment, as shown in FIGS. 8 to 13 , the control unit 51 of the analysis apparatus 50 determines whether the inspection result is a failure or a pass (not a failure) for each street site identifier 60. Specifically, the control unit 51 of the analysis apparatus 50 determines whether the inspection result is a failure, a warning (not a failure but close to a failure), or a pass (not a failure) for each street site identifier 60. The control unit 51 of the analysis apparatus 50 compares the current inspection result with a threshold value for each street site identifier 60 to determine whether the current inspection result is a failure, a warning, or a pass (not a failure, not a failure, but close to a failure). The control unit 51 of the analysis apparatus 50 also compares the current inspection result with the results of previous inspections for each street site identifier 60 to determine whether the current inspection result is a warning. For each street site identifier 60, the control unit 51 of the analysis apparatus 50 determines a warning when the inspection value of the current inspection result exceeds the inspection value of the previous inspection result by a predetermined value or more. The inspection value of the previous inspection result is, for example, an average value of the results of previous inspections for wafers We in the same lot.

[0053] The control unit 51 of the analytical device 50 determines that a warning has been issued if the test value Ha of the current test result falls outside the warning limit range defined by an upper threshold and a lower threshold. The control unit 51 of the analytical device 50 also determines that a failure has been issued if the test value Ha of the current test result falls outside the failure limit range defined by an upper threshold that is higher than the upper threshold of the warning limit and a lower threshold that is lower than the lower threshold of the warning limit. The same applies to the test results Wa, Pa, Ta, Oa, Sa, Ra, Rs, and Rr.

[0054] The control unit 51 of the analytical device 50 also acquires the deviation value between the test value Ha of the current test result and the test value Ha of the test results up to the previous test, and determines that a warning has been issued if the absolute value of the acquired deviation value is equal to or greater than the deviation warning limit threshold. The control unit 51 of the analytical device 50 also acquires the deviation value between the test value Hr of the current test result and the test value Hr of the test results up to the previous test, and determines that a warning has been issued if the absolute value of the acquired deviation value is equal to or greater than the deviation warning limit threshold. The control unit 51 of the analytical device 50 also acquires the deviation value between the test value Hr of the current test result and the test value Hr of the test results up to the previous test, and determines that a warning has been issued if the absolute value of the deviation value Hr of the current test result is less than the deviation warning limit threshold and the test value Hr of the current test result is within the warning limit. The same applies to the inspection results for Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, Sr, Ra, Rs, and Rr.

[0055] In Figure 14, parts 71, 72, 73, and 74 of the street part identifier 60 that have been determined to be warnings or failures are shown with different hatching. Part 71 is a part where warnings or failures occur in a dotted pattern. Part 72 is a part where warnings or failures occur in a line pattern. Part 73 is a part where multiple warnings or failures occur in a line pattern and in parallel. Part 74 is a part where warnings or failures occur in an area pattern.

[0056] When warnings or failures occur in a dotted pattern, as in portion 71, it is highly likely that the warnings or failures are caused by dot-like foreign matter being mixed into the wafer holder of each processing device. When warnings or failures occur in a line, as in portion 72, it is highly likely that the warnings or failures are caused by the grooving and dicing processes, which are performed line by line. When warnings or failures occur in a line and in parallel, as in portion 73, it is highly likely that the warnings or failures are caused by a difference in the longitudinal and lateral tension of the expanding tape Te. When warnings or failures occur in an area, as in portion 74, it is highly likely that the warnings or failures are caused by the stress relief process, which is performed area by area. As such, the arrangement (pattern) of the warning or failure street site identifiers 60 varies depending on the cause of the warning or failure. Therefore, it is possible to estimate the cause of the warning or failure from the arrangement of the warning or failure street site identifiers 60. Note that the arrangement of the warning or failure street site identifiers 60 shown in FIG. 14 is merely an example. Although not shown in FIG. 14, a warning or defect may occur over the entire wafer We, in addition to the spot, line, and area-like defects.

[0057] 15 , the control unit 51 of the analysis device 50 estimates the cause of the warning or failure based on the arrangement state of the warning or failure street site identifier 60. The arrangement state of the warning or failure street site identifier 60 includes dot-like, line-like, area-like, and the entire wafer We. That is, the control unit 51 of the analysis device 50 determines whether the arrangement state of the warning or failure street site identifier 60 is dot-like, line-like, area-like, or the entire wafer We. Then, the control unit 51 of the analysis device 50 estimates the cause of the warning or failure based on the determined arrangement state of the warning or failure street site identifier 60.

[0058] The cause of the warning or failure also differs depending on whether the warning or failure occurs suddenly or continuously. Therefore, the control unit 51 of the analyzer 50 estimates the cause of the warning or failure based on whether the warning or failure occurs suddenly or continuously. A warning or failure occurring suddenly means that the warning or failure is not continuing. In other words, it means that a warning or failure has occurred in a location that was not marked with a warning or failure in the results of the previous test. Furthermore, a warning or failure occurring continuously means that the warning or failure has continued to occur. In other words, it means that a warning or failure has continued to occur in the same location in the results of multiple consecutive tests, including the results of the current test.

[0059] In FIG. 15 , "contamination" refers to the following: In other words, "contamination" in stress relief processing means that a warning or failure is caused by foreign matter being present between the wafer holder 13 and the wafer We. "contamination" in grooving processing means that a warning or failure is caused by foreign matter being present between the wafer holder 25 and the wafer We. "contamination" in dicing processing means that a warning or failure is caused by foreign matter being present between the wafer holder 34 and the wafer We. "contamination" in expanding processing means that a warning or failure is caused by foreign matter being sandwiched between the expanding tape Te and the wafer We.

[0060] "Adhered matter" means that "contamination" adhering to the wafer holding table during each process is the cause of a warning or failure. "Mark detection" means that foreign matter or coating on the alignment mark of the wafer We interferes with image processing for detecting the alignment mark, causing a warning or failure.

[0061] Furthermore, "insufficient warm-up air" refers to the following: In stress relief processing, "insufficient warm-up air" means that the finish polishing section 15 was in the middle of its temperature transient characteristic, which caused the warning or failure. In grooving processing, "insufficient warm-up air" means that the laser irradiation section 26 was in the middle of its temperature transient characteristic, which caused the warning or failure. In dicing processing, "insufficient warm-up air" means that the laser irradiation section 35 was in the middle of its temperature transient characteristic, which caused the warning or failure. In expanding processing, "insufficient warm-up air" means that the tape cooling section 45 was in the middle of its temperature transient characteristic, which caused the warning or failure.

[0062] Furthermore, "tape mount" refers to a state in which there is a large difference in tension between the vertical and horizontal directions of the expanding tape Te attached to the ring frame Rf, which causes a warning or failure. Furthermore, "top surface contamination" refers to a state in which contamination on the top surface of the wafer We interferes with the control of moving the laser irradiation unit 35 up and down to follow the top surface of the wafer We during dicing, which causes a warning or failure. Furthermore, "illumination degradation" refers to a state in which degradation of the light source interferes with image processing to detect alignment marks on the wafer We, which causes a warning or failure.

[0063] "Pad wear" means that the pad of the finish polishing unit 15 has worn out, making it impossible to uniformly polish the wafer We to the expected thickness, which is the cause of a warning or failure. "Processing speed" means that the horizontal movement speed of the wafer We is reduced because it becomes difficult to control the vertical movement of the laser irradiation unit 35 to follow the top surface of the wafer We during dicing due to the unevenness of the top surface of the wafer We exceeding its limit, which is the cause of a warning or failure. "Temperature NG" means that the warning or failure is caused by insufficient cooling of the expanding tape Te by the tape cooling unit 45 during the expanding process, or by insufficient heating of the expanding tape Te by the heat shrink unit during the expanding process.

[0064] The control unit 51 of the analysis device 50 estimates the cause of the warning or failure from relationship information 81 as shown in FIG. 15 based on the determination result of whether the warning or failure occurs suddenly or continuously and the determination result of the arrangement state of the warning or failure street site identifier 60. The relationship information 81 indicates the relationship between whether the warning or failure occurs suddenly or continuously, the arrangement state of the warning or failure street site identifier 60, and the cause of the warning or failure. The relationship information 81 is created in advance and stored in the storage unit of the analysis device 50.

[0065] Here, when an inspection result is a warning or failure, the warning or failure may be due to the processing corresponding to that inspection. However, because the impact on processing quality extends to downstream processing, the warning or failure may be due to processing upstream of the processing corresponding to that inspection. Figure 16 shows inspection results that are theoretically correlated. The term "theoretical correlation" does not necessarily mean that a warning or failure inspection result necessarily means that there is a correlation, but rather that there is a possibility of a correlation. For example, inspection result Ra is theoretically correlated with inspection results Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, and Sr. When inspection result Ra is a warning or failure, if a correlation is found between inspection results Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, and Sr, the warning or failure may not be due to the expanding processing corresponding to inspection result Ra, but may be due to the processing corresponding to the correlated inspection result.

[0066] For this reason, the control unit 51 of the analysis apparatus 50 infers the cause of a warning or failure based on a correlation coefficient between the results of multiple tests. Specifically, the control unit 51 of the analysis apparatus 50 infers the cause of a warning or failure based on a correlation coefficient between the result of a first test determined to be a warning or failure and the result of a second test that is theoretically correlated with the first test. Based on the result of the first test determined to be a warning or failure, the control unit 51 of the analysis apparatus 50 identifies the result of a second test that is theoretically correlated with the first test from correlation information 82 such as that shown in FIG. 16 . Then, the control unit 51 of the analysis apparatus 50 obtains a correlation coefficient between the result of the first test and the identified second test. Then, the control unit 51 of the analysis apparatus 50 infers the cause of a warning or failure based on the obtained correlation coefficient. Note that the correlation information 82 indicates whether or not there is a theoretical correlation between the results of multiple tests. The correlation information 82 is created in advance and stored in the memory unit of the analysis apparatus 50.

[0067] An example of how to estimate the cause of a warning or a failure will be described with reference to Figures 17 to 19. The cause is estimated by the control unit 51 of the analyzer 50.

[0068] 17 , assume that test result Ra is determined to be a warning because the test value falls outside the warning limit range. In this case, based on correlation information 82, it is determined whether there is any test result that has a theoretical correlation with test result Ra. Then, since there is a test result that has a theoretical correlation with test result Ra, test results Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, and Sr are identified from correlation information 82 as test results that have a theoretical correlation with test result Ra. Then, correlation coefficients between test result Ra and each of test results Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, and Sr are obtained. The correlation coefficients are calculated, for example, using the following equation (1): where γ is the correlation coefficient S ｘｙ : Covariance of x and y S ｘ : Standard deviation of x S ｙ : Standard deviation of y n: Total number of two-variable data (x, y) x ｉ , y ｉ: Individual numerical values ​​￣x (x with overbar), ￣y (y with overbar): Average value of x and y.

[0069] In formula (1), "x" and "y" indicate the test results for which a correlation coefficient is obtained. For example, when a correlation coefficient between test result Ra and test result Wa is obtained, "x" indicates test result Ra, and "y" indicates test result Wa. The number of samples of "x" and "y" is the test results of all street site identifiers 60. That is, the number of samples of "x" is the sum of the total number of R** and the total number of C**. Furthermore, the number of samples of "y" is the sum of the total number of R** and the total number of C**. For example, when a correlation coefficient between test result Ra and test result Wa is obtained, the test values ​​of test results Ra for all R** and all C** and the test values ​​of test results Wa for all R** and all C** are used as samples, and the correlation coefficient between test result Ra and test result Wa is obtained according to formula (1).

[0070] In the example shown in FIG. 17 , correlation coefficients were obtained between the inspection result Ra and each of the inspection results Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, and Sr, and the correlation coefficient between the inspection result Ra and the inspection result Ta was the highest. Although the inspection result Ta is not a warning or a failure, it is highly likely to be correlated with the inspection result Ra. This suggests that the warning for the inspection result Ra may be caused by the dicing process upstream of the expanding process. However, the warning for the inspection result Ra may also be caused by a process further upstream of the dicing process.

[0071] Therefore, based on the correlation information 82, it is determined whether or not there is a test result that has a theoretical correlation with the test result Ta. Then, since there is a test result that has a theoretical correlation with the test result Ta, the test results Ha and Hr are identified from the correlation information 82 as test results that have a theoretical correlation with the test result Ra. Then, a correlation coefficient between the test result Ta and each of the test results Ha and Hr is obtained. The correlation coefficient can be calculated, for example, using Equation (1).

[0072] In the example shown in FIG. 17 , the correlation coefficients between the test result Ta and each of the test results Ha and Hr were obtained, and the correlation coefficient between the test result Ta and the test result Ha was the highest. Although the test result Ha is not a warning or a failure, it is highly likely that it is correlated with the test result Ta. This suggests that the cause of the failure or warning in the test result Ra may lie in the stress relief process further upstream than the dicing process. Then, based on the correlation information 82, it is determined whether there is an test result that has a theoretical correlation with the test result Ha. Since there is no test result that has a theoretical correlation with the test result Ha, the cause of the warning in the test result Ra is estimated corresponding to the test result Ha.

[0073] Specifically, based on the relationship information 81, the cause of the warning in the inspection result Ha, which is a warning, is estimated as the cause of the warning in the inspection result Ra. At this time, it is determined whether the warning occurs suddenly or continuously, and the layout state of the warning street site identifier 60 is also determined. Then, based on the determination result of whether the warning occurs suddenly or continuously and the determination result of the layout state of the warning street site identifier 60, the cause of the warning in the inspection result Ra is estimated from the relationship information 81. In the example shown in FIG. 17 , the warning occurs suddenly and the layout state of the warning street site identifier 60 is a point. Therefore, it is estimated that the cause of the warning in the inspection result Ra is "point contamination." That is, it is estimated that the warning in the inspection result Ra was caused by a point-like, medium-sized foreign object being mixed between the wafer holder 13 and the wafer We during stress relief processing.

[0074] The operator is notified of the estimated cause of the warning, for example, by being displayed on the display unit of the analysis device 50 or an external display unit. The operator takes measures depending on the estimated cause of the warning. For example, as a measure, the operator cleans the inside of the stress relief processing apparatus 10 (particularly, cleaning the wafer holder 13) and confirms that the cleanliness level inside the stress relief processing apparatus 10 is within specifications.

[0075] If the correlation coefficients between the inspection result Ra and each of the inspection results Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, and Sr are obtained and no inspection result has a high correlation coefficient, it is highly likely that the cause of the warning in the inspection result Ra is the expanding process itself, rather than the upstream processing. Therefore, if no inspection result has a correlation coefficient exceeding a threshold value (e.g., 0.5), the cause of the warning in the inspection result Ra is estimated to be the cause of the warning in the inspection result Ra, based on the relationship information 81. In the example shown in FIG. 18 , the warning occurred suddenly, and the warning street site identifier 60 is arranged in a dotted state. Therefore, it is estimated that the cause of the warning in the inspection result Ra is "small dot contamination." That is, it is estimated that the cause of the warning in the inspection result Ra is a dotted, small-sized foreign object sandwiched between the expanding tape Te and the wafer We during the expanding process.

[0076] Furthermore, if the correlation coefficient between the inspection result Ta and each of the inspection results Ha and Hr is obtained and no inspection result has a high correlation coefficient, it is highly likely that the cause of the warning in the inspection result Ra is the dicing process, not the upstream process. Therefore, if no inspection result has a correlation coefficient exceeding a threshold value (e.g., 0.5), the cause of the warning in the inspection result Ta is presumed to be the cause of the warning in the inspection result Ra, based on the relationship information 81. In the example shown in FIG. 19 , the warning occurred suddenly, and the warning street site identifier 60 is arranged in a dotted state. Therefore, it is presumed that the cause of the warning in the inspection result Ra is "dot contamination." That is, it is presumed that the cause of the warning in the inspection result Ra is the presence of a dotted, medium-sized foreign object between the wafer holder 34 and the wafer We during the dicing process.

[0077] The above has been an example of the test result Ra, but the same basically applies to the test results Ha, Hr, Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, Sr, Rs, and Rr. Also, the case where a warning occurs because the test result is outside the warning limit range has been described, but the same basically applies to the case where a defect occurs because the test result is outside the failure limit range, and the case where a warning occurs because the test result is outside the dissociation warning limit range.

[0078] 20 and 21 , the control unit 51 of the analytical device 50 confirms the effectiveness of the countermeasure based on the change in the correlation coefficient before and after the countermeasure for the estimated cause of the warning or failure. Furthermore, the control unit 51 of the analytical device 50 determines whether there is a cause of the warning or failure other than the estimated cause of the warning or failure based on the change in the correlation coefficient before and after the countermeasure for the estimated cause of the warning or failure.

[0079] FIG. 20 shows an example of the correlation coefficient after the countermeasure in the example shown in FIG. 17 is taken. After the countermeasure shown in FIG. 20 , the correlation coefficient between the test result Ra and the test result Ta decreases, while the correlation coefficient between the test result Ra and the test results other than the test result Ta increases, compared to before the countermeasure shown in FIG. 17 . Furthermore, the test result Ra falls within the warning limit. Furthermore, the correlation coefficient between the test result Ta and each of the test results Ha and Hr remains unchanged, indicating a high correlation. However, it can be seen that the improvement in the test result Ha due to the countermeasure improves the test result Ta, and the test result Ra now falls within the warning limit. In other words, the change in the correlation coefficient before and after the countermeasure and the fact that the test result Ra now falls within the warning limit indicate that the countermeasure was effective.

[0080] FIG. 21 shows another example of the correlation coefficient after the countermeasures in the example shown in FIG. 17 have been implemented. After the countermeasures in FIG. 21 , the correlation coefficient between the test result Ra and the test result Ta has decreased, while the correlation coefficient between the test result Ra and test results other than the test result Ta has increased, compared to the case before the countermeasures in FIG. 17 . However, the test result Ra exceeds the warning limit. This indicates that the countermeasures were ineffective. In this case, there is a high possibility that there is another cause other than the estimated cause. In the example shown in FIG. 21 , since no test results had a correlation coefficient exceeding the threshold, it is estimated that "small spot contamination" is the cause of the warning for the test result Ra, as in the example shown in FIG. 18 . If there are test results with a high correlation coefficient, it may be determined whether there are test results that have a theoretical correlation with the test results with a higher correlation coefficient, and the cause may be estimated, as in the example shown in FIG. 17 .

[0081] (Effects of this embodiment) In this embodiment, the following effects can be obtained.

[0082] In this embodiment, as described above, a process is provided in which the results of multiple inspections are linked to street site identifiers 60 for identifying wafer sites defined by multiple streets St, and the results are analyzed. This allows the results of multiple inspections resulting from multiple processes to be linked to the street site identifiers 60 and analyzed, making it possible to easily understand the influence between the multiple processes. Furthermore, by linking the results of multiple inspections to the street site identifiers 60, the results of the inspections can be easily compared. As a result, the results of multiple inspections can be easily analyzed.

[0083] Furthermore, in this embodiment, as described above, the step of analyzing the results of the multiple inspections includes a step of determining whether the inspection result is defective or pass (not defective) for each street portion identifier 60. This makes it easy to know whether the inspection result is defective or pass, and therefore, if the inspection result is defective, countermeasures can be implemented promptly.

[0084] Furthermore, in this embodiment, as described above, the process of analyzing the results of the multiple inspections includes a process of determining, for each street portion identifier 60, whether the inspection result is a failure, a warning (not a failure but close to a failure), or a pass. This allows the warning to be used to identify signs of a failure, and therefore, as soon as the signs of a failure are identified, countermeasures can be implemented promptly. As a result, the occurrence of defects can be suppressed.

[0085] Furthermore, in this embodiment, as described above, the step of analyzing the results of the multiple tests includes a step of estimating the cause of the warning or failure based on the correlation coefficient between the results of the multiple tests. This allows the cause of the warning or failure to be estimated with high accuracy, and therefore allows appropriate countermeasures to be implemented based on the estimated cause.

[0086] Furthermore, in this embodiment, as described above, the step of analyzing the results of the multiple tests includes a step of estimating the cause of the warning or failure based on a correlation coefficient between the result of a first test that is determined to be a warning or failure and the result of a second test that is theoretically correlated with the first test. This allows the cause of the warning or failure to be estimated more accurately, and therefore allows more appropriate countermeasures to be implemented based on the estimated cause.

[0087] Furthermore, in this embodiment, as described above, a step of confirming the effectiveness of the countermeasure based on the change in the correlation coefficient before and after the countermeasure for the estimated cause of the warning or failure is provided. This allows the effectiveness of the countermeasure to be confirmed, making it possible to understand whether the cause has been corrected. Furthermore, if the countermeasure is not effective, other causes can be investigated or other countermeasures can be taken.

[0088] Furthermore, in this embodiment, as described above, the step of confirming the effectiveness of the countermeasure includes a step of determining whether there is a cause of the warning or failure other than the estimated cause of the warning or failure, based on a change in the correlation coefficient before and after the countermeasure for the estimated cause of the warning or failure is taken. This allows for the prompt implementation of a countermeasure for the cause of the warning or failure, if there is a cause of the other warning or failure.

[0089] In addition, in this embodiment, as described above, the multiple processes include the stress relief process, the grooving process, the dicing process, and the expanding process, which makes it possible to easily analyze the results of multiple inspections when the stress relief process, the grooving process, the dicing process, and the expanding process are performed.

[0090] Furthermore, in this embodiment, as described above, the step of analyzing the results of the multiple inspections includes a step of determining, for each street portion identifier 60, that if the inspection value of the current inspection result exceeds the inspection value of the previous inspection result by a predetermined value or more, that the result is not a defect but is a warning indicating a defect approaching. As a result, if a sign of a defect is observed because the inspection value of the current inspection result exceeds the inspection value of the previous inspection result by a predetermined value or more, the sign of a defect can be identified by issuing a warning. As a result, when a sign of a defect is identified, countermeasures can be implemented quickly, thereby effectively suppressing the occurrence of defects.

[0091] Furthermore, in this embodiment, as described above, the step of analyzing the results of the multiple inspections includes a step of estimating the cause of the warning or failure based on the arrangement state of the warning or failure street site identifiers 60. This allows the cause of the warning or failure to be estimated with high accuracy, since the arrangement state (pattern) of the warning or failure street site identifiers 60 differs depending on the cause of the warning or failure.

[0092] Furthermore, in this embodiment, as described above, the layout state of the warning or failure street site identifiers 60 includes dot-like, line-like, area-like, and the entire wafer. As a result, depending on the cause of the warning or failure, the layout state (pattern) of the warning or failure street site identifiers 60 will be at least one of dot-like, line-like, area-like, and the entire wafer, so that the cause of the warning or failure can be more accurately estimated.

[0093] Furthermore, in this embodiment, as described above, the step of analyzing the results of the multiple tests includes a step of estimating the cause of the warning or failure based on whether the warning or failure occurs suddenly or continuously. This allows the cause of the warning or failure to be accurately estimated, since the cause of the warning or failure differs depending on whether the warning or failure occurs suddenly or continuously.

[0094] [Modifications] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the description of the above-mentioned embodiments, and further includes all modifications (modifications) within the meaning and scope of the claims.

[0095] For example, in the above embodiment, an example was shown in which the wafer processing system includes a stress relief processing device, a grooving processing device, a dicing processing device, and an expanding processing device as wafer processing devices, but the present invention is not limited to this. In the present invention, the wafer processing system may include one or more of the stress relief processing device, the grooving processing device, the dicing processing device, and the expanding processing device as wafer processing devices. That is, the multiple processes performed on the wafer may include one or more of the stress relief processing, the grooving processing, the dicing processing, and the expanding processing. Furthermore, the wafer processing system may include devices other than the stress relief processing device, the grooving processing device, the dicing processing device, and the expanding processing device as wafer processing devices. That is, the multiple processes performed on the wafer may include processes other than the stress relief processing, the grooving processing, the dicing processing, and the expanding processing.

[0096] In the above embodiment, an example was shown in which the inspection for wafer processing includes an inspection for stress relief processing, an inspection for grooving processing, an inspection for dicing processing, and an inspection for expanding processing, but the present invention is not limited to this. In the present invention, the inspection for wafer processing may include one or more of an inspection for stress relief processing, an inspection for grooving processing, an inspection for dicing processing, and an inspection for expanding processing. Furthermore, the inspection for wafer processing may include inspections other than an inspection for stress relief processing, an inspection for grooving processing, an inspection for dicing processing, and an inspection for expanding processing.

[0097] In the above embodiment, an example in which a wafer inspection device is provided in a wafer processing device has been described, but the present invention is not limited to this. In the present invention, a wafer inspection device may be provided independently of a wafer processing device.

[0098] In the above embodiment, an example is shown in which the inspection result is judged to be either "failure," "warning," or "pass," but the present invention is not limited to this. In the present invention, the inspection result may be judged to be either "failure" or "pass" without judging to be a warning.

[0099] In the above embodiment, the effectiveness of a countermeasure is confirmed based on a change in the correlation coefficient before and after the countermeasure is taken for the cause of a warning or failure, but the present invention is not limited to this. In the present invention, the effectiveness of a countermeasure does not have to be confirmed based on a change in the correlation coefficient before and after the countermeasure is taken for the cause of a warning or failure.

[0100] In the above embodiment, an example was shown in which a warning is issued when the test value of the current test result exceeds the test value of the previous test result by a predetermined value or more, but the present invention is not limited to this. In the present invention, it is not necessary to compare the test value of the current test result with the test value of the previous test result.

[0101] Furthermore, in the above embodiment, examples have been shown in which the layout state of the street site identifiers includes dot-like, linear, area-like, and the entire wafer, but the present invention is not limited to this. In the present invention, the layout state of the street site identifiers may include one or several of dot-like, linear, area-like, and the entire wafer. Furthermore, the layout state of the street site identifiers may include states other than dot-like, linear, area-like, and the entire wafer.

[0102] 10 Stress relief processing device (wafer processing device) 20 Grooving processing device (wafer processing device) 24a Inspection unit (inspection device) 27a Inspection unit (inspection device) 30 Dicing processing device (wafer processing device) 35a Inspection unit (inspection device) 40 Expanding processing device (wafer processing device) 47a Inspection unit (inspection device) 50 Analysis device 60 Street portion identifier 100 Wafer processing system Ch Semiconductor chip Ha, Hr, Wa, Wr, Pa, Pr, Ta, Tr, Oa, Or, Sa, Sr, Ra, Rs, Rr Inspection result St Street We Wafer

Claims

1. A step of performing a plurality of processes on a wafer on which a plurality of semiconductor chips and a plurality of streets are arranged; a step of performing a plurality of inspections on the plurality of processes; and a step of analyzing the results of the plurality of inspections by associating them with a street site identifier for identifying a site of the wafer defined by the plurality of streets. A wafer processing method comprising:

2. The wafer processing method according to claim 1, wherein the step of analyzing the results of the plurality of inspections includes, for each of the street site identifiers, a step of determining whether the inspection result is a defect or a non-defect good.

3. The wafer processing method according to claim 2, wherein the step of analyzing the results of the plurality of inspections includes, for each of the street site identifiers, a step of determining whether the inspection result is a defect, a warning near the defect but not the defect, or a good.

4. The wafer processing method according to claim 3, wherein the step of analyzing the results of the plurality of inspections includes a step of estimating a cause of the warning or the defect based on a correlation coefficient between the results of the plurality of inspections.

5. The wafer processing method according to claim 4, wherein the step of analyzing the results of the plurality of inspections includes a step of estimating a cause of the warning or the defect based on a correlation coefficient between a result of a first inspection determined to be the warning or the defect and a result of a second inspection that is theoretically correlated with the first inspection.

6. The wafer processing method according to claim 4, further comprising a step of confirming the effectiveness of a countermeasure based on a change in the correlation coefficient before and after the countermeasure for the estimated cause of the warning or the defect.

7. The wafer processing method according to claim 6, wherein the step of confirming the effectiveness of the countermeasure includes, based on a change in the correlation coefficient before and after the countermeasure for the estimated cause of the warning or the defect, a step of determining whether there is another cause of the warning or the defect different from the estimated cause of the warning or the defect.

8. The wafer processing method according to claim 1, wherein the plurality of processes includes at least one of stress relief processing for removing processing strain by polishing the wafer, grooving processing, dicing processing, and expand processing.

9. The step of analyzing the results of the plurality of inspections includes, for each of the street site identifiers, a step of determining that when the inspection value of the result of the current inspection exceeds the inspection value of the result of the previous inspections by a predetermined value or more, it is not a defect but a warning in the vicinity of the defect. The wafer processing method according to claim 1.

10. The step of analyzing the results of the plurality of inspections includes a step of estimating the cause of the warning or the defect based on the arrangement state of the street site identifiers of the warning or the defect. The wafer processing method according to claim 3.

11. The arrangement state of the street site identifiers of the warning or the defect includes at least one of a dot shape, a linear shape, an area shape, and the whole of the wafer. The wafer processing method according to claim 10.

12. The step of analyzing the results of the plurality of inspections includes a step of estimating the cause of the warning or the defect based on whether the warning or the defect occurs suddenly or continuously. The wafer processing method according to claim 3.

13. A wafer processing system comprising: a plurality of wafer processing apparatuses that perform a plurality of processes on a wafer on which a plurality of semiconductor chips and a plurality of streets are arranged; a plurality of wafer inspection apparatuses that perform a plurality of inspections on the plurality of processes; and an analysis apparatus that analyzes the results of the plurality of inspections, linked to a street site identifier for identifying a site of the wafer determined by the plurality of streets.

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