Power semiconductor device

The power semiconductor device addresses stress, dielectric breakdown, and heat dissipation challenges by using a semiconductor package with an exposed heat dissipation surface, a heat dissipation member with specific geometric features, and an insulating plate that enhances creepage distance and dielectric withstand voltage.

WO2025115274A1PCT designated stage expired Publication Date: 2025-06-05ASTEMO LTD
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Patent Information

Application Number
PCT/JP2024/024610
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-11-29
Filing Date
2024-07-08
Publication Date
2025-06-05

AI Technical Summary

Technical Problem

Existing power semiconductor devices face challenges in reducing stress, improving dielectric breakdown voltage, and enhancing heat dissipation, particularly when using high-voltage ceramic insulating members that may crack under pressure.

Method used

The power semiconductor device incorporates a semiconductor package with a heat dissipation surface exposed, a heat dissipation member with a convex portion and a concave portion, and an insulating plate positioned between the semiconductor package and the heat dissipation member. The insulating plate is designed to overlap with the sealing member and external terminals, ensuring increased creepage distance and dielectric withstand voltage.

Benefits of technology

This configuration achieves stress reduction, improved dielectric breakdown voltage, and enhanced heat dissipation performance, resulting in a highly reliable power semiconductor device.

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Abstract

This power semiconductor device comprises: a semiconductor package which has a semiconductor element, a conductor part that is thermally and electrically connected to the semiconductor element, and a sealing member that molds and seals the semiconductor element and the conductor part, and in which a heat dissipation surface, which is a surface of the conductor part on the side opposite to the surface connected to the semiconductor element, is exposed from the sealing member; a heat dissipation member which is disposed so as to face the heat dissipation surface; and an insulating plate which is provided between the semiconductor package and the heat dissipation member, wherein part of the insulating plate is disposed at least outwardly of the sealing member in a planar direction, the heat dissipation member has a projection that projects toward the heat dissipation surface and is provided with a projection surface that faces the heat dissipation surface, and a recess that is provided around the projection in the planar direction and that is provided with a surface formed further away from the insulating plate in a stacking direction than the projection surface is, the projection surface is formed to be larger in the planar direction than is the heat dissipation surface disposed so as to face the projection surface, and the recess is formed at a position where the insulating plate and an end of the sealing member overlap in plan view.
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Description

Power Semiconductor Devices

[0001] The present invention relates to a power semiconductor device.

[0002] In order to reduce the burden on the environment, the use of hybrid vehicles and electric vehicles is becoming more widespread, and emphasis is being placed on miniaturization and cost reduction of power semiconductor devices in power conversion devices, which are one of the components installed in these vehicles. In order to miniaturize power semiconductor devices that generate a large amount of heat, it is necessary to improve cooling performance. For example, Patent Document 1 discloses the configuration of a power semiconductor device in which a power module is provided with a cooler via a thermal conductive member and an insulating member, and the power module, the thermal conductive member, and the cooler are connected to ensure cooling performance.

[0003] JP 2016-105451 A

[0004] In the technology described in Patent Document 1, when a power module is designed to support high voltages, an insulating member is provided to ensure insulation between the heat dissipation member and the external terminals of the semiconductor module. This insulating member applies pressure to the heat dissipation member, thereby reducing thermal resistance and ensuring cooling performance, thereby improving long-term reliability. However, pressure applied to insulating members with high dielectric strength, such as ceramic plates, can cause cracks, which can lead to reduced reliability. In view of this, an object of the present invention is to provide a highly reliable power semiconductor device that achieves reduced stress, improved dielectric strength, and improved heat dissipation.

[0005] The power semiconductor device has a semiconductor element, a conductor portion thermally and electrically connected to the semiconductor element, and a sealing member that mold-seals the semiconductor element and the conductor portion, and is equipped with a semiconductor package in which a heat dissipation surface, which is the surface of the conductor portion opposite the surface that connects to the semiconductor element, is exposed from the sealing member, a heat dissipation member arranged opposite the heat dissipation surface, and an insulating plate provided between the semiconductor package and the heat dissipation member, a portion of the insulating plate is arranged at least outside the sealing member in a planar direction, and the heat dissipation member has a convex portion that protrudes toward the heat dissipation surface and has a protruding surface that faces the heat dissipation surface, and a concave portion that is arranged around the convex portion in the planar direction and has a surface that is formed farther from the insulating plate in the stacking direction than the protruding surface, and the protruding surface is formed larger in the planar direction than the heat dissipation surface that is arranged opposite to it, and the concave portion is formed at a position where an end of the sealing member and the insulating plate overlap in a planar view.

[0006] It is possible to provide a highly reliable power semiconductor device that achieves reduced stress, improved dielectric strength, and improved heat dissipation.

[0007] 1 is a cross-sectional view of a semiconductor package in a power semiconductor device; 2 is a cross-sectional view of a power semiconductor device according to a first embodiment of the present invention; 3 is an exploded plan view of the power semiconductor device of FIG. 2; 4 is a cross-sectional view of a power semiconductor device according to a second embodiment of the present invention; 5 is an exploded plan view of the power semiconductor device of FIG. 4;

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] (First Embodiment and Overall Configuration of the Present Invention) (FIG. 1) A semiconductor package 100, which functions as a semiconductor module in a power semiconductor device, includes a semiconductor element 1, a first conductor 3a, a second conductor 3b, and an external terminal 3c. The first conductor 3a and the second conductor 3b are thermally and electrically connected to the semiconductor element 1 and are made of, for example, copper, a copper alloy, aluminum, or an aluminum alloy. An electrode provided on one surface of the semiconductor element 1 is joined to the first conductor 3a by a bonding material 2. An electrode provided on the other surface of the semiconductor element 1 is joined to the second conductor 3b by the bonding material 2. The bonding material 2 is, for example, a solder material, a sintered material, or the like.

[0011] The first conductor 3a and the second conductor 3b are mold-sealed such that a heat dissipation surface 10a, which is the surface opposite to the surface connected to the semiconductor element 1, is exposed from the sealing resin 10, which is a sealing member. This allows the semiconductor package 100 to dissipate heat generated in the semiconductor package 100 to a heat dissipation member 7, which will be described later, via the heat dissipation surfaces 10a exposed on both sides. The external terminals 3c are provided so that a portion of the terminal protrudes from the sealing member 10 to the outside, thereby allowing the semiconductor package 100 to be electrically connected to external wiring (not shown).

[0012] (FIG. 2) The first conductor 3a is connected to the insulating plate 4, which is an insulating layer having electrical insulation properties, on the heat dissipation surface 10a via a heat conduction layer 5a made of a heat conductive material. The insulating plate 4 is connected to a heat conduction layer 5b made of a heat conductive material on the surface opposite to the surface to which the first conductor 3a is connected, and is connected to the heat dissipation member 7 via the heat conduction layer 5b. In this way, of the heat dissipation members 7 provided on both surfaces of the semiconductor package 100, one heat dissipation member 7 faces the heat dissipation surface 10a of the first conductor 3a.

[0013] The second conductor 3b is connected to the insulating plate 4 on the heat dissipation surface 10a via the thermally conductive layer 5a. The insulating plate 4 is connected to the thermally conductive layer 5b on the surface opposite to the surface to which the second conductor 3b is connected, and is then connected to the heat dissipation member 7. In this way, of the heat dissipation members 7 provided on both surfaces of the semiconductor package 100, the other heat dissipation member 7 faces the heat dissipation surface 10a of the second conductor 3b.

[0014] The insulating plate 4 and the thermally conductive layers 5a and 5b sandwiching the insulating plate 4 are provided between the semiconductor package 100 and the heat dissipation member 7 and are in close contact with each other. As a result, a refrigerant flows inside the heat dissipation member 7, and the semiconductor package 100 ensures cooling performance by conducting heat generated from the semiconductor element 1 to the heat dissipation member 7 via the thermally conductive layers 5a and 5b and the insulating plate 4, and also electrically insulates the semiconductor package 100 from the heat dissipation member 7.

[0015] The insulating plate 4 is an insulating sheet made of a material with high thermal conductivity and high dielectric strength, and the material may be, for example, a ceramic such as aluminum oxide (alumina), aluminum nitride, or silicon nitride, or may contain fine powder of these materials.

[0016] The heat conductive layers 5a and 5b are made of a material having heat conductivity, such as heat conductive grease, a thermal interface material (TIM), or a heat dissipation sheet.

[0017] The heat dissipation member 7 is made of a thermally conductive material, such as a composite material of Cu, a Cu alloy, Cu-C, or Cu-CuO, or a composite material of Al, an Al alloy, AlSiC, or Al-C.

[0018] The heat dissipation member 7 has protruding portions 7c that protrude toward the heat dissipation surface 10a of the first conductor portion 3a and the heat dissipation surface 10a of the second conductor portion 3b and have protruding surfaces 7d that face the respective heat dissipation surfaces 10a. The heat dissipation member 7 also has recessed portions 7e that are provided around the protruding portions 7c in the planar direction and are formed farther away from the insulating plate 4 in the stacking direction than the protruding surfaces 7d. The protruding surfaces 7d are larger in the planar direction than the opposing heat dissipation surfaces 10a, so that the heat dissipated from the heat dissipation surfaces 10a can be reliably absorbed by the heat dissipation member 7 without deteriorating the heat dissipation performance. The heat dissipation member 7 is pressed toward the semiconductor package 100 according to the arrows of the pressure applying portion 11.

[0019] The ends of the first conductor portion 3a and the second conductor portion 3b in the planar direction are designated as X1, the ends of the convex portion 7c of the heat dissipation member 7 in the planar direction are designated as X2, the ends of the sealing resin 10 in the planar direction are designated as X3, and the ends of the insulating plate 4 in the planar direction are designated as X4.

[0020] End X2 is provided at a position further outward in the planar direction than end X1, and further inward in the planar direction than end X3 of sealing member 10. Recess 7e of heat dissipation member 7 is formed at a position where end X3 of sealing member 10 and insulating plate 4 overlap in a planar view.

[0021] An end X4 of the insulating plate 4 is disposed outside an end X3 of the sealing resin 10, and at least a portion of the insulating plate 4 is provided outside the sealing resin 10 in the planar direction. The insulating plate 4 is a white ceramic plate that does not have a wiring layer that forms a conductor on either side, and the insulating plate 4 is sandwiched on both sides by the thermally conductive layers 5 a and 5 b, which contributes to suppressing cracks in the insulating plate 4.

[0022] (Figure 3) Figure 3(a) is a plan view of the semiconductor package 100 equipped with the heat dissipation member 7 of Figure 2, with the upper heat dissipation member 7, the first conductor portion 3a, and the semiconductor element 1 removed, Figure 3(b) is a plan view of the heat dissipation member 7 of Figure 3(a), and Figure 3(c) is a cross-sectional view of the heat dissipation member 7 of Figure 3(b).

[0023] As shown in Fig. 3, the heat dissipation member 7 has bolt holes 9 at each of the four corners. When bolts (not shown) are inserted into the bolt holes 9, pressure is generated in the direction indicated by the arrows on the pressure applying portion 11 (Fig. 2) of the heat dissipation member 7, pressing the heat dissipation member 7 toward the semiconductor package 100. Note that clips, leaf springs, and the like may be used instead of bolts as long as the heat dissipation member 7 is configured to be pressed toward the semiconductor package 100. Furthermore, the pressure applying portion 11 of the semiconductor package 100 may be formed at the position of the protruding portion 7c of the heat dissipation member in the stacking direction.

[0024] The semiconductor package 100 has external terminals 3c that protrude from the sealing member 10 to the outside, and the insulating plate 4 has at least a portion that overlaps the external terminals 3c in a plan view. This increases the creepage distance between the external terminals 3c and the heat dissipation members 7 formed on both sides of the semiconductor package 100, improving the dielectric strength and preventing dielectric breakdown even when the semiconductor package 100 is used at high voltage. Note that the insulating plate 4 for ensuring the creepage distance does not have to be configured to be disposed over the entire surface in the planar direction as shown in Figure 3, but may be formed only in the portion where the external terminals 3c protrude from the sealing member 10 to the outside.

[0025] The thermally conductive layer 5b is provided between the insulating plate 4 and the protruding portion 7c, so that the protruding portion 7c does not come into direct contact with the heat dissipation member 7 and therefore acts as a stress relief layer. When a load is applied to the pressure applying portion 11 of the heat dissipation member 7, the heat dissipation member 7 undergoes bending deformation with the end X2 of the protruding portion 7c as the fulcrum. The thermally conductive layer 5b on the recessed portion 7e, which is affected by the stress caused by this deformation, is made thicker in the stacking direction by the difference in height between the protruding portion 7c and the recessed portion 7e. As a result, even when pressure is applied by the pressure applying portion 11, stress is less likely to be applied to the insulating plate 4, and cracks in the insulating plate 4 are suppressed.

[0026] The heat dissipation member 7 may be made of a single member or may be made of multiple members. The heat dissipation member 7 may be provided with a water channel through which a refrigerant flows, pin fins, corrugated fins, or the like inside, or may be air-cooled or have other cooling forms.

[0027] (Second embodiment) (Figures 4 and 5) Figure 5(a) is a plan view of a semiconductor package 100 equipped with the heat dissipation member 7 of Figure 4, with the upper heat dissipation member 7, first conductor portion 3a, and semiconductor element 1 removed in the stacking direction, Figure 3(b) is a plan view of the heat dissipation member 7 of Figure 3(a), and Figure 3(c) is a cross-sectional view of the heat dissipation member 7 of Figure 3(b).

[0028] 5A, the recess 7e is formed so that, when viewed in plan, the recess 7e does not extend to the position of the bolt hole 9 of the heat dissipation member 7. Note that the end X5 of the recess 7e in the planar direction is located more outward than the end X4. This prevents the thickness of the heat dissipation member 7 from becoming thin around the bolt hole 9, which is the load-bearing portion for pressing the heat dissipation member 7 toward the semiconductor package 100, thereby enabling efficient pressure application.

[0029] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0030] (1) A semiconductor package 100 includes a semiconductor element 1, conductors 3a and 3b thermally and electrically connected to the semiconductor element 1, and a sealing member 10 for mold-sealing the semiconductor element 1 and the conductors 3a and 3b, and a heat dissipation surface 10a of the conductors 3a and 3b opposite to the surface connected to the semiconductor element 1, which is exposed from the sealing member 10, a heat dissipation member 7 disposed opposite to the heat dissipation surface 10a, and an insulating plate 4 provided between the semiconductor package 100 and the heat dissipation member 7, and a part of the insulating plate 4 is sealed in a planar direction. The heat dissipation member 10 is disposed at least outside the sealing member 10, and has a protruding portion 7c that protrudes toward the heat dissipation surface 10a and has a protruding surface 7d that faces the heat dissipation surface 10a, and a recessed portion 7e that is disposed around the protruding portion 7c in the planar direction and has a surface that is formed farther from the insulating plate 4 than the protruding surface 7d in the stacking direction, the protruding surface 7d being larger in the planar direction than the heat dissipation surface 10a that is disposed opposite, and the recessed portion 7e is formed at a position where the end X3 of the sealing member 10 overlaps the insulating plate 4 in a plan view. In this way, a highly reliable power semiconductor device can be provided that achieves reduced stress, improved dielectric strength, and improved heat dissipation.

[0031] (2) The insulating plate 4 is a white ceramic plate without a conductive wiring layer. By using such a member, stress can be reduced and the dielectric strength can be improved.

[0032] (3) The semiconductor package 100 has terminals 3c that protrude from the sealing member 10 to the outside, and the insulating plate 4 overlaps at least a portion of the terminals 3c in a plan view, thereby ensuring a creepage distance between the heat dissipation member 7 and the terminals 3c and improving the dielectric strength.

[0033] (4) A thermally conductive material is provided between the insulating plate 4 and the heat dissipation member 7. This allows the semiconductor package 100 and the heat dissipation member 7 to be electrically insulated from each other while the heat generated from the semiconductor package 100 is transferred to the heat dissipation member 7.

[0034] (5) A thermally conductive material is provided between the insulating plate 4 and the semiconductor package 100, or between the insulating plate 4 and the heat dissipation member 7. This allows the semiconductor package 100 and the heat dissipation member 7 to be electrically insulated from each other, while allowing heat generated from the semiconductor package 100 to be transferred to the heat dissipation member 7.

[0035] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted.

[0036] REFERENCE SIGNS LIST 1 semiconductor element 2 bonding material 3a first conductor portion 3b second conductor portion 3c external terminal 4 insulating plate 5a, 5b thermal conduction layer 7 heat dissipation member 7c convex portion of heat dissipation member 7d protruding surface 7e concave portion of heat dissipation member 9 bolt hole 10 sealing resin 10a heat dissipation surface 11 pressure portion X1 end of conductor portion X2 end of convex portion of heat dissipation member X3 end of sealing resin X4 end of insulating plate X5 end of concave portion of heat dissipation member 100 semiconductor package

Claims

1. A power semiconductor device comprising: a semiconductor package having a semiconductor element, a conductor portion thermally and electrically connected to the semiconductor element, and a sealing member that mold-seals the semiconductor element and the conductor portion, the semiconductor package having a heat dissipation surface exposed from the sealing member, the heat dissipation surface being the surface of the conductor portion opposite to the surface connected to the semiconductor element; a heat dissipation member arranged opposite the heat dissipation surface; and an insulating plate provided between the semiconductor package and the heat dissipation member, a portion of the insulating plate being arranged at least outside the sealing member in a planar direction, the heat dissipation member having a convex portion protruding toward the heat dissipation surface and providing a protruding surface facing the heat dissipation surface, and a concave portion provided around the convex portion in the planar direction and providing a surface formed away from the insulating plate in the stacking direction compared to the protruding surface, the protruding surface being formed larger in the planar direction than the heat dissipation surface arranged opposite, and the concave portion being formed at a position where an end of the sealing member and the insulating plate overlap in a planar view.

2. A power semiconductor device according to claim 1, wherein the insulating plate is a white ceramic plate not provided with a wiring layer made of a conductor.

3. A power semiconductor device according to claim 1, wherein the semiconductor package has terminal parts protruding from the sealing member to the outside, and the insulating plate has at least a portion overlapping with the terminal parts in a plan view.

4. A power semiconductor device according to claim 1, wherein a thermally conductive material is provided between said insulating plate and said heat dissipation member.

5. A power semiconductor device according to claim 1, wherein a thermally conductive material is provided between said insulating plate and said semiconductor package, or between said insulating plate and said heat dissipation member.

Citation Information

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