Semiconductor device, electronic device, and vehicle

Abstract

An overcurrent protection circuit 34 limits an output current IOUT to an overcurrent protection threshold IocpL or less from an instruction to turn on an output switch 9 until a terminal-to-terminal voltage Vds becomes less than a detection threshold Vx (until t51). After the terminal-to-terminal voltage Vds has become less than the detection threshold Vx, the overcurrent protection circuit 34 forces the output switch 9 off when the output current IOUT exceeds an overcurrent protection threshold IocpH (>IocpL), and cancels the forced turn-off when the output current IOUT becomes less than the overcurrent protection threshold IocpH (t51-54). Once the number of times the output switch 9 is forced off reaches an upper limit value after the terminal-to-terminal voltage Vds has become less than the detection threshold Vx, the overcurrent protection circuit 34 forces the output switch 9 off when the output current IOUT exceeds the overcurrent protection threshold IocpH, and cancels the forced turn-off when time T2 has elapsed (after t54).

Description

Semiconductor devices, electronic devices, vehicles

[0001] The present disclosure relates to a semiconductor device, an electronic device, and a vehicle.

[0002] The applicant of the present application has proposed many new technologies relating to semiconductor devices called IPDs (intelligent power devices) and SPSs (smart power switches) (see, for example, Patent Document 1).

[0003] International Publication No. 2017 / 187785

[0004] [Summary] However, conventional semiconductor devices have room for improvement in the method of driving a capacitive load (combined with an abnormality protection function).

[0005] For example, a semiconductor device according to the present disclosure includes an output switch and an overcurrent protection circuit configured to detect an output current flowing through the output switch and apply overcurrent protection, wherein the overcurrent protection circuit operates to limit the output current to a first overcurrent protection threshold or less until a first time period has elapsed since an instruction to turn on the output switch has been issued or a voltage across the output switch has fallen below a detection threshold, whichever comes first, and when the voltage across the output switch has fallen below the detection threshold before the first time period has elapsed since an instruction to turn on the output switch has been issued, the output current is limited to the first overcurrent protection threshold or less. The output switch is forcibly turned off when the output current exceeds a second overcurrent protection threshold that is greater than the current protection threshold, and the forced turning off of the output switch is released when the output current falls below the second overcurrent protection threshold. After the point in time when the first time period has elapsed since the output switch was instructed to turn on, or the point in time when the number of times the output switch has been forcibly turned off since the voltage across the output switch fell below the detection threshold, whichever comes first, the output switch is forcibly turned off when the output current exceeds the second overcurrent protection threshold, and the forced turning off of the output switch is released when the second time period has elapsed.

[0006] FIG. 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. FIG. 2 is a diagram showing a first embodiment of the semiconductor device. FIG. 3 is a diagram showing an example of an electronic device including a mechanical fuse. FIG. 4 is a diagram showing a second embodiment of the semiconductor device. FIG. 5 is a diagram showing a first example of an abnormality protection operation. FIG. 6 is a diagram showing a second example of an abnormality protection operation. FIG. 7 is a diagram showing a third example of an abnormality protection operation. FIG. 8 is a diagram showing a fourth example of an abnormality protection operation. FIG. 9 is a diagram showing a first example of a startup operation in the second embodiment. FIG. 10 is a diagram showing a second example of a startup operation in the second embodiment. FIG. 11 is a diagram showing a third example of a startup operation in the second embodiment. FIG. 12 is a diagram showing a third embodiment of the semiconductor device. FIG. 13 is a diagram showing a turn-off behavior in the third embodiment. FIG. 14 is a diagram showing a startup behavior in the third embodiment. FIG. 15 is a partially enlarged view of a portion of FIG. 14. FIG. 16 is a diagram showing a fourth embodiment of the semiconductor device. FIG. 17 is a diagram showing an example of generating a count expiration signal. FIG. 18 is a diagram showing an example of the configuration of a control circuit. FIG. 19 is a diagram showing an example of generating an upper limit count reached signal. Fig. 20 is a diagram showing an example of mode transition. Fig. 21 is a diagram showing a first example of a startup operation in the fourth embodiment. Fig. 22 is a diagram showing a second example of a startup operation in the fourth embodiment. Fig. 23 is a diagram showing a third example of a startup operation in the fourth embodiment. Fig. 24 is a diagram showing the external appearance of a vehicle.

[0007] 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. Electronic device A of this configuration example includes a semiconductor device 1, a DC power supply 2, and a load 3.

[0008] The semiconductor device 1 is a high-side switch IC (a type of IPD) that connects / disconnects a DC power supply 2 and a load 3, and is configured by integrating a power MISFET (metal insulator semiconductor field effect transistor) 9 and a controller 10.

[0009] The semiconductor device 1 also includes a plurality of external electrodes as means for establishing electrical connection with the outside of the device. Referring to the figure, the semiconductor device 1 includes a drain electrode 11 (corresponding to the power supply electrode VBB), a source electrode 12 (corresponding to the output electrode OUT), an input electrode 13 (corresponding to the input electrode IN), and a reference voltage electrode 14 (corresponding to the ground electrode GND).

[0010] The power MISFET 9 is an example of an insulated gate power transistor (=output switch), and functions as a high-side switch element that connects / disconnects the drain electrode 11 and the source electrode 12 .

[0011] The controller 10 includes a plurality of types of functional circuits that realize various functions, including, for example, a circuit that generates a gate drive signal VG that drives and controls the power MISFET 9 based on an external electrical signal.

[0012] The drain electrode 11 transmits a power supply voltage VB to the drain of the power MISFET 9 and various circuits of the controller 10. The source electrode 12 is connected to the source of the power MISFET 9 and transmits an output voltage VOUT and an output current IOUT to the load 3. A signal line (e.g., a wire harness) laid between the source electrode 12 and the load 3 generally has an inductance component L (and a resistance component). The input electrode 13 transmits an input voltage (input signal) for driving the controller 10. The reference voltage electrode 14 transmits a reference voltage (e.g., a ground voltage) to the controller 10. A resistance component R generally accompanies the reference voltage electrode 14 and the ground terminal.

[0013] <Semiconductor Device (First Embodiment)> Figure 2 is a diagram showing a first embodiment of the semiconductor device 1 (= the electrical structure of the semiconductor device 1 shown in Figure 1). The following description will be given taking as an example a case where the semiconductor device 1 is mounted on a vehicle. When mounted on a vehicle, the semiconductor device 1 can be used as a high-side switch for controlling the supply of current to a light source such as a bulb lamp or an LED (light emitting diode) lamp, or to other types of electronic control devices.

[0014] The semiconductor device 1 includes a drain electrode 11 , a source electrode 12 , an input electrode 13 , a reference voltage electrode 14 , an enable electrode 15 , a sense electrode 16 , a gate control wiring 17 , a power MISFET 9 , and a controller 10 .

[0015] The drain electrode 11 (=power supply electrode VBB) is connected to a DC power supply 2. The drain electrode 11 provides a power supply voltage VB to the power MISFET 9 and the controller 10. The power supply voltage VB may be 10 V or more and 20 V or less. On the other hand, the source electrode 12 (=output electrode OUT) is connected to a load 3.

[0016] The input electrode 13 (=input electrode IN) may be connected to an MCU (micro controller unit), a DC / DC converter, an LDO (low drop out) regulator, or the like. The input electrode 13 provides an input voltage to the controller 10. The input voltage may be 1 V or more and 10 V or less. The reference voltage electrode 14 is connected to a reference voltage wiring (ground terminal). The reference voltage electrode 14 provides a reference voltage to the power MISFET 9 and the controller 10.

[0017] The enable electrode 15 may be connected to the MCU. An electrical signal for enabling or disabling some or all of the functions of the controller 10 is input to the enable electrode 15. The sense electrode 16 transmits an electrical signal for detecting an abnormality in the controller 10 to an external device. The sense electrode 16 may be pulled up or down by a resistor.

[0018] The gate of the power MISFET 9 is connected to the controller 10 (particularly, a gate control circuit 25 described later) via a gate control wiring 17. The drain of the power MISFET 9 is connected to a drain electrode 11. The source of the power MISFET 9 is connected to the controller 10 (particularly, a current detection circuit 27 described later) and a source electrode 12.

[0019] The controller 10 includes a sensor MISFET 21 , an input circuit 22 , a current / voltage control circuit 23 , a protection circuit 24 , a gate control circuit 25 , an active clamp circuit 26 , a current detection circuit 27 , a power supply reverse connection protection circuit 28 , and an abnormality detection circuit 29 .

[0020] The gate of the sensor MISFET 21 is connected to the gate control circuit 25. The drain of the sensor MISFET 21 is connected to the drain electrode 11. The source of the sensor MISFET 21 is connected to the current detection circuit 27.

[0021] The input circuit 22 is connected to the input electrode 13 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0022] The current / voltage control circuit 23 is connected to a protection circuit 24, a gate control circuit 25, a power supply reverse connection protection circuit 28, and an abnormality detection circuit 29. The current / voltage control circuit 23 may include a logic circuit.

[0023] The current / voltage control circuit 23 generates various voltages in response to the electrical signals from the input circuit 22 and the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage / reference current generation circuit 33.

[0024] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 30 may generate a drive voltage between 5 V and 15 V, which is obtained by subtracting 5 V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0025] The first constant voltage generating circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generating circuit 31 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The first constant voltage is input to the protection circuit 24 (more specifically, to the open load detection circuit 35, etc., which will be described later).

[0026] The second constant voltage generating circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generating circuit 32 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The second constant voltage is input to the protection circuit 24 (more specifically, an overheat protection circuit 36 ​​and an undervoltage lockout circuit 37, which will be described later).

[0027] The reference voltage / reference current generating circuit 33 generates a reference voltage and a reference current for the various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to the various circuits. If the various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0028] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The protection circuit 24 includes an overcurrent protection circuit 34, an open load detection circuit 35, an overheat protection circuit 36, and an undervoltage lockout circuit 37.

[0029] The overcurrent protection circuit 34 protects the power MISFET 9 from an overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25 and the source of the sensor MISFET 21. The overcurrent protection circuit 34 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, to a drive signal output circuit 40, which will be described later).

[0030] The open load detection circuit 35 detects a short state and an open state of the power MISFET 9. The open load detection circuit 35 is connected to the current / voltage control circuit 23 and the source of the power MISFET 9. A signal generated by the open load detection circuit 35 is input to the current / voltage control circuit 23.

[0031] The overheat protection circuit 36 ​​monitors the temperature of the power MISFET 9 and protects the power MISFET 9 from an excessive temperature rise. The overheat protection circuit 36 ​​is connected to the current / voltage control circuit 23. The overheat protection circuit 36 ​​may include a temperature-sensing device such as a temperature-sensing diode or a thermistor. A signal generated by the overheat protection circuit 36 ​​is input to the current / voltage control circuit 23.

[0032] The undervoltage lockout circuit 37 prevents the power MISFET 9 from malfunctioning when the power supply voltage VB is less than a predetermined value. The undervoltage lockout circuit 37 is connected to the current / voltage control circuit 23. A signal generated by the undervoltage lockout circuit 37 is input to the current / voltage control circuit 23.

[0033] The gate control circuit 25 controls the on and off states of the power MISFET 9 and the sensor MISFET 21. The gate control circuit 25 is connected to the current / voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0034] The gate control circuit 25 outputs a gate drive signal VG to the gate control wiring 17 in response to an electric signal from the current / voltage control circuit 23 and an electric signal from the protection circuit 24. The gate drive signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. Specifically, the gate control circuit 25 controls the gate drive signal VG in response to an electric signal (input signal) applied to the input electrode 13 to turn the power MISFET 9 on / off.

[0035] More specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates in response to an electrical signal from the current / voltage control circuit 23 to generate a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 generates a boosted voltage VCP based on the electrical signal from the oscillation circuit 38. The boosted voltage VCP generated by the charge pump circuit 39 is input to the drive signal output circuit 40.

[0036] The drive signal output circuit 40 operates by receiving the boosted voltage VCP output from the charge pump circuit 39, and generates a gate drive signal VG in response to an electrical signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). The gate drive signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. The sensor MISFET 21 and the power MISFET 9 are simultaneously controlled by a gate control circuit 25.

[0037] The active clamp circuit 26 protects the power MISFET 9 from back electromotive force. The active clamp circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamp circuit 26 may include a plurality of diodes.

[0038] The active clamp circuit 26 may include a plurality of diodes connected to each other in a forward bias state. The active clamp circuit 26 may include a plurality of diodes connected to each other in a reverse bias state. The active clamp circuit 26 may include a plurality of diodes connected to each other in a forward bias state and a plurality of diodes connected to each other in a reverse bias state.

[0039] The multiple diodes may include pn junction diodes, Zener diodes, or a combination of pn junction diodes and Zener diodes. The active clamp circuit 26 may include multiple Zener diodes connected to each other in a biased manner. The active clamp circuit 26 may include a Zener diode and a pn junction diode connected to each other in a reverse biased manner.

[0040] The current detection circuit 27 detects the currents flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal in response to the electrical signal (=output current IOUT) generated by the power MISFET 9 and the electrical signal (=sense current ISNS that behaves in the same way as the output current IOUT) generated by the sensor MISFET 21. The current detection signal is input to the abnormality detection circuit 29.

[0041] The power supply reverse connection protection circuit 28 protects the current / voltage control circuit 23, the power MISFET 9, etc. from reverse voltage when the DC power supply 2 is reverse connected. The power supply reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current / voltage control circuit 23.

[0042] Abnormality detection circuit 29 monitors the voltage of protection circuit 24. Abnormality detection circuit 29 is connected to current / voltage control circuit 23, protection circuit 24, and current detection circuit 27. If an abnormality (such as a voltage fluctuation) occurs in any of overcurrent protection circuit 34, open load detection circuit 35, overheat protection circuit 36, and undervoltage malfunction suppression circuit 37, abnormality detection circuit 29 generates an abnormality detection signal corresponding to the voltage of protection circuit 24 and outputs it to the outside.

[0043] More specifically, the abnormality detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two inputs, one output, and one selection control input. The protection circuit 24 and the current detection circuit 27 are connected to the inputs of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output of the first multiplexer circuit 41. The current / voltage control circuit 23 is connected to the selection control input of the first multiplexer circuit 41.

[0044] The first multiplexer circuit 41 generates an abnormality detection signal in response to the electrical signal from the current / voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0045] The second multiplexer circuit 42 has two inputs and one output. The inputs of the second multiplexer circuit 42 are connected to the output of the second multiplexer circuit 42 and the enable electrode 15. The output of the second multiplexer circuit 42 is connected to the sense electrode 16.

[0046] When an MCU is connected to enable electrode 15 and a pull-up or pull-down resistor is connected to sense electrode 16, an ON signal is input from the MCU to enable electrode 15, and an abnormality detection signal is extracted from sense electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to sense electrode 16. An abnormal state of semiconductor device 1 is detected based on this electrical signal.

[0047] 3 is a diagram showing an example of an electronic device equipped with a mechanical fuse. The electronic device B of this configuration example includes a control unit B10, a battery B20, a load B30, and a fuse box B40.

[0048] The control unit B10 drives a load B30 by receiving a power supply voltage VB from a battery B20 via a fuse box B40. Referring to the figure, the control unit B10 includes a DC / DC converter B11, a microcomputer B12, an upper switch B13, a power supply electrode B14, an output electrode B15, and a reference voltage electrode B16. The control unit B10 may be, for example, an ECU (electronic control unit).

[0049] The DC / DC converter B11 generates a desired internal power supply voltage from the power supply voltage VB and outputs it to each part (such as the microcomputer B12) of the control unit B10.

[0050] The microcomputer B12 receives the internal power supply voltage from the DC / DC converter B11 and controls the on / off of the upper switch B13.

[0051] The upper switch B13 is connected between the power supply electrode B14 and the output electrode B15, and is controlled to be turned on / off in response to an instruction from the microcomputer B12.

[0052] The power supply electrode B14 is supplied with a power supply voltage VB from a battery B20 via a fuse box B40. The output electrode B15 is connected to a load B30 via a wire W3, for example. The reference voltage electrode B16 is connected to a ground terminal, for example.

[0053] The fuse box B40 includes n fuses B41(1) to B41(n), an input electrode B42, and output electrodes B43(1) to B43(n).

[0054] The fuse B41(i) (where i = 1, 2, ..., n) is connected between the input electrode B42 and the output electrode B43(i). The fuse B41(i) is a so-called mechanical fuse, and when a current exceeding the rated current flows through it, it melts down due to Joule heat, thereby protecting the circuit.

[0055] The input electrode B42 is connected to the positive terminal of the battery B20 (=the terminal to which the power supply voltage VB is applied) via, for example, a wire W1. The output electrode B43(1) is connected to the power supply electrode B14 of the control unit B10 via, for example, a wire W2.

[0056] Electronic device B using fuse box B40 has two problems. First, the reaction time of fuse B41(i) (i.e., the time required for it to blow) is unknown and inaccurate. As a result, damage to the control unit B10 it protects can often be a problem. Second, blown fuse B41(i) must be replaced. In many cases, a complete system replacement (i.e., a replacement of fuse box B40) is required.

[0057] To solve the above problem, it is conceivable to use an electronic fuse (so-called e-fuse) using an IPD instead of a mechanical fuse. However, the control unit B10 often has its own input capacitor in a subsystem such as the DC / DC converter B11. Therefore, from the perspective of the electronic fuse, the control unit B10 functions as a capacitive load with a large capacitance (generally in the mF range).

[0058] Therefore, in a typical IPD with an electronic fuse, the output switch must be large so that the overheat protection function does not activate even if a large inrush current flows when the control unit B10 starts up, which increases the cost of the IPD.

[0059] Incidentally, if a precharge circuit using discrete components is provided, it is possible to avoid increasing the size of the IPD output switch, but this would require an increase in the number of components and a larger PCB (printed circuit board), which could result in an increase in the cost of the entire electronic device.

[0060] A novel semiconductor device that can solve the above problems will be proposed below.

[0061] 4 is a diagram showing a second embodiment of the semiconductor device 1 (i.e., a configuration example of the semiconductor device 1 replacing a mechanical fuse). In the electronic device B of this configuration example, the fuse box B40 is replaced with the semiconductor device 1, based on the electronic device B shown in FIG.

[0062] The control unit B10, which is externally attached to the source electrode 12 (=output electrode OUT) of the semiconductor device 1, functions as a capacitive load with a large capacitance value when viewed from the semiconductor device 1. Therefore, the control unit B10 is depicted equivalently as a parallel circuit of a capacitor C1 and a resistor R1. Also shown in this figure is a resistor R2 for pulling down the sense electrode 16 to the ground terminal.

[0063] The semiconductor device 1 has a configuration basically similar to that of the first embodiment ( FIG. 2 ) described above, and further includes a CMODE enable electrode 51, an input circuit 52, and a mode control circuit 53. Therefore, the components already described are given the same reference numerals as in FIG. 2 to avoid redundant explanation, and the following description will focus on new components and components related to them.

[0064] The power MISFET 9 is an output switch that connects / disconnects the drain electrode 11 and the source electrode 12 in response to a gate drive signal VG.

[0065] The overcurrent protection circuit 34 detects the output current IOUT flowing through the power MISFET 9 and controls the gate drive signal VG to provide overcurrent protection.

[0066] The overheat protection circuit 36 ​​detects the temperature to be monitored and controls the gate drive signal VG to provide overheat protection.

[0067] The temperature to be monitored may be a first temperature Temp1 detected in the power element formation region including the power MISFET 9. The first temperature Temp1 may be, for example, a pn junction temperature Tj1 in the power element formation region.

[0068] The temperature to be monitored may be a temperature difference ΔTemp (=Temp1-Temp2) between a first temperature Temp1 and a second temperature Temp2 detected in an area other than the power element forming area. The second temperature Temp2 may be, for example, a pn junction temperature Tj2 in the analog circuit forming area or the logic circuit forming area, or may be a case temperature Tc of the semiconductor device 1 or an ambient temperature Ta.

[0069] The CMODE enable electrode 51 is an external electrode for switching the mode control circuit 53 between enabled and disabled.

[0070] The input circuit 52 shapes the waveform of the electrical signal applied to the CMODE enable electrode 51 and outputs it to the mode control circuit 53 .

[0071] The mode control circuit 53 generates a mode control signal S1 for switching between the normal mode and the capacitive load drive mode for each of the overcurrent protection circuit 34 and the overheat protection circuit 36. The mode control signal S1 is output to each of the overcurrent protection circuit 34 and the overheat protection circuit 36.

[0072] The mode control circuit 53 is enabled, for example, when the electrical signal applied to the CMODE enable electrode 51 is at a high level, and is in a state where it can switch the logic level of the mode control signal S1. For example, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode when the mode control signal S1 is at a high level, and are set to the capacitive load drive mode when the mode control signal S1 is at a low level.

[0073] In the capacitive load driving mode, the overcurrent protection circuit 34 performs a current limiting operation to limit the output current IOUT to an overcurrent protection threshold Iocp or less. In particular, in the capacitive load driving mode, the overcurrent protection threshold Iocp is set to a second overcurrent protection threshold Iocp2 (e.g., Iocp2=Iocp1×0.7) that is lower than the first overcurrent protection threshold Iocp1 set in the normal mode.

[0074] Moreover, the overheat protection circuit 36 ​​repeatedly forcibly turns off and restarts the power MISFET 9 every time the monitored temperature (for example, the aforementioned temperature difference ΔTemp) rises up to the overheat protection threshold Ttsd. In particular, in the capacitive load drive mode, the overheat protection threshold Ttsd is set to a second overheat protection threshold Ttsd2 (for example, Ttsd2=30° C.) that is lower than the first overheat protection threshold Ttsd1 (for example, Ttsd1=90° C.) that is set in the normal mode.

[0075] On the other hand, the mode control circuit 53 is disabled, for example, when the electrical signal applied to the CMODE enable electrode 51 is at a low level. In this case, the mode control signal S1 is fixed at a high level. Therefore, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode.

[0076] As described above, in the electronic device B of this configuration example, the aforementioned fuse box B40 is replaced with the semiconductor device 1. That is, when the output current IOUT becomes excessive (for example, several tens to 100 A), the power MISFET 9 is forcibly turned off, thereby limiting or cutting off the output current IOUT quickly and accurately. Therefore, both the semiconductor device 1 and the control unit B10 can be safely protected. Furthermore, unlike a configuration using a mechanical fuse, there is no need to replace a blown fuse B41(i) even if a failure occurs.

[0077] Furthermore, the semiconductor device 1 has a capacitive load driving mode as one of its operation modes, and can therefore appropriately drive a capacitive load (control unit B10 in this figure) without increasing the size of the power MISFET 9 or requiring additional external components.

[0078] The following describes the difference between the normal mode and the capacitive load driving mode of the semiconductor device 1, focusing on the abnormality protection operation of the semiconductor device 1. This description will make clear the advantages of using the capacitive load driving mode.

[0079] 5 is a diagram showing a first example of the abnormality protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0080] This figure shows the behavior when a resistive load (or an inductive load) is driven by the semiconductor device 1 of the second embodiment ( FIG. 4 ). In this case, when the electrical signal applied to the input electrode IN rises to a high level, the output voltage VOUT rises to the power supply voltage VB. Furthermore, the output current IOUT reaches a target value (nominal value) without exceeding the overcurrent protection threshold Iocp.

[0081] The above behavior occurs regardless of whether the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode or the capacitive load drive mode. In other words, when a resistive load or an inductive load is driven by the semiconductor device 1 of the second embodiment ( FIG. 4 ), there is no particular effect on the operation of the semiconductor device 1 even if the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode.

[0082] On the other hand, when a capacitive load is driven by the semiconductor device 1 of the second embodiment (Figure 4), the behavior of the semiconductor device 1 differs depending on whether the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to normal mode or capacitive load drive mode.

[0083] 6 is a diagram showing a second example of the abnormality protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0084] This figure shows the behavior when a capacitive load (e.g., control unit B10) is driven by the semiconductor device 1 of the second embodiment (FIG. 4). This figure also assumes that the electrical signal applied to the CMODE enable electrode 51 is at a low level and the mode control signal S1 is fixed at a high level. In other words, this figure shows the behavior when the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode.

[0085] In this case, when the electrical signal applied to the input electrode IN rises to a high level, a large inrush current flows through the capacitive load, causing the output current IOUT to increase sharply. At this time, the overcurrent protection circuit 34 performs a current limiting operation so that the output current IOUT is equal to or less than the overcurrent protection threshold Iocp (=Iocp1).

[0086] Furthermore, when the capacitance value of the capacitive load is large and the element size of the power MISFET 9 is small, the heat generated by the power MISFET 9 increases. As a result, the overheat protection circuit 36 ​​repeatedly forcibly turns off and restarts the power MISFET 9 every time the temperature to be monitored (for example, the aforementioned temperature difference ΔTemp) rises up to the overheat protection threshold Ttsd (=Ttsd1).

[0087] Note that a certain cooling time Tcd is required from when the power MISFET 9 is forcibly turned off by the overheat protection operation until it is restarted. During this time, the output current IOUT continues to be not supplied to the capacitive load. Therefore, as shown in the figure, there is a risk that this will cause problems in starting up the output voltage VOUT.

[0088] If the element size of the power MISFET 9 is increased, the overheat protection operation is less likely to be activated, and the output voltage VOUT can be raised correctly. However, as described above, increasing the size of the power MISFET 9 leads to an increase in the cost of the semiconductor device 1.

[0089] 7 is a diagram showing a third example of the abnormality protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0090] 6, this figure shows the behavior when a capacitive load (e.g., control unit B10) is driven by the semiconductor device 1 of the second embodiment (FIG. 4). Also, as in the previous example, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to normal mode. However, the overcurrent protection operation in normal mode differs from that in the previous example.

[0091] Referring to this figure, the overcurrent protection circuit 34 performs an off-latch operation to forcibly keep the power MISFET 9 off when the output current IOUT increases to the overcurrent protection threshold Iocp (=Iocp1).

[0092] This type of off-latch operation is extremely effective when the objective is to comply with strict safety standards such as the AEC-Q100-012 standard. However, when considering driving a capacitive load, it must be said to be inappropriate. This is because the forced off-latch of the power MISFET 9 completely cuts off the supply of the output current IOUT to the capacitive load, preventing the output voltage VOUT from rising at all.

[0093] Therefore, when the overcurrent protection circuit 34 performs an off-latch operation, there is no point in increasing the size of the power MISFET 9, and an external precharge circuit becomes essential.

[0094] 8 is a diagram showing a fourth example of the abnormality protection operation in the semiconductor device 1 of the second embodiment (FIG. 4). In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0095] 6 and 7, this figure shows the behavior when a capacitive load (e.g., control unit B10) is driven by the semiconductor device 1 of the second embodiment (FIG. 4). However, it differs from the previous figures in that the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode rather than the normal mode.

[0096] Referring to this figure, in the capacitive load drive mode, the overcurrent protection circuit 34 performs a current limiting operation to limit the output current IOUT to an overcurrent protection threshold Iocp (=Iocp2<Iocp1) or less. The overheat protection circuit 36 ​​repeatedly forcibly turns off and restarts the power MISFET 9 every time the monitored temperature (for example, the aforementioned temperature difference ΔTemp) rises up to the overheat protection threshold Ttsd (=Ttsd2<Ttsd1).

[0097] In this way, in the capacitive load drive mode, both the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd (at least the overheat protection threshold Ttsd) are lowered compared to the normal mode, and the power MISFET 9 is repeatedly forced off and restarted.

[0098] Therefore, the cooling time Tcd from when the power MISFET 9 is forcibly turned off by the overheat protection operation until it is restarted is shortened. As a result, it becomes possible to charge the capacitive load and raise the output voltage VOUT without increasing the size of the power MISFET 9 or requiring an external precharge circuit.

[0099] In this way, in the capacitive load drive mode, it is possible to appropriately drive a capacitive load that is difficult to drive in the normal mode.

[0100] As described above, in the capacitive load drive mode, the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd are lowered compared to those in the normal mode, so that the semiconductor device 1 and the capacitive load (e.g., the control unit B10) connected thereto are maintained within a safe operation area (SOA) while the capacitive load is being charged.

[0101] In addition, in the capacitive load driving mode, at least one of the second overcurrent protection threshold Iocp2 and the second overheat protection threshold Ttsd2 may be gradually increased to the first overcurrent protection threshold Iocp1 and the first overheat protection threshold Ttsd1 in response to an increase in the output voltage VOUT or over time.

[0102] Furthermore, the mode control circuit 53 may switch the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​from the capacitive load drive mode to the normal mode when a predetermined recovery condition (described in detail later) is satisfied (see "CMODE EXIT" in the figure).

[0103] For example, the overcurrent protection operation after returning to the normal mode may be a current limiting operation that limits the output current IOUT to an overcurrent protection threshold Iocp (=Iocp1) or less, similar to the capacitive load driving mode.

[0104] Furthermore, for example, the overcurrent protection operation after returning to the normal mode may be a hiccup operation in which the power MISFET 9 is repeatedly forced off and restarted every time the output current IOUT increases up to the overcurrent protection threshold Iocp (=Iocp1). Such a hiccup operation can suppress heat generation in the power MISFET 9 more effectively than the above-described current limiting operation.

[0105] Furthermore, for example, the overcurrent protection operation after returning to the normal mode may be an off-latch operation that continues to forcibly turn off the power MISFET 9 when the output current IOUT increases to the overcurrent protection threshold value Iocp (=Iocp1). Such an off-latch operation further enhances safety when an overcurrent occurs compared to the above-mentioned current limiting operation and hiccup operation.

[0106] In this way, the semiconductor device 1 of this configuration example can switch between the normal mode and the capacitive load drive mode as needed, and is therefore compatible with process technologies in which the on-resistance of the power MISFET 9 is relatively high and stricter overcurrent protection operation is required.

[0107] To summarize the operation and architecture of the capacitive load driving mode described above, the most important attributes are:

[0108] (1) In the capacitive load drive mode, an overheat detection / restart operation (a state in which the power MISFET 9 is repeatedly forced off by overheat detection and restarted by overheat release) is forced as an overheat protection operation. As a result, the capacitive load is repeatedly charged until the output voltage VOUT rises sufficiently.

[0109] (2) In the capacitive load driving mode, the current limiting operation is forced as an overcurrent protection operation, which prevents the output current IOUT from being latched off before the capacitive load is fully charged.

[0110] (3) In the capacitive load driving mode, the overcurrent protection threshold Iocp is lowered (Iocp1 → Iocp2). This reduces the peak inrush current flowing through the capacitive load during charging. For example, the second overcurrent protection threshold Iocp2 set in the capacitive load driving mode may be 70% of the first overcurrent protection threshold Iocp1 set in the normal mode (i.e., Iocp2 = Iocp1 × 0.7). However, the above ratio is not limited to this.

[0111] (4) In the capacitive load drive mode, the overheat protection threshold Ttsd is lowered (Ttsd1 → Ttsd2). This has two effects. The first is that the semiconductor device 1 is maintained in the safe operating area while the capacitive load is not fully charged, i.e., while the capacitive load functions as a virtual short circuit. The second is that the semiconductor device 1 is quickly cooled to the overheat release temperature (safe temperature), which accelerates the timing of restarting the power MISFET 9 and allows the capacitive load to continue to be charged. In other words, a charge pump effect is obtained, which allows the output voltage VOUT to be reliably raised.

[0112] (5) When the output voltage VOUT becomes higher than a predetermined threshold voltage Vth, the capacitive load driving mode is automatically restored to the normal mode. That is, the threshold voltage Vth corresponds to the termination threshold of the capacitive load driving mode. As described above, the overcurrent protection operation after restoration to the normal mode may be any of the current limiting operation, the hiccup operation, and the off-latch operation.

[0113] (6) The semiconductor device 1 may be automatically restored to the normal mode after a predetermined time (e.g., 50 ms) has elapsed since the capacitive load drive mode was set, thereby maintaining the semiconductor device 1 within the safe operating area even in the event of an output short circuit or other fault.

[0114] (7) The semiconductor device 1 includes a CMODE enable electrode 51 for enabling / disabling the mode control circuit 53 (and thus the capacitive load drive mode). This allows the user to freely decide whether or not to use the capacitive load drive mode. Furthermore, the mode control circuit 53 can be easily enabled / disabled without applying any special mechanism (such as high-frequency PWM [pulse width modulation] drive or multi-level input) to the input electrode IN.

[0115] 9 is a diagram showing a first example of the startup operation of the semiconductor device 1 according to the second embodiment (FIG. 4). In this diagram, from top to bottom, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are depicted.

[0116] This figure shows the behavior when a purely resistive load (for example, R1=2Ω, C1=0 F) is driven by the semiconductor device 1 of the second embodiment (FIG. 4). The on-resistance of the power MISFET 9 is set to 4 mΩ.

[0117] As shown in the figure, the mode control circuit 53 drops the mode control signal S1 to low level when the power MISFET 9 transitions to on. Therefore, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode described above. Note that the capacitive load drive mode does not have any effect on the drive operation (e.g., slew rate) of the resistive load.

[0118] Furthermore, when a predetermined recovery condition is satisfied, the mode control circuit 53 raises the mode control signal S1 to a high level, thereby switching the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​from the capacitive load drive mode to the normal mode.

[0119] Referring to this figure, the recovery condition is that the output voltage VOUT has been detected to be higher than a predetermined threshold voltage Vth. For example, the threshold voltage Vth may be set to a voltage value (Vth = VB - Vx) that is lower than the power supply voltage VB (e.g., 14 V) by a bias voltage Vx (e.g., 2 V). With this setting, the capacitive load drive mode is automatically terminated when the output voltage VOUT has risen sufficiently.

[0120] Alternatively, the above-mentioned restoration condition may be that a predetermined time (for example, 50 ms) has elapsed since the mode control signal S1 was made low.

[0121] 10 is a diagram showing a second example of the startup operation of the semiconductor device 1 according to the second embodiment (FIG. 4). In this diagram, as in the case of FIG. 9, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are depicted in this order from top to bottom.

[0122] 1 shows the behavior when a capacitive load (for example, R1=2Ω, C1=1 mF) is driven by the semiconductor device 1 of the second embodiment (FIG. 4). The on-resistance of the power MISFET 9 is set to 4 mΩ.

[0123] As shown in the figure, when the power MISFET 9 transitions to ON, the mode control signal S1 is pulled down to a low level, and the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode. As a result, the output voltage VOUT rises to the threshold voltage Vth within a startup time t1 (e.g., less than 2 ms) within the required range. The conditions for returning from the capacitive load drive mode to the normal mode (output voltage monitoring or timer monitoring) are the same as those described above.

[0124] 11 is a diagram showing a third example of the startup operation of the semiconductor device 1 according to the second embodiment (FIG. 4). In this diagram, as in FIGS. 9 and 10, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are depicted from top to bottom.

[0125] 10. Note that this figure shows the behavior when the semiconductor device 1 of the second embodiment (FIG. 4) drives a capacitive load (for example, R1=2Ω, C1=4 mF) larger than that in FIG. 10. The on-resistance of the power MISFET 9 is set to 4 mΩ.

[0126] As shown in the figure, when the power MISFET 9 transitions to ON, the mode control signal S1 is pulled down to a low level, and the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode. As a result, the output voltage VOUT rises to the threshold voltage Vth within a startup time t2 within the required range (e.g., less than 7.5 ms). The conditions for returning from the capacitive load drive mode to the normal mode (output voltage monitoring or timer monitoring) are the same as those described above.

[0127] 12 is a diagram showing a third embodiment (corresponding to a comparative example to be compared with the fourth embodiment described later) of the semiconductor device 1. The semiconductor device 1 of this embodiment is based on the second embodiment (FIG. 4) described above, and further includes a high-speed turn-off circuit 60.

[0128] In addition, in this figure, as components of the drive signal output circuit 40, a transistor M1 (for example, a P-channel MISFET), a transistor M2 (for example, an N-channel MISFET), and current sources CS1 and CS2 are clearly shown.

[0129] In this figure, a resistance component R11 and an inductance component L11 of the wire harness are depicted between the application terminal of the power supply voltage VB and the drain of the power MISFET 9. In addition, in this figure, a resistance component R12 and an inductance component L12 of the wire harness are depicted between the source of the power MISFET 9 and a reference potential terminal (for example, a ground terminal).

[0130] The current source CS1 (corresponding to the first current source) generates a first current I1 for charging the gate capacitance (not shown) of the power MISFET 9 when the gate drive signal VG is switched to a high level (= logic level when on).

[0131] The current source CS2 (corresponding to the second current source) generates a second current I2 for discharging the gate capacitance (not shown) of the power MISFET 9 when the gate drive signal VG is switched to a low level (= logic level when off).

[0132] The source of transistor M1 is connected to the application terminal of boost voltage VCP via current source CS1. The source of transistor M2 is connected to the application terminal of output voltage VOUT via current source CS2. The drains of transistors M1 and M2 are both connected to the gate of power MISFET 9 (=application terminal of gate drive signal VG). The gate of transistor M1 is connected to the application terminal of gate voltage GM1. The gate of transistor M2 is connected to the application terminal of gate voltage GM2. It can be understood that gate voltages GM1 and GM2 are each supplied from current / voltage control circuit 23.

[0133] The transistors M1 and M2 connected in this manner form a half-bridge output stage of the drive signal output circuit 40. Referring to this diagram, the transistor M1 connects / disconnects the current source CS1 and the gate of the power MISFET 9 in response to a gate voltage GM1. The transistor M2 connects / disconnects the current source CS2 and the gate of the power MISFET 9 in response to a gate voltage GM2.

[0134] For example, when the electrical signal (input signal) applied to the input electrode 13 is at a high level (=the logical level when the power MISFET 9 is turned on), both gate voltages GM1 and GM2 are set to a low level. As a result, the transistor M1 is turned on, and the transistor M2 is turned off. At this time, the gate capacitance (not shown) of the power MISFET 9 is charged by a first current I1 that flows from the application terminal of the boosted voltage VCP via the current source CS1 and the transistor M1 to the gate of the power MISFET 9. Therefore, the gate drive signal VG becomes a high level (≈VCP). As a result, the power MISFET 9 is turned on.

[0135] Furthermore, for example, when the electrical signal (input signal) applied to the input electrode 13 is at a low level (=the logical level when the power MISFET 9 is turned off), both of the gate voltages GM1 and GM2 are set to a high level. As a result, the transistor M1 is turned off and the transistor M2 is turned on. At this time, the gate capacitance (not shown) of the power MISFET 9 is discharged by a second current I2 that flows from the gate of the power MISFET 9 via the transistor M2 and the current source CS2 to the application terminal of the output voltage VOUT. Therefore, the gate drive signal VG is set to a low level (≈VOUT). As a result, the power MISFET 9 is turned off.

[0136] In this way, the transistors M1 and M2 are complementarily turned on / off in response to the electrical signal (input signal) applied to the input electrode 13, and further to the gate voltages GM1 and GM2.

[0137] The high-speed turn-off circuit 60 turns off the power MISFET 9 at high speed with a second gate discharge capability higher than the first gate discharge capability of the drive signal output circuit 40 in response to the abnormality detection signal DET (e.g., an overcurrent protection signal or an overheat protection signal).

[0138] Referring to the figure, the high-speed turn-off circuit 60 includes a transistor M3 (e.g., an N-channel MISFET). The drain of the transistor M3 is connected to the gate of the power MISFET 9. The source of the transistor M3 is connected to the source of the power MISFET 9 (=the application terminal of the output voltage VOUT). The gate of the transistor M3 is connected to the application terminal of the abnormality detection signal DET.

[0139] The transistor M3 connected in this manner connects / disconnects the gate and source of the power MISFET 9 in response to the abnormality detection signal DET.

[0140] For example, when the abnormality detection signal DET is at a high level (=the logical level when an abnormality is detected), the transistor M3 is turned on, and therefore the gate discharge path of the drive signal output circuit 40 (=the transistor M2 and the current source CS2 connected in series between the gate and source of the power MISFET 9) is bypassed by the transistor M3.

[0141] As a result, the gate drive signal VG is pulled down to a low level (≈VOUT) without delay via the transistor M3 without relying on the drive signal output circuit 40. Therefore, the power MISFET 9 is turned off at high speed in a shorter time than in a normal turn-off using the drive signal output circuit 40.

[0142] On the other hand, when the abnormality detection signal DET is at a low level (= the logical level when no abnormality is detected), the transistor M3 is turned off, and therefore, there is no problem with the charge / discharge control of the gate drive signal VG by the drive signal output circuit 40.

[0143] 13 is a diagram showing the turn-off behavior of the semiconductor device 1 of the third embodiment (FIG. 12). The solid line represents the drain-source voltage Vds of the power MISFET 9. The small dashed line represents the output current IOUT flowing through the power MISFET 9. The large dashed line represents the power consumption Pc (=IOUT×Vds) of the power MISFET 9.

[0144] For example, when a ground fault occurs in the source electrode 12 (=output electrode OUT), the power MISFET 9 is forcibly turned off by an abnormality protection operation (for example, an overcurrent protection operation or an overheat protection operation). When the drain-source voltage Vds of the power MISFET 9 reaches a predetermined maximum peak value (=active clamp voltage Vclp) as a result of the forcible turning off of the power MISFET 9, the active clamp circuit 26 operates to return the power MISFET 9 to an on state (strictly speaking, a state in which the power MISFET 9 is not fully turned off).

[0145] The power MISFET 9 is maintained in the on state until the inductive energy stored in the inductance component of the load short-circuit path is dissipated (which may also be understood as regeneration, absorption, or consumption). Here, the semiconductor device 1 needs to turn the power MISFET 9 off and then back on so that the inductive energy stored in the inductance component of the load short-circuit path (= the total energy that needs to be safely dissipated) when the power MISFET 9 is turned off is minimized. Furthermore, the semiconductor device 1 needs to control the turn-off of the power MISFET 9 so that the instantaneous maximum junction temperature does not exceed the absolute maximum rating.

[0146] In the semiconductor device 1 of this embodiment, the maximum peak value of the power consumption Pc becomes relatively large due to the high-speed turn-off of the power MISFET 9. However, when the maximum value of the drain-source voltage Vds (=active clamp voltage Vclp) remains the same, the clamp time tclp (=degauss time) required to completely dissipate all of the inductive energy stored in the inductance component of the load short-circuit path is shortened in accordance with Faraday's law.

[0147] Therefore, the total power consumption (total energy) that needs to be safely dissipated by the active clamp operation is reduced, resulting in a lower maximum junction temperature of the power MISFET 9. Thus, the introduction of the high-speed turn-off circuit 60 makes it possible to improve the harness ground fault resistance.

[0148] <Start-up Failure Caused by High-Speed ​​Turn-Off> Fig. 14 is a diagram showing the startup behavior of the semiconductor device 1 according to the third embodiment (Fig. 12). Fig. 15 is a partially enlarged view of a portion (a dashed-dotted line frame α) of Fig. 14. In both figures, the power supply voltage VB, the output voltage VOUT, and the output current IOUT are depicted from top to bottom.

[0149] At time t11, the semiconductor device 1 is started up in the capacitive load drive mode. As described above, in the capacitive load drive mode, the output current IOUT is limited to be equal to or less than the overcurrent protection threshold Iocp (=Iocp2<Iocp1), and the power MISFET 9 is repeatedly forced off and restarted every time the monitored temperature (for example, the aforementioned temperature difference ΔTemp) rises up to the overheat protection threshold Ttsd (=Ttsd2<Ttsd1).

[0150] Here, if the above-mentioned high-speed turn-off is performed when the power MISFET 9 is forcibly turned off, overshoot and undershoot of the output voltage VOUT occur. Furthermore, if the output current IOUT increases sharply when the power MISFET 9 is restarted, the power supply voltage VB may drop transiently.

[0151] Due to the above behavior, when the output voltage VOUT exceeds the threshold voltage Vth (=VB-Vx) at time t12, the semiconductor device 1 returns from the capacitive load drive mode to the normal mode earlier than normal. At this time, the overcurrent protection operation switches to the hiccup operation described above. Therefore, depending on the load being driven, the output voltage VOUT may not rise to the desired value (≈power supply voltage VB).

[0152] In particular, when a wire harness is connected to the drain electrode 11 (=power supply electrode VBB) and the source electrode 12 (=output electrode OUT), the drain-source voltage Vds of the power MISFET 9 is likely to decrease, which may accelerate the timing of switching from the capacitive load drive mode to the normal mode, resulting in a start-up failure of the capacitive load.

[0153] In the following, in view of the above considerations, a fourth embodiment capable of eliminating start-up failure of a capacitive load will be proposed.

[0154] 16 is a diagram showing a fourth embodiment of the semiconductor device 1. In the semiconductor device 1 of this embodiment, an overcurrent protection circuit 34 detects an output current IOUT flowing through a power MISFET 9 (corresponding to an output switch) and applies overcurrent protection.

[0155] Referring to this figure, the overcurrent protection circuit 34 includes a detection circuit 341, a control circuit 342, and an output circuit 343 as components for performing an overcurrent protection operation after the capacitive load drive mode ends, more specifically, for performing forced-off control of the power MISFET 9 including the above-mentioned hiccup operation.

[0156] The detection circuit 341 outputs an internal signal S11 corresponding to the result of comparison between the output current IOUT and the overcurrent protection threshold IocpH, for example, after the mode control signal S1 output from the mode control circuit 53 falls from high to low. The detection circuit 341 may also receive an input of a sense voltage Vs (∝IOUT) corresponding to the output current IOUT.

[0157] The mode control circuit 53 may raise the mode control signal S1 to a high level when an instruction to turn on the power MISFET 9 is given, for example, when the input electrode 13 (=input electrode IN) is set to a high level. On the other hand, the mode control circuit 53 may lower the mode control signal S1 to a low level when the drain-source voltage Vds of the power MISFET 9 falls below the detection threshold Vx (=the above-mentioned bias voltage Vx).

[0158] That is, in the semiconductor device 1 of this embodiment, the mode control signal S1 goes high in the capacitive load drive mode described above, and goes low after the capacitive load drive mode ends. In this way, the logic level of the mode control signal S1 may be reversed from that shown in the second embodiment (FIGS. 9 to 11).

[0159] For example, the internal signal S11 goes high when the output current IOUT is greater than the overcurrent protection threshold IocpH. On the other hand, the internal signal S11 goes low when the output current IOUT is smaller than the overcurrent protection threshold IocpH. However, when the mode control signal S1 is high, the internal signal S11 is fixed (masked) at low.

[0160] The overcurrent protection threshold IocpH may be set to a value (for example, 90 A) greater than the overcurrent protection threshold IocpL (for example, 60 A) set in the capacitive load driving mode. The overcurrent protection threshold IocpH may have hysteresis.

[0161] The control circuit 342 outputs an internal signal S12 upon receiving, for example, the mode control signal S1 and the count completion signal S2 output from the mode control circuit 53, and the internal signal S11 output from the detection circuit 341. The internal configuration and operation of the control circuit 342 will be described later.

[0162] 17 is a diagram showing an example of generating the count end signal S2. This diagram illustrates the terminal voltages (IN / CMODE) of the input electrode 13 and the CMODE enable electrode 51, the mode control signal S1, and the count end signal S2.

[0163] At time t31, when a high-level terminal voltage (IN / CMODE) is applied to each of the input electrode 13 and the CMODE enable electrode 51, the mode control signal S1 rises to a high level, and the semiconductor device 1 enters the capacitive load driving mode.

[0164] At time t31, the mode control circuit 53 starts counting a time T1 (for example, 50 ms). A CR timer or the like may be used as the time measuring means for the time T1.

[0165] At time t32, when the count of time T1 expires, the mode control signal S1 is pulled down to low level. That is, the capacitive load driving mode is terminated not only when the drain-source voltage Vds of the power MISFET 9 falls below the detection threshold Vx, but also when time T1 has elapsed. In this case, the semiconductor device 1 transitions from the capacitive load driving mode to the normal mode without passing through the intermediate mode (details of which will be described later).

[0166] In addition, a pulse is generated in the count completion signal S2 when a time T1 has elapsed since the power MISFET 9 was instructed to be turned on.

[0167] 16, the main parts of the overcurrent protection circuit 34 will be described. The output circuit 343 receives the internal signals S11 and S12 and outputs a forced-off signal S34 for the power MISFET 9.

[0168] For example, the forced-off signal S34 goes low when the internal signal S11 is high, and goes high when the internal signal S11 is low. The forced-off signal S34 is maintained at low for a time T2 (e.g., 50 ms) after a pulse is generated in the internal signal S12 (details will be described later).

[0169] For example, when the forced-off signal S34 is at a low level, the drive signal output circuit 40 forcibly turns off the power MISFET 9. On the other hand, when the forced-off signal S34 is at a high level, the drive signal output circuit 40 cancels the forced-off of the power MISFET 9.

[0170] Although not explicitly shown in the figure, the overcurrent protection circuit 34 also includes components for performing an overcurrent protection operation in the capacitive load drive mode, more specifically, a current limiting operation for limiting the output current IOUT to an overcurrent protection threshold Iocp or less by lowering the gate drive signal VG of the power MISFET 9.

[0171] 18 is a diagram showing an example of the configuration of the control circuit 342. The control circuit 342 of this example configuration includes a logical product operator AND, D flip-flops FF1 to FF4, inverters INV1 to INV3, a multiplexer MUX, and a non-logical sum operator NOR.

[0172] The D flip-flop FF1 latches the inverted output signal XQ1 input to the data terminal (D) when the internal signal S11 input to the clock terminal (>) rises to high level, and outputs it as the output signal Q1 from the output terminal (Q). Also, the D flip-flop FF1 resets the output signal Q1 to low level when the reset signal RST input to the reset terminal (o) falls to low level.

[0173] The D flip-flop FF2 latches the inverted output signal XQ2 input to the data terminal (D) when the inverted output signal XQ1 input to the clock terminal (>) rises to high level, and outputs it as the output signal Q2 from the output terminal (Q). Also, the D flip-flop FF2 resets the output signal Q2 to low level when the reset signal RST input to the reset terminal (o) falls to low level.

[0174] The D flip-flop FF3 latches the inverted output signal XQ3 input to the data terminal (D) when the inverted output signal XQ2 input to the clock terminal (>) rises to high level, and outputs it as the output signal Q3 from the output terminal (Q). Also, the D flip-flop FF3 resets the output signal Q2 to low level when the reset signal RST input to the reset terminal (o) falls to low level.

[0175] For example, when the mode control signal S1 input to the clock terminal (>) rises to a high level, the D flip-flop FF4 latches the high-level signal VH input to the data terminal (D) and outputs it as an output signal Q4 from the output terminal (Q). Also, the D flip-flop FF4 resets the output signal Q4 to a low level when the intermediate mode completion signal S22 input to the reset terminal (o) falls to a low level.

[0176] The inverter INV1 inverts the logic level of the output signal Q1 to generate an inverted output signal XQ1.

[0177] The inverter INV2 inverts the logic level of the output signal Q2 to generate an inverted output signal XQ2.

[0178] The inverter INV3 inverts the logic level of the output signal Q3 to generate an inverted output signal XQ3.

[0179] The logical product operator AND performs a logical product operation on each of the output signals Q1 to Q3 to generate an upper limit number reached signal S21. The upper limit number reached signal S21 goes high when all of the output signals Q1 to Q3 are at high level. The upper limit number reached signal S21 goes low when at least one of the output signals Q1 to Q3 is at low level.

[0180] Among the above components, the n-stage (n is an integer of 1 or more, for example, n=3 in this figure) D flip-flops FF1 to FF3 and inverters INV1 to INV3, and the AND logic unit AND are configured such that the number of pulses of the internal signal S11 is equal to or greater than the upper limit of 2. ｎ A counter CNT is formed that generates a pulse in the upper limit count reaching signal S21 when the count reaches -1 (7 in this figure).

[0181] The NOR logic unit NOR generates an intermediate mode expiration signal S22 by performing a NOR logic operation on the count expiration signal S2 and the upper limit number reached signal S21. The intermediate mode expiration signal S22 goes low when at least one of the count expiration signal S2 and the upper limit number reached signal S21 is high. The intermediate mode expiration signal S22 goes high when both the count expiration signal S2 and the upper limit number reached signal S21 are low.

[0182] The multiplexer MUX selects and outputs either the output signal Q1 or the upper limit count reached signal S21 as the internal signal S12 in response to the output signal Q4. The output signal Q1 can be understood as a signal synchronized with the internal signal S11. However, the internal signal S11 itself may be input to the multiplexer MUX instead of the output signal Q1.

[0183] 1, when the output signal Q4 is at a high level, the multiplexer MUX selects and outputs the upper limit number reached signal S21 as the internal signal S12. The output signal Q4 is kept at a high level until the time T1 has elapsed since the mode control signal S1 was raised to a high level as an instruction to turn on the power MISFET 9, at which point the count completion signal S2 is raised to a high level, or until the number of pulse generation times of the internal signal S11 reaches the upper limit and a pulse is generated in the upper limit number reached signal S21, whichever comes first.

[0184] On the other hand, when the output signal Q4 is at a low level, the multiplexer MUX selects and outputs the output signal Q1 as the internal signal S12. The output signal Q4 is reset to a low level at the earlier of the time T1 when the count completion signal S2 rises to a high level after the mode control signal S1 rises to a high level as an instruction to turn on the power MISFET 9, or the time when the number of pulse generation times of the internal signal S11 reaches the upper limit and a pulse is generated in the upper limit number reach signal S21.

[0185] 19 is a diagram showing an example of generation of the upper limit count reached signal S21 by the counter CNT. In this diagram, from top to bottom, the internal signal S11, the output signals Q1 to Q3, and the upper limit count reached signal S21 are depicted.

[0186] At time t41, when the first pulse is generated in the internal signal S11, the output signal Q1 rises to a high level. Meanwhile, the output signals Q2 and Q3 are both maintained at a low level. Therefore, the upper limit count reached signal S21 goes low.

[0187] At time t42, when a second pulse is generated in the internal signal S11, the output signal Q2 rises to a high level. Meanwhile, the output signal Q2 falls to a low level, and the output signal Q3 remains at a low level. Therefore, the upper limit count reached signal S21 goes low.

[0188] At time t43, when the third pulse is generated in the internal signal S11, the output signal Q1 rises to high level again. At this time, the output signal Q2 is maintained at high level, but the output signal Q3 is maintained at low level. Therefore, the upper limit count reached signal S21 goes low level.

[0189] At time t44, when the fourth pulse is generated in the internal signal S11, the output signal Q3 rises to a high level. Meanwhile, the output signals Q1 and Q2 both fall to a low level. Therefore, the upper limit count reached signal S21 goes low.

[0190] At time t45, when the fifth pulse is generated in the internal signal S11, the output signal Q1 rises to high level again. At this time, the output signal Q3 is maintained at high level, but the output signal Q2 is maintained at low level. Therefore, the upper limit count reached signal S21 goes low level.

[0191] At time t46, when the sixth pulse is generated in the internal signal S11, the output signal Q2 rises to high level again. At this time, the output signal Q3 is maintained at high level, but the output signal Q1 falls to low level. Therefore, the upper limit count reached signal S21 goes low level.

[0192] At time t47, when the seventh pulse is generated in the internal signal S11, the output signal Q1 rises to high level again. At this time, the output signals Q2 and Q3 are maintained at high level. Therefore, the upper limit count reached signal S21 rises to high level.

[0193] In this way, when the number of pulses generated by the internal signal S11 reaches the upper limit (7 times), a pulse is generated in the upper limit reached signal S21. Note that the upper limit can be adjusted as desired by increasing or decreasing the number of D flip-flops that form the counter CNT.

[0194] 20 is a diagram showing an example of mode transitions in the fourth embodiment. From the top, the diagram depicts the mode control signal S1, the internal signals S11 and S12, the forced-off signal S34, and the operation mode. The operation modes depicted in the diagram are a capacitive load drive mode (CMODE), an intermediate mode (MID), and a normal mode (NORMAL).

[0195] Before time t51, the mode control signal S1 is at a high level. Therefore, the semiconductor device 1 is in the capacitive load drive mode (CMODE). The mode control signal S1 is maintained at a high level until a time T1 has elapsed since the power MISFET 9 was instructed to be turned on, or until the drain-source voltage Vds of the power MISFET 9 falls below the detection threshold Vx, whichever comes first.

[0196] In the above-described capacitive load drive mode (S1=H), the overcurrent protection circuit 34 limits the output current IOUT to an overcurrent protection threshold IocpL (e.g., 60 A) or less. Furthermore, the overheat protection circuit 36 ​​forcibly turns off the power MISFET 9 when the monitored temperature (e.g., the aforementioned temperature difference ΔTemp) exceeds the overheat protection threshold TtsdL (e.g., 30° C.). On the other hand, the overheat protection circuit 36 ​​cancels the forced turn-off of the power MISFET 9 when the monitored temperature falls below the overheat protection threshold TtsdL. In this way, the overcurrent protection operation and the overheat protection operation in the capacitive load drive mode (S1=H) are as described above.

[0197] In the capacitive load drive mode (S1=H), the internal signal S11 is fixed at a low level. Therefore, the internal signal S12 also remains at a low level. As a result, the forced off signal S34 is maintained at a high level.

[0198] At time t51, the drain-source voltage Vds of the power MISFET 9 falls below the detection threshold Vx before the lapse of time T1 (S2=L) from the instruction to turn on the power MISFET 9, and as a result, the mode control signal S1 is lowered to the low level. After this, the semiconductor device 1 is in the intermediate mode (MID) until either the lapse of time T1 or the time when the number of pulse generation times of the internal signal S11 reaches the upper limit value (four times in this figure), whichever comes first (time t54 in this figure).

[0199] The time when the time T1 has elapsed may be interpreted as the time when the count completion signal S2 rises to a high level, and the time when the number of pulses generated by the internal signal S11 reaches the upper limit may be interpreted as the time when a pulse is generated in the upper limit number reached signal S21.

[0200] When the capacitive load drive mode is released (S1=L) at time t51, the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd are increased (e.g., from 60 A to 90 A and from 30° C. to 60° C.), respectively. In addition, the output slew rate SR of the gate drive signal VG may be increased (e.g., from 1.5 A / μs to 7 A / μs).

[0201] At time t51, when the output current IOUT exceeds the overcurrent protection threshold IocpH (e.g., 90 A), a first pulse is generated in the internal signal S11. As a result, the forced-off signal S34 falls to low level. Therefore, the power MISFET 9 is forced off and the output current IOUT is cut off.

[0202] However, at this point, the number of pulses generated by the internal signal S11 has not yet reached the upper limit (four). Therefore, even if a pulse is generated in the internal signal S11, the internal signal S12 is maintained at a low level. Therefore, the forced-off signal S34 is not maintained at a low level for the entire time T2 (e.g., 50 ms). In other words, the normal hiccup operation triggered by the internal signal S12 is not performed.

[0203] When the output current IOUT is cut off at time t51, the output current IOUT falls below the overcurrent protection threshold IocpH, causing the internal signal S11 to fall to low level. As a result, the forced-off signal S34 rises to high level, and the forced-off of the power MISFET 9 is released.

[0204] At times t52 and t53, the second and third pulses are generated in the internal signal S11 each time the output current IOUT exceeds the overcurrent protection threshold IocpH. However, the number of pulses generated in the internal signal S11 has not yet reached the upper limit (four). Therefore, similar to time t51, the normal hiccup operation is not performed, and the power MISFET 9 is repeatedly forced to be turned off and released depending on the comparison result between the output current IOUT and the overcurrent protection threshold IocpH.

[0205] Thereafter, at time t54, when the number of pulses generated by the internal signal S11 reaches the upper limit (four), the upper limit reached signal S21 (and hence the internal signal S12) rises to a high level. Therefore, the forced-off signal S34 is maintained at a low level for a period of time T2. That is, a normal hiccup operation triggered by the internal signal S12 is performed. In other words, after time t54, the semiconductor device 1 enters the normal mode (NORMAL).

[0206] At time t55, when the time T2 has elapsed, the forced-off signal S34 rises to high level, releasing the forced-off of the power MISFET 9. As a result, the output current IOUT starts to flow again.

[0207] At time t56, when the output current IOUT exceeds the overcurrent protection threshold IocpH, the internal signal S11 rises to a high level. Since the aforementioned time t55, the multiplexer MUX has been in a state of selecting and outputting the output signal Q1 (or the internal signal S11) as the internal signal S12. Therefore, when the internal signal S11 rises to a high level, the internal signal S12 also rises to a high level without delay. As a result, the forced-off signal S34 is again maintained at a low level for the time T2. In other words, the normal hiccup operation triggered by the internal signal S12 continues.

[0208] In the intermediate mode (MID) described above, the intervals (times t51 to t52, t52 to t53, and t53 to t54) at which the power MISFET 9 is repeatedly forced off and released have a length (on the order of μs) according to the response speed of the detection circuit 341. Note that a length according to the response speed of the detection circuit 341 may result in an on / off cycle that is too short. In such a case, a delay on the order of μs may be added.

[0209] In this way, in the intermediate mode (MID), the power MISFET 9 is repeatedly forced off and released at shorter intervals than in the hiccup operation in the normal mode (NORMAL). Therefore, even if the capacitive load drive mode (CMODE) ends before the output voltage VOUT has risen sufficiently, the capacitive load can be charged without any problems.

[0210] Furthermore, after the capacitive load drive mode is terminated at time t51, the overheat protection circuit 36 ​​forcibly turns off the power MISFET 9 when the monitored temperature exceeds the overheat protection threshold TtsdH (e.g., 60°C). On the other hand, the overheat protection circuit 36 ​​cancels the forced turn-off of the power MISFET 9 when the monitored temperature falls below the overheat protection threshold TtsdH. In this manner, the overheat protection operation after the capacitive load drive mode is terminated (S1=L) is as described above. Note that the timing for switching the overheat protection threshold Ttsd may be the start timing of the normal mode (NORMAL) rather than the start timing of the intermediate mode (MID). In the latter case, safety is improved. However, the load drive capability may be reduced.

[0211] Therefore, although not explicitly shown in the figure, in the intermediate mode (MID), the intervals (times t51 to t52, t52 to t53, and t53 to t54) at which the power MISFET 9 is repeatedly forced off and released may have a length corresponding to the response speed of the overheat protection circuit 36. However, regardless of whether the intervals depend on the response speed of the detection circuit 341 or the overheat protection circuit 36, the intervals at which the power MISFET 9 is repeatedly forced off and released will be sufficiently short (on the order of μs) compared to the aforementioned time T2 (for example, 50 ms).

[0212] Also, this figure shows an example in which, after the capacitive load drive mode (CMODE) ends at time t51, the number of pulses generated by the internal signal S11 reaches the upper limit (four times) at time t54, resulting in a transition from the intermediate mode (MID) to the normal mode (NORMAL).

[0213] However, when the time T1 has elapsed since the instruction to turn on the power MISFET 9, the transition from the intermediate mode (MID) to the normal mode (NORMAL) is made even before the number of pulses generated by the internal signal S11 reaches the upper limit number.

[0214] 21 is a diagram showing a first example of the startup operation in the fourth embodiment. In this diagram, from top to bottom, the output voltage VOUT, the mode control signal S1, the overheat protection signal TSD, and the output current IOUT are depicted.

[0215] The overheat protection signal TSD goes to a high level when the monitored temperature is higher than the overheat protection threshold. On the other hand, the overheat protection signal TSD goes to a low level when the monitored temperature is lower than the overheat protection threshold. When the overheat protection signal TSD is at a high level, the power MISFET 9 is forced off. When the overheat protection signal TSD is at a low level, the forced off of the power MISFET 9 is released.

[0216] The simulation conditions for this figure are: inductance value Lwire of the wire harness = 0.1 μH; resistance value Rwire of the wire harness = 0.2 mΩ; power supply voltage VB = 14 V; and ambient temperature Ta = 25°C.

[0217] Under the above simulation conditions, the semiconductor device 1 is in the capacitive load drive mode (S1=H) from time t61 to t62. During this time, the capacitive load is sufficiently charged, and the output voltage VOUT rises to near the power supply voltage VB. Therefore, in this diagram, neither the overcurrent protection operation nor the overheat protection operation is activated after time t62. Therefore, the pulse drive of the power MISFET 9 in the aforementioned intermediate mode (MID) is not performed either.

[0218] 22 is a diagram showing a second example of the startup operation in the fourth embodiment. In this diagram, as in the above-mentioned FIG. 21, the output voltage VOUT, the mode control signal S1, the overheat protection signal TSD, and the output current IOUT are depicted in this order from top to bottom.

[0219] The simulation conditions in this figure are: inductance value L = 1 μH of the wire harness, resistance value R = 2 mΩ of the wire harness, power supply voltage V = 14 V, and ambient temperature Ta = 25° C. In other words, compared to the above-mentioned Figure 21, the inductance value L and resistance value R of the wire harness are each 10 times larger.

[0220] Under the above simulation conditions, the semiconductor device 1 is in the capacitive load drive mode (S1=H) from time t71 to t72. However, at time t72, the capacitive load drive mode ends before the output voltage VOUT rises sufficiently. As a result, in this diagram, after time t72, the overcurrent protection operation and the overheat protection operation are activated twice in the intermediate mode described above (see the circles for the output current IOUT). At this time, the power MISFET 9 is repeatedly forced off and released at intervals shorter than those of a normal hiccup operation. Therefore, after time t72, the output voltage VOUT rises to near the power supply voltage VB.

[0221] 23 is a diagram showing a third example of the startup operation in the fourth embodiment. In this diagram, as in the above-mentioned Figs. 21 and 22, the output voltage VOUT, the mode control signal S1, the overheat protection signal TSD, and the output current IOUT are depicted in this order from top to bottom.

[0222] The simulation conditions in this figure are a wire harness inductance value Lwire = 2.5 μH, a wire harness resistance value Rwire = 5 mΩ, a power supply voltage VB = 14 V, and an ambient temperature Ta = 25° C. In other words, compared to the previously mentioned FIG. 22, the wire harness inductance value Lwire and resistance value Rwire are further increased by 2.5 times.

[0223] Under the above simulation conditions, the semiconductor device 1 is in the capacitive load drive mode (S1=H) from time t81 to t82. However, at time t82, the capacitive load drive mode ends immediately after the output voltage VOUT begins to rise. As a result, in this diagram, after time t82, the overcurrent protection operation and overheat protection operation are activated five times in the intermediate mode described above (see the circles for the output current IOUT). At this time, the power MISFET 9 is repeatedly forced off and released at intervals shorter than those of a normal hiccup operation. Therefore, after time t82, the output voltage VOUT rises to near the power supply voltage VB.

[0224] Of the intervals at which the power MISFET 9 is repeatedly forced off and released, the relatively short intervals are due to the response speed of the detection circuit 231, and the relatively long intervals are due to the response speed of the overheat protection circuit 36.

[0225] <Application Example to Low-Side Switch IC> In the above embodiment, a high-side switch IC that replaces a mechanical fuse is illustrated, but the capacitive load drive mode can be implemented in a wide range of IPDs, for example.

[0226] For example, the above-mentioned power MISFET 9 may be provided as a low-side switch element that establishes / cuts conduction between an output electrode to which one end of a load is connected and a reference voltage electrode to which a reference voltage (for example, a ground voltage) is applied.

[0227] In this case, the mode control circuit 53 may set the operating mode to the capacitive load drive mode when the output voltage VOUT applied to the output electrode is higher than a predetermined threshold voltage Vth′, and may set the operating mode to the normal mode when the output voltage VOUT is lower than the threshold voltage Vth′.

[0228] The threshold voltage Vth′ may be a voltage (=GND+Vy) generated based on a reference voltage (e.g., a ground voltage). That is, the threshold voltage Vth′ may be different from the aforementioned threshold voltage Vth (=VB−Vx) generated based on the power supply voltage VB.

[0229] <Application to Vehicles> Fig. 24 is an external view showing an example of the configuration of a vehicle. The vehicle X of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0230] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0231] The semiconductor device 1 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0232] <Additional Notes> The following additional notes are provided regarding the above disclosure: According to the present disclosure, it is possible to appropriately drive a capacitive load without impairing the fault protection function.

[0233] [Supplementary Note 1] An output switch (9); and an overcurrent protection circuit (34) configured to detect an output current (IOUT) flowing through the output switch (9) and apply overcurrent protection, wherein the overcurrent protection circuit (34) operates to limit the output current (IOUT) to a first overcurrent protection threshold (IocpL) or less until a first time (T1) has elapsed since a command to turn on the output switch (9) has been issued, or until a voltage (Vds) across the output switch (9) falls below a detection threshold (Vx), whichever comes first; When the voltage (Vds) across the output switch (9) falls below the detection threshold (Vx) before the first time (T1) has elapsed since the output switch (9) was instructed to be turned on, if the output current (IOUT) exceeds a second overcurrent protection threshold (IocpH) that is greater than the first overcurrent protection threshold (IocpL), the output switch (9) is forcibly turned off, and if the output current (IOUT) falls below the second overcurrent protection threshold (IocpH), the forced turning off of the output switch (9) is canceled; The semiconductor device (1) operates to forcibly turn off the output switch (9) when the output current (IOUT) exceeds the second overcurrent protection threshold (IocpH) after the first time (T1) has elapsed since an instruction to turn on the output switch (9) has been issued or the number of times the output switch (9) is forcibly turned off after the voltage (Vds) across the output switch (9) falls below the detection threshold (Vx), whichever comes first, and to cancel the forcible turning off of the output switch (9) after the second time (T2) has elapsed.

[0234] [Supplementary Note 2] The overcurrent protection circuit (34) comprises: a detection circuit (341) configured to output a first internal signal (S11) according to a comparison result between the output current (IOUT) and the second overcurrent protection threshold (IocpH) after the voltage (Vds) across the output switch (9) falls below the detection threshold (Vx); and a control circuit (342) configured to generate a pulse in a second internal signal (S12) when the first time (T1) has elapsed since an instruction to turn on the output switch (9) has been issued or when the number of pulse generation times of the first internal signal (S11) reaches the upper limit, whichever comes first, and to output the first internal signal (S11) or a signal (Q1) synchronized therewith as the second internal signal (S12) after the time point. an output circuit (343) configured to receive the first internal signal (S11) and the second internal signal (S12) as inputs and generate a forced-off signal S34 for the output switch (9), wherein the forced-off signal (S34) is maintained at an off-state logic level for the second time (T1) after a pulse is generated in the second internal signal (S12).

[0235] [Supplementary Note 3] The semiconductor device (1) according to Supplementary Note 2, wherein the control circuit (342) includes: a counter (CNT) configured to generate a pulse in an upper limit count reached signal (S21) when the number of pulse generation times of the first internal signal (S11) reaches the upper limit value; and a multiplexer (MUX) configured to output the upper limit count reached signal (S21) as the second internal signal (S12) until the first time (T1) has elapsed since the output switch (9) was instructed to turn on or until a pulse is generated in the upper limit count reached signal (S21), whichever comes first, and to output the first internal signal (S11) or a signal (Q1) synchronized therewith as the second internal signal (S12) after that time.

[0236] [Supplementary Note 4] The semiconductor device (1) according to any one of Supplementary Notes 1 to 3, further comprising an overheat protection circuit (36) configured to detect monitored temperatures (Temp1, ΔTemp) and apply overheat protection.

[0237] [Supplementary Note 5] The overheat protection circuit (36) operates to forcibly turn off the output switch (9) when the monitored temperature (Temp1, ΔTemp) exceeds a first overheat protection threshold (TtsdL) until the first time (T1) has elapsed since the output switch (9) was instructed to be turned on or the voltage (Vds) across the output switch (9) falls below the detection threshold (Vx), whichever comes first, and to cancel the forcible turning off of the output switch (9) when the monitored temperature (Temp1, ΔTemp) falls below the first overheat protection threshold (TtsdL); The semiconductor device (1) according to Appendix 4 operates such that, after the first time (T1) has elapsed since an instruction to turn on the output switch (9) has been issued or the voltage (Vds) across the output switch (9) falls below the detection threshold (Vx), whichever comes first, the output switch (9) is forcibly turned off when the monitored temperature (Temp1, ΔTemp) exceeds a second overheat protection threshold (TtsdH) that is higher than the first overheat protection threshold (TtsdL), and the forced turning off of the output switch (9) is cancelled when the monitored temperature (Temp1, ΔTemp) falls below the second overheat protection threshold (TtsdH).

[0238] [Appendix 6] The semiconductor device (1) according to appendix 4 or 5, wherein the monitored temperature (Temp1, ΔTemp) is a first temperature (Temp1) detected in a power element region including the output switch (9), or a temperature difference (ΔTemp) between the first temperature (Temp1) and a second temperature (Temp2) detected outside the power element region.

[0239] [Supplementary Note 7] The semiconductor device (1) according to any one of Supplementary Notes 1 to 6, further comprising a high-speed turn-off circuit (60) configured to turn off the output switch (9) at a higher speed when an abnormality is detected than when no abnormality is detected.

[0240] [Appendix 8] The semiconductor device (1) according to any one of Appendices 1 to 7, wherein the output switch (9) is a high-side switch configured to establish / shut off conduction between a power supply electrode (11) and an output electrode (12), or a low-side switch configured to establish / shut off conduction between the output electrode (12) and a reference voltage electrode (14).

[0241] [Supplementary Note 9] An electronic device (B) comprising: a semiconductor device (1) according to any one of Supplementary Notes 1 to 8; and a load (B10) connected to the semiconductor device.

[0242] [Supplementary Note 10] A vehicle (X) equipped with the electronic device (B) according to Supplementary Note 9.

[0243] <Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0244] 1 Semiconductor device (high-side switch IC) 2 DC power supply 3 Load 9 Power MISFET (output switch) 10 Controller 11 Drain electrode (power supply electrode) 12 Source electrode (output electrode) 13 Input electrode 14 Reference voltage electrode 15 Enable electrode 16 Sense electrode 17 Gate control wiring 21 Sensor MISFET 22 Input circuit 23 Current / voltage control circuit 24 Protection circuit 25 Gate control circuit 26 Active clamp circuit 27 Current detection circuit 28 Power supply reverse connection protection circuit 29 Abnormality detection circuit 30 Drive voltage generation circuit 31 First constant voltage generation circuit 32 Second constant voltage generation circuit 33 Reference voltage / reference current generation circuit 34 Overcurrent protection circuit 341 Detection circuit 342 Control circuit 343 Output circuit 35 Load open detection circuit 36 ​​Overheat protection circuit 37 Undervoltage malfunction suppression circuit 38 Oscillator circuit 39 Charge pump circuit 40 Drive signal output circuit 41 First multiplexer circuit 42 Second multiplexer circuit 51 CMODE enable electrode 52 Input circuit 53 Mode control circuit 60 High-speed turn-off circuit A Electronic device AND Logical product operator B Electronic device B10 Control unit (ECU) B11 DC / DC converter B12 Microcomputer B13 Upper switch B14 Power supply electrode B15 Output electrode B16 Reference voltage electrode B20 Battery B30 Load B40 Fuse box B41(1) to B41(n) Fuses B42 Input electrode B43(1) to B43(n) Output electrode C1 Capacitor CNT Counter CS1, CS2 Current sources FF1 to FF4 D flip-flops INV1 to INV3 InvertersL, L11, L12: Inductance components M1 to M3: Transistors MUX: Multiplexer NOR: Negative OR operator R, R11, R12: Resistance components R1, R2: Resistors W1 to W3: Wires X: Vehicle

Claims

1. A device comprising: an output switch; and an overcurrent protection circuit configured to detect an output current flowing through the output switch and apply overcurrent protection thereto, wherein the overcurrent protection circuit operates to limit the output current to a first overcurrent protection threshold or less until a first time has elapsed since an instruction to turn on the output switch is issued or until a voltage across the output switch falls below a detection threshold, whichever occurs first; and when the voltage across the output switch falls below the detection threshold before the first time has elapsed since an instruction to turn on the output switch is issued, the device operates to forcibly turn off the output switch when the output current exceeds a second overcurrent protection threshold that is higher than the first overcurrent protection threshold, and to release the forcible turning off of the output switch when the output current falls below the second overcurrent protection threshold, a first time period after an instruction to turn on the output switch has elapsed or a number of times the output switch has been forcibly turned off since the voltage across the output switch has fallen below the detection threshold has reached an upper limit, whichever comes first, and the output switch is forcibly turned off when the output current exceeds the second overcurrent protection threshold, and the forced turning off of the output switch is released when a second time period has elapsed.

2. The semiconductor device according to claim 1, wherein the overcurrent protection circuit includes: a detection circuit configured to output a first internal signal according to a comparison result between the output current and the second overcurrent protection threshold value after the voltage across the output switch falls below the detection threshold; a control circuit configured to generate a pulse in a second internal signal at the earlier of the first time elapsed after an instruction to turn on the output switch or the number of pulse generation times of the first internal signal reaching the upper limit value, and to output the first internal signal or a signal synchronized therewith as the second internal signal after that time; and an output circuit configured to receive inputs of the first internal signal and the second internal signal, and to output a forced-off signal for the output switch, wherein the forced-off signal is maintained at an off logical level for the second time period after a pulse is generated in the second internal signal.

3. The semiconductor device according to claim 2, wherein the control circuit comprises: a counter configured to generate a pulse in an upper limit reached signal when the number of pulse generation times of the first internal signal reaches the upper limit; and a multiplexer configured to output the upper limit reached signal as the second internal signal until the first time has elapsed since the output switch is instructed to be turned on or a pulse is generated in the upper limit reached signal, whichever comes first, and to output the first internal signal or a signal synchronized therewith as the second internal signal after that time.

4. The semiconductor device according to claim 1, further comprising an overheat protection circuit configured to detect a monitored temperature and activate overheat protection.

5. The semiconductor device according to claim 4, wherein the overheat protection circuit operates to forcibly turn off the output switch when the monitored temperature exceeds a first overheat protection threshold until the first time has elapsed since the output switch was instructed to turn on or the voltage across the output switch falls below the detection threshold, whichever occurs first, and to forcibly turn off the output switch when the monitored temperature falls below the first overheat protection threshold, after the first time has elapsed since the output switch was instructed to turn on or the voltage across the output switch falls below the detection threshold, whichever occurs first, and to forcibly turn off the output switch when the monitored temperature exceeds a second overheat protection threshold higher than the first overheat protection threshold, and to cancel the forced off of the output switch when the monitored temperature falls below the second overheat protection threshold.

6. The semiconductor device according to claim 4 or 5, wherein the monitored temperature is a first temperature detected in a power element region including the output switch, or a temperature difference between the first temperature and a second temperature detected outside the power element region.

7. The semiconductor device according to claim 1, further comprising a high-speed turn-off circuit configured to turn off said output switch when an abnormality is detected faster than when no abnormality is detected.

8. A semiconductor device according to any one of claims 1 to 7, wherein the output switch is a high-side switch configured to establish / cut off conduction between a power supply electrode and an output electrode, or a low-side switch configured to establish / cut off conduction between an output electrode and a reference voltage electrode.

9. An electronic device comprising: a semiconductor device according to any one of claims 1 to 8; and a load connected to the semiconductor device.

10. A vehicle comprising the electronic device according to claim 9.

Images