Display panel, smart glass comprising same, and manufacturing method thereof

Abstract

A display panel may be provided, the display panel comprising: an a-first electrode electrically connected to a pixel circuit of a first pixel and electrically connected to a first light-emitting layer in a first contact hole; a b-first electrode electrically connected to a pixel circuit of a second pixel and electrically connected to a second light-emitting layer in a second contact hole in which at least a portion of the first light-emitting layer is removed; a c-first electrode electrically connected a pixel circuit of a third pixel and electrically connected to a third light-emitting layer in a third contact hole in which at least a portion of the first and second light-emitting layers is removed; and a second electrode electrically connected to the pixel circuit of each of the first to third pixels, and connected to the first to third light-emitting layers in a fourth contact hole in which at least a portion of the first to third light-emitting layers is removed.

Description

Display panel, smart glass including same, and method for manufacturing same

[0001] Embodiments of the present disclosure relate to a display panel, a smart glass including the same, and a method of manufacturing the same.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting display devices (OLEDs) is increasing.

[0003] As the display device displays images in an area close to the user's eyes, a high-resolution and thin display device (or display panel) is required.

[0004] It should be understood that such background information is intended to provide useful context for understanding the technology. Background information may include ideas, concepts, or insights that were not part of what was known or understood by those skilled in the art prior to the effective filing date of the disclosed subject matter.

[0005] The technical challenge to be solved is to provide a display panel capable of displaying high-resolution images, smart glasses including the same, and a method for manufacturing the same.

[0006] The technical challenge to be solved is to provide a thin display panel, smart glass including the same, and a method for manufacturing the same.

[0007] A display panel according to embodiments of the present disclosure may include a substrate in which a first pixel emitting light of a first wavelength band, a second pixel emitting light of a second wavelength band, and a third pixel emitting light of a third wavelength band are arranged, and each of the first to third pixels includes a pixel circuit. The display panel may further include a first light-emitting layer positioned on the substrate and emitting light of a first wavelength band, a second light-emitting layer positioned on the first light-emitting layer and emitting light of a second wavelength band, and a third light-emitting layer positioned on the second light-emitting layer and emitting light of a third wavelength band. The display panel may include an a-first electrode electrically connected to a pixel circuit of a first pixel and electrically connected to a first light-emitting layer in a first contact hole, a b-first electrode electrically connected to a pixel circuit of a second pixel and electrically connected to the second light-emitting layer in a second contact hole from which at least a portion of the first light-emitting layer has been removed, a c-first electrode electrically connected to a pixel circuit of a third pixel and electrically connected to the third light-emitting layer in a third contact hole from which at least a portion of the first and second light-emitting layers has been removed, and a second electrode electrically connected to the pixel circuits of each of the first to third pixels and electrically connected to the first to third light-emitting layers in a fourth contact hole from which at least a portion of the first to third light-emitting layers has been removed.

[0008] The first light-emitting layer may include a first semiconductor layer that provides electrons, a second semiconductor layer that provides holes, and an active layer positioned between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer may be electrically connected to one of the a-first electrode and the second electrode, and the second semiconductor layer may be electrically connected to the other of the a-first electrode and the second electrode.

[0009] The thickness of the first semiconductor layer may be thicker than the thickness of the second semiconductor layer. The first semiconductor layer may be electrically connected to the second electrode, and the second semiconductor layer may be electrically connected to the a-first electrode.

[0010] The display panel may include a passivation layer positioned on a substrate and covering side surfaces of the a-th to c-th first electrodes, a first insulating layer positioned on the passivation layer, a first transparent conductive layer positioned between the passivation layer and the first light-emitting layer, and to which the a-th first electrode is electrically connected in a region where at least a portion of the passivation layer is removed. The display panel may further include a second insulating layer positioned on a second light-emitting layer, a second transparent conductive layer positioned between the second insulating layer and the second light-emitting layer, and to which the b-th first electrode is electrically connected in a region where at least a portion of the passivation layer is removed, a third insulating layer positioned on the second light-emitting layer, and a third transparent conductive layer positioned between the third insulating layer and the third light-emitting layer, and to which the c-th first electrode is electrically connected in a region where at least a portion of the passivation layer is removed.

[0011] The display panel may further include a light-shielding layer positioned in via holes surrounded by a passivation layer. The via holes may include a first via hole positioned in an area where at least a portion of the first insulating layer, the first transparent conductive layer, the first light-emitting layer, the second insulating layer, the second transparent conductive layer, the second light-emitting layer, the third insulating layer, the third transparent conductive layer, and the third light-emitting layer is removed, a second via hole positioned in an area where at least a portion of the first insulating layer, the first transparent conductive layer, the first light-emitting layer, the second insulating layer, the second transparent conductive layer, and the second light-emitting layer is removed, and a third via hole positioned in an area where at least a portion of the first insulating layer, the first transparent conductive layer, and the first light-emitting layer is removed.

[0012] The light-shielding layer can be formed using at least one of an electrolytic plating process and a deposition process.

[0013] The shading layer can be planarized on the passivation layer.

[0014] The first wavelength band may be a red wavelength band, the second wavelength band may be a green wavelength band, and the third wavelength band may be a blue wavelength band.

[0015] Each of the first to third insulating layers may include an inorganic insulating layer.

[0016] Embodiments of the present disclosure may provide a method for manufacturing a display panel. The method may include a step of forming a third light-emitting layer, a third transparent conductive layer, a third insulating layer, a second light-emitting layer, a second transparent conductive layer, a second insulating layer, a first light-emitting layer, a first transparent conductive layer, and a first insulating layer on a temporary substrate. The method may further include a step of forming a first via hole, a second via hole, and a third via hole on the first insulating layer, wherein the first via hole exposes at least a portion of the third light-emitting layer, the second via hole exposes at least a portion of the second light-emitting layer, and the third via hole exposes at least a portion of the first light-emitting layer. The method may further include a step of forming a first passivation layer surrounding the first to third via holes and a step of forming a first contact hole, a second contact hole, and a third contact hole on the first passivation layer, wherein the first contact hole exposes at least a portion of the third transparent conductive layer, the second contact hole exposes at least a portion of the second transparent conductive layer, and the third contact hole exposes at least a portion of the first transparent conductive layer. The method may further include a step of forming a second passivation layer surrounding the first to third contact holes, a step of removing the second passivation layer from an area corresponding to the first to third contact holes, and a step of forming a fourth contact hole on the second passivation layer. The method may provide a method for manufacturing a display panel, including the steps of forming a c-th first electrode in a first contact hole, forming a b-th first electrode in a second contact hole, forming an a-th first electrode in the first contact hole, and forming a second electrode in a second contact hole, electrically connecting the a-th to c-th first electrodes and the second electrode to a pixel circuit of the substrate, and detaching a temporary substrate.

[0017] The step of forming first to third via holes on the first insulating layer may include the steps of forming a first photoresist including a first pattern on the first insulating layer, forming a first via hole exposing at least a portion of the third light-emitting layer in an area corresponding to the first pattern, and forming a second photoresist including a second pattern on the first insulating layer. The step of forming the first to third via holes on the first insulating layer may further include the steps of forming a second via hole exposing at least a portion of the second light-emitting layer in an area corresponding to the second pattern, forming a third photoresist including a third pattern on the first insulating layer, and forming a third via hole exposing at least a portion of the first light-emitting layer in an area corresponding to the third pattern.

[0018] The step of forming first to third contact holes on the first passivation layer may include the steps of forming a fourth photoresist including a fourth pattern on the first passivation layer, forming a first contact hole exposing at least a portion of the third transparent conductive layer in a region corresponding to the fourth pattern, and forming a fifth photoresist including a fifth pattern on the first passivation layer. The step of forming the first to third contact holes on the first passivation layer may further include the steps of forming a second contact hole exposing at least a portion of the second transparent conductive layer in a region corresponding to the fifth pattern, forming a sixth photoresist including a sixth pattern on the first passivation layer, and forming a third contact hole exposing at least a portion of the first transparent conductive layer in a region corresponding to the sixth pattern.

[0019] The step of removing the second passivation layer in the area corresponding to the first to third contact holes may include the step of forming a seventh photoresist including a seventh pattern on the second passivation layer, the seventh pattern being formed by removing at least a portion of the seventh photoresist in the area corresponding to the first to third contact holes, and the step of removing the second passivation layer in the area corresponding to the seventh pattern.

[0020] The step of forming a fourth contact hole on the second passivation layer may include the step of forming an eighth photoresist including an eighth pattern on the second passivation layer, and the step of forming a fourth contact hole in an area corresponding to the eighth pattern.

[0021] The method may further include forming a light-shielding layer in an area corresponding to the first to third via holes in an area surrounded by the first passivation layer.

[0022] The shading layer can be formed using a damascene process.

[0023] The shading layer can be formed using at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0024] The first passivation layer and the second passivation layer can form one passivation layer.

[0025] The temporary substrate may be a third temporary substrate. The step of forming a third light-emitting layer, a third transparent conductive layer, a third insulating layer, a second light-emitting layer, a second transparent conductive layer, a second insulating layer, a first light-emitting layer, a first transparent conductive layer, and a first insulating layer on the temporary substrate may include the steps of growing the first light-emitting layer on the first temporary substrate, growing the second light-emitting layer on the second temporary substrate, growing the third light-emitting layer on the third temporary substrate, and forming a first intermediate insulating layer on the first light-emitting layer. The step of forming the third light-emitting layer, the third transparent conductive layer, the third insulating layer, the second light-emitting layer, the second transparent conductive layer, the second insulating layer, the first light-emitting layer, the first transparent conductive layer, and the first insulating layer on the temporary substrate may further include the steps of forming a second intermediate insulating layer on the second light-emitting layer, forming a third intermediate insulating layer on the third light-emitting layer, forming a fourth intermediate insulating layer on the fourth temporary substrate, and forming a fifth intermediate insulating layer on the fifth temporary substrate. The step of forming a third light-emitting layer, a third transparent conductive layer, a third insulating layer, a second light-emitting layer, a second transparent conductive layer, a second insulating layer, a first light-emitting layer, a first transparent conductive layer, and a first insulating layer on the temporary substrate may further include a step of forming a first insulating layer by bonding a first intermediate insulating layer and a fourth intermediate insulating layer, a step of forming a sixth intermediate insulating layer by bonding a second intermediate insulating layer and a fifth intermediate insulating layer, a step of detaching the first temporary substrate, and a step of detaching the second temporary substrate.The step of forming a third light-emitting layer, a third transparent conductive layer, a third insulating layer, a second light-emitting layer, a second transparent conductive layer, a second insulating layer, a first light-emitting layer, a first transparent conductive layer, and a first insulating layer on the temporary substrate may include a step of forming a seventh intermediate insulating layer on the first light-emitting layer, a step of forming an eighth intermediate insulating layer on the second light-emitting layer, a step of forming a third insulating layer by bonding the third intermediate insulating layer and the eighth intermediate insulating layer, a step of detaching the fifth temporary substrate, a step of forming a first insulating layer by bonding the sixth intermediate insulating layer and the seventh intermediate insulating layer, and a step of detaching the fourth temporary substrate.

[0026] Embodiments of the present disclosure may provide a smart glass including a lens unit that displays an image and a frame that supports the lens unit. The lens unit may include a first pixel that emits light of a first wavelength band, a second pixel that emits light of a second wavelength band, and a third pixel that emits light of a third wavelength band, and each of the first to third pixels may include a substrate including a pixel circuit. The lens unit may further include a first light-emitting layer positioned on the substrate and emitting light of the first wavelength band, a second light-emitting layer positioned on the first light-emitting layer and emitting light of the second wavelength band, and a third light-emitting layer positioned on the second light-emitting layer and emitting light of the third wavelength band. The lens unit may further include an a-first electrode connected to the pixel circuit of the first pixel and electrically connected to the first light-emitting layer in the first contact hole, a b-first electrode connected to the pixel circuit of the second pixel and electrically connected to the second light-emitting layer in the second contact hole from which at least a portion of the first light-emitting layer has been removed, a c-first electrode connected to the pixel circuit of the third pixel and electrically connected to the third light-emitting layer in the third contact hole from which at least a portion of the first and second light-emitting layers has been removed, and a second electrode connected to the pixel circuit of each of the first to third pixels and electrically connected to the first to third light-emitting layers in the fourth contact hole from which at least a portion of the first to third light-emitting layers has been removed.

[0027] According to the embodiments of the present disclosure, a display panel, a smart glass including the same, and a manufacturing method thereof, a high-resolution image can be displayed.

[0028] According to the embodiments of the present disclosure, the display panel, the smart glass including the same, and the manufacturing method thereof, the display panel can be manufactured in a thin shape.

[0029] FIG. 1 is a schematic plan view showing a display panel according to embodiments of the present disclosure.

[0030] FIG. 2 is a schematic equivalent circuit diagram of a pixel according to embodiments of the present disclosure.

[0031] FIG. 3 is a schematic cross-sectional view of a display panel according to embodiments of the present disclosure.

[0032] FIGS. 4A to 39 are schematic drawings for explaining a method of manufacturing a display panel according to embodiments of the present disclosure.

[0033] FIG. 40 is a schematic drawing showing a display panel manufactured according to FIGS. 4a to 39.

[0034] FIGS. 41 to 44 are schematic examples of electronic devices according to embodiments of the present disclosure.

[0035] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be implemented in various different forms and is not limited to the embodiments described herein.

[0036] To clearly explain the present invention, irrelevant parts have been omitted, and the same reference numerals are used to designate identical or similar components throughout the specification. Accordingly, the reference numerals described above may also be used in other drawings.

[0037] In addition, the size and thickness of each component shown in the drawing may be arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0038] As used herein, the terms "about" or "approximately" encompass values ​​and means within an acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0039] Additionally, the expression "same" in the description may mean "substantially the same." That is, it may be the same to the extent that a person with ordinary knowledge would be convinced that they are the same.

[0040] Terms such as a, b, c, first, and second may be used to describe various components, but these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0041] Terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0042] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0043] In this specification and claims, the term "and / or" is intended to include any combination of "and" and "or" for purposes of meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B." The terms "and" and "or" can be used in a conjunction or disjunction sense and can be understood to be equivalent to "and / or."

[0044] In the specification and claims, the phrase "at least one of" is intended, for purposes of meaning and interpretation, to include the meaning of "at least one selected from the group of." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. It is further understood that terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical context, and will not be interpreted in an idealized or overly formal sense unless specifically defined herein.

[0046] FIG. 1 is a schematic plan view showing a display panel (PNL) according to embodiments of the present disclosure.

[0047] In Fig. 1, a display device that can use a light-emitting element as a light source, and in particular, a display panel (PNL) provided in the display device, is illustrated.

[0048] For convenience of explanation, the structure of the display panel (PNL) is briefly illustrated in FIG. 1, focusing on the display area (DA). However, depending on the embodiment, at least one driving circuit unit (for example, at least one of a scan driving unit and a data driving unit), wires, and / or pads that are not illustrated may be further arranged on the display panel (PNL).

[0049] Referring to FIG. 1, a display panel (PNL) may include a substrate (SUB) and a unit pixel (PXU) disposed on the substrate (SUB). The unit pixel (PXU) may include a plurality of pixels (PXL). For example, the unit pixel (PXU) may include a first pixel (PXL1), a second pixel (PXL2), and a third pixel (PXL3). Hereinafter, when at least one of the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) is arbitrarily referred to, or when two or more types of pixels are comprehensively referred to, the term "pixel (PXL)" or "pixels (PXL)" will be used.

[0050] The substrate (SUB) constitutes the base member of the display panel (PNL), and may be a rigid or flexible substrate or film. For example, the substrate (SUB) may be a rigid substrate made of glass or tempered glass, or a flexible substrate (or thin film) made of plastic or metal, and the material and / or properties of the substrate (SUB) are not particularly limited. For example, the substrate (SUB) may be made of a silicon substrate.

[0051] A display panel (PNL) and a substrate (SUB) for forming the same may include a display area (DA) for displaying an image and a non-display area (NDA) excluding the display area (DA). Pixels (PXL) may be arranged in the display area (DA). Various wires, pads, and / or built-in circuits connected to the pixels (PXL) of the display area (DA) may be arranged in the non-display area (NDA). The pixels (PXL) may be formed in stripes or pentiles. TM ) can be arranged regularly according to the array structure, etc. However, the array structure of pixels (PXL) is not necessarily limited thereto, and pixels (PXL) can be arranged in the display area (DA) in various structures and / or methods.

[0052] According to an embodiment, two or more types of pixels (PXL) that emit light of different colors may be arranged in the display area (DA). For example, a first pixel (PXL1) that emits light of a first wavelength band (or a first color), a second pixel (PXL2) that emits light of a second wavelength band (or a second color), and a third pixel (PXL3) that emits light of a third wavelength band (or a third color) may be arranged in the display area (DA). At least one of the first to third pixels (PXL1, PXL2, PXL3) that are adjacent to each other may constitute one unit pixel (PXU) that can emit light of various colors. For example, the first to third pixels (PXL1, PXL2, PXL3) may each be a sub-pixel that emits light of a predetermined color. According to an embodiment, the first pixel (PXL1) may be a red pixel emitting light in a red wavelength band, the second pixel (PXL2) may be a green pixel emitting light in a green wavelength band, and the third pixel (PXL3) may be a blue pixel emitting light in a blue wavelength band, but is not necessarily limited thereto. The red wavelength band may be, for example, about 630 to about 750 nm (nanometer). The green wavelength band may be, for example, about 495 to about 570 nm. The blue wavelength band may be, for example, about 450 to about 495 nm.

[0053] In one embodiment, the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) each have light-emitting elements that emit light of the same color, and include color conversion layers and / or color filters of different colors disposed on the respective light-emitting elements, thereby emitting light of a first color, a second color, and a third color, respectively. In another embodiment, the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) each have light-emitting elements of a first color, a light-emitting element of a second color, and a light-emitting element of a third color as light sources, thereby emitting light of a first color, a second color, and a third color, respectively. However, the color, type, and / or number of the pixels (PXLs) constituting the unit pixel (PXU) are not particularly limited. That is, the color of the light emitted by each pixel (PXL) can be varied.

[0054] A pixel (PXL) may include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a predetermined power source (e.g., a first power voltage and a second power voltage).

[0055] In one embodiment, each pixel (PXL) may be configured as an active pixel. However, the type, structure, and / or driving method of the pixels (PXL) applicable to the display device is not particularly limited. For example, each pixel (PXL) may be configured as a pixel of a passive or active light-emitting display device with various structures and / or driving methods.

[0056] FIG. 2 is a schematic equivalent circuit diagram of a pixel (PXL) according to embodiments of the present disclosure.

[0057] Figure 2 illustrates the electrical connection relationship of components included in a pixel (PXL) that can be applied to an active display device. However, the types of components included in a pixel (PXL) are not necessarily limited thereto.

[0058] According to an embodiment, the pixel (PXL) illustrated in FIG. 2 may be any one of the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) provided in the display panel (PNL) of FIG. 1. The first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may have structures substantially identical to or similar to each other.

[0059] Referring to FIG. 2, each pixel (PXL) may include a light-emitting element (LD) that generates light of a brightness corresponding to a data signal. The pixel (PXL) may include a pixel circuit (PXC) configured to drive the light-emitting element (LD).

[0060] According to an embodiment, the pixel (PXL) may include at least one light-emitting element (LD) electrically connected between a first power line (PL1) to which a first power voltage (ELVDD) is applied and a second power line (PL2) to which a second power voltage (ELVSS) is applied. For example, the light-emitting element (LD) may include a first electrode (ET1) connected (e.g., electrically connected) to the pixel circuit (PXC) and the first power line (PL1), and a second electrode (ET2) connected (e.g., electrically connected) to the second power line (PL2). In one embodiment, the first electrode (ET1) may be an anode electrode, and the second electrode (ET2) may be a cathode electrode. The light-emitting element (LD) may further include a light-emitting structure that receives voltage from the first electrode (ET1) and the second electrode (ET2) to emit light. The light-emitting structure is described below with reference to the drawings of FIG. 3 and below.

[0061] The first power supply voltage (ELVDD) and the second power supply voltage (ELVSS) may have different potentials. At this time, the potential difference between the first and second power supply voltages (ELVDD, ELVSS) may be set to be higher than the threshold voltage of the light-emitting element (LD) during the light-emitting period of the pixel (PXL).

[0062] The light-emitting element (LD) can function as a light source of the pixel (PXL). The light-emitting element (LD) can emit light with a brightness corresponding to the driving current supplied through the pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a driving current corresponding to the grayscale value of the corresponding frame data. Accordingly, the light-emitting element (LD) can emit light with a brightness corresponding to the driving current, and the light-emitting structure can emit light.

[0063] The pixel circuit (PXC) may be connected (e.g., electrically connected) to the scan line (SLi) and the data line (DLj) of the pixel (PXL). For example, when the pixel (PXL) is arranged in the i-th row (i is an integer greater than or equal to 1) and the j-th column (j is an integer greater than or equal to 1) of the display area (DA; see FIG. 1), the pixel circuit (PXC) of the pixel (PXL) may be connected to the i-th scan line (SLi) and the j-th data line (DLj) of the display area (DA). According to an embodiment, the pixel circuit (PXC) may include first and second transistors (TR1, TR2) and a storage capacitor (Cstg). However, the structure of the pixel circuit (PXC) according to embodiments of the present disclosure is not limited to the embodiment illustrated in FIG. 2.

[0064] The first transistor (TR1) may include a gate electrode connected (e.g., electrically connected) to a first node (N1). The first transistor (TR1) may include a first electrode connected (e.g., electrically connected) to a second node (N2). The first transistor (TR1) may include a second electrode connected (e.g., electrically connected) to a first power line (PL1). The first electrode may be one of a source electrode and a drain electrode (e.g., a drain electrode). The second electrode may be the other of the source electrode and the drain electrode (e.g., the source electrode). A current (e.g., a driving current) corresponding to a voltage applied to the first node (N1) may flow through the first transistor (TR1). The first transistor (TR1) may be referred to as a driving transistor.

[0065] The second transistor (TR2) may be configured to input a data voltage (Vdata) to the pixel circuit (PXC). The second transistor (TR2) may include a gate electrode connected (e.g., electrically connected) to the ith scan line (SLi). The second transistor (TR2) may be configured to input the data voltage (Vdata) to the pixel circuit (PXC) in response to a scan signal (SCAN) input to the ith scan line (SLi) (e.g., a scan signal (SCAN) of a turn-on level). Referring to FIG. 2, the second transistor (TR2) may be configured to switch an electrical connection between the jth data line (DLj) and the first node (N1). The second transistor (TR2) may be referred to as a switching transistor.

[0066] The storage capacitor (Cstg) may include one electrode connected (e.g., electrically connected) to a first node (N1) and the other electrode connected (e.g., electrically connected) to a second node (N2). The storage capacitor (Cstg) may be configured to maintain a voltage difference between the first node (N1) and the second node (N2). For example, the storage capacitor (Cstg) may be configured to maintain a data voltage (Vdata) applied to the first node (N1) for a predetermined period (e.g., one frame period).

[0067] In FIG. 2, a pixel circuit (PXC) is illustrated, including a second transistor (TR2) configured to write a data voltage (Vdata) to a pixel (PXL), a storage capacitor (Cstg) for storing the data voltage, and a first transistor (TR1) configured to supply a driving current corresponding to the data voltage (Vdata) to a light-emitting element (LD). However, the embodiments of the present disclosure are not limited thereto, and the structure of the pixel circuit (PXC) may be variously modified. For example, the pixel circuit (PXC) may further include a transistor element configured to compensate for a change in a threshold voltage of the first transistor (TR1), a transistor element configured to initialize the voltage of the first node (N1), and / or a transistor element configured to control the length of time for which the light-emitting element (LD) (or light-emitting elements) emits light. According to an embodiment, the pixel circuit (PXC) may further include circuit elements such as a boosting capacitor for boosting the voltage of the first node (N1).

[0068] Referring to FIG. 2, a pixel circuit (PXC) according to embodiments of the present disclosure is illustrated in an embodiment in which each of the first and second transistors (TR1, TR2) is implemented as a transistor including a p-type semiconductor layer (e.g., a p-channel metal oxide semiconductor (PMOS)). However, embodiments of the present disclosure are not limited thereto, and at least one of the first and second transistors (TR1, TR2) may be configured as a transistor including an n-type semiconductor layer (e.g., an n-channel metal oxide semiconductor (NMOS)). The p-type semiconductor layer may include, for example, a metal oxide semiconductor. The n-type semiconductor layer may include, for example, a polycrystalline silicon semiconductor.

[0069] FIG. 3 is a schematic cross-sectional view of a display panel according to embodiments of the present disclosure.

[0070] Referring to FIG. 3, a cross-sectional view of a unit pixel (PXU) in a display panel is illustrated, and more specifically, a light-emitting structure (EMS), a first electrode (ET1), and a second electrode (ET2) in the unit pixel (PXU) are illustrated in detail.

[0071] Embodiments according to the present disclosure may have unit pixels (PXU) (or pixels) arranged on a display panel. The display panel according to embodiments of the present disclosure may include a substrate (SUB), a light-emitting structure (EMS) arranged on the substrate (SUB), a first electrode (ET1), and a second electrode (ET2). The display panel may further include a light-blocking layer (370) configured to prevent light emitted from each pixel from being mixed.

[0072] The substrate (SUB) may be composed of a silicon (Si) substrate, a silicon carbide (SiC) substrate, or the like. However, the embodiments of the present disclosure are not limited thereto.

[0073] The pixel circuits of each pixel included in the unit pixel (PXU) can be arranged on the substrate (SUB). Referring to FIG. 3, the pixel circuit (381) of the first pixel (PXL1; refer to FIG. 1), the pixel circuit (382) of the second pixel (PXL2; refer to FIG. 1), and the pixel circuit (383) of the third pixel (PXL3; refer to FIG. 1) are illustrated as being arranged on the substrate (SUB).

[0074] A second power line (PL2; see FIG. 2) may be arranged on the substrate (SUB). Referring to FIG. 3, a second power line (390) is illustrated, which may correspond to the second power line (PL2) in the equivalent circuit diagram of FIG. 2.

[0075] The first electrode (ET1) may include an a-first electrode (ET1a), a b-first electrode (ET1b), and a c-first electrode (ET1c). The a-first electrode (ET1a) may be connected to a pixel circuit (381) of a first pixel. The b-first electrode (ET1b) may be connected to a pixel circuit (382) of a second pixel. The c-first electrode (ET1c) may be connected to a pixel circuit (383) of a third pixel.

[0076] The second electrode (ET2) can be connected to the second power line (390). Accordingly, the second electrode (ET2) can function as a common electrode of the first to third pixels (PXL1 to PXL3; see FIG. 1).

[0077] The light-emitting structure (EMS) may include a passivation layer (310), an insulating layer (320), a transparent conductive layer (330), a first semiconductor layer (340), an active layer (350), a second semiconductor layer (360), etc. The first semiconductor layer (340), the active layer (350), and the second semiconductor layer (360) may constitute a light-emitting layer.

[0078] The passivation layer (310) may be positioned on the substrate (SUB) (e.g., covering the substrate (SUB)). The passivation layer (310) may be configured to electrically insulate between the metal (e.g., copper (Cu)) constituting the light-shielding layer (370) and the light-emitting structure (EMS). The passivation layer (310) may include, for example, an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx). However, the embodiments of the present disclosure are not limited thereto.

[0079] The insulating layer (320) may be positioned on the passivation layer (310). The insulating layer (320) may perform a function of preventing the transparent conductive layer (331) from being directly connected to the substrate (SUB). The insulating layer (320) may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx). The insulating layer (320) may include a first insulating layer (321), a second insulating layer (322), and a third insulating layer (323).

[0080] The transparent conductive layer (330) may be disposed on the insulating layer (320). The first transparent conductive layer (330) may include a metal or a metal oxide. For example, the first conductive layer (330) may include at least one of various transparent conductive materials, including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO). The transparent conductive layer (330) may be implemented to be substantially transparent or translucent so as to satisfy a predetermined light transmittance. Accordingly, light emitted from the light emitting structure (EMS) may pass through the transparent conductive layer (330) and be emitted to the outside of the display panel (PNL). According to an embodiment, the transparent conductive layer (330) may include a metal or a metal oxide. For example, the transparent conductive layer (330) may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and oxides or alloys thereof, but the embodiments of the present disclosure are not limited thereto. The transparent conductive layer (330) may include a first transparent conductive layer (331), a second transparent conductive layer (332), and a third transparent conductive layer (333).

[0081] The first semiconductor layer (340) may be positioned on the transparent conductive layer (330). The first semiconductor layer (340) may include either a p-type semiconductor layer or an n-type semiconductor layer. For convenience of explanation, the first semiconductor layer (340) is described below as an example in which the first semiconductor layer includes a p-type semiconductor layer, but the embodiments of the present disclosure are not limited thereto. The first semiconductor layer (340) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may include a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. The first semiconductor layer (340) may include a first-first semiconductor layer (341), a second-first semiconductor layer (342), and a third-first semiconductor layer (343).

[0082] The active layer (350) may be disposed between the first semiconductor layer (340) and the second semiconductor layer (360). The active layer (350) may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but the embodiments of the present disclosure are not limited thereto. The active layer (350) may include AlGaN, InGaN, or GaN, and various other materials may also form the active layer (350). The active layer (350) may include a first active layer (351), a second active layer (352), and a third active layer (353).

[0083] The first active layer (351), the second active layer (352), and the third active layer (353) may each be configured to emit light of different wavelength bands. For example, the first active layer (351) may be configured to emit light of a relatively long wavelength band, and the third active layer (353) may be configured to emit light of a relatively short wavelength band. For example, the first active layer (351) may be configured to emit light of a red wavelength band, the second active layer (352) may be configured to emit light of a green wavelength band, and the third active layer (353) may be configured to emit light of a blue wavelength band.

[0084] The second semiconductor layer (360) may be positioned on the active layer (350). The second semiconductor layer (360) may include the other of a p-type semiconductor layer and an n-type semiconductor layer. For convenience of explanation, the second semiconductor layer (360) is described below as an example in which the second semiconductor layer includes an n-type semiconductor layer, but the embodiments of the present disclosure are not limited thereto. The second semiconductor layer (360) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as germanium (Ge), selenium (Se), tellurium (Te), or tin (Sn). As an example, the second semiconductor layer (360) of the light emitting element (LD) may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the second semiconductor layer (360) is not limited to this, and the second semiconductor layer (360) can be composed of various other materials.

[0085] The light-shielding layer (370) may be configured to prevent color mixing. The light-shielding layer (370) surrounded by the passivation layer (310) may perform a function of electrically insulating the first electrode (ET1) and the second electrode (ET2) from each other. For example, light emitted from the first pixel (PXL1; see FIG. 1) may be emitted through an area on the a-th first electrode (ET1a). Light emitted from the second pixel (PXL2; see FIG. 1) may be emitted through an area on the b-th first electrode (ET1b). Light emitted from the third pixel (PXL3; see FIG. 1) may be emitted through an area on the c-th first electrode (ET1c). The light-shielding layer (370) may be positioned between each pixel (or between each pixel circuit) to prevent color mixing between the light emitted from each pixel.

[0086] The first electrode (ET1) may be connected to the transparent conductive layer (330). The a-first electrode (ET1a) may be connected to the first transparent conductive layer (331). The b-first electrode (ET1b) may be connected to the second transparent conductive layer (332). The c-first electrode (ET1c) may be connected to the third transparent conductive layer (333). The first electrode (ET1) may supply a positive voltage (or a voltage of a relatively high potential) to the transparent conductive layer (330).

[0087] The second electrode (ET2) may be connected to the second semiconductor layer (360) (e.g., a side surface of the second semiconductor layer (360)). The second electrode (ET2) may supply a negative voltage (or a voltage of a relatively low potential) to the second semiconductor layer (360). The thickness of the second semiconductor layer (360) may be thicker than the thickness of the first semiconductor layer (340). Accordingly, it may be relatively easy for the second electrode (ET2) to supply voltage to the second semiconductor layer (360).

[0088] The light-emitting structure (EMS) may be arranged on the substrate (SUB) in units of unit pixels (PXU). However, the embodiments of the present disclosure are not limited thereto, and the light-emitting structure (EMS) of two or more unit pixels (PXU) may be formed integrally and arranged on the substrate (SUB).

[0089] Below, a method of manufacturing a display panel including a light emitting structure (EMS) according to embodiments of the present disclosure is described in more detail.

[0090] FIGS. 4A to 39 are schematic drawings for explaining a method of manufacturing a display panel according to embodiments of the present disclosure.

[0091] Referring to FIGS. 4a, 4b, and 4c, steps of growing a light-emitting layer on a temporary substrate are illustrated.

[0092] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S410) of forming a first light-emitting layer on a first temporary substrate (BSL1), a step (S420) of forming a second light-emitting layer on a second temporary substrate (BSL2), and a step (S430) of forming a third light-emitting layer on a third temporary substrate (BSL3).

[0093] In the step of forming the first light-emitting layer (S410), a first-second semiconductor layer (361), a first active layer (351), and a first-first semiconductor layer (341) can be sequentially formed on a first temporary substrate (BSL1) (for example, in the opposite direction of the third direction (DR3) from the first temporary substrate (BSL1).

[0094] In the step of forming the second light-emitting layer (S420), a second-second semiconductor layer (362), a second active layer (352), and a second-first semiconductor layer (342) can be sequentially formed on a second temporary substrate (BSL2).

[0095] In the step of forming the third light-emitting layer (S430), a third-second semiconductor layer (363), a third active layer (353), and a third-first semiconductor layer (343) can be sequentially formed on a third temporary substrate (BSL3).

[0096] Each of the first to third temporary substrates (BSL1, BSL2, BSL3) may be formed of a sapphire substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or the like. However, the embodiments of the present disclosure are not limited thereto. For example, each of the first to third temporary substrates (BSL1, BSL2, BSL3) may utilize a single crystal substrate having a lattice structure, or the like. Each of the first to third temporary substrates (BSL1, BSL2, BSL3) may further include a buffer layer formed on one surface.

[0097] The first to third light-emitting layers may be formed by growing seed crystals by an epitaxial method. In an embodiment, each of the first to third light-emitting layers may be formed by metal organic chemical vapor deposition (MOCVD). However, the embodiments of the present disclosure are not limited thereto. For example, each of the first to third light-emitting layers may be formed by various methods known in the art, such as electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, or sputtering.

[0098] Referring to FIGS. 5a, 5b, and 5c, a step of forming a transparent conductive layer on a light-emitting layer is illustrated.

[0099] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S510) of forming a first transparent conductive layer (331) on a first light-emitting layer, a step (S520) of forming a second transparent conductive layer (332) on a second light-emitting layer, and a step (S530) of forming a third transparent conductive layer (333) on a third light-emitting layer.

[0100] In the step (S510) of forming a first transparent conductive layer (331) on the first light-emitting layer, the first transparent conductive layer (331) may be formed on the first light-emitting layer. The first transparent conductive layer (331) may be formed on the first-first semiconductor layer (341).

[0101] In the step (S520) of forming a second transparent conductive layer (332) on the second light-emitting layer, the second transparent conductive layer (332) may be formed on the second light-emitting layer. The second transparent conductive layer (332) may be formed on the second-first semiconductor layer (342).

[0102] In the step (S530) of forming a third transparent conductive layer (333) on the third light-emitting layer, the third transparent conductive layer (333) may be formed on the third light-emitting layer. The third transparent conductive layer (333) may be formed on the third-first semiconductor layer (343).

[0103] Referring to FIGS. 6a to 6c, a step of forming an insulating layer (e.g., an intermediate insulating layer) on a light-emitting layer is illustrated.

[0104] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S610) of forming a first intermediate insulating layer (611) on a first transparent conductive layer (331), a step (S620) of forming a second intermediate insulating layer (621) on a second transparent conductive layer (332), and a step (S630) of forming a third intermediate insulating layer (631) on a third transparent conductive layer (333).

[0105] Each of the first to third intermediate insulating layers (611, 621, 631) may be composed of an inorganic insulating layer. For example, each of the first to third intermediate insulating layers (611, 621, 631) may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx). However, the embodiments of the present disclosure are not limited thereto.

[0106] Referring to FIGS. 7a and 7b, a step of forming an insulating layer (e.g., an intermediate insulating layer) on a temporary substrate is illustrated.

[0107] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S710) of forming a fourth intermediate insulating layer (712) on a fourth temporary substrate (711) and a step (S720) of forming a fifth intermediate insulating layer (722) on a fifth temporary substrate (721).

[0108] In the step (S710) of forming a fourth intermediate insulating layer (712) on a fourth temporary substrate (711), the fourth intermediate insulating layer (712) can be formed in the third direction (DR3) from the fourth temporary substrate (711).

[0109] In the step (S720) of forming a fifth intermediate insulating layer (722) on a fifth temporary substrate (721), the fifth intermediate insulating layer (722) can be formed in the third direction (DR3) from the fifth temporary substrate (721).

[0110] Each of the fourth and fifth temporary substrates (711, 721) may be formed of a sapphire substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or the like. However, the embodiments of the present disclosure are not limited thereto. For example, each of the fourth and fifth temporary substrates (711, 721) may utilize a single crystal substrate having a lattice structure, or the like. Each of the fourth and fifth temporary substrates (711, 721) may further include a buffer layer formed on one surface.

[0111] Each of the fourth and fifth intermediate insulating layers (712, 722) may be composed of an inorganic insulating layer. For example, each of the fourth and fifth intermediate insulating layers (712, 722) may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx). However, embodiments of the present disclosure are not limited thereto.

[0112] Referring to FIGS. 8a and 8b, a step of bonding insulating layers (e.g., intermediate insulating layers) is illustrated.

[0113] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S810) of bonding a first intermediate insulating layer (611) and a fourth intermediate insulating layer (712) and a step (S820) of bonding a second intermediate insulating layer (621) and a fifth intermediate insulating layer (722).

[0114] In the step (S810) of bonding the first intermediate insulating layer (611) and the fourth intermediate insulating layer (712), the first intermediate insulating layer (611) and the fourth intermediate insulating layer (712) may be bonded to form the first insulating layer (321). The fourth temporary substrate (711) may be positioned in the opposite direction of the third direction (DR3) from the first insulating layer (321).

[0115] In the step (S820) of bonding the second intermediate insulating layer (621) and the fifth intermediate insulating layer (722), the second intermediate insulating layer (621) and the fifth intermediate insulating layer (722) may be bonded to form a sixth intermediate insulating layer (821). The fifth temporary substrate (721) may be positioned in the opposite direction of the third direction (DR3) from the sixth intermediate insulating layer (821).

[0116] In the step of bonding the intermediate insulating layers, the insulating layers (e.g., the second intermediate insulating layer (621) and the fifth intermediate insulating layer (722)) may be bonded to each other using heat and / or pressure, etc. However, the embodiments of the present disclosure are not limited thereto.

[0117] Referring to FIGS. 9a and 9b, the steps of detaching the temporary substrate are illustrated.

[0118] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S910) of detaching a first temporary substrate (BSL1) and a step (S920) of detaching a second temporary substrate (BSL2).

[0119] For example, in the step (S910) of detaching the first temporary substrate (BSL1), the first temporary substrate (BSL1) may be separated from the first-second semiconductor layer (361) through a laser lift-off (LLO) process. For example, in the step (S920) of detaching the second temporary substrate (BSL2), the second temporary substrate (BSL2) may be separated from the second-second semiconductor layer (362) through a laser lift-off process. However, the embodiments of the present disclosure are not limited thereto.

[0120] Referring to FIGS. 10a and 10b, a step of forming an insulating layer (e.g., an interlayer insulating layer) on a light-emitting layer is illustrated.

[0121] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S1010) of forming a seventh intermediate insulating layer (1011) on a first light-emitting layer and a step (S1020) of forming an eighth intermediate insulating layer (1021) on a second light-emitting layer.

[0122] In the step (S1010) of forming a seventh intermediate insulating layer (1011) on the first light-emitting layer, the seventh intermediate insulating layer (1011) can be formed in the third direction (DR3) from the first-second semiconductor layer (361).

[0123] In the step (S1020) of forming the eighth intermediate insulating layer (1021) on the second light-emitting layer, the eighth intermediate insulating layer (1021) can be formed in the third direction (DR3) from the second-second semiconductor layer (362).

[0124] Each of the seventh and eighth intermediate insulating layers (1011, 1021) may be composed of an inorganic insulating layer. For example, each of the seventh and eighth intermediate insulating layers (1011, 1021) may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx). However, embodiments of the present disclosure are not limited thereto.

[0125] Referring to FIG. 11, a step of bonding insulating layers (e.g., intermediate insulating layers) is illustrated.

[0126] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S1100) of bonding a third intermediate insulating layer (631) and an eighth intermediate insulating layer (1021).

[0127] In the step (S1100) of bonding the third intermediate insulating layer (631) and the eighth intermediate insulating layer (1021), the third intermediate insulating layer (631) and the eighth intermediate insulating layer (1021) may be bonded to form the third insulating layer (323). A fifth temporary substrate (721) may be positioned in the opposite direction of the third direction (DR3) from the third insulating layer (323).

[0128] In the step of bonding the intermediate insulating layers, the insulating layers (e.g., the third intermediate insulating layer (631) and the eighth intermediate insulating layer (1021)) may be bonded to each other using heat and / or pressure, etc. However, the embodiments of the present disclosure are not limited thereto.

[0129] Referring to Figure 12, the step of detaching the temporary substrate is illustrated.

[0130] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S1200) of detaching a fifth temporary substrate (721). In the step (S1200) of detaching a fifth temporary substrate (721), the fifth temporary substrate (721) may be separated from a sixth intermediate insulating layer (821).

[0131] Referring to FIG. 13, a step of bonding insulating layers (e.g., intermediate insulating layers) is illustrated.

[0132] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S1300) of bonding a sixth intermediate insulating layer (821) and a seventh intermediate insulating layer (1011).

[0133] In the step (S1300) of bonding the sixth intermediate insulating layer (821) and the seventh intermediate insulating layer (1011), the sixth intermediate insulating layer (821) and the seventh intermediate insulating layer (1011) may be bonded to form a second insulating layer (322). A fourth temporary substrate (711) may be positioned in the opposite direction of the third direction (DR3) from the second insulating layer (322).

[0134] In the step of bonding the intermediate insulating layers, the insulating layers (e.g., the sixth intermediate insulating layer (821) and the seventh intermediate insulating layer (1011)) may be bonded to each other using heat and / or pressure, etc. However, the embodiments of the present disclosure are not limited thereto.

[0135] Referring to Figure 14, the step of detaching the temporary substrate is illustrated.

[0136] The method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S1400) of detaching the fourth temporary substrate (711). In the step (S1400) of detaching the fourth temporary substrate (711), the fourth temporary substrate (711) may be separated from the first insulating layer (321).

[0137] Referring to FIGS. 15 to 20, a step of forming first, second, and third via holes (VIA1, VIA2, VIA3) using photoresist is illustrated.

[0138] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S1500) of forming a first photoresist (1510) including a first pattern (PAT1), a step (S1600) of forming a first via hole (VIA1) corresponding to the first pattern (PAT1), a step (S1700) of forming a second photoresist (1710) including a second pattern (PAT2), a step (S1800) of forming a second via hole (VIA2) corresponding to the second pattern (PAT2), a step (S1900) of forming a third photoresist (1910) including a third pattern (PAT3), and a step (S2000) of forming a third via hole (VIA3) corresponding to the third pattern (PAT3).

[0139] In the step (S1500) of forming a first photoresist (1510) including a first pattern (PAT1), the first pattern (PAT1) may be formed on the first photoresist (1510) using a photomask (not shown) on which a pattern corresponding to the first pattern (PAT1) is formed. As the first photoresist (1510), either a positive photoresist or a negative photoresist may be used, for example.

[0140] In the step (S1600) of forming a first via hole (VIA1), the first via hole (VIA1) may be formed in an area corresponding to the first pattern (PAT1). The first via hole (VIA1) may penetrate at least a portion of the first insulating layer (321), the first transparent conductive layer (331), the first-first semiconductor layer (341), the first active layer (351), the first-second semiconductor layer (361), the second insulating layer (322), the second transparent conductive layer (332), the second-first semiconductor layer (342), the second active layer (352), the second-second semiconductor layer (362), the third insulating layer (323), the third transparent conductive layer (333), the third-first semiconductor layer (343), and the third active layer (353). The first via hole (VIA1) may be formed through a dry etching process, but embodiments of the present disclosure are not limited thereto. For example, the first via hole (VIA1) may be formed through a wet etching process. When the first via hole (VIA1) according to embodiments of the present disclosure is formed through a dry etching process, the first via hole (VIA1) may be formed through a process such as vapor phase etching, plasma etching, or ion beam etching.

[0141] In the step (S1700) of forming a second photoresist (1710) including a second pattern (PAT2), the second pattern (PAT2) may be formed on the second photoresist (1710) using a photomask (not shown) on which a pattern corresponding to the second pattern (PAT2) is formed. For example, the second photoresist (1710) may be either a positive photoresist or a negative photoresist. According to an embodiment, the second photoresist (1710) may be filled in the first via hole (VIA1), but the embodiments of the present disclosure are not limited thereto.

[0142] In the step S1800 of forming a second via hole (VIA2), the second via hole (VIA2) may be formed in an area corresponding to the second pattern (PAT2). The second via hole (VIA2) may penetrate at least a portion of the first insulating layer (321), the first transparent conductive layer (331), the first-first semiconductor layer (341), the first active layer (351), the first-second semiconductor layer (361), the second insulating layer (322), the second transparent conductive layer (332), the second-first semiconductor layer (342), and the second active layer (352). The second via hole (VIA2) may be formed through a dry etching process, but the embodiments of the present disclosure are not limited thereto. For example, the second via hole (VIA2) may be formed through a wet etching process.

[0143] In the step (S1900) of forming a third photoresist (1910) including a third pattern (PAT3), the third pattern (PAT3) may be formed on the third photoresist (1910) using a photomask (not shown) on which a pattern corresponding to the third pattern (PAT3) is formed. For example, the third photoresist (1910) may be either a positive photoresist or a negative photoresist. According to an embodiment, the third photoresist (1910) may be filled in the first and / or second via holes (VIA1, VIA2), but the embodiments of the present disclosure are not limited thereto.

[0144] In the step of forming a third via hole (VIA3) (S2000), the third via hole (VIA3) may be formed in an area corresponding to the third pattern (PAT3). The third via hole (VIA3) may penetrate at least a portion of the first insulating layer (321), the first transparent conductive layer (331), the first-first semiconductor layer (341), and the first active layer (351). The third via hole (VIA3) may be formed through a dry etching process, but the embodiments of the present disclosure are not limited thereto. For example, the third via hole (VIA3) may be formed through a wet etching process.

[0145] Referring to FIGS. 21 to 23, one embodiment of a step of forming a light-shielding layer is illustrated. For example, the step of forming a light-shielding layer may include performing an electrolytic plating process (e.g., a damascene process) or a deposition process.

[0146] In one embodiment, the shading layer may be formed by electroplating. For example, the shading layer may be formed by electroplating copper (Cu) or the like into the first to third via holes (VIA1, VIA2, VIA3) using a damascene process.

[0147] In another embodiment, the light-shielding layer may be formed by a deposition method. For example, the light-shielding layer may be formed by depositing tungsten (W) or the like into the first to third via holes (VIA1, VIA2, VIA3). As the deposition process, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. may be applied. However, the embodiments of the present disclosure are not limited thereto.

[0148] Below, a description will be given of an embodiment in which a damascene process is applied to form a light-shielding layer. However, the embodiments of the present disclosure are not limited thereto, and a light-shielding layer may be formed using an electrolytic plating process other than the damascene process, or by a deposition method.

[0149] Referring to FIGS. 21 to 23, a method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S2100) of forming a first passivation layer (2110) surrounding first to third via holes (VIA1, VIA2, VIA3), a step (S2200) of electroplating a metal (2210) on the first to third via holes (VIA1, VIA2, VIA3) surrounded by the first passivation layer (2110), and a step (S2300) of forming a light-blocking layer (370).

[0150] The first passivation layer (2110) may include, for example, an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx). However, the embodiments of the present disclosure are not limited thereto. The first passivation layer (2110) may be positioned on the upper surface of the first insulating layer (321). The first passivation layer (2110) may surround layers exposed from the side surfaces of the first to third via holes (VIA1, VIA2, VIA3).

[0151] The metal (2210) can constitute a light-shielding layer (370). The metal (2210) can be freely selected according to the choice of a person skilled in the art. For example, within the range of filling the inside of the first to third via holes (VIA1, VIA2, VIA3) with the metal (2210) by electroplating through a damascene process, the metal (2210) can be freely selected according to the choice of a person skilled in the art. The metal (2210) can be, for example, copper (Cu), but the embodiments of the present disclosure are not limited thereto. For example, a metal having a relatively lower reflectivity than copper (Cu) can be used to enhance the light-shielding function by absorbing incident light. In another example, a metal having a relatively higher reflectivity than copper (Cu) can be used to reflect incident light in the upward direction, thereby increasing the brightness.

[0152] In the step (S2300) of forming a light-shielding layer (370), metals (2210) positioned on the first passivation layer (2110) may be removed, so that the metal (2210) may be removed on the first passivation layer (2110).

[0153] Referring to FIGS. 24 to 29, a step of forming first, second, and third contact holes (CNT1, CNT2, CNT3) using a photoresist is illustrated.

[0154] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S2400) of forming a fourth photoresist (2410) including a fourth pattern (PAT4), a step (S2500) of forming a first contact hole (CNT1) corresponding to the fourth pattern (PAT4), a step (S2600) of forming a fifth photoresist (2610) including a fifth pattern (PAT5), a step (S1800) of forming a second contact hole (CNT2) corresponding to the fifth pattern (PAT5), a step (S2800) of forming a sixth photoresist (2810) including a sixth pattern (PAT6), and a step (S2900) of forming a third contact hole (CNT3) corresponding to the sixth pattern (PAT6).

[0155] In the step (S2400) of forming a fourth photoresist (2410) including a fourth pattern (PAT4), the fourth pattern (PAT4) may be formed on the fourth photoresist (2410) using a photomask (not shown) on which a pattern corresponding to the fourth pattern (PAT4) is formed. As the fourth photoresist (2410), either a positive photoresist or a negative photoresist may be used, for example.

[0156] In the step (S2500) of forming the first contact hole (CNT1), the first contact hole (CNT1) may be formed in an area corresponding to the fourth pattern (PAT4). The first contact hole (CNT1) may penetrate at least a portion of the first insulating layer (321), the first transparent conductive layer (331), the first-first semiconductor layer (341), the first active layer (351), the first-second semiconductor layer (361), the second insulating layer (322), the second transparent conductive layer (332), the second-first semiconductor layer (342), the second active layer (352), the second-second semiconductor layer (362), and the third insulating layer (323). The first contact hole (CNT1) may expose at least a portion of the third transparent conductive layer (333). The first contact hole (CNT1) may be formed through a dry etching process, but embodiments of the present disclosure are not limited thereto. For example, the first contact hole (CNT1) may be formed through a wet etching process. When the first contact hole (CNT1) according to embodiments of the present disclosure is formed through a dry etching process, the first contact hole (CNT1) may be formed through a process such as vapor phase etching, plasma etching, or ion beam etching.

[0157] In the step (S2600) of forming a fifth photoresist (2610) including a fifth pattern (PAT5), the fifth pattern (PAT5) may be formed on the fifth photoresist (2610) using a photomask (not shown) on which a pattern corresponding to the fifth pattern (PAT5) is formed. For example, the fifth photoresist (2610) may be either a positive photoresist or a negative photoresist. According to an embodiment, the fifth photoresist (2610) may be filled in the first contact hole (CNT1), but the embodiments of the present disclosure are not limited thereto.

[0158] In the step (S2700) of forming the second contact hole (CNT2), the second contact hole (CNT2) may be formed in an area corresponding to the fifth pattern (PAT5). The second contact hole (CNT2) may penetrate at least a portion of the first insulating layer (321), the first transparent conductive layer (331), the first-first semiconductor layer (341), the first active layer (351), the first-second semiconductor layer (361), and the second insulating layer (322). The second contact hole (CNT2) may expose at least a portion of the second transparent conductive layer (332). The second contact hole (CNT2) may be formed through a dry etching process, but embodiments of the present disclosure are not limited thereto. For example, the second contact hole (CNT2) may be formed through a wet etching process.

[0159] In the step (S2800) of forming a sixth photoresist (2810) including a sixth pattern (PAT6), the sixth pattern (PAT6) may be formed on the sixth photoresist (2810) using a photomask (not shown) on which a pattern corresponding to the sixth pattern (PAT6) is formed. For example, the sixth photoresist (2810) may be either a positive photoresist or a negative photoresist. According to an embodiment, the sixth photoresist (2810) may be filled in the first and / or second contact holes (CNT1, CNT2), but the embodiments of the present disclosure are not limited thereto.

[0160] In the step (S2900) of forming a third contact hole (CNT3), the third contact hole (CNT3) may be formed in an area corresponding to the sixth pattern (PAT6). The third contact hole (CNT3) may penetrate at least a portion of the first insulating layer (321). The third contact hole (CNT3) may expose at least a portion of the first transparent conductive layer (331). The third contact hole (CNT3) may be formed through a dry etching process, but the embodiments of the present disclosure are not limited thereto. For example, the third contact hole (CNT3) may be formed through a wet etching process.

[0161] Referring to FIG. 30, a step of forming a passivation layer (e.g., a second passivation layer (3010)) is illustrated.

[0162] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S3000) of forming a second passivation layer (3010). The second passivation layer (3010) may form the passivation layer (310) together with the first passivation layer (2110). The second passivation layer (3010) may be formed of the same material as the first passivation layer (2110). The second passivation layer (3010) may include, for example, an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx). However, embodiments of the present disclosure are not limited thereto.

[0163] The second passivation layer (3010) may surround the first to third contact holes (CNT1, CNT2, CNT3). The second passivation layer (3010) may cover the upper surface of the light-shielding layer (370). For example, the second passivation layer (3010) may be positioned in an opposite direction from the light-shielding layer (370) in the third direction (DR3).

[0164] Referring to FIGS. 31 and 32, a step of exposing at least a portion of the transparent conductive layer is illustrated.

[0165] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S3100) of forming a seventh photoresist (3110) including a seventh pattern (PAT7), and a step (S3200) of exposing first to third transparent conductive layers (331, 332, 333) in an area corresponding to the seventh pattern (PAT7).

[0166] In the step (S3100) of forming a seventh photoresist (3110) including a seventh pattern (PAT7), the seventh pattern (PAT7) may be formed on the seventh photoresist (3110) using a photomask (not shown) on which a pattern corresponding to the seventh pattern (PAT7) is formed. As the seventh photoresist (3110), either a positive photoresist or a negative photoresist may be used, for example.

[0167] In the step (S3200) of exposing the first to third transparent conductive layers (331, 332, 333), at least a portion of the passivation layer (310) may be removed from the lower surfaces of the first to third contact holes (CNT1 to CNT3). At least a portion of the third transparent conductive layer (333) may be exposed from the lower surface of the first contact hole (CNT1). At least a portion of the second transparent conductive layer (332) may be exposed from the lower surface of the second contact hole (CNT2). At least a portion of the first transparent conductive layer (331) may be exposed from the lower surface of the third contact hole (CNT3). A dry etching process may be performed to remove at least a portion of the passivation layer (310), but embodiments of the present disclosure are not limited thereto.

[0168] Referring to FIGS. 33 and 34, a step of forming a fourth contact hole (CNT4) is illustrated.

[0169] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S3300) of forming an eighth photoresist (3310) including an eighth pattern (PAT8) and a step (S3400) of forming a fourth contact hole (CNT4) corresponding to the eighth pattern (PAT8).

[0170] In the step (S3300) of forming an eighth photoresist (3310) including an eighth pattern (PAT8), the eighth pattern (PAT8) may be formed on the eighth photoresist (3310) using a photomask (not shown) on which a pattern corresponding to the eighth pattern (PAT8) is formed. For example, either a positive photoresist or a negative photoresist may be used as the eighth photoresist (3310). The eighth photoresist (3310) may fill the first to third contact holes (CNT1 to CNT3).

[0171] In the step (S3400) of forming the fourth contact hole (CNT4), the fourth contact hole (CNT4) may be formed in an area corresponding to the eighth pattern (PAT8). The fourth contact hole (CNT4) may penetrate at least a portion of the passivation layer (310), the first insulating layer (321), the first transparent conductive layer (331), the first-first semiconductor layer (341), the first active layer (351), the first-second semiconductor layer (361), the second insulating layer (322), the second transparent conductive layer (332), the second-first semiconductor layer (342), the second active layer (352), the second-second semiconductor layer (362), the third insulating layer (323), the third transparent conductive layer (333), and the third active layer (353). The fourth contact hole (CNT4) may be formed by etching at least a portion of the third-second semiconductor layer (363). The fourth contact hole (CNT4) may be formed through a dry etching process, but the embodiments of the present disclosure are not limited thereto. For example, the fourth contact hole (CNT4) may be formed through a wet etching process. When the fourth contact hole (CNT4) according to the embodiments of the present disclosure is formed through a dry etching process, the fourth contact hole (CNT4) may be formed through a process such as vapor phase etching, plasma etching, or ion beam etching.

[0172] Referring to FIGS. 35 to 37, steps of forming first and second electrodes are illustrated.

[0173] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S3500) of forming an eighth photoresist (3310) including a ninth pattern (PAT9), a step (S3600) of depositing a metal (3610), and a step (S3700) of forming first and second electrodes.

[0174] In the step (S3500) of forming an eighth photoresist (3310) including a ninth pattern (PAT9), the ninth pattern (PAT9) may be formed on the eighth photoresist (3310) using a photomask (not shown) on which a pattern corresponding to the ninth pattern (PAT9) is formed. The ninth pattern (PAT9) may be formed to correspond to the first to third contact holes (CNT1 to CNT3). According to an embodiment, the ninth pattern (PAT9) may be formed to further correspond to the fourth contact hole (CNT4).

[0175] In the step S3600 of depositing a metal (3610), the metal (3610) may be deposited in the first to fourth contact holes (CNT1 to CNT4). The metal (3610) may include at least one of various transparent conductive materials, including, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO). The metal (3610) may be implemented to be substantially transparent or translucent so as to satisfy a predetermined light transmittance. In the step S3600 of depositing the metal (3610), a process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) may be performed.

[0176] In the step (S3700) of forming the first and second electrodes, the eighth photoresist (3310) may be removed. As the eighth photoresist (3310) is removed, the metal (3610) deposited on the eighth photoresist (3310) may be removed together. An a-first electrode (ET1a) may be formed in the third contact hole (CNT3). A b-first electrode (ET1b) may be formed in the second contact hole (CNT2). A c-first electrode (ET1c) may be formed in the first contact hole (CNT1).

[0177] Referring to FIG. 37, a light-emitting structure (EMS) may be formed on a third temporary substrate (BSL3). The light-emitting structure (EMS) may include first to third light-emitting layers, first to third transparent conductive layers (331, 332, 333), first to third insulating layers (321, 322, 323), a passivation layer (310), etc.

[0178] The light-emitting structure (EMS) may further include a light-shielding layer (370). The light-shielding layer (370) may perform a function of preventing light emitted from each pixel from being mixed.

[0179] Referring to FIGS. 38 and 39, the steps of contacting the light emitting structure (EMS) are illustrated.

[0180] A method for manufacturing a display panel according to embodiments of the present disclosure may include a step (S3800) of contacting a light-emitting structure (EMS) to a substrate (SUB) and a step (S3900) of detaching a third temporary substrate (BSL3).

[0181] In the step (S3800) of contacting the light-emitting structure (EMS) to the substrate (SUB), the first electrode may be connected to a pixel circuit (PXC; see FIG. 2), and the second electrode (ET2) may be connected to a second power line (PL2; see FIG. 2). The a-first electrode (ET1a) may be connected to the pixel circuit (381) of the first pixel (PXL1). The b-first electrode (ET1b) may be connected to the pixel circuit (382) of the second pixel (PXL2). The c-first electrode (ET1c) may be connected to the pixel circuit (383) of the third pixel (PLX3). The second electrode (ET2) may be connected to the second power line (390).

[0182] In the step of detaching the third temporary substrate (BSL3) (S3900), the third temporary substrate (BSL3) can be separated from the third-second semiconductor layer (363). In the step of detaching the third temporary substrate (BSL3) (S3900), a laser lift-off process can be performed.

[0183] FIG. 40 is a schematic drawing showing a display panel manufactured according to FIGS. 4a to 39.

[0184] The display panel manufactured according to FIGS. 4a to 39 is substantially identical to the display panel illustrated in FIG. 3.

[0185] Although the light emitting structure (EMS) of one unit pixel (PXU) is illustrated in FIG. 40, embodiments of the present disclosure are not limited thereto. For example, the light emitting structures (EMS) of two or more unit pixels (PXU) may be integrally formed and placed on a substrate (SUB).

[0186] Meanwhile, display panels according to embodiments of the present disclosure may not use a planarization layer utilizing an organic insulating layer in the process of manufacturing the light-emitting structure (EMS). This may enable the manufacturing of a thin light-emitting structure (EMS). Furthermore, the time required for the etching process can be significantly reduced.

[0187] According to embodiments of the present disclosure, a light-emitting structure (EMS) can be manufactured in units of unit pixels (PXU). This allows for providing a display panel (or display device) capable of displaying high-resolution images.

[0188] FIGS. 41 to 44 are schematic examples of electronic devices according to embodiments of the present disclosure.

[0189] Referring to FIG. 41, the display device according to the above-described embodiments may be applied to smart glasses (4100). The smart glasses (4100) may include a frame (4110) and a lens portion (4120). The smart glasses (4100) are wearable electronic devices that can be worn on a user's face, and may have a structure in which a portion of the frame (4110) can be folded or unfolded. For example, the smart glasses (4100) may be a wearable device for augmented reality (AR).

[0190] The frame (4110) may include a housing (4110b) that supports a lens unit (4120) and a leg unit (4110a) for wearing by a user. The leg unit (4110a) is connected to the housing (4110b) by a hinge and may be folded or unfolded.

[0191] The frame (4110) may include a battery, a touch pad, a microphone, and / or a camera. In addition, the frame (4110) may include a projector that outputs light and / or a processor that controls light signals.

[0192] The lens unit (4120) may be an optical member that transmits light or reflects light. The lens unit (4120) may include glass and / or transparent synthetic resin.

[0193] The display device according to the above-described embodiments may be applied to the lens unit (4120). For example, a user may recognize an image displayed by an optical signal transmitted from a projector of the frame (4110) through the lens unit (4120). For example, the user may recognize information such as the time and date displayed on the lens unit (4120).

[0194] Referring to FIG. 42, the display device according to the above-described embodiments may be applied to a head-mounted display (HMD) (4200). The head-mounted display (4200) may include a head-mounted band (4210) and a display storage case (4220). For example, the head-mounted display (4200) may be a wearable electronic device that can be worn on a user's head.

[0195] The head-mounted band (4210) can be connected to the display storage case (4220) to secure the display storage case (4220). As illustrated in FIG. 42, the head-mounted band (4210) can include a horizontal band and a vertical band to secure the head-mounted display (4200) to the user's head. The horizontal band can be provided to surround the side of the user's head, and the vertical band can be provided to surround the upper part of the user's head. However, the embodiments of the present disclosure are not limited thereto, and the head-mounted band (4210) can also be implemented in the form of a glasses frame or a helmet.

[0196] The display storage case (4220) can store a display device (or display panel (PNL; see FIG. 1)). The display storage case (4220) can include at least one lens. The lens can provide an image to a user. For example, the display device (or display panel (PNL)) according to the above-described embodiments can be applied to a left-eye lens and a right-eye lens implemented in the display storage case (4220).

[0197] Referring to FIG. 43, the display device (or display panel (PNL; see FIG. 1)) according to the above-described embodiments can be applied to a smart watch (4300). The smart watch (4300) can include a display unit (4310) and a strap unit (4320). The smart watch (4300) is a wearable electronic device, and the strap unit (4320) can be worn on a user's wrist. The display device according to the above-described embodiments can be applied to the display unit (4310). For example, the display unit (4310) can provide image data including information such as time and date.

[0198] Referring to FIG. 44, the display device (or display panel (PNL; see FIG. 1)) according to the above-described embodiments may be applied to an automotive display (4400). As an example, the automotive display (4400) may refer to an electronic device provided inside and / or outside a vehicle to provide image data.

[0199] For example, the display device (or display panel (PNL; see FIG. 1)) according to the above-described embodiments may be applied to at least one of an infotainment panel (4410), a cluster (4420), a co-driver display (4430), a head-up display (4440), a side mirror display (4450), and a rear seat display (4460) provided in a vehicle.

[0200] While embodiments are disclosed herein, and terminology is employed, they are to be construed in a generic and technical sense, not for purposes of limitation. In some instances, as will be apparent to one skilled in the art, unless specifically indicated, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, various changes in form and detail will be apparent to those skilled in the art without departing from the spirit and scope of the disclosure.

Claims

1. A substrate in which a first pixel emitting light of a first wavelength band, a second pixel emitting light of a second wavelength band, and a third pixel emitting light of a third wavelength band are arranged, each of the first to third pixels including a pixel circuit; A first light-emitting layer positioned on the substrate and emitting light of the first wavelength band; A second light-emitting layer positioned on the first light-emitting layer and emitting light of the second wavelength band; A third light-emitting layer positioned on the second light-emitting layer and emitting light of the third wavelength band; An a-first electrode electrically connected to the pixel circuit of the first pixel and electrically connected to the first light-emitting layer through the first contact hole; A b-first electrode electrically connected to the pixel circuit of the second pixel and electrically connected to the second light-emitting layer through a second contact hole from which at least a portion of the first light-emitting layer is removed; a c-first electrode electrically connected to the pixel circuit of the third pixel and electrically connected to the third light-emitting layer in a third contact hole from which at least a portion of the first and second light-emitting layers is removed; and A display panel including a second electrode electrically connected to the pixel circuit of each of the first to third pixels and electrically connected to the first to third light-emitting layers in a fourth contact hole from which at least a portion of the first to third light-emitting layers is removed.

2. In paragraph 1, The above first light-emitting layer is, A first semiconductor layer providing electrons; A second semiconductor layer providing a hole; and Including an active layer positioned between the first semiconductor layer and the second semiconductor layer, A display panel wherein the first semiconductor layer is electrically connected to one of the a-first electrode and the second electrode, and the second semiconductor layer is electrically connected to the other of the a-first electrode and the second electrode.

3. In paragraph 2, The thickness of the first semiconductor layer is thicker than the thickness of the second semiconductor layer, A display panel wherein the first semiconductor layer is electrically connected to the second electrode, and the second semiconductor layer is electrically connected to the a-first electrode.

4. In paragraph 1, The above display panel, A passivation layer positioned on the substrate and covering side surfaces of the a to c-first electrodes; A first insulating layer positioned on the passivation layer; A first transparent conductive layer positioned between the passivation layer and the first light-emitting layer, the a-first electrode being electrically connected in an area where at least a portion of the passivation layer is removed; A second insulating layer positioned on the second light-emitting layer; A second transparent conductive layer positioned between the second insulating layer and the second light-emitting layer, the second b-th electrode being electrically connected in an area where at least a portion of the passivation layer is removed; a third insulating layer positioned on the second light-emitting layer; and A display panel further comprising a third transparent conductive layer positioned between the third insulating layer and the third light-emitting layer, the c-th first electrode being electrically connected in an area where at least a portion of the passivation layer is removed.

5. In paragraph 4, The above display panel further includes a light-shielding layer positioned in the via holes surrounded by the passivation layer, The above via holes are, A first via hole located in an area where at least a portion of the first insulating layer, the first transparent conductive layer, the first light-emitting layer, the second insulating layer, the second transparent conductive layer, the second light-emitting layer, the third insulating layer, the third transparent conductive layer, and the third light-emitting layer are removed; A second via hole located in an area where at least a portion of the first insulating layer, the first transparent conductive layer, the first light-emitting layer, the second insulating layer, the second transparent conductive layer, and the second light-emitting layer are removed; and A display panel including a third via hole located in an area where at least a portion of the first insulating layer, the first transparent conductive layer, and the first light-emitting layer are removed.

6. In paragraph 5, A display panel in which the above-mentioned shade layer is formed using at least one of an electrolytic plating process and a deposition process.

7. In paragraph 6, The above-mentioned light-shielding layer is a display panel that is flattened on the above-mentioned passivation layer.

8. In paragraph 1, A display panel wherein the first wavelength band is a red wavelength band, the second wavelength band is a green wavelength band, and the third wavelength band is a blue wavelength band.

9. In paragraph 4, A display panel wherein each of the first to third insulating layers includes an inorganic insulating layer.

10. A step of forming a third light-emitting layer, a third transparent conductive layer, a third insulating layer, a second light-emitting layer, a second transparent conductive layer, a second insulating layer, a first light-emitting layer, a first transparent conductive layer, and a first insulating layer on a temporary substrate; A step of forming a first via hole, a second via hole, and a third via hole on the first insulating layer, wherein the first via hole exposes at least a portion of the third light-emitting layer, the second via hole exposes at least a portion of the second light-emitting layer, and the third via hole exposes at least a portion of the first light-emitting layer; A step of forming a first passivation layer surrounding the first to third via holes; A step of forming a first contact hole, a second contact hole, and a third contact hole on the first passivation layer, wherein the first contact hole exposes at least a portion of the third transparent conductive layer, the second contact hole exposes at least a portion of the second transparent conductive layer, and the third contact hole exposes at least a portion of the first transparent conductive layer; A step of forming a second passivation layer surrounding the first to third contact holes; A step of removing the second passivation layer in an area corresponding to the first to third contact holes; A step of forming a fourth contact hole on the second passivation layer; A step of forming a c-first electrode in the first contact hole, forming a b-first electrode in the second contact hole, forming an a-first electrode in the first contact hole, and forming a second electrode in the second contact hole; a step of electrically connecting the a to c-first electrodes and the second electrode to the pixel circuit of the substrate; and A method for manufacturing a display panel, comprising the step of detaching the temporary substrate.

11. In paragraph 10, The step of forming the first to third via holes on the first insulating layer is, A step of forming a first photoresist including a first pattern on the first insulating layer; A step of forming a first via hole exposing at least a part of the third light-emitting layer in an area corresponding to the first pattern; A step of forming a second photoresist including a second pattern on the first insulating layer; A step of forming a second via hole exposing at least a part of the second light-emitting layer in an area corresponding to the second pattern; A step of forming a third photoresist including a third pattern on the first insulating layer; and A method for manufacturing a display panel, comprising the step of forming a third via hole exposing at least a portion of the first light-emitting layer in an area corresponding to the third pattern.

12. In paragraph 10, The step of forming the first to third contact holes on the first passivation layer is: A step of forming a fourth photoresist including a fourth pattern on the first passivation layer; A step of forming a first contact hole exposing at least a part of the third transparent conductive layer in an area corresponding to the fourth pattern; A step of forming a fifth photoresist including a fifth pattern on the first passivation layer; A step of forming a second contact hole exposing at least a part of the second transparent conductive layer in an area corresponding to the fifth pattern; A step of forming a sixth photoresist including a sixth pattern on the first passivation layer; and A method for manufacturing a display panel, comprising the step of forming a third contact hole exposing at least a portion of the first transparent conductive layer in an area corresponding to the sixth pattern.

13. In paragraph 10, The step of removing the second passivation layer in the area corresponding to the first to third contact holes is, A step of forming a seventh photoresist including a seventh pattern on the second passivation layer, wherein the seventh pattern is formed by removing at least a portion of the seventh photoresist in an area corresponding to the first to third contact holes; and A method for manufacturing a display panel, comprising the step of removing the second passivation layer in an area corresponding to the seventh pattern.

14. In paragraph 10, The step of forming the fourth contact hole on the second passivation layer is, A step of forming an eighth photoresist including an eighth pattern on the second passivation layer; and A method for manufacturing a display panel, comprising the step of forming a fourth contact hole in an area corresponding to the eighth pattern.

15. In paragraph 10, A method for manufacturing a display panel further comprising the step of forming a light-blocking layer in an area corresponding to the first to third via holes in an area surrounded by the first passivation layer.

16. In paragraph 15, A method for manufacturing a display panel in which the above-mentioned light-shielding layer is formed using a damascene process.

17. In paragraph 15, A method for manufacturing a display panel, wherein the above-mentioned light-shielding layer is formed using at least one of a chemical vapor deposition method, a physical vapor deposition method, and an atomic layer deposition method.

18. In paragraph 10, A method for manufacturing a display panel, wherein the first passivation layer and the second passivation layer constitute one passivation layer.

19. In paragraph 10, The above temporary substrate is a third temporary substrate, The step of forming a third light-emitting layer, a third transparent conductive layer, a third insulating layer, a second light-emitting layer, a second transparent conductive layer, a second insulating layer, a first light-emitting layer, a first transparent conductive layer, and a first insulating layer on the temporary substrate is as follows. A step of growing the first light-emitting layer on a first temporary substrate; A step of growing the second light-emitting layer on a second temporary substrate; A step of growing the third light-emitting layer on the third temporary substrate; A step of forming a first intermediate insulating layer on the first light-emitting layer; A step of forming a second intermediate insulating layer on the second light-emitting layer; A step of forming a third intermediate insulating layer on the third light-emitting layer; A step of forming a fourth intermediate insulating layer on a fourth temporary substrate; A step of forming a fifth intermediate insulating layer on a fifth temporary substrate; A step of forming the first insulating layer by bonding the first intermediate insulating layer and the fourth intermediate insulating layer; A step of forming a sixth intermediate insulating layer by bonding the second intermediate insulating layer and the fifth intermediate insulating layer; A step of detaching the first temporary substrate; A step of detaching the second temporary substrate; A step of forming a seventh intermediate insulating layer on the first light-emitting layer; A step of forming an eighth intermediate insulating layer on the second light-emitting layer; A step of forming the third insulating layer by bonding the third intermediate insulating layer and the eighth intermediate insulating layer; A step of detaching the fifth temporary substrate; A step of forming the first insulating layer by bonding the sixth intermediate insulating layer and the seventh intermediate insulating layer; and A method for manufacturing a display panel, comprising the step of detaching the fourth temporary substrate.

20. A lens section for displaying an image; and Including a frame supporting the above lens portion, The above lens part, A substrate in which a first pixel configured to emit light of a first wavelength band, a second pixel configured to emit light of a second wavelength band, and a third pixel configured to emit light of a third wavelength band are arranged, each of the first to third pixels including a pixel circuit; A first light-emitting layer positioned on the substrate and configured to emit light of the first wavelength band; A second light-emitting layer positioned on the first light-emitting layer and configured to emit light of the second wavelength band; A third light-emitting layer positioned on the second light-emitting layer and configured to emit light of the third wavelength band; An a-first electrode connected to the pixel circuit of the first pixel and electrically connected to the first light-emitting layer through the first contact hole; A b-first electrode connected to the pixel circuit of the second pixel and electrically connected to the second light-emitting layer through a second contact hole from which at least a portion of the first light-emitting layer is removed; a c-first electrode electrically connected to the third light-emitting layer through a third contact hole from which at least a portion of the first and second light-emitting layers is removed, and connected to the pixel circuit of the third pixel; and A smart glass comprising a second electrode connected to the pixel circuit of each of the first to third pixels and connected to the first to third light-emitting layers through a fourth contact hole from which at least a portion of the first to third light-emitting layers is removed.

Images