Monolithic three-dimensional (3D) integration of two dimensional (2D) field effect transistors (FETS)

Abstract

Embodiments relate to a monolithic integrated circuit. The circuit includes a substrate and plural tiers formed on the substrate. Each tier includes a 2-D planar layer of electrical elements. The plural tiers are stacked in vertical direction so that the geometric planes of each 2-D planar layer are parallel to each other. Embodiments also relate to a method of generating a monolithic integrated circuit. The method involves depositing a nanomaterial on a substrate to generate a first tier having a 2-D planar layer of the nanomaterial. One or more electrical elements are formed in and / or on the 2-D planar layer of the first tier. An inter-layer is deposited on the first tier. A nanomaterial is deposited on the inter-layer to generate a second tier comprising a 2-D planar layer of the nanomaterial. One or more electrical elements are formed in and / or on the 2-D planar layer of the second tier.

Description

MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATION OF TWO DIMENSIONAL (2D) FIELD EFFECT TRANSISTORS (FETS)CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application is related to and claims the benefit of U.S. provisional patent application no. 63 / 604,933, filed on December 1, 2023, the entire contents of which is incorporated herein by reference.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Grant Nos. DMR-2039351 and ECCS-2042154 awarded by the National Science Foundation and under Grant No. W911NF-18- 1-0268 awarded by the U.S. Army / ARO. The Government has certain rights in the invention.FIELD OF THE INVENTION

[0003] Embodiments can relate to a monolithic integrated circuit having plural tiers formed on a surface of a substrate in which each tier is composed of a 2-D planar layer of electrical elements.BACKGROUND OF THE INVENTION

[0004] According to the international roadmap for devices and systems (IRDS - 2021), it is necessary to pursue 3D integration to maximize device integration density per die and to achieve co-integration of clustered functional stacks (like chemical / gas / optical sensing) with logic and memory. Currently, silicon technologies employ through-silicon-via (TSV) based 3D integration, which is limited in-terms of scaling TSV dimensions to the level of transistor dimensions and the increased design / fabri cation complexity associated with the use of multiple dies and wafer thinning steps. In contrast, monolithic 3D (M3D) integration can enable higher via density and design flexibility. While silicon has been the backbone of scaling transistors so far, M3D integration using silicon face several challenges such as thermal budget violations for fabricating upper tier devices in a 3D stack. On the other hand, it is theoretically studied and reported that 2D materials based M3D integration can enable scaling of tier thicknesses to sub- pm ranges (owing to their atomic thicknesses) and has the potential to achieve >150 % integration density improvement in comparison to conventional M3D approaches using silicon.SUMMARY OF THE INVENTION

[0005] Embodiments can relate to a monolithic integrated circuit. The monolithic integrated circuit can include a substrate. The monolithic integrated circuit can include plural tiers formed on a surface of the substrate. Each tier can include a 2-D planar layer of electrical elements. The plural tiers can be stacked in vertical direction. This can include being stacked so that the geometric planes of each 2-D planar layer are parallel to each other.

[0006] In some embodiments, each 2-D planar layer can be composed of a nanomaterial.

[0007] In some embodiments, the nanomaterial can be a M0S2 film and / or a WSe2 film.

[0008] In some embodiments, the electrical elements can include at least one filed-effect transistor.

[0009] In some embodiments, the at least one filed-effect transistor can include a gate, a drain, a source, and a channel formed in and / or on the 2-D planar layer.

[0010] In some embodiments, the substrate can be a semiconductor material.

[0011] In some embodiments, the semiconductor material can be SiCh or AI2O3.

[0012] In some embodiments, monolithic integrated circuit can include an inter-layer positioned between at least two tiers.

[0013] In some embodiments, the inter-layer can be configured to electrically isolate at least a portion of one tier from at least a portion of another tier of the at least two tiers.

[0014] In some embodiments, the inter-layer can be a dielectric material.

[0015] In some embodiments, the dielectric material can be AI2O3.

[0016] Embodiments can relate to a method of generating a monolithic integrated circuit. The method can involve depositing a nanomaterial on a substrate to generate a first tier including a 2- D planar layer of the nanomaterial. The method can involve forming one or more electrical elements in and / or on the 2-D planar layer of the first tier. The method can involve depositing an inter-layer on the first tier. The method can involve depositing a nanomaterial on the inter-layer to generate a second tier including a 2-D planar layer of the nanomaterial. The method can involve forming one or more electrical elements in and / or on the 2-D planar layer of the second tier.

[0017] In some embodiments, the nanomaterial of the first tier can be the same as or different from the nanomaterial of the second tier.

[0018] In some embodiments, depositing the nanomaterial to form the first tier and / or the second tier can involve a chemical vapor deposition technique.

[0019] In some embodiments, forming one or more electrical elements for the first tier and / or the second tier can involve a spin coating technique and an etching technique.

[0020] In some embodiments, the one or more electrical elements for the first tier and / or the second tier can include at least one filed-effect transistor.

[0021] In some embodiments, the at least one filed-effect transistor can include a gate, a drain, a source, and a channel.

[0022] In some embodiments, the substrate can be SiCh or AI2O3; the inter-layer can be a dielectric material; the nanomaterial can be a M0S2 film and / or a WSe2 film.

[0023] In some embodiments, the inter-layer electrically can isolate at least a portion of the first tier from at least a portion of the second tier.

[0024] Further features, aspects, objects, advantages, and possible applications of the present invention will become apparent from a study of the exemplary embodiments and examples described below, in combination with the Figures, and the appended claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, aspects, features, advantages and possible applications of the present innovation will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings. Like reference numbers used in the drawings may identify like components.

[0026] FIG. 1 shows a schematic illustrating an exemplary 3D integration of 2D FETs.

[0027] FIG. 2 shows a high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) image illustrating a cross-section of an exemplary 3-tier 3D IC based on 2D TMD.

[0028] FIG. 3 shows a scanning electron micrograph of a 2D FET with channel length, .cii = 45 nm, and contact length, Lc = 90 nm from an exemplary 2-tier 3D IC with more than 200 aggressively scaled devices.

[0029] FIG. 4 shows an optical image illustrating an exemplary wafer-scale monolithic 2-tier 3D integration of 2D FETs with more than 12,000 devices in each tier, using a fabrication process that requires low thermal budget of 180 °C.

[0030] FIG. 5 shows a HAADF-STEM image illustrating a via connection between tier 1 and 2 devices for an exemplary 3D circuit.

[0031] FIG. 6 shows schematic of an exemplary 2D FET that can be formed as an electrical element within a tier.

[0032] FIGS. 7A-7B show an exemplary wafer scale 3D integration of 2D FETs. Transfer characteristics of 10,000 M0S2 FETs on tier 1 (FIG. 7A) and tier 2 (FIG. 7B) is provided. In addition, heatmaps and the corresponding histograms of subthreshold slope, (S3), ON-current ( / ON), and threshold voltage (FTH) for five dies in each tier are illustrated.

[0033] FIG. 8 shows a top view of false colored SEM image of an exemplary 3-tier 3D device stacks with the same color-coded contact pads (gate, source and drain) representing tier 1, 2, and 3, respectively.

[0034] FIG. 9 shows a HAADF-STEM image of the cross section of an exemplary 3D stack obtained by focused ion-beam (FIB) milling on the region pointed out in FIG. 8. Each tier shows the stack of Ti / Pt gate electrode, AI2O3 / HfCE / AI2O3 gate dielectric, M0S2 channel, and the Ni / Au contacts; each tier is separated by the inter-tier dielectric (AI2O3).

[0035] FIG. 10 shows energy dispersive spectroscopy (EDS) elemental mapping of the stack in FIG. 9.

[0036] FIG. 11 shows transfer characteristics for 200 M0S2 FETs from tier 1, tier 2, and tier 3.

[0037] FIG. 12 shows transfer characteristics for 200 WSe2 FETs from tier 1, tier 2, and tier 3.

[0038] FIG. 13 shows transfer characteristics for 200 scaled M0S2 devices with Ecu = 45 nm and Lc = 90 nm on tier 1.

[0039] FIG. 14 shows transfer characteristics for 200 scaled M0S2 devices with Ecu = 45 nm and Ec = 90 nm on tier 2.

[0040] FIGS. 15A-15G show an exemplary M3D integration of CMOS WSe2 FETs. FIG. 15A is an optical image showing an M3Dintegrated, two-tier CMOS circuit based on WSe2 FETs. FIG. 15B show that in this configuration, each cell comprises four devices. Here two p-FET devices are positioned directly on top of two n-FET devices. FIG. 15C shows angled, false- colored SEM of the two-tier cell, corresponding to a two-stage inverter circuit. In particular, the via width and pitch achieved in this work are 300 nm and 1 pm, respectively. FIG. 15D shows a schematic of an M3D-integrated CMOS NAND circuit. FIG. 15 E shows an associated false-colored SEM image. The interconnects and vias are labelled, highlighting the dense connectivity obtained through M3D integration. FIG. 15F is a HAADF-STEM image showing the crosssection of the 3D NAND circuit, taken at the dotted line in FIG 15 E. Vertical elongation was applied in FIG. 15F to reveal features better. Zoomed-in HAADF-STEM and EDS elemental mapping of tier-1 (FIG. 15G) and tier-2 (FIG. 15H) WSe2 devices are displayed.

[0041] FIGS. 16A-16E show synthesis of large-area MOCVD WSe2 and fabrication of a 3D stack. FIG. 16A is an optical image of the two-inch growth of multilayer (ML) WSe? using MOCVD. FIG. 16B is an atomic force microscopy image of ML-WSe2 at the center of the wafer. Multilayer islands are observed on the coalesced film. FIG. 16C shows a HAADF- STEM image of the ML-WSe2 taken from the c axis, showing the atomic structure of the as- grown film. FIG. 16D show PL spectra of the \VSe2 film. The peak position was found to be -1.65 eV, correlating to multilayer WSe2. FIG. 16E shows Raman spectra of the WSe2 film consisting of the characteristic in-plane E^g peak at 249 cm-1 and out-of-plane 2LA(M) peak at 258 cm-1. Raman and PL spectra were both taken at ten spots across the two-inch WSe2 wafer.

[0042] FIGS. 17A-17J pertain to exemplary M3 D -integrated CMOS WSe2FETs. FIG. 17A shows transfer characteristics of 340 tier-1 WSe2 n-FETs of channel length (LCH) of 300 nm and width (W) of 1 pm. FIGS. 17B, 17C, 17D, and 17E show corresponding histograms of threshold voltage (ViH-n) (b) extracted at a drain current (IDS) of 100 nA pm-1 for the n-branch, subthreshold slope (SSn) for two orders of change in IDS (FIG. 17C), ON-current (In) (FIG. 17D) and electron field-effect mobility (pn) (FIG. 17E). FIGS. 17F, 17G, 17H, 171 and 17J show transfer characteristics of 340 tier-2 WSe2 p-FETs (FIG. 17F), with the corresponding histograms showing the distributions of Vm-p for the p-branch (FIG. 17G), SSp (FIG. 17H), Ip (FIG. 171) and hole field-effect mobility (pp) (FIG. 17J). Note that all the parameters were extracted at a drain bias (VDS) of 1 V.

[0043] FIGS. 18A, 18B, and 18C show exemplary M3D integrated logic gates by illustrating a schematic, false-colored SEM image, and output characteristics of a representative M3D integrated inverter (FIG. 18 A), NOR gate (FIG. 18B) and NAND gate (FIG. 18C). The peak gain achieved in the best-performing inverter was -79 for VDD = 3 V. Distinct logic levels were obtained for the NAND and NOR gates.

[0044] FIGS. 19A, 19B, 19C, and 19D show transfer characteristics of FETs fabricated using (FIG. 19A) bilayer, and (FIG. 19B) multilayer WSe2 films grown via MOCVD. Comparison of the extracted (FIG. 19C) IPMAX and (FIG. 19D) EIMAX for the FETs fabricated using bilayer and multilayer WSe2.

[0045] FIG. 20A shows transfer characteristics of 250 devices employing Pd and Ni contacts on WSe2 FETs. Corresponding histograms comparing the (FIG. 20B) IPMAX , and (FIG. 20C) EIMAX of the Pd- and Ni-contacted WSe2 FETs.

[0046] FIGS. 21A, 21B, and 21C show transfer characteristics of 50 tier 1 WSe2 FETs with nickel contacts before and after ILD deposition. The corresponding histograms show the change in (FIG. 21B)) EIMAX , and (FIG. 21C) SSn for both conditions. The observed improvement in IDS, shift in the VTH-n, and lack of SSn degradation confirms doping of the WSe2 channel due to the deposition of the ILD.

[0047] FIGS. 22A and 22B show Raman (FIG. 22A) and PL spectra (FIG. 22B) of the WSe2film used in this study taken at 100 points across a representative 10 pm x 10 pm area before and after ALD of AI2O3.

[0048] FIGS. 23 A, 23B, 23C, and 23D show a comparison of planar and Tier 2 WSe2 Devices. FIG. 23 A shows transfer characteristics of 240 planar and tier-2 WSe2 FETs with Pd contacts. The corresponding histograms show the change in (FIG. 23B) IPMAX, (FIG. 23C) ViH-p, and (FIG. 23D) SSp for both conditions. Devices fabricated on tier 2 outperform the planar devices, suggesting that the uniformity of growth and the transfer quality play a greater role in the performance and yield of devices.

[0049] FIGS. 24A, 24B, and 24C show effect of HfCh Transfer characteristics of 40 WSe2 FETs of LCH = 35 nm and W = 800 nm (FIG. 24 A) before and (FIG. 24B) after depositing 5 nm HfO2, demonstrating a retention of p-branch characteristics and a lack of the n-doping that was observed during following deposition of A12O3. FIG. 24C transfer characteristics of the HfO2- capped WSe2 after 20 s O2 plasma exposure, demonstrating a retention of p-branch characteristics and a lack of the n-doping that was observed following the deposition of A12O3. This approach thus enables further stacking of WSe2 FETs beyond 2 tiers as well as customization of polarity type for each tier, based on the deposited ILD.

[0050] FIGS. 25A, 25B, and 25C show inverter statistics. FIG. 25A shows output characteristics of 27 M3D integrated inverters and FIG. 25B shows the distribution of the peak gain achieved. FIG. 25C shows the output characteristics of a programmable inverter, in which the inflection point can be modified based on the VP applied.

[0051] FIG. 26 shows characterization of 2D materials and fabrication process flow for M3D integration. Panel (a) is an optical image of a 2 inch sapphire wafer with MOCVD-grown M0S2. Scale bar, 2.5 cm (1 inch). Panel (b) is the corresponding Raman spectrum with the characteristic E g peak at 387 cm-1 and Alg peak at 404 cm-1. Panel (c) is an optical image of commercially purchased monolayer graphene film on a copper substrate. Scale bar, 40 mm. Panel (d) shows corresponding Raman spectra obtained using a 532 nm laser. Panel (e) shows fabrication process flow of the 3D monolithic and heterogeneous integration of monolayer- M0S2- and graphene-based devices.

[0052] FIG. 27 shows monolithic and heterogeneous 3D ICs. Panel (a) shows an optical image of a densely packed array of M3D-integrated two-tier cells based on monolayer M0S2 and graphene. Scale bar, 25 pm. Panel (b) shows an enlarged SEM image showing that each cell in the array contains four devices, including two graphene chemitransistors above two M0S2 memtransistors. Scale bar, 3 pm. Panel (C) shows an angled SEM image. Notably, the via width and pitch achieved in this work are 3 and 4 pm, respectively. Scale bar, 3 pm. Panel (d) shows a cross-sectional STEM-HAADF image. Scale bar, 1 pm. Panel (e) shows an enlarged version of the HAADF images taken at the location marked with light orange dashed line, showing the entire M3D stack involving both M0S2 and graphene channels with a separation of 50 nm. Panel (f) shows an enlarged version of EDS mass percentage elemental mapping showing the M0S2 memtransistor and its floating-gate stack. Scale bars are 20 nm.

[0053] FIG. 28 shows characterization of M0S2 mem transistors in tier 1. Panel (a) shows transfer characteristics, that is, source-to-drain current, IDS versus back-gate voltage, VBG, taken at a constant drain voltage, VDS, of 1 V, for 50 M0S2 memtransistors with a LCH and WCH of 1 pm. Panels (b, c, and d) sow histograms showing the pFE (panel b), SS (panel c) and VTH (panel d) for these 50 devices. Panels (e) and (f) show transfer characteristics of a representative memtransistor after programming or erasing with positive (panel (e)) and negative (panel (f)) voltage pulses of varying magnitudes for 100 ps each. Panel (g) show non-volatile retention forhigh and low conductance states measured using a VBG of 0 V and a VDS of 1 V for 6,000 s. Panel (h) shows analogue programming and retention for four distinct conductance states. Panel (i) shows circuit diagrams for a comparator consisting of two M0S2 mem transistors (MT1 and MT2). Panel (j) shows a transfer curve for the comparator, that is, the output voltage, VOUT, as a function of the input voltage, VIN. S witching occurs at a VIN of 200 mV, which is denoted as the reference voltage, VREF, for the comparator. Panel (k) shows different VREF obtained by programming MT2, panel (1) shows VOUT achieved in response to an arbitrary input waveform for a VREF of 0 V and a VDD of 2 V.

[0054] FIG. 29 shows electrical characterization of graphene chemitransistors. Panel (a) shows transfer characteristics of 130 graphene chemitransistors taken at a J DS of 500 mV. Panels (b), (c), and (d) show distribution of Foimc (panel b), / / FE,N (panel c) and / / FE,P (panel d) for all 130 graphene chemitransistors. Panel (e) shows a schematic diagram of a graphene-based chemisensor consisting of two graphene chemitransistors, GC1 and GC2, connected in series. Panel (f) shows FGT as a function of FLTG with a FDD.GT of 500 mV under different concentration of NaCl solution (20, 40, 60 and 100 mM). panel (g) shows monotonic FGr evolution with increasing NaCl concentration obtained at two different FLTG values of 0.45 and 0.55 V.

[0055] FIG. 30 shows near-sensor compute using M3D ICs. Panel (a) shows an optical image of the M3D chip with a chemical solution on top. Panel (b) shows 3D circuit layout illustrating the connection between a graphene-chemitransistor-based chemical sensor in tier 2 and an M0S2- memtransistor-based comparator in tier 1, enabled by an inter-tier via. Panel (c) shows transfer curves for the chemisensor in response to two different sugar solutions. Panel (d) shows temporal evolution of the transfer curves for the dilute sugar solution when left to evaporate for 15 min. Panel (e) shows J GI measured at a FLTG of 0.75 V and and corresponding output from the comparator, I OUT (panel f), with different programmed PREF, as a function of time. Panels g and h show tansfer curves for 16 chemisensors in response to four different chemicals, Cl to C4 (panel g), and corresponding FGT extracted at a FLTG of 0.6 V (panel h). Panels i and j show onedimensional (panel i) and 2D (panel j) digital code for each chemical obtained using the same circuit architecture shown in pane (b).

[0056] FIG. 31 shows a monolithic and heterogeneous 3D integration of 2D materials. The schematic shows a M3D stack comprising graphene chemitransistor-based chemisensors in tier 2connected to MoSz-memtransistor-based comparator in tier 1 for near sensor computing application.

[0057] FIG. 32 shows surface topography and roughness of M3D IC. Atomic force microscope (AFM) images and height profdes after (panel a) fabrication of tier 1 M0S2 devices, (panel b) post-ILD deposition, and (panel c) after the via formation and fabrication of tier 2 graphene devices. Panel (d) show surface roughness on top of the ILD over 5 pm x 5 pm area showing a mean roughness of 270 pm.

[0058] FIG. 33 shows output characteristics for an M0S2 mem transistor. Output characteristics, that is, source-to-drain current, IDS, versus drain voltage, VDS, at different back-gate voltage, VBG, ranging from 0 to 7 V in steps of 1 V, for a representative M0S2 memtransistor.

[0059] FIG. 34 shows extraction of contact resistance for M0S2 memtransistors. Panel (a) shows via resistance as a function of via-area. Panel (b) shows an SEM image of the traditional transmission line measurement (TLM) design showing channel lengths of 100 nm, 200 nm, 500 nm, and 1000 nm used to extract the contact resistance. Panel (c) shows corresponding transfer characteristics for MoS2 memtransistors obtained from 25 TLM structures. Panel (d) shows extracted total resistance (RT) as a function of LCH for an inversion carrier density, ns = 5 x 1012 cm-2. Panel (e) shows RC extracted from the y-intercept of the RT versus LCH plots as a function of ns. RT = RCH + 2RC. RCH is proportional to LCH and inversely proportional to the carrier density (ns), RC, however, is independent of LCH.

[0060] FIG. 35 shows endurance measurements for an M0S2 memtransistor. The read current measured at a VBG of 0 V using a VDS of 1 V every time after programming a representative M0S2 memtransistor in its high and low conductance states for a total of 1000 cycles. No degradation in the memory ratio (MR) highlights the fact that our MoS2 memtransistors offer high endurance.

[0061] FIG. 36 shows 6 supply voltage dependence of an M0S2 memtransistor based comparator. Transfer characteristics of a representative MoS2-memtransistor-based comparator for different VDD.

[0062] FIG. 37 shows impact of ILD on MoS2 memtransistors. Transfer characteristics and extracted distributions for threshold voltage (VTH), field-effect mobility (pFE), and subthreshold swing (SS) for 50 M0S2 mem transistors with an LCH of 500 nm (panel a) before and (panel b)after the ILD deposition. We observed a negative 4.5 V shift in the median VTH value, which can be ascribed to n-type surface charge transfer doping (SCTD) from ALD AI2O3.Additionally, there was an improvement in the median pFE from 3.31 cm2V-ls-l to 7.27 cm2V-ls-l. However, the median SS experienced a degradation from 150 mV / dec to 375 mV / dec. Despite these changes, it is important to note that the functionalities of M0S2 memtransistors were not adversely affected. For example, the observed shift in VTH could be compensated using the programming capability of the FG stack to ensure proper logic levels for the intended applications.

[0063] FIG. 38 shows impact of variability on chemisensor output. cVoltage transfer curves appear complementary when GC1 and GC2 are swapped.

[0064] FIG. 39 shows digitization using a three-stage cascaded inverter based comparator. Panel (a) shows a schematic of a three-stage-inverter-based comparator circuit. Voltage transfer characteristics measured at the output of (panel b) stage 1, (panel c) stage 2, and (panel d) stage 3. Clearly, the gain improves from 172 in stage- 1 to 519 in stage-2 to 644 in stage-3. Panel (e) is an analogue output voltage (VGT) from graphene chemisensor. Results of digitization at the output of (panel f) stage 1, (panel g) stage 2, and (panel h) stage 3. Clearly, cascading a higher number of inverters to construct the comparator allows better digitization.

[0065] FIG. 40 shows 2D digital codes using M3D integration platform. Different 2D digital codes generated from the same 4 chemicals (Cl, C2, C3, and C4) under different VLTG, ranging from 0.2 V to 1.4 V.DETAILED DESCRIPTION OF THE INVENTION

[0066] The following description is of exemplary embodiments that are presently contemplated for carrying out the present invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of describing the general principles and features of the present invention. The scope of the present invention is not limited by this description.

[0067] Referring to FIG. 1-6, embodiments can relate to a monolithic integrated circuit 100. The monolithic integrated circuit 100 can include a substrate 102. The substrate 102 can be a semiconductor material (e.g., SiO2, AI2O3, GaAs, GaN, CdSe, CdTe, SiC, etc.). The monolithic integrated circuit 100 can include one or more tiers 104. The one or more tiers 104 can be formed on a surface of the substrate 102. For instance, the substrate 102 can be a wafer having atop surface and a bottom surface. The tier(s) 104 can be formed on the top surface, for example. The tier(s) 104 can be formed on the entire surface or a portion of the surface of the substrate 102.

[0068] One or more of the tiers 104 can be composed of a 2-D planar layer 106. For instance, one or more of the tiers 104 can be a monolayer of nanomaterial (e.g., M0S2 film, WSe2 film Sb2TeSe2 film, TiO2 film, etc ). It is contemplated for each tier 104 to be composed of a 2-D planar layer 106. One or more of the tiers 104 can include one or more electrical elements 108. It is contemplated for each tier 104 to include plural electrical elements 108. One or more of the electrical elements 108 can be a filed-effect transistor. For instance, the 2-D planar layer 106 can have one or more gates, drains, sources, and channels, etc. formed in and / or on the 2-D planar layer 106.

[0069] A non-limiting, exemplary, filed-effect transistor electrical element 108 can be structured as follows. The substrate 102 (e.g., Si) can have an oxide layer 110 (e.g., SiO2) formed on a surface of the substrate 102. An island layer 112 can be formed on a surface of the oxide layer 110. The island layer 112 can be AI2O3 / Pt / TiN (e.g., TiN can be formed on a surface of the oxide layer 110, Pt can be formed on a surface of the TiN layer, and AI2O3 can be formed on a surface of the TiN layer). A source 114 (e.g., Ni / Au), a drain 118 (e.g., Ni / Au), and a channel 116 (e.g., M0S2) can be formed on a surface of the island layer 112. Each of source 114, the drain 118, and the channel 116 can be form on the surface of the island layer 112, wherein the source 114 and drain 118 subtend each other and are adjacent the channel 116. In this nonlimiting, exemplary, filed-effect transistor electrical element 108, the channel 116 is the 2-D planar layer 106 within which or upon which the electrical element 108 is formed.

[0070] It is contemplated for the monolithic integrated circuit 100 to include plural tiers 104. The plural tiers 104 can be stacked in vertical direction 120. This can include being stacked so that the geometric planes of each 2-D planar layer 106 are parallel to each other. For instance, a first tier 104 can be formed on the top surface of the substrate 102, a second tier 104 can be formed on top of the first tier 104, a third tier 104 can be formed on top of the second tier, etc., wherein the geometric plane of each tier 104 is parallel to each other.

[0071] The monolithic integrated circuit 100 can include one or more inter-layers 122. The inter-lay er(s) 122 can be positioned between at least two tiers 104. For instance, any two tiers104 can have one or more inter-layers 122 located between the two tiers 104. It is contemplated for one or more of the inter-layers 122 to be configured to electrically isolate at least a portion of one tier 104 from at least a portion of another tier 104. For instance, an inter-layer 122 can be formed between the first tier 104 and the second tier 104, whereby the inter-layer 122 can electrically isolate at least a portion of the first tier 104 from at least a portion of the second tier 104. Electrically isolating the tier(s) 104 can be achieved by the inter-layer 122 being composed of a dielectric material (e.g., AI2O3, SiCh, CaCCh, etc.).

[0072] As can be appreciated from the disclosure, embodiments can relate to a method of generating a monolithic integrated circuit 100. The method can involve depositing (e.g., via chemical vapor deposition) one or more nanomaterials on a surface of a substrate 102 to generate a first tier 104. The first tier 104 can be formed as a 2-D planar layer 106 of the nanomaterial(s). One or more electrical elements 108 can be formed (e.g., via spin coating and etching) in and / or on the 2-D planar layer 106 of the first tier 104. One or more inter-layers 122 can be deposited (e.g., via chemical vapor deposition) on a surface of the first tier 104. One or more nanomaterials can be deposited (e.g., via chemical vapor deposition) on a surface of the interlayer 122 to generate a second tier 104. The second tier 104 can be formed as a 2-D planar layer 106 of the nanomat eri al (s). One or more electrical elements 108 can be formed (e.g., via spin coating and etching) in and / or on the 2-D planar layer 106 of the second tier 104. The nanomaterial(s) of the first tier 104 can be the same as or different from the nanomaterial(s) of the second tier 104.

[0073] The method above can be expanded to create additional tiers 104 and inter-layers 122.

[0074] EXAMPLES

[0075] The following disclosure discusses exemplary implementations and test data related to the same.

[0076] EXAMPLE 1

[0077] Exemplary embodiments discussed in the EXAMPLES section relate to 3D integration of FETs based on 2D materials with a facile, monolithic fabrication scheme to achieve increased device integration density and functionalities. The inventive 3D chip stack includes a vertically stacked multi-tier system with 2D transitional metal di chalcogenide (TMD) based FET devices with integrated programmable and non-volatile floating gate memory, in each tier. One of thenovelties of the system stems from the implementation of a 3D chip consisting of scaled (channel length = 300 nm) molybdenum disulfide (M0S2) based FETs with high yield of devices (>600 working devices in each tier) in a two-tier system fabricated using a scheme, which is expandable to any desired number of tiers at a very low thermal budget below -200 °C. In addition, the integration of a floating gate memory and basic Boolean logic circuits demonstrates the applicability of the inventive D architecture in modern integrated circuits (ICs) based on 2D materials. Moreover, the inventive fabrication scheme can be expanded to other transferrable 2D materials to increase the number of functionalities that can be incorporated into a 3D chip.

[0078] Along this route, the inventive M3D integration of 2D materials bypasses disadvantages associated with TSVs as well as those associated with the use of bulk semiconductors such as silicon. Here, the entire integration based on M0S2 is performed on a single die and the vias are of comparable dimensions with respect to the fabricated devices. The fabrication process temperatures of the chip is kept below 200°C, which is compatible with back-end-of-the-line (BEOL) thermal budgets, allowing one to adopt the given fabrication flow to add multiple tiers in a 2D based 3D chip without performance degradation in lower tier devices. In addition, the adoption of a non-von Neumann architecture via the integration of a programmable floating gate memory in the transistor design helps in overcoming the logic-memory bottleneck prevalent in the current IC technology. Moreover, 2D materials also offer a plethora of possibilities to add non-computational systems such as sensors (optical / biological / chemical / gas), radio-frequency devices, magnetic devices, lasers, etc., into a M3D integrated chip. Hence, the demonstration given here can manifest into a wide variety of low-cost and high-performance multifunctional platforms where logic, memory, and / or non-computational systems can be integrated in a 3D architecture.

[0079] In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as “More Moore”, but also introduces multifunctionalities for “More than Moore” technologies. While silicon-based 3D integrated circuits (ICs) are commercially available, there is limited effort on 3D integration of emerging nanomaterials such as two-dimensional (2D) materials despite their novel functionalities. Here it is demonstrated: 1) wafer-scale and monolithic 2-tier 3D integration based on M0S2 with more than 10000 field-effect transistors (FETs) in each tier; 2) 3-tier 3D integration based on bothM0S2 and WSe2 with -500 FETs in each tier; and 3) 2-tier 3D integration based on 200 scaled M0S2 FETs (channel length, ZCH = 45 nm) in each tier. Realization of 3D circuit is achieved and multifunctional capabilities including sensing and storage are demonstrated. Results presented herein serve as a foundation for more sophisticated, highly dense, and functionally divergent ICs with a larger number of tiers integrated monolithically in the third dimension.

[0080] Scaling of silicon field-effect transistors (FETs) following Moore’s law has been instrumental in enabling faster, smaller, and cheaper electronic devices. While the latest FinFET technology and its most likely successor, gate-all-around (GAA) FETs, are anticipated to extend Moore’s scaling until the end of the decade, the semiconductor industry is increasingly emphasizing three-dimensional (3D) device stacking for advancing “More Moore”. In addition, 3D integration can offer a hybrid platform to integrate non-computational devices based on novel materials across different tiers of the 3D stack, which might not be easily achievable with Si technology. This concept is often labelled as “More than Moore”.

[0081] Acknowledging the wide range of possibilities offered by 3D integration, prominent chip manufacturing companies have already showcased their advancements in 3D packaging solutions such as Intel’s Foveros, TSMC’s 3DFabric, and AMD’s 3D V-Cache. In contrast to packaging, monolithic 3D integration can allow increased interconnect density and reduced electrostatic coupling. However, for silicon-based logic, the process temperature limitation of -450 °C for upper tiers restricts the development of monolithic integration. The introduction of high-mobility channel materials such as Ge and InGaAs in upper tiers can compensate for performance but complicates fabrication. Moreover, bulk semiconductors like silicon cannot be utilized for advanced scaling due to heightened charge carrier scattering at the interfaces between the channel and dielectric at sub-3 nm channel thickness regime.

[0082] To overcome these challenges, ultra-thin-body channel materials such as two- dimensional (2D) semiconductors, carbon nanotubes, and nanowires are considered as promising candidates. In particular, recent remarkable achievements in wafer-scale synthesis, device performance, and integration strategies have put 2D semiconductors in the roadmaps of various industries. Moreover, recent demonstrations of 3D heterogenous integration of 2D materials with silicon-based microchips show significant potential for the development of functionally diverse processors.

[0083] While the above discussion highlights the growing interest in 3D integration and initial progress towards 2D / silicon hybrid 3D integration, an all-2D-based monolithic 3D integration has not yet been achieved on a large-scale. Experiments disclosed herein, however, demonstrate monolithic 3D integration of multifunctional 2D FETs based on large area-grown M0S2 and WSe2. Experiments further demonstrate the ability to generate: 1) wafer-scale monolithic 2-tier 3D integration of M0S2 FETs with more than 10,000 devices in each tier; 2) 3-tier 3D integration of both M0S2 and WSe2 FETs with 800 devices in tier 1, 800 devices in tier 2, and 450 devices in tier 3; 3) 2-tier 3D integration of more than 200 scaled M0S2 FETs in each tier with channel length, ZCH = 45 nm; and 4) demonstration of a 3D circuit based on M0S2.

[0084] 3D integration of 2D FETs

[0085] M0S2 and WSe2 films used in this study were grown on epi -ready 2-inch c-plane sapphire (OC-AI2O3) substrates using metal organic chemical vapor deposition (MOCVD). The growth parameters and other details on synthesis are outlined in the Methods section.

[0086] After material characterization, fabrication of all the 3D ICs was achieved on 285 nm SiC>2 / p++-Si substrates. Note that this substrate functions only as a carrier substrate, and, in principle, any other lithography-compatible substrate can be used. All devices mentioned in this study were composed of a 15 nm Pt back-gate, 9 nm AI2O3 / 3 nm HfO2 / 3 nm AI2O3 gatedielectric stack with an equivalent oxide thickness (EOT) of ~6 nm, 2D channel, and contact metal stack (20 nm Ni / 10 nm Au for MoS2-based samples and 20 nm Pd / 10 nm Au for the WSe2- based sample), unless specified otherwise. Each tier of devices is electrically isolated from the other using an inter-layer dielectric (ILD) (AI2O3). Here, ‘tier’ is defined as a planar layer of devices and tier 1, tier 2, and tier 3 refer to various layers of devices fabricated in a 3D chip. Further details on the fabrication process flow are given in the methods section of the EXAMPLES. Each device in the top tier was placed exactly on top of the corresponding bottom tier device. The entire fabrication process was performed within a thermal budget of 180 °C, which allows the addition of a greater number of tiers without causing any degradation to the bottom tiers.

[0087] 2-tier wafer-scale 3D stack of M0S2 FETs

[0088] Electrical characterization on different tiers was performed sequentially and before depositing necessary vias and connections for circuit demonstrations. FIGS. 7A-7B show thetransfer characteristics, e.g., drain current ( / DS) plotted against the back-gate voltage (FBG) for constant drain voltage, I DS = 1 V, for 10,000 devices on each tier with Ten = 300 nm. Note that the fabricated wafer is composed of 8 dies, each with an area of 1 cm x 1 cm, as seen in FIG. 4. The total number of devices in each tier is >30,000, of which 5 dies were characterized. FIGS. 7A-7B also show wafer-maps and corresponding histograms for subthreshold slope (SS) for 2 orders of magnitude change in IDS, ON-current ( / ON) extracted at FBG = 5 V and EDS = 1 V, and threshold voltage (FTH) extracted using the iso-current method at 100 nA for 10,000 devices across these 5 dies in tier 1 and tier 2, respectively. Transfer characteristics and variation of SS, / ON, and NTH, across different dies in each tier were analyzed. The median / ON for tier 1 and tier 2 were found to be 6.5 pA / pm and 2.7 pA / pm with standard deviations of 4.4 pA / pm and 2.0 pA / pm, respectively. The maximum ION obtained for tier 1 and tier 2 were 33 pA / pm and 16 pA / pm for an inversion carrier concentration of ns = 1.1 x 1013 cm-2 and 1.3x 1013 cm'2, respectively. The ON current values are lower than recent reports on M0S2 FETs from literature at similar n and £CH. This can be attributed to higher contact resistance associated with Ni contacts and lower field-effect electron mobility values seen in MOCVD films. The median 55 for tier 1 and tier 2 were found to be 156 mV / decade and 170 mV / decade with standard deviations of 40 mV / decade and 44 mV / decade, respectively. The minimum SS obtained for tier 1 and tier 2 were ~79 mV / decade and 85 mV / decade, respectively, which are close to the ideal SS value of 60 mV / decade. However further improvement of the 2D / dielectric interface can lead to more devices showing near-ideal 55. The median FTH for tier 1 devices was found to be 2.7 V with a standard deviation of 1.4 V, whereas tier 2 devices exhibited a median FTH of 1.6 Fwith a standard deviation of 1.2 F. Nevertheless, the device-to-device variation across 10,000 2D FETs for both tiers were similar, as evident from the standard deviation values obtained for several performance metrics, reinforcing the robustness of the fabrication process flow for the 3D stack.

[0089] 3-tier 3D stack of 2D FETs

[0090] The robustness of the fabrication process flow to a higher number of tiers was established by demonstrating 3-tier 3D ICs based on M0S2 and WSe2. A MoS2-based 3-tier stack was chosen for analysis using scanning transmission electron microscopy (STEM). An enlarged top-view false-colored SEM-BSE (backscattered electron) image of two sets of devices is given in FIG. 8. The white dotted line covers the 3-tier M0S2 device stack with the contactpads (gate, source, and drain) of the device in each tier labelled. Focused ion-beam (FIB) milling was employed to lift-out the region in the gate island pointed out with the red-line in FIG. 8. FIG. 9 shows the high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) image of the cross-section showing three sets of Ti / Pt gate, AI2O3 / HfCh / AI2O3 gate dielectric, MoS2 channel, and Ni / Au contact pads, stacked on top of each other. FIG. 10 shows the energy dispersive spectroscopy (EDS) elemental mapping of the stack. The 3-tier WSe2 stack differs from the above-described stack only with the contact metals used.

[0091] Next, statistical evaluation of the performance of both M0S2 and WSe2 FETs in all 3- tiers was conducted. Two different / .cii values were used, 300 nm and 1 pm, with a fixed channel width (WCH) of 1 pm for both M0S2 and WSe2 FETs. These 3-tier 3D ICs were comprised of 800 devices on tier 1, 800 devices on tier 2, and 450 devices on tier 3 for both M0S2 and WSe2 FETs. For better readability and analysis, FIGS. 1-12 show the transfer characteristics for 200 M0S2 FETs and 200 WSe2 FETs with LCH = 300 nm on tier 1, tier 2, and tier 3 respectively. The distributions of 5, / ON, and FTH, extracted from these transfer characteristics were analyzed. WSe2 FETs demonstrated ambipolar transport with dominant p- type conduction, which is complementary to the / / -type conduction observed in M0S2 FETs. Therefore, the performance metrics were extracted for / / -type transport in M0S2 and -type transport in WSe2. The mean, median, and standard deviation values for the extracted performance metrics for both M0S2 and WSe2 for all 3-tiers were anlyzed. Pd was the primary contact metal for WSe2 FETs to enhance the / / -type transport, due to a higher work function of Pd compared to Ni, which was used as the contact metal for M0S2 FETs.

[0092] The median / ON for WSe2 FETs for any given tier was found to be -10* lower than the median / ON for M0S2 FETs in the corresponding tier. This is primarily attributed to the relatively large Schottky barrier (SB) height for hole injection at the Pd / WSe2 interface compared to relatively smaller SB height at the Ni / MoS2 interface. The impact of the SB is also seen in the SS values. While M0S2 FETs can achieve median SS values of -125 mV / decade in tier 1 and tier 2 and -180 mV / decade in tier 3, WSe2 FETs were restricted to median SS values of -450 mV / decade across all tiers. Also notable is the fact that some M0S2 FETs were able to achieve near-ideal SS values of 66 mV / decade in tier 1 and 69 mV / decade in tier 2. The device-to-device variation, quantified on the basis of standard deviation values, for different performance metricsclearly demonstrates less variation across M0S2 FETs compared to WSe FETs in any given tier. This can be attributed to the better growth quality of M0S2, as it contains fewer S-vacancies as compared to the growth of WSe2, which is more likely to be inflicted with higher concentration of Se-vacancies. Finally, the 2D FETs in tier 3 were found to underperform compared to tier 1 and tier 2 for both M0S2 and WSe2. Such performance degradation is likely due to the strain in the transferred film originating from the complex topography on tier 3. This indicates the need for planarization techniques such as chemical mechanical polishing (CMP) for the fabrication of multi-tier 3D ICs.

[0093] Scaled 2D FETs in a 2-tier 3D stack

[0094] After achieving 2-tier wafer-scale 3D integration of M0S2 FETs and 3-tier 3D integration for both M0S2 and WSe2 FETs, the same fabrication flow was employed to fabricate 2-tiers of scaled M0S2 FETs with channel length ECH = 45 nm and contact length Lc = 90 nm (FIG. 3). Even though the fabrication flow was kept the same for scaled FETs, it required more optimization of the lithography steps to ensure an acceptable yield of scaled devices. The transfer characteristics of 200 scaled M0S2 FETs, measured at I DS = 1 V, in each tier of the 2- tier 3D stack are given in FIGS. 13-14. The extracted device performance metrics for tier 1 and tier 2, including 55, / ON, and FTH are represented with histograms in FIGS. 13-14. The mean, median, and standard deviation values of the extracted performance metrics for scaled M0S2 FETs in each tier were compared with long channel M0S2 FETs. The median ON for both tier 1 and tier 2 were found to be -40 pA / pm with a standard deviation of ~20pA / pm. The maximum / ON obtained for tier 1 and tier 2 were also found to be similar, -100 pA / pm corresponding to ns = 1.3 x 1013cm’2. However, note that despite -7* reduction in ECH, from 300 nm down to 45 nm, the median / ON value only increased by -2*, which can be ascribed to the dominance of contact resistance in Ni-contacted M0S2 FETs, coupled with slightly higher FTH values for scaled M0S2 FETs, resulting in lower overdrive voltages. The median FTH was found to be -1.9 V for scaled M0S2 FETs in each tier. The median 55 for tier 1 and tier 2 were found to be -200 mV / decade and -180 mV / decade with standard deviations of -90 mV / decade and 70 mV / decade, respectively. The minimum 55 obtained for tier 1 and tier 2 were 85 mV / decade and 87 mV / decade, respectively. The 55 values were found to be slightly higher than the values obtained for long channel devices. The device-to-device variation across the scaled devices wasfound to be similar to long channel devices for both tiers, highlighting the robustness of the fabrication process flow for the 3D stack.

[0095] Multifunctional 2D FETs

[0096] As mentioned earlier, 3D integration can enable the incorporation of non-computational systems such as sensors, memory, radio-frequency devices, etc., in different tiers of a 3D IC and support computing paradigms like in-memory computing and in / near-sensor computing. Along these lines, we demonstrate a 3D inverter and explore the memory / storage and photosensing capabilities of the M0S2 FETs. It was found that the tier 1 device behaves as the depletion load transistor with the gate and source of the device shorted, while the tier 2 device works as the driving transistor.

[0097] Furthermore, data related to transfer characteristics of 10 M0S2 FETs, demonstrates low and high conductance memory states, memory retention, and memory endurance, respectively. These illustrate non-volatile storage capabilities integrated into 2D FETs through the utilization of a floating gate stack (9 nm AhCh / Snm HfCh / S nm AI2O3) with AI2O3 layers as blocking and tunneling and HfCE for charge-trapping. The average responsivity and detectivity was obtained to be 1481 AW1and 1.32 --' IO11Jones, respectively.

[0098] This demonstrates strong support the rationale for 2D materials to be considered for 3D integration. In the past, there have been a few impressive attempts which highlighted the feasibility of stacking 2D FETs.

[0099] Challenges and opportunities

[0100] In this section, the aim is to discuss the existing challenges and future opportunities with 3D integration of 2D FETs. For example, it has been observed that the PMMA-assisted transfer technique plays a critical role in device yield and device-to-device variation amidst other factors. Therefore, a more optimized and high-throughput wafer-scale transfer technique can benefit further development of 3D ICs based on 2D materials. Alternatively, low-temperature growth of 2D materials on arbitrary substrates can enable 3D integration without requiring the transfer step during fabrication. In terms of device performance, Ni is not an ideal contact metal for n-type M0S2 FETs when compared to some of the recent low contact resistance values achieved with Bi and Sb. Similarly, improvement in the performance of p-type WSe2 FETs will necessitate further optimization of growth conditions, as well as better contact engineering strategies.Similarly, EOT for 2D FETs must be reduced below ~1 nm to enhance both on-and off-state performance. Implementation of top gate FETs is also favorable due to its area efficiency, lower parasitic capacitances, lower gate leakage, and overall performance benefits. Additionally, means to engineer the threshold voltage (I TH) for both n-type and p-type FETs must be developed for designing low-power 3D CMOS circuits.

[0101] Finally, a separate and systematic research effort is required to further optimize the 3D stack. This includes innovations in the ILD and techniques such as CMP to reduce the impact of surface topography, which will reduce device-to-device and tier-to-tier variations. In addition, for realizing larger circuits, parasitic capacitances must be minimized, propagation delays must be reduced through innovation in interconnects and circuit / layout design, and thermal issues must be mitigated by introducing spreaders / thermal vias among the layers in a 3D stack.

[0102] In summary, what has been achieved is: 1) wafer-scale monolithic 3D integration with 2D materials such as M0S2 with more than 10,000 devices in each tier; 2) 3-tier 3D integrated chips based on M0S2 and \VSe2; and 3) 3D integration based on M0S2 FETs with scaled channel length (LCH = 45 nm). In addition, logic, non-volatile memory, and sensing capabilities are demonstrated with M0S2 FETs. The demonstration, when combined with further improvements in material synthesis, wafer-scale transfer, and device design, can usher in the path for both “More Moore” and “More than Moore” technologies.

[0103] Methods

[0104] Large-area M0S2 film growth

[0105] The growth of monolayer M0S2 on 2-inch diameter c-plane sapphire was carried out in two metal-organic chemical vapor deposition (MOCVD) systems; one equipped with a cold-wall horizontal reactor with an inductively heated graphite susceptor with gas-foil wafer rotation and the other a cold-wall vertical reactor with resistive heating and mechanical rotation.Molybdenum hexacarbonyl (Mo(CO)e) and hydrogen sulfide (H2S) were used as precursors in an H2 carrier gas. The M0S2 monolayer was grown in a single-step process. Before the growth, the sapphire was ramped up under H2 to the growth temperature of 1000-1050°C and pre-annealed for 10 min. During the growth, H2S and Mo(CO)e were introduced to the reactor for a designated time to complete M0S2 monolayer growth in a single step. The Mo(CO)e flow rate was in the range of 3.5-8.6* 10’3seem and the chalcogen (H2S) flow rate was set as 400 seemwhile the reactor pressure was maintained at 50-100 Torr. Then, the M0S2 monolayer was annealed under H2 and H2S ambient for 10 min at the growth temperature before cooling down to inhibit the decomposition of the obtained M0S2 film. Using this condition, the growth of a fully coalesced monolayer M0S2 was achieved across the 2-inch sapphire substrate.

[0106] Large-area WSe2 film growth

[0107] The growth of monolayer WSe2 on 2-inch diameter c-plane sapphire was carried out in a metal-organic chemical vapor deposition (MOCVD) system equipped with a cold-wall horizontal reactor with an inductively heated graphite susceptor with gas-foil wafer rotation. Tungsten hexacarbonyl (W(CO)e) was used as the metal precursor while hydrogen sulfide (H2S) was the chalcogen source with H2 as the carrier gas. The W(CO)e powder was maintained at 30 °C and 400 Torr in a stainless-steel bubbler. The synthesis of WSe2 monolayer is based on a multi-step process, consisting of nucleation, ripening, and lateral growth steps, which was described previously. In general, the WSe2 sample was nucleated for 30s at 850 °C, then ripened for 5min at 850 °C and 5min at 1000 °C, and then grown for 20min at 1000 °C, which gives rise to a coalesced monolayer across the entire 2-inch wafer. During the lateral growth, the tungsten flow rate was set as 3.8* 10'3seem and the chalcogen flow rate was set as 75 seem while the reactor pressure was kept at 200 Torr. After growth, the substrate was cooled in H2S to 300 °C to inhibit the decomposition of the obtained WSe2 films.

[0108] Fabrication of local back-gate islands

[0109] To define the back-gate island regions, a commercially purchased substrate (thermally- grown 285 nm SiO2 on / / -Si) was spin coated with a bilayer e-beam resist stack consisting of EL6 and A3 resists at 4000 RPM for 45 s. Following application, these resists were baked at 150 °C for 90s and 180 °C for 90 s, respectively. The bilayer e-beam resist was then patterned using e-beam lithography to define the islands and developed by immersing the substrate in 1 : 1 MIBK IPA for 60s, followed by immersion in IPA for 45s. The back-gate electrodes of 5 / 15 nm Ti / Pt were then deposited using e-beam evaporation in a Temescal FC-2000 Bell Jar Deposition System. Liftoff of the remaining e-beam resist and excess metal was achieved using acetone; the substrate was then cleaned using 2-propanol (IPA) and DI water. An atomic layer deposition (ALD) process was then implemented to grow the back-gate dielectric stack consisting of 9 nm AI2O3, 3 nm HfCL, and 3 nm AI2O3 across the entire substrate, including the island regions.Access to the individual Pt back-gate electrodes was achieved via a reactive ion etch (RIE) process conducted in a Plasma- Therm Versalock 700. First, an etch pattern was defined using the ZEP e-beam resist, which was spin coated at 2500 rpm for 45s followed by baking at 180 °C for 3min. The resist was patterned using e-beam lithography and then developed using n-amyl acetate at room temperature. The dielectric stack was then dry etched using BCE gas at 5 °C for 25s. Finally, the e-beam resist was removed using Photo Resist Stripper (PRS 3000) and cleaned with IPA.

[0110] M0S2 film transfer to local back-gate islands

[0111] To fabricate the 2D FETs, MOCVD grown monolayer films were transferred from the sapphire growth substrate to the pre-fabricated island substrate using PMMA (polymethylmethacrylate) assisted transfer process. First, 2D film on sapphire substrate was spin coated with PMMA in two steps: 1000 rpm for 30 s followed by 3000 rpm for 30 s and then baked at 120 °C for 120 s. Then, thermal release tape was attached to the PMMA coated film kept at 80 °C, later immersed inside DI water kept at 80 °C followed by ultrasonic bath for 12 minutes. Capillary action causes the DI water to be drawn into the substrate / film interface, separating the PMMA / 2D film from the sapphire substrate. Then the separated PMMA / 2D film was dried using nitrogen and finally transferred onto the SiCE / Si substrate with back-gate heated at 120 °C and then slowly the temperature was raised to 180 °C to release the thermal release tape. The PMMA layer is then removed by placing the sample in an acetone bath for 3 hours, followed by an IPA bath for 15 min to clean the sample.

[0112] Scaled Device Fabrication

[0113] Scaled devices of £CH = 45 nm were fabricated after the isolation etch of M0S2. The sample is initially dipped in Surpass 4K for 60 s, rinsed in DI water, and then baked at 100 C for 60 s to improve the wettability of ZEP 1 : 1 e-beam resist. ZEP 1 : 1 was spun at 5000 RPM for 45 s and baked at 180 °C for 3 min. E-beam lithography is carried out at a beam energy of 100 keV and is developed in n-amyl acetate chilled at -10 °C for 3 min and IPA at room-temperature for 60 s. Next, e-beam evaporation is done to deposit 20 nm Ni / lOnm Au as the contact metal, followed by lift-off in PRS3000 and IPA.

[0114] Raman and photoluminescence (PL) spectroscopy

[0115] Raman and photoluminescence (PL) spectra were taken on the M0S2 film as-grown and after transfer using a Witec Alpha-300 Apyron system within a N2-ambient glovebox with ~5 ppm of O2 and H2O. Raman and PL spectra were taken using the 100X objective at a 4 mW laser power. For WSe2 Raman and PL were performed on a Horiba LabRAM HR Evolution confocal Raman microscope with a 532 nm laser. The power was 34 mW filtered at 1%. The objective magnification was 100* with a numerical aperture of 0.9, and the grating had a spacing of 1800 gr / mm for Raman and 300 gr / mm for PL.

[0116] Scanning electron microscopy (SEM)

[0117] Scanning electron microscopy (SEM) of the 2D M0S2 transistors used in this study was conducted using a Zeiss Gemini 500 field emission scanning electron microscopy (FESEM) system at an accelerating voltage of 5 kV.

[0118] Atomic Force Microscopy (AFM)

[0119] AFM was used to study the surface morphology, coverage, and thickness of the deposited layers. Scanasyst air probe AFM tips with a nominal tip radius of ~2 nm and spring constant of 0.4 N / m were employed for the measurements, and images were collected using peak-force tapping mode with a peak force of 500 pN and scan speed of 2 Hz.

[0120] TEM sample preparation

[0121] Thin TEM sample was prepared by a Thermo Fisher Scientific Helios 660 dual beam system. The sample were first lifted-out from the device and then transferred to a copper half grid from TedPella. The samples were then thinned by Ga+ion beam at a sequence of voltages: 30kV, 16kV, 8kV, 5kV and 2kV.

[0122] STEM characterization of the cross-section

[0123] The TEM samples made by FIB were characterized by a Thermo Fisher Scientific Titan3G2 60-300 TEM / STEM and a Talos F200X TEM / STEM, working with an accelerating voltage of 300 kV and 200 kV, respectively. The plane-view sample was characterized by Titan3G2 60- 300 TEM / STEM with an accelerating voltage of 80 kV. The EDX was collected with a Super-X EDX system.

[0124] Electrical Characterization

[0125] Electrical characterization of the fabricated devices was performed using a semiautomated Formfactor 12000 probe station under atmospheric conditions with a KeysightB 1500A parameter analyzer. A continuous wave white light source was used for all experiments involving light illumination unless otherwise stated.

[0126] EXAMPLE 2

[0127] The semiconductor industry is transitioning to the ‘More Moore’ era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 pm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials’ role in advancing M3D integration in complementary metal- oxide-semi conductor circuits.

[0128] The relentless pursuit of ‘More Moore’ through the scaling down of transistor dimensions over six decades has been driven by innovations in device architecture, such as the development of fin field-effect transistor (FET) technology, the integration of high-K dielectrics, improved interconnects and advancements in extreme ultraviolet lithography. These innovations have consistently contributed to the increasing density of integrated circuit (IC) components. Interestingly, although device-level scaling has been impressive, it has far outpaced packaginglevel advancements. This highlights the significance of three-dimensional (3D) integration — an ‘orthogonal scaling’ approach that offers a promising strategy for increasing device integration density and effectively addresses the constraints inherent in traditional device dimension scaling. 3D integration presents numerous advantages over traditional planar geometry, including reduced footprint, lower power consumption, higher bandwidth, shorter connection routing andlower parasitic losses from interconnects. Additionally, it enables the heterogeneous stacking of various elements, such as memory and image sensors, in a concept known as ‘More than Moore’ technology. Industrial approaches to 3D integration utilize copper microbumps and through- silicon vias (TSVs) to stack separately fabricated dies. However, TSVs have large footprints, leading to substantial parasitic capacitances and thermal / mechanical stresses. Monolithic 3D (M3D) integration addresses these limitations by sequentially fabricating inter-tier vias on a single die. This approach results in higher vertical interconnect density, shorter wire lengths (enabling higher speed and lower power loss) and transistor-level partitioning. M3D integration also allows for the incorporation of non-silicon materials in one or more tiers to enhance performance or enrich functionalities. Recently, M3D integration has incorporated lowdimensional materials such as carbon nanotubes and transition metal di chalcogenides (TMDCs). However, M3D integration with complementary FETs from the same (non-silicon) semiconducting material remains underexplored due to limited progress in developing n-type carbon nanotube FETs and p-type two-dimensional (2D) FETs. Although the demonstrations of 3D stacking of n-type M0S2 with p-type MoTe2 and n-type MoS2 with p-type WSe2 mark a step forward in the M3D integration of complementary FETs, its complete potential remains unexplored as both device and via dimensions were relatively large.

[0129] In this study, we demonstrate the M3D integration of a two-tier complementary metal- oxide-semi conductor (CMOS) chip based on n- and p-type FETs made from large-area WSe2synthesized through a metal-organic chemical vapour deposition (MOCVD) technique. We have also achieved transistor-level partitioning, resulting in the placement of 340 n-type FETs on tier 1 and 340 p-type FETs on tier 2. An important milestone in this research is the demonstration of a densely integrated inter-tier vias measuring 300 nm in width and placed with a pitch of 1 pm, rivalling state-of-the-art packaging solutions. In addition, 3D CMOS circuits including 27 inverters, 12 NAND gates and 12 NOR gates have been successfully realized. Furthermore, the M3D CMOS stack was manufactured at temperatures not exceeding 200 °C, making it compatible for integration at the back end of line for hybrid 2D / Si technologies.

[0130] Synthesis of WSe? films and enabling complementary 2D FETs

[0131] FIG. 15A shows the optical image of an array consisting of M3Dintegrated, two-tier CMOS ICs based on WSe2 FETs. Each cell in the array (FIG. 15B) contains four devices, inwhich two p-FET WSe2 FETs are positioned directly above two n-FET WSe2 FETs. FIG. 15C shows an angled, false-colored scanning electron microscopy (SEM) image of a two-stage CMOS inverter circuit. In this configuration, 300 nm vias are placed within 1 pm of each other to form the series connection between the tier-1 n-FET and tier-2 p-FET devices, highlighting the dense via integration capabilities achieved in this work. Figure ld,e shows the schematic and corresponding false-colored SEM image of an M3D-integrated NAND gate, respectively. FIG. 15F, 15G, and 15H show the high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) image and energy-dispersive X-ray spectroscopy(EDS) elemental mapping for the M3D stack, taken at the cross-section indicated by the dashed line in FIG. 15E. To achieve an M3D-integrated CMOS chip based on 2D FETs, large-area synthesis of the targeted 2D channel material is required.

[0132] The multilayer (three to four layers) WSe? films used in this study were grown using an MOCVD system. Further details about the growth conditions and synthesis parameters are outlined in Methods. An optical image showcasing the two-inch-wide multilayer WSe2 growth is presented in FIG. 16A. The multilayer formation was confirmed by atomic force microscopy (FIG. 16B), revealing a coalesced three- / four-layered film with some multilayer islands. Additional HAADF-STEM imaging (FIG. 16C) displays the crystalline 2H structure of the WSe2 film.

[0133] The photoluminescence (PL) spectra, captured from ten different areas across the wafer (FIG. 16D), indicates an average peak position at approximately 1.64 eV, further substantiating the multilayer growth. Finally, FIG. 2E presents the Raman spectra collected from the same locations, with detection of the in-plane E12g(249 cm-1), out-of-plane 2LA(M) (258 cm-1) and B2g (310 cm-1) Raman modes providing additional evidence of the multilayer composition of the WSe2 film used in this study. Next, a polymethyl methacrylate (PMMA)-assisted wet transfer technique (Methods) was used to transfer the WSe2 films from the sapphire substrate to the device fabrication substrate for assessing the electrical performance. The uniformity of the film post-transfer was confirmed using Raman spectroscopy. A crucial step for achieving CMOS capabilities using WSe2 films is the choice of layer thickness, contact metal and interlayer dielectric (ILD) material. A multilayer (three to four layers) WSe2 film was selected due to its stability in ambient conditions, high performance, ease of large-area synthesis and,most importantly, capability to achieve ambipolar conduction while maintaining a relatively large ON / OFF current ratio of >104. These characteristics enable CMOS capabilities, as well as achieve low static power consumption, which is in stark contrast to n-channel metal-oxide- semiconductor-based logic using unipolar 2D materials, such as M0S2. FIGS. 19A and 19B show the transfer characteristics, that is, the drain current (ZDS) plotted against the applied back- gate voltage (FBG), of FETS with Pd contacts based on bilayer and multilayer (three to four layer) WSe2 films, respectively, grown via MOCVD. FIGS. 19C and 19D show the corresponding histograms for / pMAx and AIMAX, respectively, which correspond to the maximum hole and electron currents.

[0134] Clearly, the multilayer WSe2 FETs show higher p-branch current compared with the bilayer WSe FETs, with almost two times improvement in / PMAX. Even more dramatic improvements are seen in the n-branch current, with ~20 times improvement for multilayer WSe2. This can be attributed to the smaller bandgap of multilayer WSe2 compared with monolay er / bilay er WSe2 and mid-gap pinning of the metal Fermi level, making it easier to achieve ambipolar transport. In addition to layer thickness, the choice of contact metal also plays a critical role in enabling CMOS functionality for WSe2 FETs. FIG. 20A displays the transfer characteristics of 250 devices utilizing Pd and Ni contacts on WSe2 films, respectively. The Pd contacts primarily yielded p-type characteristics whereas a nearly 100-fold reduction in the p- branch current was observed with Ni contacts, as illustrated by the ZPMAX histograms shown in FIG. 20B. Ni contacts also enhanced the n-branch current by almost threefold, as evident from the AIMAX histograms shown in FIG. 20C. This observation can be ascribed to the differences in how the Fermi levels of Pd and Ni align with the WSe2 bandgap — both metals enable ambipolar transport; however, Pd aligns closer to the valence band, whereas Ni aligns closer to the conduction band. To further enhance the n-FET performance, surface charge transfer doping was exploited using sub -stoichiometric AI2O3 grown via atomic layer deposition (ALD). FIGS. 21A and 21B show the transfer characteristics of 50 WSe2 FETs with Ni contacts before and after the deposition of AI2O3, along with the corresponding histograms for AIMAX, respectively. A clear negative shift in the threshold voltage and nearly 100 times improvement in the average AI AX confirms the n-type doping of WSe2 using ALD AI2O3. The p-branch current was also suppressed by nearly six orders of magnitude, enabling nearly unipolar WSe2 n-FETs. Theobserved n-type doping can be attributed to fixed charges and trap states at the WSe2 / AhO3 interface that increase the electron concentration in the WSe? channel. This is analogous to modulation doping in high-electron-mobility transistors. In addition, no degradation is seen in the subthreshold slope for the n-branch (SSn), as illustrated by the histograms shown in FIG. 21C, indicating that the donation of electrons stems from donor states that are not located within the bandgap of WSe2. Raman and PL spectroscopy were also implemented to understand the effects of ILD deposition. FIG. 22A shows the Raman spectra, in which a redshift of ~1 cm-1 is observed in the E g peak, which is indicative of an increased electron concentration in WSe2. This is further evidenced by the redshift in the PL emission spectra, along with the broadening of the main peak (FIG. 22B). The redshift and peak broadening correlate to the formation of negatively charged trions originating from an increased electron concentration in the WSe? film. Density functional theory (DFT) calculations were also employed to examine the influence of AI2O3 dielectric deposition on WSe2.

[0135] Fabrication of two-tier 3D CMOS ICs

[0136] Following the optimization of WSe2 film thickness, contact metal and dielectric interface, the fabrication of a WSe2-based, two-tier M3D CMOS IC was accomplished on a 285 nm SiO2 / p++ Si substrate. In principle, any lithography-compatible substrate can be utilized to achieve a 3D CMOS IC. Both tiers of devices consist of a 2 nm Ti / 18 nm Pt back-gate and a 9 nm AI2O3 / 3 nm HfO2 / 3 nm A12O3 back-gate dielectric stack, with an equivalent oxide thickness (EOT) of ~6 nm. The implemented gate stack provides a flash-memory -like functionality for realization of in-memory computing applications. To enable n-FET and p-FET devices in tier 1 and tier 2, respectively, different contact materials were employed: 20 nm of Ni / 10 nm of Pt for tier-1 n-FET devices and 20 nm of Pd / 10 nm of Au for tier-2 p-FET devices. To ensure electrical isolation between the n-FET devices of tier 1 and the p-FET devices of tier 2, an ~82- nm-thick layer of ALD-grown AI2O3 was used as an ILD while also servings as the n-type doping layer for tier-1 n-FET devices. Finally, a via-last approach was implemented to establish the required connections between the devices in tier 1 and tier 2, facilitating the demonstration of our circuit. The vias were constructed using 90 nm Ni and 30 nm Au, ensuring robust connectivity across tiers with a via width of 300 nm. This achievement in via dimensions underscores the enhanced packing density enabled by M3D integration techniques.

[0137] The device characteristics for tier-1 devices were re-evaluated after the completion of tier-2 fabrication. FIGS. 17A and 17F shows the transfer characteristics of 340 tier-1 and tier-2 devices, respectively, in which a nearly four-order magnitude decrease in the p-branch characteristics and two-order magnitude improvement in the n-branch characteristics are observed between the tier-1 and tier-2 devices. All devices discussed have a channel length ( / .CH) and channel width (W) of 300 nm and 1 pm respectively, unless stated otherwise, and all the parameters were extracted for a drain bias (IDS) of 1 V. FIG. 17B shows the distribution of the threshold voltage extracted from the n-branch (FTH-n) extracted using the iso-current method at a drain current ( / DS) of 100 nA pm-1 for tier-1 devices. The average FTH-n acquired for the n-branch of the tier-1 devices was 1.35 V, with a standard deviation of 0.97 V. The subthreshold slope for the n-branch (SSn; FIG. 17C) for two orders of magnitude change in / DS was also extracted, in which a minimum SSn of 142 mV dec-1, an average SSn of 282 mV dec- 1 and a standard deviation of 73 mV dec-1 were achieved for tier-1 devices. FIG. 17D shows the distribution of the n-branch ON-current (In), extracted for a carrier concentration (ns of 1.4 x 1013 cm-2 corresponding to an overdrive voltage (FOV) of 3.4 V. The maximum In achieved was 26.00 pA pm-1, with a mean and standard deviation of 10.80 and 5.84 pA pm-1, respectively. Finally, FIG. 17E shows the distribution of the extracted electron field-effect mobility (jun), obtained using the peak-transconductance method. The maximum electron mobility obtained was 6.90 cm2 V-l s-1, with an average and standard deviation of 3. 11 and 1.38 cm2V-l s-1, respectively. FIG. 17G-J outline the extracted device parameters for the p- branch in tier-2 devices. FIG. 17G the distribution of FTH-p for the same iso-current (100 nA pm-1), with an average Fm-p value of -0.84 V and a standard deviation of 0.33 V. The distinct Fm-p ranges observed between the tier-1 and tier-2 devices are pivotal for achieving CMOS circuits with discrete and well-defined logic levels. The avoidance of overlap in the threshold voltage is essential, as it ensures that each device operates at its designated logic level. The subthreshold slope for the p-branch (SSp; FIG. 17H) is extracted for two orders of magnitude change in / DS, in which a minimum SSp of 244 mV dec-1, average SSp of 570 mV dec-1 and standard deviation of 160 mV dec-1 were achieved. Although further passivation strategies to minimize the defect density present in WSe2 must be explored to further improve the subthreshold slopes, the achieved SSn and SSp values were found to be adequate for the properfunctioning of WSe2 FET-based CMOS inverters and logic gates, which will be illustrated in the subsequent sections. FIG. 171 shows the distribution of the p-branch ON current (7p), extracted for a carrier concentration (ps) of 1.64 x 1013 cm-2 corresponding to FOV of -4 V. The maximum 7p achieved was 16.00 pA pm-1, with the mean and standard deviation of 7.85 and 1.64 pA pm-1, respectively. Note that the ON current for WSe2 -based n-FET and p-FET are relatively similar, which is critical for the design of ICs. Although further improvement in material quality and interfaces can enhance the performance, our approach of combining contact and dielectric engineering to achieve nearly symmetric n-FET and p-FET characteristics is noteworthy.

[0138] Additionally, it is worth mentioning that the device-to-device variation between tier-1 and tier-2 devices is more significantly affected by the growth and transfer process of the WSe2 film, rather than the enhanced topographical complexities observed in tier 2. FIG. 23A shows the transfer characteristics between 240 planar and tier-2 devices with Pd contacts, in which the channel material for both sets of devices was synthesized under similar growth conditions and was transferred via the same PMMA-assisted wet transfer technique. Interestingly, the tier-2 devices exhibit higher ZPMAX (FIG. 23B) reduced device-to-device variation, as evidenced by the FTH-P distribution (FIG. 23C) and lower SSp (FIG. 23D). This established that the topography plays a secondary role in device-to-device variation in two-tier M3D integration of WSe FETs. However, we believe that a chemical mechanical polishing technique can be introduced as more tiers are incorporated into M3D chips, effectively addressing the challenges linked to topography. Another valid consideration is the feasibility of demonstrating p-FETs on any tier, even when the device is encapsulated with an ILD. FIGS. 24A and 24B show 40 WSe2 FETs with Pd contacts before and after 5 nm HfO2 ALD deposition. Clearly, no improvement in the n-branch characteristics is observed, although the p-branch current does degrade. It is worth mentioning that additional p-doping strategies, such as substitutional doping with vanadium or surface charge transfer doping with WOxSej’ or NOx, can be implemented to further enhance the p-FET characteristics. FIG. 24C shows the transfer characteristics of the WSe2 FETs with the HfO2 ILD after 20 s of O2 plasma. A positive shift in FTH, along with an increase in the p- branch current and suppression of the n-branch current is observed. In other words, throughcareful engineering of the contact and dielectric interfaces, it is possible to create unipolar WSe2 p-FETs and n-FETs, making them an excellent option for constructing CMOS circuits.

[0139] Monolithic and 3D integrated CMOS circuits

[0140] Following the electrical characterization of n-FET devices in tier 1 and p-FET devices in tier 2, electron-beam lithography (EBL) was employed to define 1 pm * 6 pm rectangles. Reactive ion etching (RIE) was then utilized to etch the exposed ILD, providing access to the tier-1 devices. EBL and electron-beam evaporation (EBE) were then carried out to define and deposit 300 nm vias connecting the tier-1 and tier-2 devices, thereby forming the intended circuit. It is important to note that EBL provides exceptional alignment precision, a critical parameter influencing the allowable pitch of microbumps for die stacking. FIGS. 18A, 18B, and 18C show the circuit schematic, false-colored SEM images, and output characteristics of a representative M3D-integrated inverter, NOR gate and NAND gate, respectively. The supply voltages were maintained at FDD = 3 V and Ess = 0 V for all circuit demonstrations. The topperforming inverter achieved a peak gain of ~79 at FDD = 3 V, which is comparable with the gain values obtained in vertically integrated inverters reported in previous studies for the same I DD. FIGS. 25A and 25B show the output characteristics and distribution of the peak gain achieved in the 27 fabricated inverters, underscoring the robustness of the proposed via fabrication process flow. Note that the state transition point for the inverters does not always occur at FIN / 2, which could lead to increased power usage and reduced noise immunity. To address this issue, our programmable back-gate stack can be employed to adjust the inverter’s switching threshold (FIG. 25C). By applying a programming voltage to the back-gate stacks of both tier-1 and tier-2 devices, it is possible to alter the threshold voltages of both n-type and p-type WSe2 FETs and hence adjust the inflection point. The programmed inverters demonstrated a low noise margin (NML) and high noise margin (NMH) of 1.23 and 1.49 V, respectively, nearing the ideal 1.50 V mark and aligning with results from similar studies on WSe2-based CMOS inverters. The NAND and NOR gates exhibit proper functionality, with clear differentiation between the logic levels.

[0141] Although deviations from the ideal output are observed in some circuits due to unwanted conduction in the pull-up p-FET or pull-down n-FET networks, the ratio between ‘high’ and‘low’ logic states remains substantial. This can be corrected through further suppression of the n-branch in the p-FETs and the p-branch in the n-FETs to enhance the circuit performance.

[0142] Conclusion

[0143] In conclusion, our work demonstrates the successful achievement of dense and scaled M3D integration for the realization of CMOS circuits based on n- and p-type WSe2 FETs through the utilization of 300 nm vias with a pitch of ~1 pm, connecting over 200 devices in a two-tier chip. Furthermore, the demonstration of superior packing and connectivity in M3D is exemplified through the fabrication of vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. This demonstration not only emphasizes the feasibility of M3D for 2D CMOS devices but also highlights the potential of 2D materials to drive advancements in ‘More Moore’ technologies.

[0144] Methods

[0145] WSe2 synthesis

[0146] The growth of a multilayer WSe on two-inch-diameter c-plane sapphire was carried out in an MOCVD system (https: / / doi.org / 10.60551 / znh3-mj 13) in the 2D Crystal Consortium Materials Innovation Platform (2DCC-MIP) facility at Penn State. The MOCVD system is equipped with a cold-wall horizontal reactor with an inductively heated graphite susceptor with gas-foil wafer rotation. Tungsten hexacarbonyl (W(C0)6) with purity of >99.9% (trace metals basis) purchased from Sigma-Aldrich was used as a metal precursor. Hydrogen selenide (H2Se) was used as a chalcogen gaseous precursor. Hydrogen (H2) was used as a carrier gas. The W(C0)6 powder was maintained at 30 °C and 400 torr in a stainless-steel bubbler. Synthesis of the WSe2 monolayer was based on a multistep process, consisting of nucleation, ripening and lateral growth steps, as described previously. In general, the WSe2 sample was nucleated for 30 s at 850 °C, then ripened for 5 min at 850 °C and 5 min at 1,000 °C, and then grown at 1,000 °C for growth times ranging from 25 to 35 min. During the lateral growth step, the tungsten flow rate was set as 3.8 * 10-3 s.c.c.m. and the chalcogen flow rate was set as 75 s.c.c.m., whereas the reactor pressure was maintained at 200 torr. Then, the multilayer WSe2 was annealed under ambient H2 and H2Se for 10 min and the ambient H2 and H2Se were maintained for 8 min during cool-down to provide additional time for metal adatom diffusion and to reduce selenium vacancies. Under the identical growth conditions, the number of WSe2 layers can bemanipulated by varying the growth time. The growth of a multilayer WSe2 film was achieved using an extended growth time ranging from 25 to 35 min across the two-inch sapphire substrate, which gives rise to a multilayer WSe2 across the entire two-inch wafer. Detailed growth and characterization data associated with the multilayer WSe2 samples produced in this study are available at https: / / doi.org / 10.26207 / x074-bw26. This includes substrate preparation and recipe data for samples grown by MOCVD in the 2DCC-MIP facility and standard characterization data including atomic force microscopy images and room-temperature Raman / PL spectra on the samples.

[0147] Fabrication of local back-gate islands

[0148] To define the locally back-gated island regions, a commercially purchased substrate (thermally grown 285 nm SiCh on p++-Si) was spin-coated with a bilayer electron-beam resist stack consisting of EL6 and A3 resists at 4,000 r.p.m. for 45 s. The resist stack was baked at 150 °C for 90 s and 180 °C for 90 s. The bilayer electron-beam resist was then patterned using EBL to define the islands and developed in 1 : 1 methyl isobutyl ketone :2-propanol (IP A) mixture for 60 s, followed by IPA for 45 s. The back-gate electrodes of 2 / 18 nm Ti / Pt were then deposited using EBE in a Temescal FC-2000 Bell Jar Deposition System.

[0149] Liftoff of the remaining electron-beam resist and excess metal was performed using acetone, and the substrate was then cleaned using IPA. An ALD process was then implemented to grow the back-gate dielectric stack consisting of 9 nm AI2O3, 3 nm HfCL and 3 nm AI2O3. Access to the individual Pt back-gate electrodes was achieved via an RIE process conducted in a Plasma-Therm Versalock 700 device. EBL was used to define the access pads using ZEP electron-beam resist, which was spin coated at 2,500 r.p.m. for 45 s followed by baking at 180 °C for 3 min. After exposure, the sample was developed using n-amyl acetate at room temperature. The dielectric stack was then dry etched using BCD gas at 5 °C for 25 s. Finally, the electron-beam resist was removed using a photoresist stripper (PRS 3000) and cleaned with IPA.

[0150] PMMA-assisted wet transfer technique

[0151] To fabricate the 2D FETs, MOCVD-grown monolayer films were transferred from the sapphire growth substrate to the pre-fabricated island substrate using a PMMA-assisted transfer process. Initially, the 2D film on the sapphire substrate underwent a double spin-coating processwith PMMA, both at 4,000 r.p.m. for 45 s. Subsequently, the corners of the spin-coated films were scored with a razor blade before immersion in a 1 M NaOH solution maintained at 90 °C. The NaOH permeates between the substrate / film interface due to capillary forces, which delaminates the 2D film from the growth substrate. The separated film was then fished out and subjected to three rinses in a water bath before being transferred onto the device substrate. The sample was then annealed at 50 °C and 70 °C for 10 min each to improve adhesion. The sample was subsequently placed in an acetone bath for 10 min followed by an IPA bath for 10 min to remove the PMMA resist.

[0152] Via integration process

[0153] Following the fabrication of tier-2 devices, ZEP 520A resist was spin-coated onto the substrate at 2,000 r.p.m. for 45 s and subsequently annealed at 180 °C for 3 min. A 6 pm x 1 pm rectangle was defined to expose the area containing the tier-1 source and drain terminals. After exposure, the pattern was developed in n-amyl acetate for 3 min, followed by 1 min in IPA. RIE was then performed in a Plasma- Therm Versalock 700 system using a BC13 chemistry for 100 s. Following RIE, the residual resist was removed in a PRS 3000 bath for 10 min, followed by rinsing in IPA and water for 10 min each. To create the via connection between devices, a bilayer resist consisting of PMMA ELI 1 and MMA A3 was spin coated at 4,000 r.p.m. for 45 s, followed by annealing at 150 and 180 °C for 90 s each, respectively. Vias were defined using EBL; following exposure, the sample was developed in 1 : 1 methyl isobutyl ketone:IPA for 60 s and then IPA for 60 s. EBE of 90 nm Ni and 30 nm Au was performed to ensure connectivity between the tier-1 and tier-2 devices. After EBE, the residual resist and metal were lifted off by placing the sample in 85 °C acetone for ~20 min and IPA for 10 min.

[0154] Raman and PL spectroscopy

[0155] Raman and PL spectra were taken on the multilayer WSe2 film as-grown on two-inch c- plane sapphire substrates using a WITec alpha300 apyron system within a N2-ambient glovebox with ~5 ppm of O2 and H2O. Single-point Raman and PL spectra were taken using a x 100 objective at a 4 mW laser power for 30 s and three accumulations and 5 s and two accumulations, respectively.

[0156] SEM

[0157] SEM of the 2D M0S2 transistors used in this study was conducted using a Zeiss Gemini 500 field-emission SEM system at an accelerating voltage of 5 kV.

[0158] TEM sample preparation

[0159] The TEM sample shown in FIGS. 15F-15H was prepared using a Thermo Fisher Scientific Scios 2 DualBeam focused ion beam (FIB) SEM instrument. The sample was first coated with two carbon layers using a 1.6 nA electron beam and 0.1 nA Ga ion beam in sequence. The first layer deposited by the electron beam was ~0.5 pm thick and was used to protect the surface WSe2 layer from Ga ion beam damage in the next step of carbon deposition. The second layer deposited by the Ga ion beam was approximately 4 pm thick, and was used as surface protection during ion beam milling and sample thinning. Following this, an approximately 2-pm-thick sample cross-section around the region of interest was lifted out and in situ transferred to a copper half-grid. The lamella was then thinned using a Ga ion beam at five decreasing voltage levels: 30, 16, 8, 5 and 2 kV. The ion beam voltage was gradually decreased as the sample got thinner to minimize ion beam damage.

[0160] STEM characterization

[0161] The cross-sectional STEM and EDS analyzes in FIG. 15A-15H were performed using the aberration-corrected Thermo Fisher Scientific Titan3 G2 60-300 TEM / STEM instrument, which was operated at a 300 kV accelerating voltage. This instrument was set with a C2 aperture of 70 pm, a spot size of 6 and a convergent angle of 25.2 mrad. Elemental mapping by EDS was performed with the Super-X EDS system under the STEM mode. A lower-magnification image that includes a detailed dual-electrode STEM view (FIG. 15F) was taken with a beam current of 0.07 nA. The EDS mappings were obtained using a beam current of 0.227 nA. EDS data were analyzed using Esprit software with the following parameters: 1 / 4 Q-Map pre-processing, averaging of 9 pixels for post-filtering, and the use of mass percent (norm.) for quantification. Due to the presence of more than 11 elements in the sample and the close proximity of the X-ray edges of some elements, deconvoluting signals from each element perfectly using Esprit posed a challenge. To address this, gamma and brightness adjustments were applied in Esprit to reduce the contrast of the false-positive signals and enhance the signal-to-noise ratio. A signal was considered false-positive when a strong edge for an element was missing from the spectrum while its other edge overlapped with another element’s edge. Consequently, the adjustments ingamma and brightness resulted in non-standardized color bars for each element. Thus, the elemental maps generated highlight the locations where specific elements are concentrated, but comparing the absolute intensity between different elements is not recommended. The multilayer WSe2 in FIG. 16C was imaged down its c-axis using the same TEM / STEM instrument operated at an accelerating voltage of 80 kV. The instrument was set with a C2 aperture of 70 pm and a convergence angle of 25.2 mrad, and the collection angle range of the HAADF detector was 42- 244 mrad.

[0162] Computational details

[0163] All DFT calculations were conducted using the Virtual NanoLab QuantumATK tool.We used generalized gradient approximation within the Perdew-Burke-Ernzerhof formalism and Fritz-Haber Institute (FH1) pseudopotential for exchange-correlation functionals. A Monkhorst- Pack-type mesh Appoint grid of 3 * 3 * 1 at an energy cutoff of 60 Hartree was utilized to sample the first Brillouin zone of the 4 x 4 x 1 supercell of monolayer WSe2. A vacuum space of 30 A was included perpendicular to the surface to prevent coupling between neighbouring cells. Fermi-Dirac occupation methods were used to calculate the Fermi energy relative to the vacuum level. Structures were fully relaxed until the force on each atom was below 0.01 eV A-l to minimize the total energy. Iteration control parameters included a Pulay mixer algorithm with a maximum of 100 steps and a tolerance limit of 10-5. To study oxide-TMDC interactions, we adsorbed a few molecules of A12O3 and HfO2 dielectrics on monolayer WSe? surface to balance the computational efficiency and optimized using DFT to achieve minimum-energy configurations. The generalized gradient approximation was primarily utilized for the exchangecorrelation potential to match the experimental bandgap (Eg = 1.54 eV) of monolayer WSe2.Although spin-orbit coupling affects energy band splitting in free-standing TMDC layers, its impact on oxide-TMDC interactions is negligible due to strong Fermi-level pinning. Hence, spin-orbit coupling was not considered in this study.

[0164] Electrical characterization

[0165] Electrical characterization of the fabricated M3D devices was performed using a semiautomated FormFactor 12000 probe station under atmospheric conditions with a Keysight B1500A parameter analyzer.

[0166] EXAMPLE 3

[0167] Monolithic three-dimensional (M3D) integration is being increasingly adopted by the semiconductor industry as an alternative to traditional through-silicon via technology as a way to increase the density of stacked, heterogenous electronic components. M3D integration can also provide transistor-level partitioning and material heterogeneity. However, there are few large- area demonstrations of M3D integration using non-silicon materials. Here, we report heterogeneous M3D integration of two-dimensional materials using a dense inter-via structure with an interconnect (I / O) density of 62,500 I / O per mm2. Our M3D stack consists of graphenebased chemisensors in tier 2 and molybdenum disulfide (M0S2) memtransistor-based programmable circuits in tier 1, with more than 500 devices in each tier. Our process allows the physical proximity between sensors and computing elements to be reduced to 50 nm, providing reduced latency in near-sensor computing applications. Our manufacturing process also stays below 200 °C and is thus compatible with back-end-of-line integration.

[0168] Three-dimensional (3D) integration can be used to increase transistor count per unit area and create processors with increased computational power. It can also be used to enhance chip functionalities beyond the traditional approach of increasing transistor density. Various technologies — such as analogue devices, radiofrequency devices, sensors, memories and microelectromechanical systems — can be integrated alongside digital components in this manner. There are various approaches to 3D integration. Through-silicon via (TSV) stacking offers benefits such as enhanced bandwidth and reduced interconnect lengths. TSV-based 3D integrated circuits (ICs) were originally pioneered by companies such as IBM, Samsung and Micron, and primarily concentrated on flash memories and dynamic random-access memory stacks, while other commercial providers used TSV electrodes in 3D-stacked complementary metal-oxide-semiconductor (CMOS) image sensors. Recently, technologies such as Intel’s Foveros have made it possible to create dense TSVs with a standard pitch of 50 pm, resulting in an interconnect (I / O) density of up to 400 I / O per mm2. The I / O metric is a critical performance benchmark for 3D ICs. To further increase I / O density, a transition from macro- to micro-3D heterogeneous integration via hybrid bonding is needed. This technology facilitates direct copper-to-copper pad connections with a TSV pitch of less than 10 pm, achieving 10,000 I / O per mm2. Monolithic 3D (M3D) integration can achieve vias with pitches of less than 1 pm for even higher I / O density. In M3D integration, functionally diverse layers of devices are sequentiallystacked on the same wafer to enhance routability and design flexibility while reducing inter-tier signal delay. Thus, the approach enables transistor-level heterogeneity; for example, stacking silicon p-type field-effect transistors (p-FETs) on gallium nitride (GaN) n-type FETs (n-FETs) allows for efficient power delivery and radiofrequency solutions. Similarly, integration of high- performance germanium p-FETs with Si n-FETs can advance CMOS logic applications. Two- dimensional (2D) materials have been integrated at the CMOS back-end for memristive applications. Silicon-free M3D integration was initially achieved by stacking carbon nanotube transistors and resistive memory devices. However, more recent efforts have involved M3D integration of transistors made of 2D transition metal dichalcogenides such as molybdenum disulfide (M0S2) and tungsten diselenide (WSe2). In this Article, we report M3D integration of graphene-based chemitransistors with monolayer MoS2-based mem transistors for near-sensor computing. The M3D stack includes more than 500 M0S2 mem transistors and 500 graphene chemitransistors on each tier, which are used for data processing and acquisition, respectively, with a vertical separation between processors and sensors of less than 50 nm. By exclusively using 2D materials, we demonstrate inter-tier vias measuring 3 >< 3 pm2 with a pitch of 4 pm, allowing us to achieve an interconnect density of 62,500 VO per mm2. The entire stack is fabricated at temperatures below 200 °C, making it compatible with standard back-end-of-line (BEOL) integration processes. Table 1 highlights the advances achieved in via pitch, VO density and BEOL compatibility compared to previous technologies.Table 1 : A comparison of different technologies based on inventor, materials used, via pitch (pm), VO per mm2, application and BEOL compatibility

[0169] We selected monolayer M0S2 and graphene for our demonstration because both are among the most mature 2D materials and can be grown at the wafer-scale. Furthermore, M0S2 transistors have exhibited excellent device performance and can meet the standards for advanced technology nodes, as well as enable various neuromorphic and bio-inspired applications. Graphene-based sensors offer versatility in detecting gases, biomolecules and various chemical species due to their electrochemically inert basal plane. Similarly, the high carrier mobility of graphene and emerging properties in stacked graphene layers open new possibilities for expanding the functionalities of 3D ICs.

[0170] Heterogeneous M3D chip using 2D materials

[0171] M3D integration of monolayer M0S2 memtransistors and graphene chemitransistors necessitates large-area synthesis of these materials. A metal-organic chemical vapour deposition (MOCVD) technique was used to grow monolayer M0S2 on a 5 cm (2 inch) sapphire substrate in a cold-wall horizontal reactor (see the Methods section for details), whereas graphene was commercially procured on copper (Cu) foil. FIG. 26 (panels a,b) show an optical image of the as-grown M0S2 film and its Raman spectra obtained using a 532 nm laser, respectively. The inplane E (387 cm-1) and out-of-plane Alg (404 cm-1) Raman active vibrational modes have a separation of 17 cm-1, confirming the monolayer nature of the M0S2 film. Similarly, FIG.26(panels c,d) show an optical image of the graphene on Cu foil and its Raman spectra, respectively. The distinct Raman peaks at around 1,583 and 2,674 cm-1, corresponding to the G band and 2D band, respectively, support the presence of monolayer graphene. To construct the heterogeneous M3D stack, we selected a commercially available substrate composed of 285 nm SiO2 on p++-Si.

[0172] However, it should be noted that any other substrate compatible with our fabrication process flow could also be used. The monolayer-Mo S2-memtransistor-based computational circuits were allocated to tier 1 and the graphene-chemitransistor-based sensing circuits were positioned in tier 2. This arrangement was achieved using a sequential fabrication method, as depicted schematically in FIG. 26 (panel e). To start, local back-gate electrodes (2 nm Ti / 18 nm Pt) were patterned using e-beam lithography and deposited using e-beam evaporation. This was followed by atomic layer deposition (ALD) of 15 nm AhCh / rnm FHO2 / 3 nm AI2O3 to serve as the back-gate dielectric stack for the tier 1 M0S2 devices. In this structure, the HfCh layer with a smaller bandgap functions as a charge trapping layer positioned between two layers of AI2O3, which have larger bandgaps. This stack resembles the floating-gate stack found in traditional flash memory devices, enabling non-volatile programming of the channel conductance via charge trapping and detrapping phenomena. Next, access to the back-gate metal electrodes was achieved by etching the floating-gate stack with a boron trichloride (BC13) plasma etch. The MOCVD-grown monolayer M0S2 film was then transferred from the growth substrate to the prefabricated local back-gate islands using a polymethyl methacrylate (PMMA) assisted transfer process. The M0S2 film was then patterned through e-beam lithography and etched with sulfur hexafluoride (SF6) to define the channel areas. Subsequently, the source-drain contacts and connections for the comparator circuits were delineated using e-beam lithography, followed by the deposition of 20 nm Au / 20 nm Ni / 10 nm Au and a subsequent lift-off process.

[0173] After finishing the fabrication of the tier 1 devices, a 50 nm layer of AI2O3 was deposited to act as the interlayer dielectric (ILD) separating tier 1 and tier 2. A 1 nm-thick seed layer of evaporated aluminum was applied to improve the nucleation of ALD-deposited A12O3 to overcome the inert basal plane of 2D materials. Vias with lengths of 3 pm and widths of 3 pm were patterned into the ILD using e-beam lithography and then opened with a BC13 plasma etch. A subsequent lithography step allowed for the deposition of 2 nm Ti / 28 nm Ni / 30 nm Au to fillthese vias. Note that, while we used a via pitch of 4 pm for the work discussed here, our technique permits even smaller via sizes and pitches, highlighting the advantages of M3D integration. Following via formation, graphene was transferred onto the chip from the Cu foil using a PMMA-assisted wet etching transfer method. The graphene devices in tier 2 do not require dedicated back-gate electrodes because they are designed for chemisensing applications in liquid environments, with the liquid effectively functioning as a top-gate. Subsequently, the graphene film was patterned using e-beam lithography and etched with oxygen plasma to define the channel regions. As with the tier 1, this step was followed by the patterning of source-drain contacts and gate electrodes, again using e-beam lithography. A stack of 2 nm Ti / 28 nm Ni / 30 nm Au was deposited to form these electrodes, with the excess metal being removed in a lift-off process. The final step in the fabrication of the tier 2 graphene chemitransistors involved the deposition of a 70 nm AI2O3 capping layer that covered the source-drain contacts to prevent leakage while leaving the gate area exposed to ensure direct contact with any liquid placed onto the chip.

[0174] The entire fabrication process occurs within a thermal budget of 180 °C. This temperature limit ensures compatibility with BEOL requirements, allowing for the possible addition of further tiers without compromising the integrity of lower ones. It also facilitates future integration with silicon front-end devices. While the fabrication process may seem straightforward, creating an M3D stack with diverse materials and dense vias requires overcoming substantial lithographic challenges. As more layers are added and structures are miniaturized, precise layer alignment is critical. It is also vital to ensure each layer is electrically isolated by the ILD to avoid leakage. This requires optimization of the fabrication process, including choosing suitable resists, etching recipes and deposition conditions for dielectrics and metals to maintain the structural and electrical integrity of the 3D structure. (Further details on the fabrication process flow are available in the Methods section.)

[0175] FIG. 27 (panel a) shows an optical image of a densely packed array of M3D-integrated two-tier cells based on monolayer M0S2 memtransistors and graphene chemitransistors. The enlarged scanning electron microscopy (SEM) images shown in FIG. 27 (panel b and c) reveal that each cell in the array contains four devices, namely two graphene chemitransistors located above two M0S2 memtransistors. These two graphene chemitransistors form a chemisensor,while the two M0S2 memtransistors Connected by 3 * 3 pm2 vias to the comparators in tier 1. The SEM images also show a via separation of 1 pm and thus a pitch of 4 pm between the cells. FIG. 31 shows a schematic of the M3D IC for near-sensor compute applications. FIG. 27 (panels d and e) show cross-sectional images at different magnifications, obtained using scanning transmission electron microscopy (STEM) in high-angle annular dark-field (HAADF) mode, taken at the location marked with the white dashed line in FIG. 27 (panel b). The presence of the Ti / Pt gate electrode, AhOa / HfCh / AhCE floating-gate stack, M0S2 channel, tier 1 source-drain contacts, AI2O3 ILD, graphene channel and A12O3 capping layer are indicated. FIG. 27 (panel f) displays the energy dispersive X-ray spectroscopy (EDS) elemental mapping of the area highlighted by the light orange dashed line in the magnified view shown in the rightmost HAADF image of FIG. 27 (panel f). The precise placement and dense integration of the scaled vias. FIG.32 shows atomic force microscopy (AFM) images after the fabrication of tier 1 M0S2 devices, post-ILD deposition and after via formation and fabrication of tier 2 graphene devices. Note that the topographic features are preserved after each fabrication step. Furthermore, the surface roughness remained less than 1 nm throughout the fabrication process. This clearly shows that via fabrication does not introduce variations in topography despite the etching and deposition processes involved. Also note that we have not implemented any surface planarization in this work. Although chemical mechanical polishing, a standard step in semiconductor fabrication, will probably be adopted for M3D integration when stacking many tiers, it was found to be unnecessary for the two-tier integration demonstrated here.

[0176] M0S2 memtransistors and comparator circuit

[0177] In our M3D IC, tier 1 is composed of monolayer M0S2 memtransistors that serve as the primary computing elements. These devices are used for the construction of comparator circuits responsible for processing chemical signals detected by the graphene-based chemisensors in tier 2. FIG. 28 (panel a) shows the transfer characteristics, that is, drain current (7DS) plotted against the back-gate voltage (mo), at a constant drain voltage, I DS, of 1 V for 50 M0S2 memtransistors. Here, all MoS2 memtransistors have a channel length ( / .cii) and width (JFCH) of 500 nm and 1 pm, respectively.

[0178] FIG. 28 (panels b and d), respectively, show the distribution of field-effect mobility (z / FE) extracted from peak transconductance, subthreshold slope (AS') extracted for three ordersof magnitude change in YDS and threshold voltage (FTH) extracted using the iso-current method at 100 nA pm-1 for the 50 devices. The median values for pFE, 55 and J TH were found to be -3.3 cm2V-l s— 1 , 150 mV dec-1 and 0.2 V, respectively. The median z / FE value here is lower than that of exfoliated flakes, which is expected since MOCVD-grown M0S2 generally shows smaller grain sizes with more impurities and defects. Although we have previously achieved higher / FE values through thorough optimization of growth and device design, the focus of our current study was not solely on enhancing the individual device performance. The 55 was also higher than the ideal value of -60 mV dec-1 owing to the use of a thicker oxide stack and the presence of non-idealities such as interface traps.

[0179] By using highA dielectric materials and a thinner stack, it is possible to improve 55. Similarly, FTH can be engineered through careful selection of the dielectric interface and metal gate work function. FIG. 33 shows the output characteristics of a representative memtransistor with the ON-current reaching as high as 70 pA pm-1 for a IBS of 5 V. The lower ON-current values can be attributed to the higher contact resistance, RC, of 7 k pm, associated with Ni contacts to M0S2. FIG. 34 shows the full RC extraction using a transmission on Ni-MoS2 contacts. However, it is much higher than recent reports using bismuth (Bi) and antimony (Sb) as contacts to M0S2. Nevertheless, integrating these exotic materials into standard fabrication processes poses compatibility challenges. Although enhancing the performance of M0S2 memtransistors in future M3D ICs is a desirable goal, the current performance level is sufficient for the applications intended in this work.

[0180] A key feature of our M0S2 mem transistors is their programmability, which allows reconfiguration of circuits on the basis of application need. FIG. 28 (panels e and f), show the transfer characteristics of a representative M0S2 memtransistor after programming with positive and negative voltage pulses applied to the local back gate, with varying magnitudes ranging from 4 to 12 V and -4 to -12 V, respectively, with the same pulse time for 100 ps each. The resulting shifts in I TH can be attributed to the trapping and detrapping of carriers in the floating-gate stack. FIG. 28 (panel g), illustrates the non-volatile retention for the high and low conductance states measured using a FBG of 0 V and a FDS of 1 V for 6,000 s. The memory ratio (MR) between the two states show minimal degradation from -4 x 103 to -103. The projected retention before MR decays to 1 was found to be around 1 day on the basis of the experimentalfit. Similarly, FIG. 28 (panel h), shows non-volatile retention characteristics for four distinct analogue conductance states, each for 1,000 s. FIG. 35 presents the programming endurance over 1,000 cycles. Although demonstrating longer-term retention and additional endurance cycles would be ideal, the current performance is adequate for numerous edge applications.

[0181] FIG. 28 (panel i), shows the circuit diagrams for a comparator consisting of two M0S2 memtransistors (MT1 and MT2), connected in series. Note that MT1 is made to serve as a depletion load by shorting its gate terminal to its source terminal. FIG. 28 (panel j), shows the transfer curve for the comparator, that is, the output voltage, POUT, measured at node, N2, as a function of the input voltage, KIN, applied to node N3 (the gate terminal of MT2). For KIN = -1 V, MT2 is in the OFF-state (open circuit), pulling up KOUT to the KDD of 5 V, which is applied to the source terminal of MT1 (node Nl). Similarly, for KIN = 1 V, MT2 is in the ON-state (short circuit), pulling down KOUT to the KGND of 0 V, which is applied to the drain terminal of MT2 (node N4). This explains why KOUT switches from 5 to 0 V as Fin is swept from -1 to 1 V. This switching occurs at KIN = 200 mV, which is denoted as the reference voltage, KREF, of the comparator. Interestingly, KREF can be adjusted by programming MT2 as shown in FIG. 28 (panel k). FIG. 36 shows the comparator output for different KDD. Finally, FIG. 28 (panel 1), shows the output of the comparator in response to an arbitrary input waveform for a KREF of 0 V and a KDD of 2 V. It is important to note here that, while the ILD affects the performance of the M0S2 mem transistors due to n-type surface charge transfer doping from ALD-grown AI2O3, as shown in FIG. 37, the functionalities of M0S2 memtransistor-based circuits are not adversely affected. For example, the observed shift in F TH is compensated using the programming capability of the floating-gate stack to ensure proper logic levels for the intended applications.

[0182] Graphene chemitransistor-based sensing module

[0183] Tier 2 of our M3D IC incorporates graphene chemitransistors that are specifically engineered to allow direct application of chemical solutions onto the chip for chemi sensing. These solutions play the role as a liquid top-gate for the graphene chemitransistors, due to the formation of an electric double layer at the graphene channel and chemical solution interface. This electric double layer functions as an ultra-thin dielectric layer and is therefore crucial for controlling the conductance of the channel when an electrical bias is applied to the solution. FIG. 29 (panel a) shows the transfer characteristics, that is, / DS plotted as a function of the liquid top-gate voltage (FLTG), for 130 graphene chemitransistors in aqueous solution at a constant EDS of 500 mV. The observed transfer curves are quintessential to graphene with the global minima referred to as the Dirac points. Additionally, the graphene chemitransistors exhibit ambipolar transport, that is, they demonstrate both electron and hole conduction, which is a direct consequence of graphene being a zero-bandgap semiconductor.

[0184] FIGS. 29 (panels b,c,d), respectively, depict the distribution of the Dirac voltage (Foirac), that is, the applied FLTG that results in a minimum / DS, and the electron and hole mobility values ( / / FE,N and / / FE,P) extracted from their respective peak transconductances for these 130 graphene chemitransistors. The median values for FDirac, / FE,N and / FE.P were found to be 1.1 V, 126 cm2 V-l s~l and 219 cm2 V~1 s~l, respectively. The device-to-device variation can be ascribed to imperfections introduced in the graphene during growth, transfer and / or chemitransistor fabrication processes. Although such variation is generally undesirable for most applications, here it presents an opportunity for designing a chemisensor, as discussed in the following section.

[0185] Each chemisensor in our M3D IC comprises two graphene chemitransistors (GC1 and GC2) connected in series as shown using the circuit schematic in FIG. 29 (panel e). The output from the chemisensor is obtained at node N2. FIG. 29 (panel f) shows the output voltage (FGT) as a function of F LTG with a supply voltage (FDD,GT) of 1 V when deionized (DI) water with different concentrations of NaCl is used as the liquid solution. The distinct shapes of these response curves directly arise from the device-to-device variation. Without this variation, the output of the chemisensor would be a horizontal straight line with a FGT of 500 mV irrespective of the chemical solution. Nevertheless, the F GT obtained at FLTG values of 0.45 and 0.55 V show monotonic changes with the increasing concentration of NaCl in DI water, as illustrated using the bar plots in FIG. 29 (panel g). This confirms the functioning of the graphene-based circuit as a chemisensor, offering the ability to adjust the FLTG for optimal sensitivity.

[0186] Additionally, it should be noted that the characteristics of the voltage transfer curve can vary depending on the position of the Dirac points in individual graphene chemitransistors, as illustrated in FIG. 38. While the exact shape of these curves is not critical for the application demonstrated here, consistent performance is crucial for future practical use. This will require further development of graphene devices. Initially, minimizing device-to-device variationthrough optimized CVD growth conditions and improved transfer processes is key. Subsequently, we can reintroduce variation between two graphene chemitransistors by utilizing the memristive properties of graphene, as detailed in our previous work. Although our current study intentionally uses device-to-device variation to achieve the desired curve shape, our aim is to control this variation to guarantee reproducibility.

[0187] M3D chip for near-sensor computing applications

[0188] Near-sensor computing is a transformative approach that allows processing of data close to where it is generated, as opposed to transmitting it over long distances to central processing units: that is, cloud-based computing. Such a shift enables real-time analysis of data, leading to lower latency and faster decision making, and contributes to better bandwidth, accuracy and energy efficiency. As a result, this proximity-driven approach has far-reaching implications in many applications, with extra consideration to the field of chemical sensing. For example, in environmental monitoring and industrial process control, the ability to detect chemical events or anomalies in real-time enables early warning systems and proactive measures to mitigate potential risks and safety issues. We illustrate this concept by using our M3D IC to detect instances where the concentration of a certain chemical in a solution rises above a set limit, as shown in FIG. 30 (panel a).

[0189] The near-sensor computing architecture used for the task is illustrated in FIG. 30 (panel b). Here, the output node of a graphene-chemitransistorbased chemisensor in tier 2 is connected to the input node of an MoS2-memtransistor-based comparator circuit in tier 1, as facilitated by an inter-tier via. FIG. 30 (panel c) displays the transfer curves for the chemisensor when exposed to two different sugar solutions created by mixing a sugary beverage with water in ratios of 1: 1 (dilute, red curve) and 2:1 (concentrated, blue curve). These curves were recorded immediately after the solutions were applied to the chip. In contrast, FIG. 30 (panel d) illustrates how these response curves evolve over time as a dilute sugar solution is left to evaporate for 15 min, gradually increasing its sugar concentration. FIG. 30 (panel e) shows Fa measured at I LTG = 0.75 V as a function of time as the solution evaporates. As can be seen, J & starts at ~0.7 V and eventually decreases to 0.5 V after 10 min; this can be read as if the device is shifting from the dilute transfer characteristics shown in FIG. 30 (panel c) to the more concentrated transfer characteristics due to an increase in sugar concentration. This establishes that FGr serves as anindication of sugar level in the solution. Note that while we have not functionalized individual graphene chemisensors, functionalized multiplexed arrays can enhance the selectivity and sensitivity of our proposed architecture when incorporating more complex and diverse chemicals.

[0190] Next, to develop an alert system, the analogue output voltage (Phr) needs to be transformed into a digital signal to trigger subsequent modules. This is accomplished using the programmable comparator based on M0S2 mem transistors depicted in FIG. 30 (panel f), for several distinct reference voltages, PREF. Notably, the output logic shifts when the sugar concentration surpasses a specific allowable limit predefined by PREF. AS anticipated, the time required to activate the alert system is shorter when the objective is to signal at lower concentrations and longer at higher concentrations. The non-idealities observed in the digitization process can be ascribed to the lower gain of the comparator circuit reducing the abruptness of state transition from 0 V to DD, that is, digital 0 state to the digital 1 state. The gain can be improved either by using a CMOS inverter, which will require integration of both n- and p-type 2D memtransistors, or by cascading multiple depletion-mode inverters. FIG. 39 shows the results of digitization using a three-stage-cascaded-inverter-based comparator circuit.

[0191] We also show how the 3D IC array can be exploited for chemical codification by harnessing the response variation among the graphene-based chemisensors. FIG. 30 (panel g) shows the transfer curves for 16 chemisensors in response to four different chemicals, Cl to C4. FIG. 30 (panel h) shows the corresponding For values extracted at PLTG of 0.6 V, which form an analogue code for each chemical. Using the same circuit architecture shown in FIG. 30 (panel b), this analogue code can be converted to a one-dimensional or 2D digital code as shown FIG. 30 (panels i and j), respectively. The comparator PREF was set to 250 mV. Note that by tuning the read voltage, PLTG, or by using the programmability of the MoS2-memtransistor-based comparator to adjust PREF, it is possible to generate different codes for the same chemicals, as shown in FIG. 40. Nevertheless, while these demonstrations are straightforward, they have broad implications for near-sensor computing, offering potential application in more complex scenarios through the integration of intricate circuits and additional sensors. Also, the physical proximity of less than 50 nm between sensing and computing modules achieved in ourheterogeneous M3D chip based on 2D materials is better than state-of-the-art packaging solutions that use distinct technologies in these components.

[0192] Conclusions

[0193] We have reported a monolithic heterogeneous 3D integration of graphene-based chemitransistors and monolayer-MoS2-based memtransistors across two tiers using a dense intertier via structure with an interconnect density of 62,500 I / O per mm2. The M3D stack can be fabricated at temperatures below 200 °C, making it compatible with BEOL integration. Notably, the vertical proximity between sensors and computing elements in our stack is 50 nm, surpassing current 3D packaging solutions and potentially reducing computational latency and improving bandwidth.

[0194] Methods

[0195] Large-area monolayer M0S2 film growth Monolayer M0S2 was deposited on epi-ready 2-inch c-sapphire substrate by MOCVD. An inductively heated graphite susceptor equipped with wafer rotation in a cold-wall horizontal reactor (https: / / doi.org / 10.60551 / znh3-mj 13) was used to achieve uniform monolayer deposition. Molybdenum hexacarbonyl (Mo(CO)e) and hydrogen sulfide (H2S) were used as precursors. Mo(CO)e maintained at 25 °C and 625 torr in a stainless-steel bubbler was used to deliver 4.7 * 10-3 seem of the metal precursor for the growth, while 400 seem of H2s was used for the process. M0S2 deposition was carried out at 1,000 °C and 50 torr in H2 ambient, with monolayer growth being achieved in 11 min. Before growth, the substrate was baked at 1,000 °C in H2 for 10 min. Following growth, the substrate was cooled in H2S to 300 °C to inhibit the decomposition of the M0S2 film. More details on the growth process can be found in an earlier study.

[0196] M0S2 film transfer to local back-gate island

[0197] Film transfer from the growth substrate to the application substrate was performed using a PMMA-assisted wet transfer process. First, the as-grown M0S2 on the sapphire substrate was spin-coated with PMMA and left to sit for 24 h to ensure good PMMA-M0S2 adhesion. The corners of the spin-coated film were then scratched using a razor blade and immersed in DI water kept at 50 °C for 2 h. Capillary action caused the DI water to be preferentially drawn into the substrate-MoS2 interface, owing to the hydrophilic nature of sapphire and hydrophobic nature of M0S2 and PMMA, separating the PMMA-M0S2 stack from the sapphire substrate. Theseparated film was then fished from the DI water using a clean glass slide and rinsed in three separate water baths for 15 min each before finally being transferred onto the application substrate. Subsequently, the substrate was baked at 50 and 70 °C for 15 min each to remove moisture and promote film adhesion, thus ensuring a pristine interface, before the PMMA was removed by immersing the sample in acetone for 1 h and the substrate was cleaned with a subsequent 30 min isopropyl alcohol (IP A) bath.

[0198] SEM

[0199] SEM of the 2D M0S2 transistors used in this study was conducted using a Zeiss Gemini 500 field emission SEM system at an accelerating voltage of 5 kV.

[0200] TEM sample preparation

[0201] The TEM sample was prepared using a Thermo Fisher Scientific (TFS) Scios 2 DualBeam focused ion beam SEM instrument. The sample was coated with two carbon layers initially: the first layer, ~0.5 pm thick, was deposited by a 1.6 nA electron beam to protect the surface of M0S2 and WSe2 layer from the following Ga ion beam damage during the second layer of carbon deposition. The second layer, approximately 3 pm thick, was deposited using a 0.3 nA Ga ion beam to provide surface protection for later ion beam milling and sample thinning. After this coating process, the sample with a 2-pm-thick cross-section from the region of interest was extracted and transferred in situ to a copper half-grid. Then the lamella was thinned using a Ga ion beam at progressively lower voltages (30, 16, 8, 5 and 2 kV) to minimize ion beam damage as the sample became thinner.

[0202] STEM characterization of the cross-section

[0203] In this study, the TFS Titan3 G2 60-300 S / TEM was used to perform STEM and EDS analyses. To mitigate carbon deposition, a 15 min beam shower was applied in the STEM setting, with a dwell time of 0.05 ps, *5,000 magnification and 150 pm C2 aperture. The STEM and EDS analyses were operated with an acceleration voltage of 300 kV, featuring a spot size of 6, a C2 aperture of 70 pm and a convergent angle of 25.2 mrad. Elemental mapping was performed using the Super-X EDS system in STEM mode. A series of HAADF-STEM images of the 3D IC were captured at a beam current of 0.07 nA, followed by EDS mappings at a beam current of 0.30 nA. EDS analysis was conducted using Esprit software, incorporating 1 / 8 Q-Map preprocessing and the series fit deconvolution method. Peak-to-background (P / B) ZAFquantification was used to generate mass percentage (norm.) elemental maps, with a postfilter averaging 9 pixels.

[0204] AFM

[0205] AFM was used to study the surface morphology, coverage and thickness of the deposited layers. Scanasyst air probe AFM tips with a nominal tip radius of about 2 nm and spring constant of 0.4 N m-1 were used for the measurements, and the images were collected using peak-force tapping mode with a peak force of 14 nN and a scan speed of 2 Hz.

[0206] Raman spectroscopy

[0207] Raman characterization on M0S2 and graphene was taken using a Horiba LabRAM HR Evolution confocal Raman microscope with a 532 nm laser. The power was 34 mW filtered at 1%. The objective magnification was x 100 with a numerical aperture of 0.9, and the grating had a spacing of 1,800 gr mm-1 for Raman.

[0208] Electrical characterization

[0209] Electrical characterization of the fabricated devices was performed using a semiautomated Formfactor 12000 probe station under atmospheric conditions with a Keysight B 1500A parameter analyzer. A continuous wave white light source was used for all experiments involving light illumination unless otherwise stated.

[0210] References

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[0212] It should be understood that the disclosure of a range of values is a disclosure of every numerical value within that range, including the end points. It should also be appreciated that some components, features, and / or configurations may be described in connection with only one particular embodiment, but these same components, features, and / or configurations can beapplied or used with many other embodiments and should be considered applicable to the other embodiments, unless stated otherwise or unless such a component, feature, and / or configuration is technically impossible to use with the other embodiment. Thus, the components, features, and / or configurations of the various embodiments can be combined together in any manner and such combinations are expressly contemplated and disclosed by this statement.

[0213] It will be apparent to those skilled in the art that numerous modifications and variations of the described examples and embodiments are possible considering the above teachings of the disclosure. The disclosed examples and embodiments are presented for purposes of illustration only. Other alternate embodiments may include some or all of the features disclosed herein. Therefore, it is the intent to cover all such modifications and alternate embodiments as may come within the true scope of this invention, which is to be given the full breadth thereof.

[0214] It should be understood that modifications to the embodiments disclosed herein can be made to meet a particular set of design criteria. Therefore, while certain exemplary embodiments of the compositions, materials, apparatuses, and methods of using and making the same disclosed herein have been discussed and illustrated, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:

1. A monolithic integrated circuit, comprising: a substrate; plural tiers formed on a surface of the substrate, each tier comprising a 2-D planar layer of electrical elements, the plural tiers being stacked in vertical direction so that the geometric planes of each 2-D planar layer are parallel to each other.

2. The monolithic integrated circuit of claim 1, wherein: each 2-D planar layer is composed of a nanomaterial.

3. The monolithic integrated circuit of claim 1, wherein: the nanomaterial is a M0S2 film and / or a WSe2 film.

4. The monolithic integrated circuit of claim 1, wherein: the electrical elements include at least one filed-effect transistor.

5. The monolithic integrated circuit of claim 4, wherein: the at least one filed-effect transistor includes a gate, a drain, a source, and a channel formed in and / or on the 2-D planar layer.

6. The monolithic integrated circuit of claim 1, wherein: the substrate is a semiconductor material.

7. The monolithic integrated circuit of claim 6, wherein: the semiconductor material is SiCh or AI2O3.

8. The monolithic integrated circuit of claim 1, further comprising: an inter-layer positioned between at least two tiers.

9. The monolithic integrated circuit of claim 8, wherein:the inter-layer is configured to electrically isolate at least a portion of one tier from at least a portion of another tier of the at least two tiers.

10. The monolithic integrated circuit of claim 8, wherein: the inter-layer is a dielectric material.

11. The monolithic integrated circuit of claim 10, wherein: the dielectric material is AI2O3.

12. A method of generating a monolithic integrated circuit, the method comprising: depositing a nanomaterial on a substrate to generate a first tier comprising a 2-D planar layer of the nanomaterial; forming one or more electrical elements in and / or on the 2-D planar layer of the first tier; depositing an inter-layer on the first tier; depositing a nanomaterial on the inter-layer to generate a second tier comprising a 2-D planar layer of the nanomaterial; and forming one or more electrical elements in and / or on the 2-D planar layer of the second tier.

13. The method of generating a monolithic integrated circuit of claim 12, wherein: the nanomaterial of the first tier is the same as or different from the nanomaterial of the second tier.

14. The method of generating a monolithic integrated circuit of claim 12, wherein: depositing the nanomaterial to form the first tier and / or the second tier involves a chemical vapor deposition technique.

15. The method of generating a monolithic integrated circuit of claim 12, wherein: forming one or more electrical elements for the first tier and / or the second tier involves a spin coating technique and an etching technique.

16. The method of generating a monolithic integrated circuit of claim 12, wherein: the one or more electrical elements for the first tier and / or the second tier includes at least one filed-effect transistor.

17. The method of generating a monolithic integrated circuit of claim 16, wherein: the at least one filed-effect transistor includes a gate, a drain, a source, and a channel.

18. The method of generating a monolithic integrated circuit of claim 12, wherein: the substrate is SiCh or AI2O3; the inter-layer is a dielectric material; and / or the nanomaterial is a M0S2 film and / or a WSe2 film.

19. The method of generating a monolithic integrated circuit of claim 12, wherein: the inter-layer electrically isolates at least a portion of the first tier from at least a portion of the second tier.

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