Semiconductors devices, and their manufacture, including thermal-pathway vias

Abstract

In one example, a semiconductor has a set of one or more scaffolding tiers, each tier of the set of one or more scaffolding tiers including a stack of material layers. The stacked layers include: a device layer in which at least one hot-spot region is located; a thin poly crystalline diamond (PCD) layer, located between the device layer and a thick layer, thermally coupled to said at least one hot-spot region of the device layer; and the thick layer has a plurality of diamond vias, providing respective thermal pathways, with diamond-via end portions that are thermally coupled to the PCD layer. The thick layer includes elongated diamond-filled thermal-pathway vias having end portions thermally coupled to the PCD layer for enabling thermal energy to flow from said at least one hot-spot region into and / or through the thick layer.

Description

SEMICONDUCTORS DEVICES, AND THEIR MANUFACTURE, INCLUDING THERMAL-PATHWAY VIASBACKGROUND[0001 j Aspects of the present disclosure are related generally to the field of semiconductor devices and their manufacturing methodologies involving poly crystalline diamond growth, and as may be exemplified by non-limiting examples including high-power and / or high-speed circuits in semiconductor devices in which thermal management can play an important role during operation of such circuits.10002] High power and high-frequency amplifiers, such as those implemented with GaN (gallium nitride? and SiC (silicon carbide) power transistors, are non-limiting examples of types of semiconductor technology which have benefited from the use of diamond for thermal management (e.g., due to hot spots in the device layer). In these and related semiconductor technologies, it has been appreciated that there has been significant efforts to effect cooling in such devices, especially as both the operation frequency and power associated with the devices are increasing every day. In many semiconductor devices, in order to increase the power output of such devices in a wide frequency range from DC to nun-wave, active cooling of the active I hot spot region (e.g., transistor channel or PN junction) is required. Self-heating in the channel degrades device performance and shortens device lifetime. The lack of a low thermal resistance path to dissipate the heat has been a problematic issue in connection with semiconductor devices.

[0003] In more specific contexts, one issue for increasing power density in semiconductor devices is channel self-heating. This is an issue that reduces device lifetime and can eventually result in device or system failure. In order to integrate diamond into semiconductor devices for thermal management purposes, the temperature and the time duration, as well as the grow th rate, play very important roles. In certain example applications, it can be important not to damage the device physically and its performance (e.g., breakdown voltage, output current, cut-off frequency, maximum frequency, output power, power added efficiency, etc.) after or during diamond integration. It can also be important to minimize the thermal boundary resistance between the diamond and the device’s hot spot (e.g., transistor channel) along with maximizing diamond thermal conductivity. These important aspects may lead to rigorous restrictions to the effective growth window for high-quality diamond. For example, in accordance with certain experiments, since the monocry stalline diamond has a dielectric constant ~5.7, using this material as part of back- end-of-line (BEOL) interlayer dielectrics and passivation layers can assert parasiticcapacitance which degrades high-frequency performance, in part due to metal interconnect layers being deposited onto an already -patterned wafer (e.g., with devices including transistors, capacitors, resistors, etc., being connected to each other according to metal-wiring deposition). A porous diamond layer may reduce the dielectric constant while keeping the thermal conductivity greater than 100-times larger than today’s state-of-the-art porous SiCOH in the foundry process. The dielectric constant of the diamond layer can be controlled in a range between 1 to 5. 0004] In the above and / or other specific contexts, due to the large thermal conductivity of diamond (e.g., 300-2200 W / mK), polycrystalline diamond can be grown on top of high- power high-frequency semiconductor devices for removing the heat from the high temperature spot in the transistor channel to improve device performance and lifetime.Poly crystalline diamond can be grown using a microwave plasma chemical vapor deposition (MPCVD) system. MPCVD utilizes hydrogen and methane (CPU) gases as the main reactants in the chamber. By igniting the plasma at 2.45 GHz these gases will be activated to atomic hydrogen and CH? Atomic hydrogens are necessary to break C-H bonds at the surface and attach CH3+to the surface for diamond growth. Atomic hydrogen promotes the formation of diamond over graphite by making the graphite to diamond conversion energy lower. Since a hydrogen plasma is the main species in the diamond growth chamber, high temperature combined with hydrogen gas and H+radicals can cause the decomposition and etching of the substrate (GaN, Ga2O3, and InP). Damaging the substrate can degrade device performance and, in some serious cases, can cause device failure.

[0005] These and other matters have presented challenges for a variety of relevant embodiments and applications involving high-power and / or high-frequency circuits, such as high-power and / or high-frequency amplifiers, including (as non-limiting examples) devices such as Si-based LDMOS, BIT, IGBT, GaN, power HEMT, SiC and / or Ga2O3transistors, high-frequency devices such as RF GaN HEMTs, InP HBTs, and GaAs based FETs, and Si- based chips (such as MOSFETs, insulated gate-bipolar transistors (IGBTs), gate turn-off (GTOs), and sihcon-controlled rectifiers), as may be used in a wide range of applications such as computing modules, memories, data centers, high-end wireless (e.g., 5G and 6G) communications, airborne radars, and automotive radars.SUMMARY OF VARIOUS ASPECTS AND EXAMPLES

[0006] Various examples / embodiments presented by the present disclosure are directed to issues such as those addressed above and / or others which may become apparent from the following disclosure. In specific exemplary contexts, it will be appreciated that aspects of certain embodiments are directed to certain methods involving poly crystalline diamond growth on semiconductor materials and apparatuses (e.g., chips, chip sets, wafer, circuits, systems and the like) developed at least in part by using aspects, steps and / or features of such methods.[000? ] Consistent with a certain type of specific example embodiment according to the present disclosure, a semiconductor apparatus has at least one set of stacked layers, each such set including: a device layer in which at least one hot-spot region is located; and a thin poly crystalline diamond (PCD) layer, located between the device layer and another layer. In more specific examples, the other layer (sometimes referred to as a thick layer) may form part of the set of stacked layers with the thick layer being thermally coupled to said at least one hot-spot region of the device layer, and having a plurality of (thermally -conductive) diamond vias. The diamond vias may be used to provide respective thermal pathways, with diamondvia end portions that are thermally coupled to the PCD layer. The thick layer includes (e.g., elongated) diamond-filled thermal-pathway vias having end portions thermally coupled to the PCD layer for enabling thermal energy to flow from said at least one hot-spot region into and / or through the thick layer. The set of stacked layers may be part of one or more scaffolding tiers (e.g., including a single tier or anywhere between two and twenty tiers), and with such tiers typically being in combination to provide complementary efforts in dissipating thermal energy from the semiconductor apparatus.

[0008] Consistent with and optionally building on the above type of examples, the semiconductor apparatus may be further characterized as follows. The PCD layer may: be at least predominantly composed of or formed by nanocrystalline diamond particles (e.g., average diameter of 3 nm to 100 nm) and / or microcrystalline diamond particles (e.g., average diameter of 100 nm to 30 pm), and / or include at least a predominant amount of diamond particles which are linked and / or connected to one another (e.g., through covalent bonds). The thick layer may include: diamond particles at least some of which are porously arranged; a porous arrangement of SiCh, SiCOH, and / or diamond (e.g., nanocrystalline and / or microcrystalline particles) grown within the porous arrangement. The semiconductor apparatus may further include a heat sink thermally coupled and secured to a side of the thick layer facing away from the PCD layer.

[0009] In certain more-specific examples, the above-noted thick layer may include: one or more materials, e.g., having porously -arranged PCD particles that surround at least a portion of at least one of the plurality of the thermal-pathway vias; relatively large-grained particles, wherein the diameter sizing of the relatively large-grained poly crystalline diamond particles corresponds to an average diameter in a range from 100 nm -10000 nm; and / or one or more dielectric-type materials that surround at least a portion of at least one of the plurality of the thermal-pathway vias, wherein the one or more dielectric-type materials are from among materials including: SiCh, SiCOH, diamond, and material(s) defining one or more air gaps as the dielectric.[0010 j Also, the above-noted type of semiconductor apparatus may further include a SiNx-based layer, between the device region and the PCD layer, that is highly resistive to Id- plasma etching and is to: protect the active region from decomposition and physical damage, facilitate dissipation of heat, when the semiconductor device is in use, from the active region to the diamond region, act as a buffer layer for smooth phonon transport through an interface between the device layer and the PCD layer, and facilitate a low thermal boundary resistance.

[0011] In such examples involving such a tier with the device layer, the semiconductor apparatus may include a dielectric layer (e.g., including at least one from among SiCh, AI2O3, SiC and SiNx) between the device region and the PCD layer, and / or with the thick layer including one or more dielectric materials in a porous arrangement that surrounds at least a portion of at least one of the plurality of the thermal-pathway vias.

[0012] In another type of specific example embodiment, the present disclosure is directed to exemplary methods, one or more of which involve a step of forming or operating a semiconductor device having a thin polycrystalline diamond (“PCD”) layer proximal (e.g., over or against) the device layer, with the PCD layer including nanocry stalline diamond particles of which at least a predominant amount are linked and / or connected to one another. The PCD layer may be part of a set of one or more scaffolding tiers, each tier of the set of one or more scaffolding tiers including a stack of material layers (“the stacked layers”).

[0013] In such exemplary methods involving formation of the PCD layer proximate the device layer, the PCD layer may be grown using a monolayer of diamond particles on a solvent-cleaned surface (e.g., using High-purity Isopropyl Alcohol or IP A), wherein the diamond particles have an average diameter in a range from 100 nm to 10 pm, the nanocrystalline and / or microcrystalline diamond particles have an average diameter in a range from 3 nm to 500 nm, and the PCD layer is formed to have a porousness densitycharacterized as a function of a density of the diamond particles in the PCD layer, and the PCD layer has a thickness in a range from 100 nm to 5 pm. 0014] In more specific examples according to present disclosure, forming diamond in one or more such PCD layers may involve use of one or more of the following stages: (a) mixed-seeding stage in which a monolayer of diamond nanoparticles, having an average diameter of 3 nm - 100 nm, is deposited proximal a surface of the device layer, and in which one or more layers of microparticles, having an average diameter of 100 nm to 10 pm, are deposited after the monolayer of diamond nanoparticles is deposited; (b) a diamond linking stage, earned out after the mixed seeding stage, in which an amount of CH4 is temporarily increased (e.g., in a range of 4% - 10%), as a burst or temporary increase in application amount, for linking and interconnecting microparticles; and (c) facilitating, between diamond in the PCD layer and a surface of the device layer, low thermal grain-to-grain boundary resistance and low thermal boundary resistance to be in a range of 1 m2K / GW - 20 m2K / GW, and in some cases minimizing the thermal boundary resistance. 00 IS] Such exemplary methods, according to the present disclosure, may also include forming a semiconductor apparatus (e.g., wafer or device), at a dielectric-type interface layer between diamond in the PCD layer and a surface of the device layer that is proximate a transistor channel region (e.g., of a GaN, GaaCh, and / or InP type), wherein the diamond in the PCD layer is high-phase purity diamond with large grain sizes characterized by using only H2 and CH4 in their formation, and / or by maintaining a diamond growth temperature at a constant level and varying plasma power and pressure to control etching, wherein the diamond grow th temperature may be maintained at a level depending on a type of the transistor (or its channel) is: a GaN type, a GazCh type, and an InP type.

[0016] In such exemplary methods involving such a tier-type configuration, the stacked layers include one or more of various features such as: a device layer in which at least one hot-spot region is located; a thick layer, stacked with the PCD layer between the device layer and the thick layer, including a plurality of diamond-filled thermal-pathway vias, through which thermal energy is to flow in a direction from said at least one hot-spot region into and / or through the thick layer; and, optionally, a dielectric layer (as characterized above) between the device region and the PCD layer and acting to protect the device region, provide a smooth transition at the boundary with a surface of the device region (among other functions). At least a portion of the thick layer, including at least one of the thermal-pathway vias, may be formed to provide at least one highly conductive thermal path characterized as having an average thermal conductivity in a range from 50-2200 W / m / K. One or more of themethods may including forming another one of the set of tiers by: repeating in sequence the provision of the device layer (optionally the dielectric layer), the PCD layer, and the thick / via-providing layer, wherein a plurality of tiers are formed to provide respective conductive thermal paths leading heat away from the one or more hot spot regions (aka one or more channel and / or junction regions), for example, to a heat sink. In certain more-specific example implementations according to the present disclosure, the diamond (PCD) layer is to spread the heat laterally (effectively increasing the size of the hot spot), by having the diamond vias remove the heat from one stacked tier to the next PCD layer through high- thermally conductive highways (e.g., including the PCD layer(s) and the vias), thereby mitigating or preventing localized heat formation and its corresponding damage to the electrical and physical aspects of the device(s).(0017] The above discussion is not intended to describe each aspect, embodiment or every implementation of the present disclosure. The figures and detailed description that follow also exemplify various embodiments.BRIEF DESCRIPTION OF FIGURES

[0018] Various example embodiments, including experimental examples, may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, each in accordance with the present disclosure, in which: (0019] FIG. 1 is a flow diagram showing one or more structures transitioning into a semiconductor device, according to certain exemplary aspects of the present disclosure;

[0020] FIG. 2 is another flow diagram showing one or more structures also transitioning into a semiconductor device having multiple stacked tiers of layers, according to certain exemplary aspects of the present disclosure;

[0021] FIG. 3 is a diagram showing example methods involving an optional porous matrix, with and without seeding, useful in forming one of the layers in one of more of the structures related to that shown in FIG. 1 or FIG. 2, according to certain exemplary aspects of the present disclosure;

[0022] FIG. 4 is a diagram showing an example method involving an optional porous matrix, with diamond-based seeding, useful in forming one of the layers in one of more of the structures related to that shown in FIG. 1 or FIG. 2, according to certain exemplary aspects of the present disclosure;

[0023] FIG. 5 is a set of related diagram showing an example method involving diamond-filled vias which may be used in one of more of the structures related to that show n in FIG. 1 or FIG. 2, according to certain exemplary aspects of the present disclosure;

[0024] FIG. 6 is another set of related diagram showing an example method involving diamond-filled vias which may be used in one of more of the structures related to that shown in FIG. 1 or FIG. 2, according to certain exemplary aspects of the present disclosure;10025] FIGs. 7A and 7B, also according to certain exemplary aspects of the present disclosure, show a side view (FIG. 7A) of multi-tiered architecture of a semiconductor apparatus and a SEM micrograph (FIG. 7B) of a diamond scaffolding which can be used in such an architecture; and

[0026] FIGs. 8A-8C, also according to certain exemplary aspects of the present disclosure, show beneficial aspects of examples: with and without diamond (FIG. 8 A) for a corresponding two-tiered architecture of a semiconductor apparatus (FIG. 8B), and without diamond scaffolding (top) and with diamond scaffolding (bottom) (FIG. 8C).

[0027] While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation.DETAILED DESCRIPTION

[0028] Aspects of the present disclosure are believed to be applicable to a variety of different exemplary types of apparatuses and methods involving devices characterized at least in part by stacked set of layers for including a device layer, a PCD layer and a via-providing (aka thick) layer as may be used as part of a one or more scaffolding tiers. While certain aspects of the present disclosure are not necessarily so limited, an understanding of specific examples in the following description may be understood from discussion in such specific exemplary contexts.

[0029] Accordingly, in the following description various specific details are set forth to describe specific examples presented herein. It should be apparent to one skilled in the art, however, that one or more other examples and / or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same connotation and / or reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination.

[0030] Exemplary aspects of the present disclosure, including apparatuses and / or methods, are directed to and involve a semiconductor structure that has at least one set of stacked layers, each such set including: a device layer in which at least one hot-spot region is located; a thin poly crystalline diamond (PCD) layer, located between the device layer and a thick layer, thermally coupled to said at least one hot-spot region of the device layer; and the thick layer having a plurality of diamond vias, providing respective thermal pathways, with diamond-via end portions that are thermally coupled to the PCD layer. The thick layer includes diamond-filled thermal-pathway vias having end portions thermally coupled to the PCD layer for enabling thermal energy to flow from said at least one hot-spot region into and / or through the thick layer.

[0031] In some instances, exemplary aspects of the present disclosure are directed to and involve apparatuses and / or methods that have a set of one or more scaffolding tiers, each tier of the set of one or more scaffolding tiers including a stack of material layers, with the stacked layers including a device layer and including PCD layer located between the device layer and a thick layer, as characterized above. As formed or implemented to be used as partof one or more scaffolding tiers, in some instances as many as twenty tiers may be used in combination to provide complementary efforts in dissipating thermal energy from the semiconductor apparatus.

[0032] In the above and / or other specific contexts consistent with examples of the present disclosure, due to the large thermal conductivity of diamond (e.g., 300-2200 W / mK), poly crystalline diamond in certain examples is grown on top of high-power high-frequency semiconductor devices (e g., on and connecting with the pillar-shaped vias in the thick layer) for removing the heat from the hot (high temperature) spot in the transistor channel to improve device performance and lifetime. In more specific examples, poly crystalline diamond is grown using a microwave plasma chemical vapor deposition (MPCVD) system, with MPCVD utilizing hydrogen and methane (CH4) gases as the main reactants in the chamber. 0033] Consistent with the above aspects, such a manufactured device or method of such manufacture may involve aspects presented and claimed in U.S. Provisional Application Serial No. 63 / 605,071 filed on December 1, 2023 (STFD.461P1 S23-503) with Appendices A-C, to which priority is claimed. To the extent permitted, such subject matter is incorporated by reference in its entirety generally and to the extent that further aspects and examples (such as experimental and / more-detailed embodiments) may be useful to supplement and / or clarify.

[0034] Accordingly, in the following description various specific details are set forth to describe specific examples presented herein. It should be appreciated that one or more other examples and / or variations of these examples may be practiced without all the specific details disclosed herein for a given example. In certain instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, same connotation and / or reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment (including those discussed in Appendices A-C of the above-identified U.S.Provisional Application) even though the combination is not explicitly shown or explicitly described as a combination.

[0035] FIGS. 1 and 2 are representative flow diagrams showing one or more structures transitioning into a semiconductor device, according to certain exemplary aspects of the present disclosure. Each of the structures shown in FIGs. 1 and 2 show a specific example of a set of stacked layers as characterized hereinabove.

[0036] More specifically, FIG. 1 shows one such stacked layer to include a thin poly crystalline diamond (PCD) layer 110, a thick layer 115, and a device layer 117 (e.g., as part of a substrate material) including one or more hot-spot regions 125. The thick layer 115 has a plurality of diamond vias 120, which may be elongated and arranged to provide respective thermal pathways, with diamond-via end portions shown to be thermally coupled to the PCD layer 110 for enabling thermal energy to flow from the hot-spot region(s) into and / or through the thick layer (and in some instances, through portions of the substrate in one or more directions away from the hot-spot region(s)). In the examples represented by FIG. 2 (similarly depicted in FIG. 1), this figure shows at least one such PCD layer 210 (110 of FIG. 1 or 610 of FIG 6), at least one thick layer 215 (115 of FIG. 1), at least one device layer 217 (117 of FIG. 1), a plurality of diamond vias 220 (120 of FIG. 1) and hot spot regions 225 (125 of FIG. 1).

[0037] FIG. 2 shows a more-specific example in which multiple sets of such stacked layers form part of tiers (sometimes scaffolding tiers) to be used in combination to dissipate thermal energy from the semiconductor device. In such tier-based examples, especially involving multiple tiers with each tier respectively having such a device layer stacked with the PCD layer, the semiconductor apparatus may include a very thin dielectric layer between the device region and the PCD layer. This dielectric layer may be, for example, material with at least material composition from among SiCh, AI2O3, SiC and SiNx. For instance, with the thin dielectric layer implemented as a SiNx-based layer (e.g., at least dominated by SiNx) between the device region and the PCD layer, the SiNx-based layer serves to protect the device layer as it is highly resistive to H-plasma etching, thereby protecting the hot spot (e.g., active) region from decomposition and physical damage, facilitating dissipation of heat when the semiconductor device is in use by enabling the heat to flow from the active region to the diamond region, acting as a buffer layer for smooth phonon transport through an interface between the device layer and the PCD layer, and facilitating a low thermal boundary resistance at the interface between the device layer and the PCD layer.

[0038] In related methodology involving formation of such a thin dielectric layer, exemplary methods according to the present disclosure may also include forming at least a portion of the semiconductor device, at a dielectric-type interface layer between diamond in the PCD layer and a surface of the device layer that is proximate a transistor channel region (e.g., of a GaN, Ga2O3, and / or InP type), wherein the diamond in the PCD layer is high-phase purity diamond with large grain sizes characterized by using only H2 and CF in their formation, and / or by maintaining a diamond growth temperature at a constant level andvarying plasma power and pressure to control etching, wherein the diamond growth temperature may be maintained at a level depending on a type of the transistor as follows: at about 700° C for a GaN type, at about 500° C for a Ga2CL type, and at about 350° C for an InP type.

[0039] In various examples, the PCD layer (110 or 210) may be implemented in different ways and / or with different dimensions, material composition(s), and the like. As examples, in certain specific implementations such as depicted in FIG. 1, the PCD layer may be at least predominantly composed of or formed by diamond particles (e.g., nanocrystalline particles with diameters from about 5 nm to 100 nm), and at least a predominant amount of the diamond particles may be linked and / or connected to one another, for example, through covalent bonds.[00401 The thick layer 115 or 215 may include diamond particles at least some of which are porously arranged, such as is shown in FIGs. 1, 2, 3 and 4, by using a porous arrangement of S1O2, SiCOH, and / or diamond (e.g., nanocrystalline and / or microcrystalline) particles grown within the porous arrangement. In specific instance, relatively large-size grained particles are implemented by microcrystalline diamond particles having diameters (or collectively an average diameter) from about 100-10,000 nm. Depending on the specific implementation, such apparatuses and / or methods involve forming the thick region so as to include the vias in an adjacently -located thick region, without the thick region altogether, or with such a thick region that does not include the vias. Experimentation, however, shows that use of the diamond vias in the thick region provides significant advantages including optimization of low thermal grain-to-grain boundary resistance and low thermal boundary' resistance.(004 l j In certain more-specific examples, the above-noted thick layer may include: one or more materials (e.g., having porously-arranged or not) PCD particles that surround at least a portion of at least one of the plurality of the thermal-pathway vias.

[0042] The device layer, as 117 or 217 of FIG. 1 or FIG. 2, is shown to include one or more hot spot regions, which are generally depicted to represent, as noted above, channels of transistors or semiconductor junctions (e.g., PN junctions) such as, but not limited to those which may be used in optical components such as lasers and laser-emitting diodes (LEDs).

[0043] FIGs. 3 and 4 show diagrams involving example methods and related structures of involving respective porous material in a so-called thick layer (as shown more generally in FIG. 1 or FIG. 2) of a tiered (or matrix-type) architecture, the approaches shown with seeding and without seeding. FIG. 3 includes, nearest the top, a pair of images in an upper portion andanother pair of images nearest the bottom of sheet. The pair of images in an upper portion are cross-sectional views, expanded at different magnitudes, to show nanocrystalline diamond growth in the pores of a porous Si material, without seeding of diamond particles. The pair of images in an lower portion are cross-sectional views, expanded at different magnitudes, to show microcrystalline diamond growth in the pores of a porous SiCh material, with seeding of diamond particles.

[0044] As shown in the depictions of FIG. 4, the semiconductor apparatus may include additional aspects or features. As shown in the images on the left side of FIG. 4, the semiconductor apparatus may further include an arrangement of porous and non-porous material 430 to form the thick layer (e.g., with diamond vias 435). As shown at the bottom right side of FIG. 4, the semiconductor apparatus may also include a heat sink 440 thermally coupled to the diamond vias through a substrate layer. In other examples, the heat sink may be secured to a side of the thick layer facing away from the PCD layer 445 shown as a layered plane of diamond along the top of the structure of FIG. 4.

[0045] FIG. 5 and 6 show different views of diamond vias, such as vias 120 of FIG. 1 or 220 of FIG. 2. In various experimental examples consistent with the depictions of FIGs. 5 and 6, a SiCh layer (1-50 pm thickness) was deposited onto a silicon substrate using plasma- enhanced (PE) CVD. Via holes (50 nm-10 pm) were patterned and then etched using reactive ion etching (RIE). The vias were subsequently filled with large-grain, nearly isotropic PCD through a low-temperature (<450°C) and / or a high temperature ranges up to 850°C plasma- assisted chemical vapor deposition technique, where selective diamond nucleation was employed to prevent void formation within the vias. To reduce the surface RMS roughness for subsequent fabrication steps, a PCD polishing process using an argon ion beam milling technique was developed. A second layer of SiCE (1-50 pm thickness) was deposited onto the polished PCD layer (100 nm-10 um) and via holes (50 nm to 10 pm diameter at the base) were etched by the same techniques as the first layer. A second layer of PCD was grown on top by MPCVD without an additional diamond nucleation layer until a monolithic PCD coverage across the via regions. Selective argon ion beam milling and RIE with an oxy en / argon plasma were applied alternately, which refined the diamond surface RMS roughness and achieved uniformity in PCD layer thickness (100 nm-10 um) across regions with varying fill factors.

[0046] Also in connection with such experimental examples consistent with the depictions of FIGs. 5 and 6, BEOL-compatible 2-tier diamond matrix scaffold structures were implementations in combination with Si O2 and on top of a Si wafer, for example, withdiamond being nucleated and grown conformally in the via holes with various aspect ratios (e.g., 1:4, 1 :2, 1: 1, and 2:1 (width:height)) to form the thermally -conductive vias. In one more-specific experimental process according to the present disclosure, the vias are formed by providing apertures (e.g., by etching to create trenches) in the dielectric material. In FIG. 5: the top left of FIG. 5 shows a side view of the dielectric layers (to form the thick layer) with several such trenches, an exploded side view of one such trench is shown at the lower left; an exploded top view, looking into the trenched aperture, is shown at the top right, and the lower right shows a top view an array of such trenched apertures.[004?] Consistent with these depictions of FIG. 5, one experimental process used for nucleation and growth of diamond vias. First via holes were created in an SiCh dielectric layer with opening diameters of 2, 5, and 10 pm and aheight of 3.5 and 7.5 pm. The density of the vias on the surface varied from 1 to 10% (via area / pitch2). Before starting the low- temperature growth, conformal diamond nucleation was formed in the via holes on the top surface. The grow th of the diamond was permitted to continue until the holes were filled with diamond and reached a planar surface on the top (445 of FIG. 4, 610 of FIG. 6, etc.). To enhance thermal benefit of the filled vias, the diamond growth is carefully controlled for filling the via holes conformally so as to avoid having the via holes being formed with voids (e.g., air gaps) within one or more of the filled vias; this may be realized, for example, by carefully balancing between mass transport limited and surface reaction limited to avoid reactant concentration limited chemical vapor deposition (CVD) at different stages of the growth in the via apertures.[004 1 In related experimentation according to the present disclosure, ultra-dense 3D architectures were implemented with via-based floor planning to identify via locations according to hotspot locations of different device (compute and / or logic) layers. Due to such floor planning, a misalignment (e.g., 1-10 pm) between the thermal vias of the two adjacent tiers may be unavoidable. In previously-known ILD (Inter-Layer Dielectric) processing, such misalignment can result in adverse thermal issues and trapping of heat in various areas of such dense 3D IC (integrated-circuit) chips. By implementing diamond matrix integrated ILD, according to examples of the present disclosure, the negative impact of via misalignment can be reduced by spreading the heat uniformly over the entire tier area and effectively directing the heat flow to the (bottom) heatsink located distal to the device layer(s).

[0049] FIG. 6 illustrates an example of how the heat (e.g., from one or more hot spot regions) can be spread uniformly in this manner, along a PCD layer 610, to effectively directthe heat flow to a heatsink 640. The image to the top left of FIG. 6 shows that the top portion of the diamond spreads the heat away from the hot spot, with the diamond-filled vias passing the heat away from the top diamond portion. The porous dielectric layer, surrounding the vias increases the efficiency of the overall heat removal while keeping the dielectric constant low (as discussed previously). The depiction in the top center of FIG. 6 is an exploded view of one of the vias from the image to the left, and the depiction at the bottom center of FIG. 6 is top-down view showing an array of the vias.

[0050] In further related experimental efforts according to the present disclosure, a process flow of a 2-tier diamond integrated ILD structure has been successfully implemented. In this case, the first-tier diamond layer was used as the nucleation layer for the second-tier diamond via and the top diamond layer. The diamond grows selectively in the via holes and fills up them first. After the diamond reaches the top of the via hole, the diamond grows isotropically in both lateral and vertical directions. This results in isotropic diamond grains and enhanced lateral thermal conductivity compared with conventional diamond growth techniques. For a 1% via fill, the average grain size exceeds 20 pm, corresponding to a thermal conductivity of -1800 W / m / K. Average grain size for 5% and 10% via fills are ~8 pm and -6 pm, respectively. The vertical growth rate is promoted in the via holes, and the lateral growth rate is enhanced on top of the trenches to provide a highly thermally conductive plane all over the tier. The result is a scaffold structure of diamond around the ILD layer to provide a sustainable solution to the thermal issue of 3D vertically integrated chips.

[0051] For the above-discussed specific experimental implementations, crystal quality was assessed and characterized. To assess diamond crystalline quality and residual stress Raman spectra of different spots on various via fill % were measured (e.g., showing sp3orbitals of diamond forming four C-C bonds in a tetrahedral configuration). This 3D structure of C-C bonds have a lattice vibration frequency -1332 cm . All the samples exhibited strong sp3peaks with a FWHM between 4.3 cm'1and 5.8 cm'1close to singlecrystal diamond (~4 cm'1). The diamond layer in the middle of the vias (not exactly on top of the vias) showed a narrower sp3peak, which can be due to the less grains disorientations, unlike the growth in the vias. An insignificant broad non-diamond carbon sign can be observed around 1450-1550 cm'1, which realizes a high phase purity diamond growth. A compressive residual stress was measured in the diamond layer for all samples due to the presence of sp3peak red shift. The sample without via shows a smaller compressive stress at 0.35 GPa, while including the via beneath the top diamond layer increases the stress value to0.9 GPa, and with maximum measured stress being lower than the delamination threshold in the diamond layer. Also, XRD patterns were measured on top of the diamond layer to identify the crystalline phases, and it was observed that the ultimate dominating diamond planes depend strongly on the growth rate in each direction (e.g., the lower the growth rate will result in the same plane (PCD layer) dominating)(0052] In certain more-specific and / or experimental proof-of-concept examples, successful outcomes have resulted from carrying out different combinations of specific steps used in forming the PCD layer and / or, as may be applicable, one or more of the tier-type structures the PCD layer. Consistent with such specific examples and successful outcomes, various implementations are characterized by one or more of the following steps or stages (aka aspect). One such aspect involves formation of the PCD layer proximate the device layer, with the PCD layer grown using a monolayer of diamond particles on a solvent-cleaned surface. In certain of these examples, the PCD layer has a thickness in a range from 100 nm to 5 pm, and the diamond particles have an average diameter in a variety of ranges (e.g., from 3 nm to 500 nm, from 100 nm to 1000 nm, and from 100 nm 10 pm), and the PCD layer may be formed to have a porousness density characterized as a function of a density of the diamond particles in the PCD layer.(00531 In more specific examples according to present disclosure, forming diamond in one or more such PCD layers may involve use of one or more of the following stages: (a) mixed-seeding stage in which a monolayer of diamond nanoparticles, having an average diameter of 3 nm - 100 nm, is deposited proximal a surface of the device layer, and in which one or more layers of microparticles, having an average diameter of 100 nm to 10 pm, are deposited after the monolayer of diamond nanoparticles is deposited; (b) a diamond linking stage, earned out after the mixed seeding stage, in which an amount of CH4 is temporarily increased (e.g., in a range of 4% - 10%), as a burst or temporary increase in application amount, for linking and interconnecting microparticles; and (c) facilitating, between diamond in the PCD layer and a surface of the device layer, low thermal grain-to-grain boundary resistance and low thermal boundary resistance to be in a range of 1 m2K / GW - 20 m2K / GW, and in some cases minimizing the thermal boundary resistance.

[0054] In certain specific embodiments, aspects involving formation of the abovediscussed PCD layer and / or the stack in which the PCD layer is arranged, may include a combination of stages of fabrication processing according to the present disclosure. These stages may be implemented alone but in many instances are used in combination of two or more of the following five stages (or sometimes “steps”).

[0055] First is the mixed seeding stage. In this stage, first a monolayer of diamond nanoparticles (average 3-100 nm in diameter) is deposited on the surface (after solvent cleaning) using polymer-assisted methods. Then, one or multiple layers of microparticles (average 100 nm to 10 pm in diameter) are deposited on top of nanoparticles to provide the porous section of the diamond layer. The pore density varies by modifying the microparticles’ density.

[0056] The second stage may be referred to as a diamond linking. After seeding, a short high CH4% (CH4 / H2 : 4-10%) that is sufficient to link all the microparticles and connect them for lower thermal grain-to-grain boundary resistance. In this stage, the processing causes a thin nanoparticle layer (e.g., the PCD layer 110 of FIG. 1) to cover the substrate very quickly after the start of the growth to prevent any damage and to provide extremely low thermal boundary resistance between diamond and the substrate or device channel (1-20 m2K / GW).

[0057] The third stage concerns the diamond vias (e.g., the PCD layer 120 of FIG. 1). Depending on the thermal properties requirements, the diamond vias are formed within the porous diamond layer, which consists of dense, large-grained polycrystalhne diamond. The area percentage of diamond vias may vary from 0.5% of the area to -100% of the area. In some specific implementations, the diamond vias may be replaced by, or used with, copper thermal vias.

[0058] The fourth stage concerns diamond heat spreading tiers (as shown in FIG. 2) and inter-tiers, referring to such tiers as may be stacked vertically and / or horizontally, and the number and arrangement(s) of the tiers depend on the cooling requirements of the design. In some examples, athin (100 nmto 5 pm) and highly thermally conductive (TC: 50-1300 W / m / K, or 500-1800 W / m / K) diamond layer is grown on top (e.g., a top diamond layer as 220’ of FIG. 2 or 620 of FIG. 6) of one or more of the tiers for efficient lateral heat spreading. This last step provides a highly conductive thermal path from the channel / j unctions to thermal vias (diamond or copper), transporting the heat away to the heat sink.

[0059] The fifth stage concerns multiple heat spreading tiers, with stages 1-4 being repeated for multi-tier system-on-chips such as monolithic heterogeneous 3D integrations to provide efficient cooling.

[0060] Also according to the present disclosure, using such manufacture-related methodology and types of semiconductor architecture and / or semiconductor-type apparatuses, circuit operations at high power and / or high frequency may be realized while maintaining relatively low levels of heat within the device layer(s) of such structures by useof the PCD and / or diamond vias being used to dissipate thermal energy from hot spot regions of the device layer(s). These benefits apply to a wide variety of semiconductor-based circuits includes those operating based on junctions and channels involving Si-based LDMOS, BIT, IGBT, GaN, power HEMT, SiC and / or Ga2Ch transistors, high-frequency devices (e.g., RF GaN HEMTs, InP HBTs, and GaAs based FETs), and Si-based chips (e.g., MOSFETs, insulated gate-bipolar transistors (IGBTs), gate turn-off (GTOs), and sihcon-controlled rectifiers). As examples, such semiconductor-based circuits may be used in and to advantage a wide range of applications including but not limited to computing modules, memories, data centers, high-end wireless (e.g., 5G and 6G) communications, airborne radars, and automotive radars. Also, examples and aspects of the present disclosure may be applied to many different types of processes and devices including certain mentioned in Appendix A and / or Appendix B of the above-identified U.S. Provisional Application.

[0061] In the above and other contexts, example embodiment and aspects of the present disclosure have been successfully demonstrated in more-detailed and / or experimental efforts and example embodiments to realize numerous outcomes. As examples, such more specific / experimental efforts have enabled significant improvements for increasing power density in semiconductor devices by mitigating channel self-heating; consequently, premature reduced device lifetime and eventually device or system failure are avoided.

[0062] Also, such efforts have been able to realize integration of diamond into semiconductor devices to advantage not only thermal management purposes, but also to manage the temperature and the time duration, as well as the growth rate, of the diamond during manufacture. During manufacture, it is vital not to damage the semiconductor device (e.g., wafer) physically and / or in terms of its ability to perform according to specifications (e.g., breakdown voltage, output current, cut-off frequency, maximum frequency, output power, power added efficiency, etc.) after or during diamond integration. Related aspects benefited by examples of the present disclosure are minimizing the thermal boundary resistance between the diamond and the device channel along with maximizing diamond thermal conductivity. These important aspects, if not addressed, may apply rigorous restrictions to the effective growth window for high-quality diamond. For example, in accordance with certain experiments, since the monocrystalline diamond has a dielectric constant ~5.7, using this material as part of back-end-of-line interlayer dielectrics and passivation layers can assert parasitic capacitance which degrades high-frequency performance in system-on-chips and power amplifiers. Further, use of a porous diamond layer, in such layered stacks according to examples of the present disclosure, has beeneffective in such experimental efforts to reduce the dielectric constant while keeping the thermal conductivity greater than 100-times larger than currently commercially-available porous SiCOH in the foundry process for such devices (e.g., with the dielectric constant of the diamond layer controlled in a range between 1 to 5, and for example in one instance with low thermal boundary resistance in the range of 1.9 m2K / GW with Si).[006 A device layer, such as 117 or 217 of FIG. 1 or FIG. 2, may be implemented in structures other than depicted in FIGs. 1 and / or 2, but still operative to manifest one or more hot spot regions. These regions (depicted generally in FIGs. 1 and 2) may represent transistors channels, areas relatively distant from such channels but within the device layer substrate that is observed or suspected as at least occasionally developing high temperatures (similar to that of transistors channels), and / or semiconductor junctions (e.g., PN junctions) such as those used in optical components. Among many, such optical components may correspond to one or more of the following: lasers, laser-emitting diodes (LEDs), and other optical components having phonon / photon-active semiconductor junctions. Consistent herewith and according to certain specific example aspects, implementations of the present disclosure may be used in overcoming or mitigating certain adverse effects such as wavelength shift in the emission wavelength for III-V and III-Nitnde based micro-LEDs and / or lasers producing Red-Green-Blue (RGB) matrix or standalone, for any of many different types of digital displays or for optical communication. If such effects are not addressed, the reliability and functionality of such devices may be compromised such as by resulting in failure in the functioning of a display and / or communication link. In RGB-type display technologies, particularly Red LED is often grown on III-V or high In-composition III-Nitride materials. Being a narrow bandgap type of semiconductor, under operation at high drive current the thermal bottle neck is formidable. With any device transfer (pick and place, layer transfer, mass transfer and integration) the quality of the materials degrades. This means the LED or lasers containing semiconductor layers are more prone to defects. With an increase in the drive current, the junction temperature of the device rises and causes degradation in the performance. The heat generated in LEDs and laser devices impacts the operation of co-located electronics and, accordingly, the benefit of aspects of the present disclosure can be enormous.0064 Diamond may be used as a heat sink (FIG. 6) in various types of exemplary devices. In certain specific devices such as those involving micro-LED architecture, according to the present disclosure, heat removal from such devices is done precisely from the hot spot in order to prevent (or significantly mitigate) any wavelength shifts. Consistent herewith, one example technique according to the present disclosure is directed to growing poly crystalline and isotropic diamond in a low- or high-temperature (e.g., from 300 to 800°C), close to the RGB containing micro-LED layers so as to prevent the wavelength shifts in Red (which is most susceptible or vulnerable), followed by yellow, green, and blue. This follows as the material bandgap increases from Red to Blue, and the narrower Red bandgap is more vulnerable to thermal bottleneck.

[0065] According to examples of the present disclosure, placing the diamond close to the hot spot has been found to be the most effective method of heat removal, and low thermal budget growth permits this attribute to be realized. Particular experimental examples according to the present disclosure, are directed to the growth and / or deposition of poly crystalline diamond (with thermal conductivities ranging from 50W / m / K to 1800W / m / k) on III-V and III-Nitrides. Thermal boundary resistance in such implementations can be set and / or tested based on various factors involving structural implementation and diamond growth details, such as diamond growth parameters (temperatures, control in stages of growth, power and pressure, etc.) and in aspects of the thermal structure (or thermal field plate) realized from such growth (e.g., anisotropy ratio being close to unity and / or more isotropic than columnar).

[0066] Also according to certain exemplary aspects of the present disclosure, FIGs. 7A and 7B, show a side view (FIG. 7A) of multi-tiered architecture of a semiconductor apparatus and a SEM micrograph (FIG. 7B) of a diamond scaffolding which can be used in such an architecture. In these specific experimental examples, it has been surprisingly demonstrated that: diamond has a thermal conductivity >5000x larger than previously -known interlayer dielectric and 3-5x larger than copper; diamond replaces part of the interlayer dielectric to provide a lateral heat spreader; and diamond vias can be implemented to provide a highly thermally conductive path to the heat sink.

[0067] FIGs. 8A-8C, also according to certain exemplary aspects of the present disclosure, show beneficial aspects of diamond and diamond scaffolding with FIG. 8A showing maximum and average temperatures without (top) and with diamond (bottom) with heat being generated at the top, FIG. 8B showing a corresponding two-tiered architecture of a semiconductor apparatus (and similar that shown in FIG. 2), and FIG. 8C showing maximumand average temperatures without diamond scaffolding (top) and with diamond scaffolding (bottom) with heat being generated at the top.

[0068] While the present disclosure discusses particular experimental examples, the approaches discussed herein apply to implementing diamond growth for integration with a variety of different types of electronic and opto-electronic devices. This is because such diamond growth, according to the present disclosure, can be integrated on metals, dielectric, trenches, and most any geometry. For example, in connection with one particular experimental example according to the present disclosure, thin-film poly crystalline diamond is grown so as to provide a thermally -efficient mechanism for passing heat away from the hot spot(s) of the devices and also to be bendable. With these attributes, such a thermally efficient mechanism can be applied and effectively used on a variety of device surfaces, and within devices, that are rigid, flexible or may be somewhat both rigid and flexible (e.g., intended to be rigid but susceptible to occasional being flexed or stressed as though flexed).

[0069] In other examples of the present disclosure, low-temperature diamond is grown and / or implemented as part of such a laser or LED-type device, with advantages thereof including manufacturing steps being compatible with currently-available technology, foundry processes, and / or ILD technology (relating to injection laser diode technology), integration of the diamond as close as 2 nm to 50 nm to the hot spot, and the ability to grow the diamond on any substrate such as those used with rigid and flexible electronics. In connection with such optical devices, the above-type of PCD layers may be grown directly over or on such a structure using low-thermal budget diamond growth at temperatures below 400° C (e.g., 300- 400° C). With such a laser or LED-type device, the PCD may be grown against (e.g., directly or indirectly via a SiN buffer layer) on a cap and window layer, with a gain layer and then a mirror layer being below.

[0070] Various experimental examples, some of which are discussed hereinbelow (along with exemplary material methods), have demonstrated that the above-characterized aspects, structures and methodologies may be used in one or more semiconductive devices to form semiconductor circuits and devices. As examples, the above-disclosed scaffolding architecture for 3D dense chips provides exceptional thermal management due to its excellent thermal conductivity (e.g., using diamond thermal vias). Its low thermal boundary resistance with Si and dielectrics (such as S1O2) ensures minimal thermal bottlenecks, enhancing the 3D chip's overall thermal management and reliability. Also, such specific devices have been successfully demonstrated with BEOL-compatible 2-tier diamond matrix scaffold structures in combination with SiCh and on top of a Si wafer (e.g., with diamond being nucleated andgrown conformally in the via holes with various aspect ratios to form the thermally - conductive vias. A relatively low residual stress of 0.35-0.9 GPa and an FWHM as low as 4.3 cm-1were measured using Raman spectroscopy. A plane (over at least most if not all the tier) was measured as the dominating plane after the growth on top, while the plane was the dominating plane inside the trenches mid-growth. This highly thermally conductive diamond matrix (thermal conductivity between 500-1500 W / m / K) can be used not only for Si technology but also for GaN and GasCh technologies to push the boundaries of output power by lowering the junction / channel temperature.[00? I ] Certain of these examples have implemented 3D thermal scaffolding, such as shown to the right side of FIG. 2 but in three dimensions, as a cooling technique particularly targeting ultra-dense 3D ICs (e.g., < 100 nm pitch 3D connections) with high-power compute elements in the device layers of the 3D stack. According to such specific and / or experimental examples according to the present disclosure, the fabricated 3D thermal scaffolding uses BEOL-compatible polycrystalline diamond to form thermal pathways to the heatsink using both a 3D heat spreader layer and thermal vias, which in certain applications is an important combination for highly effective 3D heat extraction. These structures — including the first BEOL-compatible, void-free diamond vias — may be characterized using a 3D thermal platform with heaters simulated to emulate thermal hotspots in ultra-dense 3D ICs. In connection with these efforts, >10* reduction has been achieved in temperature rise for a wide range of heater sizes. Detailed physical design and 3D thermal simulations in COMSOL matching experiment indicate that, with advanced heatsinks, such scaffolding can effectively stack at least 15 ultra-dense 3D Al accelerators (> 1.3 kW / cm2) with peak temperature below 125°C at <10% footprint increase. For example, one such effort involved a COMSOL model (a simulation tool to model and analyze multi-physical phenomena) used to match experiments that predicted such 3D thermal scaffolding structures can cool 15 ultra-dense 3D stacked Al accelerator tiers below 125°C peak temperature at 9.4% footprint increase. Using this model, in certain experiments the PCD vias of the present disclosure show larger cooling benefits than copper vias and in some applications (e.g., for delivering power or signals) these PCD vias were used in combination with metal-type vias to improve 3D IC performance.

[0072] The diamond's film thickness and grain structure were measured using crosssection and plan-view imaging by scanning electron microscopy (SEM) on an FEI Nova NanoSEM 430. A focused Ion Beam SEM (FEI Helios NanoLab 600i DualBeam) was used to prepare and image the cross-section of the two-tier diamond via structure!

[0073] Additionally, atomic vibrational frequencies in the CVD coating were analyzed using a Horiba Labram HR Evolution Raman System, which can relate these frequencies to the strength of inter-atomic bonds, thereby identifying different carbon bond types in CVD diamond. A Green laser (argon ion laser at 532 nm) operated at 4 and 5 mW for all measurements, with the shift in the main diamond bandwidth (at 1332 cm’1) used to assess the degree of stress in the thin coating. Residual stresses in the films were also determined using the sp3 peak shift measurement in the Raman spectra of the diamond layer.1 074] The skilled artisan would also recognize various terminology as used in the present disclosure by way of their plain meaning. As examples, the Specification may describe and / or illustrates aspects useful for implementing the examples by way of various semiconductor materials / circuits which may be illustrated as or using terms such as layers, blocks, modules, device, system, unit, controller, and / or other circuit-type depictions. Such semiconductor and / or semiconductive materials (including portions of semiconductor structure) and circuit elements and / or related circuitry may be used together with other elements to exemplify' how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It would also be appreciated that terms to exemplify orientation, such as upper / lower, left / right, top / bottom and above / below, may be used herein to refer to relative positions of elements as shown in the figures. It should be understood that the terminology' is used for notational convenience only and that in actual use the disclosed structures may be oriented different from the orientation shown in the figures. Thus, the terms should not be construed in a limiting manner.Based upon the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, methods as exemplified in the Figures may involve steps carried out in various orders, with one or more aspects of the embodiments herein retained, or may involve fewer or more steps. Such modifications do not depart from the true spirit and scope of various aspects of the disclosure.

Claims

What is Claimed:

1. An apparatus comprising: a semiconductor device having a set of one or more scaffolding tiers, each tier of the set of one or more scaffolding tiers including a stack of material layers (“the stacked layers”), the stacked layers including a device layer in which at least one hot-spot region is located, a thin poly crystalline diamond layer (“the PCD layer”) that is thermally coupled to said at least one hot-spot region of the device layer, and a thick thermally-conductive material layer (“the thick layer”) having a plurality of diamond vias to provide a plurality of respective thermal pathways, with diamond-via end portions that are thermally coupled to the PCD layer.

2. The apparatus of claim 1, wherein the PCD layer is at least predominantly composed of or formed by nanocry stalline and / or microcrystalline diamond particles, and during use of the semiconductor device, thermal energy is to flow in a direction from said at least one hotspot region into and / or through the thick layer and into the plurality of thermal-pathway vias, and wherein the one or more device hot spots channels correspond to or include at least one of: device active regions; and device junctions.

3. The apparatus of claim 1, wherein the PCD layer includes nanocrystalline and / or microcrystalline diamond particles, at least a predominant amount of which are linked and / or connected to one another, and the thick layer includes diamond particles at least some of which are porously arranged.

4. The apparatus of claim 1, wherein the thick layer includes: a porous arrangement of SiCh and / or SiCOH; and microcrystalline and / or microcrystalline diamond is grown within the porous arrangement.

5. The apparatus of claim 1, further including a heat sink thermally coupled and secured to a side of the thick layer facing away from the PCD layer.

6. The apparatus of claim 1, wherein the set of one or more scaffolding tiers includes between two and twenty tiers.

7. The apparatus of claim 1, further including a SiNx-based layer, between the device layer and the PCD layer, that is highly resistive to H-plasma etching and is to protect the active region from decomposition and physical damage, facilitate dissipation of heat, when the semiconductor device is in use, from the active region to the diamond region, act as a buffer layer for smooth phonon transport through an interface between the device layer and the PCD layer, and facilitate a low thermal boundary resistance, wherein the thick layer includes an arrangement of particles, a predominant portion of which are porously arranged.

8. The apparatus of claim 1, wherein the thick layer includes: one or more materials having porously-arranged PCD particles that surround at least a portion of at least one of the plurality of thermal-pathway vias, and / or a porous arrangement of relatively large-grained particles, wherein the diameter sizing of the relatively large-grained PCD particles corresponds to an average diameter in a range from 100 nm -10000 nm.

9. The apparatus of claim 1, wherein the thick layer includes one or more dielectric-type materials that surround at least a portion of at least one of the plurality of thermal-pathway vias, wherein the one or more dielectric-type materials are from among materials including: SiCh, SiCOH, diamond, and one or materials defining at least one air gap as the dielectric.

10. The apparatus of claim 1, further including a dielectric layer between the device region and the PCD layer, wherein the dielectric layer includes at least one from among SiCh. AI2O3, SiC and SiNx, and the thick layer includes one or more dielectric materials in a porous arrangement that surrounds at least a portion of at least one of the plurality of thermalpathway vias.

11. A method comprising: forming or operating a semiconductor device having a set of one or more scaffolding tiers, each tier of the set of one or more scaffolding tiers including a stack of material layers (“the stacked layers”), the stacked layers includinga device layer in which at least one hot-spot region is located, a thin poly crystalline diamond layer (“the PCD layer”), located proximal the device layer, including nanocrystalline diamond particles (‘the diamond particles”) of which at least a predominant amount are linked and / or connected to one another, and a thick layer, stacked with the PCD layer between the device layer and the thick layer, including a plurality' of diamond-filled thermal-pathway vias through which thermal energy is to flow in a direction from said at least one hot-spot region into and / or through the thick layer.

12. The method of claim 11, further including growing the PCD layer in part by temporary increasing use of CH4 around the diamond particles and, in response, causing at least a predominant amount of particles, within the PCD layer, to be linked and connected in the PCD layer after seeding the diamond particles, wherein the PCD layer is grown through use of mixed seeding of the diamond particles, and the step of causing diamond particles, in the PCD layer, to be linked and connected, is to minimize a thermal grain-to-grain boundary resistance in a range of 1-20 m2K / GW.

13. The method of claim 11, wherein said forming the PCD layer involves deposition or growth of a monolayer of diamond particles on a solvent-cleaned surface, the diamond particles having an average diameter in a range from 100 nm to 10 pm, wherein nanocrystalline and / or microcrystalline diamond particles have an average diameter in a range from 3 nm to 500 nm, and the PCD layer is formed to have a porousness density characterized as a function of a density of the diamond particles in the PCD layer, and the PCD layer has a thickness in a range from 100 nm to 5 pm.

14. The method of claim 11, further including causing at least a predominant amount of particles in the PCD layer to be linked and connected by increased an amount of CH4 around the diamond particles to facilitate maximization of said at least a predominant amount of microparticles in the PCD layer to be linked and connected, thereby optimizing low thermal grain-to-grain boundary resistance and a low thermal boundary resistance proximal to the one or more hot-spot regions.

15. The method of claim 11, wherein at least a portion of the thick layer, including at least one of the plurality of diamond-filled thermal-pathway vias, provides at least one highlyconductive thermal path characterized as having an average thermal conductivity in a range from 50-2200 W / m / K.

16. The method of claim 11, including forming another one of the set of tiers by: repeating in sequence each of the steps of claim 11, wherein the plurality of tiers are formed to provide respective conductive thermal paths away from the one or more hot spot regions, as one or more channel and / or junction regions, to a heat sink.

17. The method of claim 11, wherein diamond particles, in the PCD layer, are caused to be linked and connected, for facilitating or optimizing low thermal grain-to-grain boundary resistance near the one of more hot-spot regions, by growing the diamond particles using a temporary burst or increased use of CP that involves application of a percent of CH4 during a growth stage of the PCD particles as being porous, wherein the percent of CH4, in a range from 4-10% greater, is an increased level of CH4 in an application involving use of CH4.

18. The method of claim 11, further including: forming diamond in at least one of the PCD layer proximal a surface of the device layer and the other layer, by use of multiple stages from among: (a) mixed-seeding stage in which a monolayer of diamond nanoparticles, having an average diameter of 3 nm - 100 nm, is deposited proximal the surface of the device layer, and in which one or more layers of microparticles, having an average diameter of 100 nm to 10 pm, are deposited after the monolayer of diamond nanoparticles is deposited; (b) a diamond linking stage, carried out after the mixed seeding stage, in which an amount of CPU is temporarily increased in a range of 4% - 10%, as a burst or temporary increase in application amount, for linking and interconnecting microparticles; and (c) facilitating, between diamond in the PCD layer and a surface of the device layer, low thermal grain-to- grain boundary resistance and low thermal boundary resistance to be in a range of 1 m2K / GW - 20 m2K / GW.

19. The method of claim 11, further including: forming a dielectric-type interface layer between diamond in the PCD layer and a surface of the device layer that is proximate a channel region of a transistor of a type including at least one of GaN, Ga2O3, and InP, wherein the diamond in the PCD layer is high-phase purity diamond with large grain sizes characterized by using only H2 and CPU in their formation.

20. The method of claim 11, further including: forming a dielectric-type layer at an interface between diamond in the PCD layer and a surface of the device layer that is proximate a channel region of a transistor, by maintaining a diamond growth temperature at a constant level and varying plasma power and pressure to control etching.

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