An integrated pixel cell for a display device and / or optical communication device

Abstract

An integrated pixel cell for a display device and / or optical communication device, an LED array, and method of fabricating an integrated pixel cell for a display device and / or optical communication device. The integrated pixel cell for a display device and / or optical communication device comprises a light emitting element; a photo detecting element; CMOS circuitry for the light emitting element and the photo detecting element, wherein the CMOS circuitry, the light emitting element and the photo detecting element are provided on a same substrate of the integrated pixel cell; wherein the photo detecting element is configured to detect a part of radiated light from the light emitting element; and wherein output voltages or currents of the light emitting element and the light detecting element are detectable by a calibration circuit to calibrate the light emitting element's current or light intensity.

Description

[0001] AN INTEGRATED PIXEL CELL FOR A DISPLAY DEVICE AND / OR OPTICAL COMMUNICATION DEVICE

[0002] CROSS-REFERENCE TO RELATED APPLICATION

[0003] This application claims the benefit of United States of America Provisional Patent Application No. 63 / 602,700 filed on November 27, 2023, the content of which is incorporated herein by reference in its entirety for all purposes.

[0004] FIELD OF INVENTION

[0005] The present invention relates broadly to an integrated pixel cell for a display device and / or optical communication device, to an array comprising a plurality of integrated pixel cells, and to a method of fabricating an integrated pixel cell for a display device and / or optical communication device.

[0006] BACKGROUND

[0007] Any mention and / or discussion of prior art throughout the specification should not be considered, in any way, as an admission that this prior art is well known or forms part of common general knowledge in the field.

[0008] The next-generation micro-display technology spans from applications in a large-size TV screen with a low pixel density and high subpixel pitch to an AR (augmented reality) microdisplay application with a high pixel density and low subpixel pitch.

[0009] Since a heterogeneous wafer bonding technology has been developed, silicon-based microLED (light emitting device) displays are suitable for all the above applications to handle a brightness non-uniformity issue of an LED array using CMOS circuits. However, brightness calibration requires sophisticated circuit design to address non-uniformity issues, resulting in large circuit areas and power consumption. Typically, either LED current sensing or voltage sensing circuitry needs to be designed to measure LED brightness indirectly. The indirectly measured current or voltage cannot accurately represent actual LED brightness due to LED non-uniformity in an array. Furthermore, as the pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging.

[0010] Embodiments of the present invention seek to address at least one of the above problems. SUMMARY

[0011] In accordance with a first aspect of the present invention, there is provided an integrated pixel cell for a display device and / or optical communication device, comprising a light emitting element; a photo detecting element;

[0012] CMOS circuitry for the light emitting element and the photo detecting element, wherein the CMOS circuitry, the light emitting element and the photo detecting element are provided on a same substrate of the integrated pixel cell; wherein the photo detecting element is configured to detect a part of radiated light from the light emitting element; and wherein output voltages or currents of the light emitting element and the light detecting element are detectable by a calibration circuit to calibrate the light emitting element’s current or light intensity.

[0013] In accordance with a second aspect of the present invention, there is provided an LED array comprising a plurality of integrated pixel cells of the first aspect, wherein the calibration circuit is configured to perform calibration for an individual one or a group of the integrated pixel cells.

[0014] In accordance with a third aspect of the present invention, there is provided a method of fabricating an integrated pixel cell for a display device and / or optical communication device, comprising the steps of providing a light emitting element; providing a photo detecting element; providing CMOS circuitry for the light emitting element and the photo detecting element, wherein the CMOS circuitry, the light emitting element and the photo detecting element are provided on a same substrate of the integrated pixel cell; configuring the photo detecting element to detect a part of radiated light from the light emitting element; and detecting output voltages or currents of the light emitting element and the light detecting element by a calibration circuit to calibrate the light emitting element’s current or light intensity. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:

[0016] FIG. 1 A shows an existing monolithic integration of III-V LED with Si CMOS of the prior art, specifically a basic LED driver and its layout.

[0017] FIG. IB shows an existing monolithic integration of III-V LED with Si CMOS of the prior art, specifically a simplified layout of the integrated LED driver and its vertical structure

[0018] FIG. 2A shows an example of an existing LED array with an encoder, specifically a schematic view.

[0019] FIG. 2B shows an example of an existing LED array with an encoder, specifically a simplified layout (top view).

[0020] FIG. 3 A shows an LED-PD paired pixel cell according to an example embodiment, specifically a schematic view.

[0021] FIG. 3B shows an LED-PD paired pixel cell of FIG. 3 A, specifically a simplified layout (top view).

[0022] FIG. 3C shows an LED-PD paired pixel cell according to an example embodiment, specifically a schematic view.

[0023] FIG. 3D shows an LED-PD paired pixel cell of FIG. 3C, specifically a simplified layout (top view).

[0024] FIG. 4A shows an LED-PD paired pixel cell according to an example embodiment, specifically a simplified layout (top view).

[0025] FIG. 4B shows an LED-PD paired pixel cell of FIG. 4A, specifically a vertical structure schematic view.

[0026] FIG. 4C shows an LED-PD paired pixel cell according to an example embodiment, specifically a simplified layout (top view).

[0027] FIG. 4D shows an LED-PD paired pixel cell of FIG. 4C, specifically a vertical structure schematic view.

[0028] FIG. 5 A shows an LED-PD paired pixel cell according to an example embodiment, specifically a schematic view illustrating ON / OFF operation.

[0029] FIG. 5B shows an LED-PD paired pixel cell of Fig. 5 A, specifically a simplified layout (top view). FIG. 5C shows part of the LED-PD paired pixel cell of Fig. 5A, specifically a schematic diagram illustrating operation of a calibration block of the LED-PD paired pixel cell.

[0030] FIG. 6 shows an LED-PD paired pixel cell array according to an example embodiment, specifically a simplified layout (top view).

[0031] FIG. 7A shows an LED-PD paired pixel cell array with a common monitoring circuit according to an example embodiment, specifically a schematic view.

[0032] FIG. 7B shows an LED-PD paired pixel cell array of FIG. 7 A , specifically a simplified layout (top view).

[0033] FIG. 8A shows a schematic view of an LED-PD paired pixel cell according to an example embodiment and a simplified layout (top view) of an LED-PD paired pixel cell array, both with alternative LED-PD paired cells, namely LED-CMOS configuration, according to example embodiments.

[0034] FIG. 8B shows a schematic view of an LED-PD paired pixel cell according to an example embodiment and a simplified layout (top view) of an LED-PD paired pixel cell array, both with CMOS-LED-CMOS configuration, according to example embodiments.

[0035] FIG. 9 shows a basic example of an LED pixel integrated with CMOS digital circuitry 900 for use in an example embodiment.

[0036] FIG. 10 shows an example schematic of an LED-PD paired pixel cell 1000 integrated with CMOS analog control / calibration circuits, according to an example embodiment.

[0037] FIG. 11 shows a (simplified) layout of an LED-PD paired pixel cell 1100 with CMOS Analog Circuits, according to an example embodiment.

[0038] FIG. 12 shows a (simplified) layout of an LED-PD paired pixel cell 1200 with CMOS Analog Circuits, according to an example embodiment.

[0039] FIG. 13 shows a flow chart illustrating a method of fabricating an integrated pixel cell for a display device and / or optical communication device, according to an example embodiment.

[0040] DETAILED DESCRIPTION

[0041] With the proliferation of smart devices in mobile, AR / VR (virtual reality), and large screen applications, digital display technology based on micro-LEDs is becoming more attractive and popular in the early stage of commercialization.

[0042] In recent years, the transfer technology by which the pixelized LEDs are integrated with Silicon CMOS circuits has been developed. FIG. 1 A shows a schematic diagram of the simplest form of an existing integrated LED pixel 100 consisting of a III-V LED 102 and a CMOS driver 104, with its layout shown in FIG. IB. As shown in FIG. IB, the III-V LED 102 and the CMOS driver 104 are vertically integrated on a Si substrate 106 and connected together using metal plugs 108 and CMOS BEOL metal stack 110.

[0043] FIGs 2 A and B. 2 show a schematic diagram and a simplified layout (top view) an example of an existing LED array 200 implementation with an encoder 202 and the integrated pixels 204- 207, each as shown in FIGs. 1 A and IB.

[0044] However, such existing LED array implementation requires sophisticated circuit design to address brightness non-uniformity issues, leading to large circuit areas and power consumption. Furthermore, as the pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging.

[0045] Embodiments of the present invention provide a monolithically integrated LED - PD (photodetection element) paired pixel cell enabling direct brightness measurements for calibration of brightness non-uniformity of LED arrays, for micro-LED display applications. The integrated LED-PD paired pixel cell according to example embodiments and arrays of LED-PD paired pixel cells according to example embodiments advantageously also reduce the circuit complexity and thus make a pixel size smaller with less power consumption, for example for realizing future micro-displays with high pixel density. In various example embodiments, a basic pixel structure / topology and its variations for LED array implementation are also provided. The use of an integrated LED-PD paired pixel cell according to example embodiments advantageously leads to simple calibration circuitry and arrays, small pixel size for high pixel density, and low power consumption.

[0046] In example embodiment, having a nearby integrated PD, the PD inherently generates current proportional to actual LED light intensity or brightness and thus can drastically simplify sensing processes / circuitry, as well as provide more accurate current or voltage that represents actual LED brightness, rather than current from a sensing circuit to indirectly measures LED brightness.

[0047] A schematic diagram of an integrated LED-PD paired pixel cell 300 according to an example embodiment and its simplified layout (top view) are shown in FIGs. 3A and 3B, respectively. The LED-PD paired pixel cell 300 in this example embodiments includes an III-V LED 302, a III-V PD 304 and related CMOS circuitry 306 implemented on the same substrate 307, in the example embodiment Si, where the PD 304 can detect a part of the radiated light from the paired LED 302. The output voltages or currents of PD 304 / LED 302 can be used to calibrate the LED 302 current or light intensity. In this example embodiment, the CMOS circuitry 306 is provided inside the LED-PD paired pixel cell 300 and can directly monitor the output of PD 304 / LED 302 (Voutl~2) and generate the control voltage (Vin3) to calibrate the LED light intensity, internally.

[0048] In the example embodiment shown in FIGs. 3A and 3B, PD 304 is shown to be formed in the III-V layer(s) (i.e. in the form of a III-V photodetector / photodiode). However, in another example embodiment shown in FIGs. 3C and 3D, an LED-PD paired pixel cell 320 includes an III-V LED 322, a PD 324 and related CMOS circuitry 326 implemented on the same substrate 327, in the example embodiment Si, where the PD 324 is formed in the CMOS layer(s), here indicated as part of the CMOS circuitry 326 (i.e. in the form of a CMOS photodetector / photodiode, or a CMOS phototransistor). In yet another example embodiment, PDs may be formed in both the III-V layer(s) (i.e. in the form of a III-V photodetector / photodiode) and the CMOS layer(s) (i.e. CMOS photodetector / photodiode, or CMOS phototransistor), for example if one wants to provide two (or more) different Transmitter (Tx) -> Receiver (Rx) pathways.

[0049] It is noted that in other example embodiments, an external micro-processor or circuitry, or a combination of CMOS circuitry provided inside the LED-PD paired pixel cell and an external micro-processor or circuitry, can monitor the output of PD / LED and generate a control voltage to adjust the current of the LED.

[0050] A simplified layout (top view) of an integrated LED-PD paired pixel cell 400 includes an III- V LED 404, a PD 406 and related CMOS circuitry 407 implemented on the same substrate 409, in the example embodiment Si, according to another example embodiment and its vertical structure are shown in FIGs. 4A and 4B, respectively. A CMOS BEOL metal structure / pattem 402 inserted between LED 404 and PD 406 advantageously increases the reflection of light into PD 406, which improves the sensitivity of PD 406. It is noted that while light is omnidirectional, the integrated LED 404 and PD 406 each have only one side 408, 410 open to radiate or receive light, in this example embodiment. Thus, the inserted CMOS BEOL metal structure / pattern 402 depending upon the remaining III-V and CMOS layout patterns can help increase the amount of light received in PD 406, as depicted in FIG. 4B. Preferably, the metal structure / pattern 402 should be simple following the law of reflection (i.e. the angle of reflection is equal to the angle of incidence). In addition, in example embodiments, the following parameters are preferably also considered: 1) There is typically a size limit on the metal structure (according to foundry’s design rules). For example, if the LED and / or PD sizes are big, the metal structure / pattem 402 can be split into a few pieces (e.g. an array of squares). 2) If high-speed CMOS and III-V circuitry is placed near LED and / or PD, the metal structure / pattern 402 should preferably not be close to that circuitry to avoid adding parasitic capacitance and negative effects to high speed circuits, while still effectively cover the LED- PD pair with the closest vicinity for more reflected light into the PD.

[0051] In the example embodiment shown in FIGs. 4A and 4B, PD 404 is shown to be formed in the III-V layer(s) (i.e. in the form of a III-V photodetector / photodiode). However, in another example embodiment shown in FIGs. 4C and 4D, an LED-PD paired pixel cell 420 includes an III-V LED 424, a PD 426 and related CMOS circuitry 426 implemented on the same substrate 427, in the example embodiment Si, where the PD 424 is formed in the CMOS layer(s), here indicated as part of the CMOS circuitry 426 (i.e. in the form of a CMOS photodetector / photodiode, or CMOS phototransistor). Again, a CMOS BEOL metal structure / pattern 422 is inserted between LED 424 and PD 426 advantageously increases the reflection of light into PD 406, which improves the sensitivity of PD 406. In yet another example embodiment, PDs may be formed in both the III-V layer(s) (i.e. in the form of a III-V photodetector / photodiode) and the CMOS layer(s) (i.e. Si CMOS photodetectors / photodiodes, or CMOS phototransistors), for example if one want to provide two (or more) different Transmitter (Tx) -> Receiver (Rx) pathways.

[0052] In the following description, example embodiments with the PD formed in the III-V layer(s) (i.e. in the form of a III-V photodetector / photodiode) will be described, however, each of those example embodiments may alternatively or additionally have the / a PD formed in the CMOS layer(s) (i.e. Si CMOS photodetectors / photodiodes, or CMOS phototransistors)

[0053] A schematic diagram of an integrated LED-PD paired pixel cell 500 according to another example embodiment and its simplified layout (top view) are shown in FIGs. 5A and 5B, respectively. An LED 502 and a PD 504 for each pixel can be selectively turned on and off by means of control signals (e.g. Vinl and Vin2 in the schematic diagram in FIG. 5A). When Vinl(or Vin2) is logic ‘O’, both terminals of the LED 502 (or PD 504) are grounded (i.e. no bias) and its driver transistor 508 (or 510), which are part of the Si CMOS circuit 506, is also turned off. FIG. 5C shows a schematic diagram illustrating the calibration block 512 implemented using internal analog circuitry in the Si CMOS circuit 506 (FIG. 5B) in this example embodiment, and / or an external microprocessor in different example embodiments, for sensing outputs from both LED 502 (FIG. 5A and 5B), i.e. Voutl, and PD 504 (FIG. 5A and 5B), i.e. Vout2, which are utilized to generate the LED brightness calibration signal (i.e. Vin3).

[0054] When implementing a digital display using micro-LED technology, designers typically face two challenges - form-factor and power consumption - especially in mobile and wearable devices.

[0055] FIG. 6 shows a simplified layout (top view) of an LED array 600 according to an example embodiment, comprising LED-PD paired cells e.g. 601, 602 according to example embodiments as described above. The LED array 600 can perform automatic calibration for an individual or for a group of LED-PD pixels e.g. 601, 602 with help of CMOS encoder circuits e.g. 604 that can select individual or a group of LED-PD paired cells e.g. 601, 602 to monitor the internal signals and control them if needed. In various example embodiments, the CMOS calibration circuit may be integrated either inside or outside of a pixel cell. In other words, a pixel cell could include a LED-PD pair and CMOS calibration circuit as part of the cell’s CMOS e.g. 606, or CMOS calibration circuitry shared for a group of pixel cells by selecting and connecting to a corresponding pixel cell could be separate from the pixel cells and implemented external to the cells, e.g. as part of the CMOS encoder circuits e.g. 604.

[0056] A schematic diagram of an LED array 700 according to another example embodiment and its simplified layout (top view) are shown in FIGs. 7A and 7B, respectively. The LED array 700 has commonly used CMOS circuit part integrated with the Si CMOS encoder, together indicated at numeral 702 for a group of cells e.g. 703, 704. In such an example embodiment, one commonly used CMOS circuit for a group of pixel cells as well as a CMOS encoder for the same group of pixels are provided. While in the example embodiments described above the LEDs were cathode grounded and the PDs were anode-grounded, the present invention is not limited to that configuration.

[0057] For example, a schematic diagram of an LED-PD paired cell 800 according to another example embodiment and a simplified layout (top view) of an LED array 802 according to an another example embodiment are shown in FIG. 8A, with the LEDs 804 having an anode- VDD connection and the PD 806 having a cathode- VDD connection.

[0058] As another example, a schematic diagram of an LED-PD paired cell 810 according to another example embodiment and a simplified layout (top view) of an LED array 812 according to another example embodiment are shown in FIG. 8B, with ‘CMOS-LED-CMOS configuration’ between VDD 814 and GND 816.

[0059] FIG. 9 shows a basic example of an LED pixel integrated with CMOS digital circuitry 900 for use in an example embodiment. A Pulse Width Modulation (PWM) signal 902 is provided to aNAND gate 904 to adjust the light intensity of the LED 906 via the MOSFET driver, generally indicated at numeral 908. LED 906 is integrated with CMOS circuitry. An AND gate 910 is provided to select an LED pixel in a large array according to Row and Column Select signals 912, 914, respectively. A Toggling Circuit 916 is provided with a configuration using a D flipflop 918 to control the light intensity of LED 906 through PWM signal 902 when both Row and Column Selection signals 912, 914 correctly choose the pixel.

[0060] FIG. 10 shows an example of an LED-PD paired pixel cell 1000 integrated with CMOS analog control / calibration circuits, according to an example embodiment. An analog voltage is provided as Data signal 1002 to control a main LED driver 1004 current. Capacitor 1006 is provided to keep the Data voltage signal 1002 stable during the array frame rate. An Auxiliary LED driver 1008 is provided, gate-coupled to a feedback voltage signal 1010 to adjust (and / or calibrate) the light intensity of LED 1012. A Select signal 1014 controls a switch 1016 to select a pixel. A small resistor 1018 is provided for LED 1012 current sensing. An amplifier 1020 is provided to generate a feedback voltage to the Auxiliary LED driver 1008 using LED 1012 and / or PD 1022 currents. LED 1012 is integrated with CMOS circuitry. A Diode, Transistor, or LED (with reverse direction) is provided as the PD 1022.

[0061] FIG. 11 shows a (simplified) layout of an LED-PD paired pixel cell 1100 with CMOS Analog Circuits, according to an example embodiment. Examples of the CMOS Circuitry generally indicated at numerals 1102 and 1104 include CMOS digital logic circuits to control / enable LED 1106 / PD 1108. CMOS analog circuits to compensate for the defects of LED 1106 and / or to control the light intensity of LED 1106. CMOS RF / analog / digital circuits to make multi - Gbps optical interconnect communication possible between LED 1106 (i.e. transmitter) and PD 1108 (i.e. receiver).

[0062] FIG. 12 shows a (simplified) layout of an LED-PD paired pixel cell 1200 with CMOS Analog Circuits, according to an example embodiment. Examples of the CMOS Circuitry generally indicated at numerals 1202 and 1204 include CMOS digital logic circuits to control / enable LED 1206 / PD 1208. CMOS analog circuits to compensate for the defects of LED 1206 and / or to control the light intensity of LED 1206. CMOS RF / analog / digital circuits to make multi- Gbps optical interconnect communication possible between LED 1206 (i.e. transmitter) and PD 1208 (i.e. receiver). In this example embodiment, a metal structure / pattem generally indicated at numeral 1210 is provided, here in the form of an array of squares e.g. 1212. It is noted that for a display device, the metal structure / pattem preferably has a partial coverage between LED and PD, as described above with reference to FIGs. 4A and 4B. On the other hand, for an optical communication device, metal structure / pattem 1210 can fully cover the LED-PD pair as shown in FIG. 12 where the CMOS circuitry is an optical receiver.

[0063] In an example embodiment, an integrated pixel cell for a display device and / or optical communication device is provided, comprising a light emitting element; a photo detecting element; CMOS circuitry for the light emitting element and the photo detecting element, wherein the CMOS circuitry, the light emitting element and the photo detecting element are provided on a same substrate of the integrated pixel cell; wherein the photo detecting element is configured to detect a part of radiated light from the light emitting element; and wherein output voltages or currents of the light emitting element and the light detecting element are detectable by a calibration circuit to calibrate the light emitting element’s current or light intensity.

[0064] The calibration circuit may comprise an external micro-processor or circuitry.

[0065] The calibration circuit may be comprised in the CMOS circuitry of the integrated pixel cell.

[0066] The calibration circuit may be configured to monitor the output voltages or currents of the light emitting element and the light detecting element and to generate a calibration signal for driving the light emitting device.

[0067] The photo detecting element may comprise one or more of a group consisting of a photodiode, an LED with a reverse direction, and a transistor.

[0068] The integrated pixel cell may comprise a CMOS BEOL metal structure / pattern disposed between the light emitting element and the photo detecting element for reflecting a portion of the radiated light to the light detecting element.

[0069] The light emitting element and the light detecting element may be configured to receive signals for selectively applying bias / no-bias at the light emitting element and the photo detecting element and for selectively turning on / off driver transistors of the light emitting element and the light detecting element, respectively.

[0070] The light emitting element may be cathode-grounded and the photo detecting element may be anode-grounded.

[0071] The light emitting element’s anode may have a VDD connection and the photo detecting element’s cathode may have a VDD connection. The integrated pixel cell may be configured in a CMOS-(III-V)-CMOS configuration between a ground connection and a VDD connection.

[0072] In an example embodiment, an LED array is provided comprising a plurality of integrated pixel cells of example embodiments described herein, wherein the calibration circuit is configured to perform calibration for an individual one or a group of the integrated pixel cells.

[0073] The calibration circuit may comprise a CMOS encoder circuit configured to select the individual one or the group of the integrated pixel cells for calibration.

[0074] The LED array may comprise a common CMOS circuit for the plurality of integrated pixel cells.

[0075] FIG. 13 shows a flow-chart 1300 illustrating a method of fabricating an integrated pixel cell for a display device and / or optical communication device, according to an example embodiment. At step 1302, a light emitting element is provided. At step 1304, a photo detecting element is provided. At step 1306, CMOS circuitry for the light emitting element and the photo detecting element is provided, wherein the CMOS circuitry, the light emitting element and the photo detecting element are provided on a same substrate of the integrated pixel cell. At step 1308, the photo detecting element is configured to detect a part of radiated light from the light emitting element. At step 1310, output voltages or currents of the light emitting element and the light detecting element are detected by a calibration circuit to calibrate the light emitting element’s current or light intensity.

[0076] The calibration circuit may comprise an external micro-processor or circuitry.

[0077] The calibration circuit may be comprised in the CMOS circuitry of the integrated pixel cell.

[0078] The method may comprise configuring the calibration circuit to monitor the output voltages or currents of the light emitting element and the light detecting element and to generate a calibration signal for driving the light emitting device.

[0079] The photo detecting element may comprise one or more of a group consisting of a photodiode, an LED with a reverse direction, and a transistor.

[0080] The method may comprise disposing a CMOS BEOL metal structure / pattern between the light emitting element and the photo detecting element for reflecting a portion of the radiated light to the light detecting element.

[0081] The method may comprise configuring the light emitting element and the light detecting element to receive control signals for selectively applying bias / no-bias at the light emitting element and the photo detecting element and for selectively turning on / off driver transistors of the light emitting element and the light detecting element, respectively.

[0082] The light emitting element may be cathode-grounded and the photo detecting element is anodegrounded. The light emitting element’s anode may have a VDD connection and the photo detecting element’s cathode may have a VDD connection.

[0083] The method may comprise configuring the integrated pixel cell in a CMOS-(III-V)-CMOS configuration between a ground connection and a VDD connection.

[0084] The method may comprise configuring the calibration circuit to perform calibration for an individual integrated pixel cell or a group of the integrated pixel cells in an LED array.

[0085] The calibration circuit may comprise a CMOS encoder circuit and the method may comprise configuring the CMOS encoder circuit to select the individual one or the group of the integrated pixel cells for calibration.

[0086] The method may comprise providing a common CMOS circuit for the plurality of integrated pixel cells.

[0087] The methods according to example embodiments can for example be implemented using existing heterogeneous wafer bonding technology for integration of LED (e.g. III-V LED) and CMOS circuitry on one substrate, as is understood by a person skilled in the art. For a description of example existing heterogeneous wafer bonding technologies for integration of LED (e.g. III-V LED) and CMOS circuitry on one substrate reference is made to WO2013152176A1, W02018132070A1, and W02021061052A1, the contents of which are incorporated herein by reference in its entirety for all purposes.

[0088] Industrial applications of embodiment so the present invention include, but are not limited to:

[0089] 1. Smart devices including smart watch / phone with micro-LED displays

[0090] 2. Consumer VR and AR / MR micro-displays

[0091] 3. Super-size displays including high-definition TVs

[0092] Aspects of the systems and methods described herein may be implemented on computing device(s), including cloud-based computing device(s) and / or Intemet-of-Things computing device(s), for example as functionality programmed into any of a variety of circuitry, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits (ASICs). Some other possibilities for implementing aspects of the system include: microcontrollers with memory (such as electronically erasable programmable read only memory (EEPROM)), embedded microprocessors, firmware, software, etc. Furthermore, aspects of the system may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course, the underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (MOSFET) technologies like complementary metal-oxide semiconductor (CMOS), bipolar technologies like emitter-coupled logic (ECL), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, etc.

[0093] The various functions or processes disclosed herein may be described as data and / or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and / or other characteristics. Computer-readable media in which such formatted data and / or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and / or instructions through wireless, optical, or wired signaling media or any combination thereof. When received into any of a variety of circuitry (e.g. a computer), such data and / or instruction may be processed by a processing entity (e.g., one or more processors).

[0094] It will be appreciated by a person skilled in the art that numerous variations and / or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive. Also, the invention includes any combination of features described for different embodiments, including in the summary section, even if the feature or combination of features is not explicitly specified in the claims or the detailed description of the present embodiments.

[0095] In general, in the following claims, the terms used should not be construed to limit the systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Accordingly, the systems and methods are not limited by the disclosure, but instead the scope of the systems and methods is to be determined entirely by the claims.

[0096] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of "including, but not limited to." Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words "herein," "hereunder," "above," "below," and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word "or" is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

Claims

CLAIMS1. An integrated pixel cell for a display device and / or optical communication device, comprising a light emitting element; a photo detecting element;CMOS circuitry for the light emitting element and the photo detecting element, wherein the CMOS circuitry, the light emitting element and the photo detecting element are provided on a same substrate of the integrated pixel cell; wherein the photo detecting element is configured to detect a part of radiated light from the light emitting element; and wherein output voltages or currents of the light emitting element and the light detecting element are detectable by a calibration circuit to calibrate the light emitting element’s current or light intensity.

2. The integrated pixel cell of claim 1, wherein the calibration circuit comprises an external micro-processor or circuitry.

3. The integrated pixel cell of claim 1 , wherein the calibration circuit is comprised in the CMOS circuitry of the integrated pixel cell.

4. The integrated pixel cell of any one of the preceding claims, wherein the calibration circuit is configured to monitor the output voltages or currents of the light emitting element and the light detecting element and to generate a calibration signal for driving the light emitting device.

5. The integrated pixel cell of any one of the preceding claims, wherein the photo detecting element comprises one or more of a group consisting of a photodiode, an LED with a reverse direction, and a transistor.

6. The integrated pixel cell of any one of the preceding claims, comprising a CMOS BEOL metal structure / pattem disposed between the light emitting element and the photo detecting element for reflecting a portion of the radiated light to the light detecting element.

7. The integrated pixel cell of any one of the preceding claims, wherein the light emitting element and the light detecting element are configured to receive signals for selectively applying bias / no-bias at the light emitting element and the photo detecting element and for selectively turning on / off driver transistors of the light emitting element and the light detecting element, respectively.

8. The integrated pixel cell of any of any one of the preceding claims, wherein the light emitting element is cathode-grounded and the photo detecting element is anode-grounded.

9. The integrated pixel cell of any of claims 1 to 7, wherein the light emitting element’s anode has a VDD connection and the photo detecting element’s cathode has a VDD connection.

10. The integrated pixel cell of any of claims 1 to 7, configured in a CMOS-(III-V)-CMOS configuration between a ground connection and a VDD connection.

11. An LED array comprising a plurality of integrated pixel cells of any one of the preceding claims, wherein the calibration circuit is configured to perform calibration for an individual one or a group of the integrated pixel cells.

12. The LED array of claim 8, wherein the calibration circuit comprises a CMOS encoder circuit configured to select the individual one or the group of the integrated pixel cells for calibration.

13. The LED array of claims 8 or 9, comprising a common CMOS circuit for the plurality of integrated pixel cells.

14. A method of fabricating an integrated pixel cell for a display device and / or optical communication device, comprising the steps of providing a light emitting element; providing a photo detecting element; providing CMOS circuitry for the light emitting element and the photo detecting element, wherein the CMOS circuitry, the light emitting element and the photo detecting element are provided on a same substrate of the integrated pixel cell; configuring the photo detecting element to detect a part of radiated light from the light emitting element; and detecting output voltages or currents of the light emitting element and the light detecting element by a calibration circuit to calibrate the light emitting element’s current or light intensity.

15. The method of claim 14, wherein the calibration circuit comprises an external microprocessor or circuitry.

16. The method of claim 14, wherein the calibration circuit is comprised in the CMOS circuitry of the integrated pixel cell.

17. The method of any one of claims 14 to 16, comprising configuring the calibration circuit to monitor the output voltages or currents of the light emitting element and the light detecting element and to generate a calibration signal for driving the light emitting device.

18. The method of any one of claims 14 to 17, wherein the photo detecting element comprises one or more of a group consisting of a photodiode, an LED with a reverse direction, and a transistor.

19. The method of any one of claims 14 to 18, comprising disposing a CMOS BEOL metal structure / pattern between the light emitting element and the photo detecting element for reflecting a portion of the radiated light to the light detecting element.

20. The method of any one of claims 14 to 19, comprising configuring the light emitting element and the light detecting element to receive control signals for selectively applying bias / no-bias at the light emitting element and the photo detecting element and for selectively turning on / off driver transistors of the light emitting element and the light detecting element, respectively.

21. The method of any of claims 14 to 20, wherein the light emitting element is cathode- grounded and the photo detecting element is anode-grounded.

22. The method of any of claims 14 to 20, wherein the light emitting element’s anode has a VDD connection and the photo detecting element’s cathode has a VDD connection.

23. The method of any of claims 14 to 20, comprising configuring the integrated pixel cell in a CMOS-(III-V)-CMOS configuration between a ground connection and a VDD connection.

24. The method of any one of claims 14 to 23, comprising configuring the calibration circuit to perform calibration for an individual integrated pixel cell or a group of the integrated pixel cells in an LED array.

25. The method of claim 24, wherein the calibration circuit comprises a CMOS encoder circuit and the method comprises configuring the CMOS encoder circuit to select the individual one or the group of the integrated pixel cells for calibration.

26. The method of claims 24 or 25, comprising providing a common CMOS circuit for the plurality of integrated pixel cells.

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