Method for producing a power semiconductor device and power semiconductor device

Abstract

A method for producing a power semiconductor device (1) with at least one metal support (2) and at least one power semiconductor chip (3) which are connected to one another wherein at least one metal bonding layer (4) is specified, comprising - providing the at least one metal support (2), - providing the at least one semiconductor chip (3), - applying at least one filler metal (5) on the at least one metal support (2) or the at least one power semiconductor chip (3), - applying a plurality of microparticles (6) on the at least one metal support (2), the at least one power semiconductor chip (3) or the at least one filler metal (5), - arranging the at least one metal support (2) on the at least one power semiconductor chip (3), and - generating the at least one metal bonding layer (4) by a thermal treatment of the at least one filler metal (5), wherein - the at least one metal bonding layer (4) has a uniform thickness (2), which is dependent on a size of the microparticles (6). Further, a power semiconductor device (1) is specified.

Description

[0001] Description

[0002] METHOD FOR PRODUCING A POWER SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR DEVICE

[0003] The present disclosure relates to a method for producing a power semiconductor device and power semiconductor device .

[0004] For typical welding diodes , WD, are produced by using a typical soldering or a typical brazing process resulting in a typically metallic bondline . However, during soldering or brazing, parts of the typical WD that are to be j oined expand, while a corresponding solder preform or a corresponding brazing preform or paste reflows . In particular, a thermal expansion of the parts is not negligible , as the parts are bulky and large in diameter when compared to mm-si zed chip-based semiconductors . However, a precise control of the spacing of the parts that are bonded together cannot be ensured with such a standard method . In particular, when the parts are j oined, various geometrical non-uni formities occur which lead to a non-uni form bondline thickness .

[0005] Embodiments of the disclosure relate to a method for producing a power semiconductor device , with which an improved bond layer is producible . A further embodiment relates to a power semiconductor device with such an improved bond layer .

[0006] This is achieved by the subj ect-matter of the independent claims . Further embodiments are evident from the dependent claims and the following description . The method for producing a power semiconductor device with at least one metal support and at least one power semiconductor chip which are connected to one another with at least one metal bonding layer is described . For example , the power semiconductor device comprises , for example , the metal support , the metal bonding layer and the power semiconductor chip being stacked on top of one another in vertical direction . Each bonding metal support , metal bonding layer and power semiconductor chip extends in particular in a main extension plane oriented perpendicular to the vertical direction . Exemplarily, the metal support is in direct contact to the metal bonding layer and the metal bonding layer is in direct contact to the power semiconductor chip . In particular, the metal bonding layer attaches the metal support to the power semiconductor chip in a mechanically stable manner . This means , in particular, that the metal support and the power semiconductor chip cannot be detached from one another non-destructively .

[0007] For example , the power semiconductor device comprises exactly one metal support and exactly one power semiconductor chip being connected to one another with exactly one metal bonding layer . Alternatively, the power semiconductor device comprises a plurality of metal supports , a plurality of power semiconductor chips and / or a plurality of metal bonding layers .

[0008] Exemplarily, the at least one power semiconductor chip is arranged between at least two metal supports , wherein the at least one power semiconductor chip is connected to each of the at least two metal supports with at least one metal bonding layer . In this case , the metal supports are arranged above one another in vertical direction . Exemplarily, at least two power semiconductor chips are arranged on the at least one metal support , wherein the at least two power semiconductor chips are spaced apart from one another in lateral direction . For example , each of the at least two power semiconductor chips is connected to the at least one metal support by an individual metal bonding layer or all of the at least two power semiconductor chips are connected to the at least one metal support by a common metal bonding layer .

[0009] The term "power" here and in the following, for example , refers to power semiconductor devices and power semiconductor chips adapted for processing voltages and currents of more than 100 V and / or of more than 1 kA. The power semiconductor device is , for example , a welding diode , WD . The WD is in particular used for medium and high frequency welding equipment and optimi zed for high current recti fiers . An on- state voltage of the WD is , for example , comparatively low and an output current is comparatively high . The WD operates , exemplarily, at frequencies of at least 0 . 5 kHz or at least 1 kHz with welding currents of at least 5 kA or at least 10 kA. The WD is , exemplarily, a housing-less welding diode , HLWD .

[0010] According to an embodiment of the method, the at least one metal support is provided . In particular, the metal support is prefabricated . The metal support comprises , for example , a metal and / or a metal alloy comprising the metal . The metal is , for example , at least one of molybdenum and copper . In particular, the metal support has a round, elliptical or polygonal shape . Preferably, the metal support has the shape of a disc . Exemplarily, the metal support has a maximal extension in lateral directions, in particular a diameter of the disc, of at least 10 mm or at least 40 mm and / or at most 150 mm or at most 70 mm. A thickness in vertical direction of the metal support is smaller than the maximal extension, for example, at least 0.5 mm or at least 1 mm and / or at most 10 mm or at most 5 mm, e.g., approximately 2 mm.

[0011] According to the embodiment of the method, the at least one semiconductor chip is provided. In particular, the semiconductor chip comprises a semiconductor wafer or a part of the semiconductor wafer. The semiconductor wafer comprises, for example, a semiconductor material. The semiconductor material is, for example, silicon. In particular, the semiconductor chip, in particular the semiconductor wafer, has a round, elliptical or polygonal shape. The shape of the semiconductor chip, in particular the semiconductor wafer, can be equal or different to the shape of the metal support.

[0012] Exemplarily, the semiconductor chip, in particular the semiconductor wafer, has a maximal extension in lateral directions being smaller than the maximal extension of the metal support. Exemplarily, the maximal extension of the semiconductor chip, in particular the semiconductor wafer, is at least 2 % or 5 % smaller than the maximal extension of the metal support.

[0013] A thickness in vertical direction of the semiconductor wafer is, for example, at least 0.05 mm or at least 0.1 mm and / or at most 0.5 mm or at most 0.3 mm, e.g., approximately 0.25 mm. According to the embodiment of the method, at least one filler metal is applied on the at least one metal support or the at least one power semiconductor chip . The filler metal comprises , for example , a metal being at least one of tin, Sn, lead, Pb, silver, Ag, aluminium, Al , gold, Au, titanium, Ti , copper, Cu, nickel , Ni .

[0014] The filler metal is , for example , provided as a preform or a paste . When applying the filler metal on the metal support or the power semiconductor chip, the filler metal is provided in a non- flowable form when the filler metal is provided as the preform or in a semi- flowable form when the filler metal is provided as the paste .

[0015] In particular, the filler metal is applied directly to a main surface of the metal support or directly to a main surface of the semiconductor chip being in particular formed by a main surface of the semiconductor wafer .

[0016] Exemplarily, a plurality of filler metals , each formed as a layer, can be applied on the metal support or the semiconductor chip . In particular, the filler metals are spaced apart from one another in lateral direction . I f the plurality of metal supports is provided, the filler metal is applied to each metal support separately . I f the plurality of semiconductor chips is provided, the filler metal is applied to each semiconductor chip separately or a common filler metal is applied to all of the power semiconductor chips .

[0017] The filler metal , for example , covers the main surface to which it is applied to a large extent . "To a large extent" means here that at least 90 % or at least 95 % of the respective main surface is covered by the filler metal . According to the embodiment of the method, a plurality of microparticles is applied on the at least one metal support , the at least one power semiconductor chip or the at least one filler metal . I f the filler metal is applied to the metal support , the microparticles are applied to the power semiconductor chip or the filler metal . I f the filler metal is applied to the semiconductor chip, the microparticles are applied to the metal support chip or the filler metal .

[0018] In particular, the microparticles are applied directly to the main surface of the metal support , directly to the main surface of the semiconductor chip, being in particular formed by the main surface of the semiconductor wafer, or directly to a main surface of the filler metal .

[0019] For example , the microparticles are not embedded in the filler metal . "Not embedded" means that an outer surface of each of the microparticles is not completely covered by the filler metal . This is to say that each of the microparticles is not surrounded three-dimensionally by the filler metal .

[0020] Each microparticle has a maximal extension of at least 0 . 1 pm to at most 100 pm . In particular, the microparticles are solid microparticles .

[0021] According to the embodiment of the method, the at least one metal support is arranged on the at least one power semiconductor chip . In particular, the metal support and the power semiconductor chip are arranged above one another such that the metal filler and the microparticles are arranged between the metal support and the power semiconductor chip in vertical direction . Exemplarily, the metal support is arranged on the power semiconductor chip, the filler metal is in direct contact to the microparticles and the microparticles are in direct contact to the metal support or the power semiconductor chip .

[0022] According to the embodiment of the method, the at least one metal bonding layer is generated by a thermal treatment of the at least one filler metal . In particular, thermal treatment comprises the filler metal being heated to a first temperature and subsequently cooled to a second temperature . This is to say that the at least one filler metal is heated and cooled for forming the at least one metal bonding layer . Exemplarily, an arrangement of the least one metal support , the at least one filler metal , the plurality of microparticles and the at least one power semiconductor chip is heated and subsequently cooled .

[0023] The first temperature is , for example , at least 150 ° C and / or at most 800 ° C . The second temperature is , for example , at mo st 50 ° C .

[0024] For example , during the heating, the filler metal melts such that the filler metal is present in a flowable form . Exemplarily, the microparticles can be surrounded laterally by the filler metal during heating .

[0025] Exemplarily, a predetermined force is applied on the metal support and / or the power semiconductor chip in vertical direction such that the metal support and the power semiconductor chip are pressed together in vertical direction by the predetermined force . When the filler metal melts , the microparticles are in particular pushed in the filler metal . In particular, the microparticles delimit a spacing in vertical direction of the metal support and the power semiconductor chip when heating the metal support , the filler metal and the power semiconductor chip .

[0026] For example , during cooling, the filler metal becomes solid such that the metal bonding layer is formed . This metal bonding layer provides the mechanically stable connection of the power semiconductor chip to the metal support .

[0027] According to the embodiment of the method, the at least one metal bonding layer has a uni form thickness which is dependent on a si ze of the microparticles . Exemplarily, the microparticles define the spacing in vertical direction of the metal support and the power semiconductor chip, in particular when the filler metal is melted during heating . In particular during cooling, the filler metal becomes exemplarily solid such that the metal bonding layer is formed, wherein the metal bonding layer has a thickness dependent on the si ze of the microparticles - which have defined the spacing in vertical direction . In particular, the thickness is defined in vertical direction .

[0028] The uni form thickness of the metal bonding layer is , for example , characteristic for a constant thickness of the metal bonding layer over a whole extension in lateral directions of the metal bonding layer, in particular without signi ficant variations or irregularities in its thickness . "Signi ficant variations" means that variations in the thickness can be present due to production tolerances and interface defects .

[0029] Exemplarily, the metal bonding layer has a first main surface facing the metal support and a second main surface facing the power semiconductor device . The first main surface is directly connected to the metal support in a mechanically stable manner and the second main surface is directly connected to the power semiconductor device in a mechanically stable manner . In particular, the first main surface and the second main surface extend parallel to one another over the whole extensions in lateral directions thereof , exemplarily without signi ficant variations . Thus , the produced metal bonding layer exhibits in particular a surface parallelism of the bonded parts .

[0030] For example , the spacing from the main surfaces of the metal support and the power semiconductor device facing one another in vertical direction is uni form over the whole extensions in lateral directions thereof .

[0031] Typically, due to di f ferent thermal properties of di f ferent materials of the power semiconductor device to be produced, and due to the comparatively high load currents during operation of the power semiconductor device to be produced, di f ferent parts of the power semiconductor device to be produced are extremely stressed during power cycling . The on- state voltage must remain very low, and thermal resistance of the parts and j oints must be kept minimal . Advantageously, the produced power semiconductor device with the uni form metal bonding layer thickness achieves an excellent thermal and electrical conductivity simultaneously .

[0032] Thus , for example , a load cycle capability of millions of cycles , corresponding to years of a device operation, can be advantageously achieved for such a produced power semiconductor device under the severe conditions described herein above . In sum, the method advantageously produces a power semiconductor device with a high degree of robustness in load cycling due to its uni form metal bonding layer . Such a power semiconductor device has an increased li fetime . Further, customer return rate can be decreased and the electrical yield of the power semiconductor device can be increased . It is advantageously possible to utili ze the thickness control , depending on the si ze of the microparticles , on every kind of soldered or brazed semiconductor device .

[0033] In particular, such a metal bonding layer provides a comparatively low thermal resistance and / or a comparatively low electrical resistance in combination with a strong mechanical strength and / or good shear strength absorption .

[0034] The power semiconductor device with such a metal bonding layer provides the advantage , for example , that it also functions under operating conditions at temperatures of at least 120 ° C or at least 190 ° C . Advantageously, even under these conditions no impact on electrical properties of the power semiconductor chip and its ohmic contact occurs .

[0035] According to a further embodiment of the method, at least a part of the at least one metal support and / or at least a part of the at least one power semiconductor chip is removed after the generation of the at least one metal bonding layer . For example , additionally, at least a part of the one metal bonding layer is removed when removing at least a part of the at least one metal support and / or at least a part of the at least one power semiconductor chip .

[0036] Exemplarily, the metal bonding layer is removed in places where the microparticles are incorporated in the metal bonding layer . In particular, the finally produced power semiconductor device does not comprise the microparticles . Advantageously, a function of the metal bonding layer is not altered by microparticles .

[0037] Alternatively, the metal bonding layer is removed in places where the microparticles are not incorporated in the metal bonding layer . In particular, the finally produced power semiconductor device comprises the microparticles . Advantageously, a function with respect to an electrical conductivity, a thermal conductivity and / or a mechanical strength of the metal bonding layer can be improved by microparticles .

[0038] According to a further embodiment of the method, the at least one filler metal is a solder or a braze . Exemplarily, the first temperature is , for example , at least 150 ° C and at most 350 ° C when the filler metal is a solder . Exemplarily, the first temperature is , for example at least 400 ° C and at most 800 ° C when the filler metal is a braze .

[0039] According to a further embodiment of the method, the microparticles are applied on a main surface of the at least one metal support , the at least one metal support or the at least one filler metal in at least one predetermined region . The predetermined region corresponds , for example , to a shape of a ring, an ellipse or a polygon .

[0040] I f the microparticles are applied in a plurality of predetermined regions , each predetermined region can be arranged on virtual grid points of a virtual grid . The virtual grid is , for example , a regular or irregular polygonal grid . Advantageously, the electrical conductivity, the thermal conductivity and / or the mechanical strength of the metal bonding layer can be structured by the arrangement of the microparticles dependent on a location of the predetermined regions .

[0041] According to a further embodiment of the method, the at least one predetermined region is located in a peripheral region of the respective main surface . Exemplarily, the microparticles are applied in the peripheral region at least regionally on the respective surface .

[0042] The peripheral region is , for example , located at an outer edge delimiting the respective main surface . In particular, the peripheral region surrounds a central region of the respective main surface . The central region is located, for example , at a centre of mass of the respective main surface . For example , the central region is free of the microparticles . Exemplarily, the peripheral region extends from an edge of the respective main surface in lateral directions in direction to the central region . The peripheral region has , for example , a minimal extent in the direction to the central region of at least 0 . 1 mm and at most 2 mm .

[0043] According to a further embodiment of the method, the microparticles each have the shape of a microsphere . The microsphere is a three-dimensional obj ect , where all points on an outer surface of the microsphere are approximately equidistant from a centre of the microsphere . "Approximately equidistant" means that a sphericity of the microsphere is at least 99 % and / or an in-range conformity of the microsphere is at least 99 % . According to a further embodiment of the method, the microparticles are arranged in a monolayer . Exemplarily, the monolayer is characteristic for a single layer of the microparticles . In particular, the microparticles are arranged side by side in a two-dimensional manner in lateral directions . For example , the microparticles are arranged without any stacking or overlapping in vertical direction .

[0044] According to a further embodiment of the method, the microparticles are monodisperse . In particular, all of the microparticles have approximately the same maximal extension . Exemplarily, a variation of the maximal extension of the microparticles is at most 5 % .

[0045] According to a further embodiment of the method, the microparticles are sel f-arranging . Exemplarily, when applying the microparticles on the respective main surface , the microparticles are configured to order themselves in a close- packed and / or orderly structure . In particular, the sel farrangement occurs due to a minimi zation of energy within the microparticles , e . g . , driven by interparticle forces , including van der Waals forces and electrostatic interactions .

[0046] Advantageously, the sel f-arrangement of the microparticles , in particular the monolayer, is carried out without the need for external intervention .

[0047] According to a further embodiment of the method, the microparticles have the same diameters . Exemplarily, a variation of the diameters of the microparticles is at most 5 % or at most 2 % . According to a further embodiment of the method, each of the microparticles has a diameter of at least 10 pm and at most 50 pm. In particular, the microparticles each have a diameter of at least 35 pm and at most 37 pm.

[0048] According to a further embodiment of the method, a melting temperature of the microparticles is at least 450 °C. In particular, the melting temperature of the microparticles is at least 600 °C or at least 800 °C.

[0049] According to a further embodiment of the method, the microparticles are electrically insulating or electrically conducting. Exemplarily, the microparticles comprise a dielectric material such as glass, e.g., borosilicate glass or soda-lime glass. Alternatively, the microparticles comprise an electrically conductive material such as a metal.

[0050] In particular, when using glass for the microparticles, the melting temperatures of such microparticles is comparatively high, e.g., 830 °C for borosilicate glass and, e.g., 650°C for soda-lime glass.

[0051] According to a further embodiment of the method, when applying the plurality of microparticles a suspension in which the plurality of microparticles is included is applied on the at least one metal support, the at least one power semiconductor chip or the at least one filler metal. Exemplarily, the suspension comprises a liquid and the microparticles. In particular, the microparticles are provided in the liquid. The liquid comprises, for example, at least one of ethanol and isopropanol. The microspheres are , for example , mixed with the liquid with a mass ratio of 1 : 50 .

[0052] According to a further embodiment of the method, a liquid of the suspension is removed after the application thereof . Exemplarily, the liquid is configured to evaporate when heat is applied . The heat is applied, for example , by a hot plate , an oven and / or an infrared, IR, lamp . After removal , in particular evaporation, of the liquid, the microparticles remain on the respective main surface .

[0053] According to a further embodiment of the method, when applying the plurality of microparticles , the suspension is applied in the form of droplets . The droplets are applied, for example , to the predetermined region, where the droplets cover the peripheral region at least regionally .

[0054] Moreover, a power semiconductor device is described which can be produced, or which is produced by the method described herein above . Therefore , the features as described in connection with the method are also applicable for the power semiconductor device and vice versa .

[0055] According to an embodiment , the power semiconductor device comprises at least one metal support .

[0056] According to the embodiment , the power semiconductor device comprises at least one power semiconductor chip .

[0057] According to the embodiment , the power semiconductor device comprises at least one metal bonding layer connecting the at least one metal support to the at least one power semiconductor chip . According to the embodiment of the power semiconductor device , the metal bonding layer has a uni form thickness .

[0058] According to the embodiment of the power semiconductor device , the uni form thickness of the metal bonding layer deviates from a mean thickness of the metal bonding layer by at most plus minus 20 % . In particular, the uni form thickness deviates from a mean thickness by at most plus minus 15 % , by at most plus minus 10 % or by at most plus minus 5 % .

[0059] In particular, a spacing from the main surfaces of the metal support and the power semiconductor device facing one another in vertical direction is uni form over the whole extension in lateral directions thereof . The spacing in vertical direction deviates from a mean spacing by at most plus minus 20 % , by at most plus minus 15 % , by at most plus minus 10 % or by at most plus minus 5 % .

[0060] According to the embodiment of the power semiconductor device , the at least one metal bonding layer is produced dependent on a si ze of the microparticles .

[0061] The accompanying Figures are included to provide a further understanding . In the Figures , elements of the same structure and / or functionality may be referenced by the same reference signs . It is to be understood that the embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale .

[0062] Figures 1 , 2 , 3 and 4 show schematic method stages of the method for producing a power semiconductor device according to an exemplary embodiment . Figures 5 , 6 and 7 schematically show a power semiconductor device and its operational properties according to an exemplary embodiment .

[0063] Figures 8 and 9 each schematically show a method stage of the method for producing a power semiconductor device according to an exemplary embodiment .

[0064] Figure 10 schematically shows an arrangement of microparticles of a power semiconductor device according to an exemplary embodiment .

[0065] The at least one metal support 2 is provided in the method stage according to Figure 1 , wherein a plurality of microparticles 6 are applied on the metal support 2 . The metal support 2 has the shape of a disc .

[0066] The microparticles 6 are incorporated in a suspension 10 . The suspension 10 is applied on a main surface of the metal support 2 at least regionally in a peripheral region 8 of the main surface . In particular, the suspension 10 is applied in the form of droplets . After application of the suspension 10 with the microparticles 6 , a liquid 11 of the suspension 10 is removed by applying a heat . After removal of the liquid 11 , the microparticles 6 are arranged on the main surface of the metal support 2 , in particular at least regionally in the peripheral region 8 .

[0067] Each of the microparticles 6 has the shape of a microsphere , wherein all diameters of the microspheres are equal to one another . Equal to one another means that the diameters can di f fer from a mean diameter value by at most 5 % . The mean diameter value is , for example , approximately 36 pm . Further, a sphericity of the microsphere is at least 99 % and an inrange conformity of the microsphere is at least 99 % .

[0068] The microparticles 6 are arranged on the main surface of the metal surface as a monolayer . In particular, the microparticles 6 are sel f-arranged side by side in a two- dimensional manner in lateral directions .

[0069] In the method stage according to Figure 2 , a semiconductor chip is provided on which a filler metal 5 is applied . The filler metal 5 particularly completely covers a main surface of the semiconductor chip, which can be the main surface of a semiconductor wafer . The filler metal 5 is either a solder or a braze . Exemplarily the filler metal 5 is formed of a preform or a paste , which is applied on the main surface of the semiconductor chip .

[0070] The semiconductor chip on which the filler metal 5 is applied is arranged on the metal support 2 with the microparticles 6 , such that the filler metal 5 and the microparticles 6 face one another . In this method stage , the microparticles 6 and the filler metal 5 are in direct contact to one another, but the microparticles 6 are not embedded, i . e . , incorporated, in the filler metal 5 .

[0071] In the method stage according to Figure 3 , a metal bonding layer 4 is generated by a thermal treatment of the filler metal 5 . The arrangement of the metal support 2 , microparticles 6 , filler metal 5 and power semiconductor chip 3 is heated to a first temperature , such that the filler metal 5 melts . When the filler metal 5 melts , the microparticles 6 can be introduced in the material of the filler metal 5 and the microparticles 6 can define a spacing in vertical direction between the metal support 2 and the power semiconductor chip 3 . Subsequently, the arrangement is cooled to a second temperature , e . g . room temperature , such that the material of the filler metal 5 becomes to the metal bonding layer 4 , which connects the metal support 2 and the power semiconductor chip 3 in a mechanically stable manner .

[0072] The generated metal bonding layer 4 of the produced power semiconductor device 1 has a uni form thickness 7 , which is dependent on a si ze of the microparticles 6 . Further, the main surfaces of the generated metal bonding layer 4 , i . e . a top surface facing and directly connected to the power semiconductor chip 3 and a bottom surface facing and directly connected to the metal support 2 , are parallel to one another over a whole extension in lateral directions thereof .

[0073] The microparticles 6 , i . e . the si ze of the microparticles 6 in vertical direction, define a spacing between the power semiconductor chip 3 and the metal support 2 . That is , a uni form bonding layer being in particular straight along lateral directions is produced, resulting in a parallel arrangement of the semiconductor chip and the metal support 2 .

[0074] A part of the semiconductor chip, in particular the semiconductor wafer, is removed in the peripheral region 8 in Figure 4 of the power semiconductor device 1 . In particular, the peripheral region 8 surrounds a central region 9 in lateral directions . It is possible that the semiconductor wafer is further processed before the provision and alternatively or additionally it is possible that the semiconductor wafer is further processed after the semiconductor wafer is attached to the metal support 2 .

[0075] The produced power semiconductor device 1 according to the exemplary embodiment of Figure 5 is a welding diode , WD . A diameter of the WD in lateral directions is , for example , approximately 30 mm to 60 mm . The metal support 2 , the meta bonding layer and the semiconductor chip are stacked above one another in vertical direction .

[0076] The cross-section in Figure 6 corresponds to the cut indicated in Figure 5 A to A' , marked with a dashed line . A thickness of the metal support 2 is approximately 2 mm, a thickness of the metal bonding layer 4 is approximately 0 . 04 mm and a thickness of the semiconductor chip, in particular the wafer, is approximately 0 . 25 mm .

[0077] The diagram of Figure 7 exemplarily illustrates a typical cycle of a WD in an application . A weld current I in kA is provided on the y-axis and a weld time pulses t in ms are provided on the x-axis .

[0078] The droplets of the suspension 10 including the microparticle 6 are applied on the metal support 2 by a pipette 12 in the peripheral regions 8 , as shown in Figure 8 .

[0079] The droplets of the suspension 10 including the microparticle 6 are applied on the metal support 2 at predetermined regions in the peripheral region 8 in Figure 9 . The predetermined regions are arranged on virtual grid points of a virtual grid, being in particular a quadrangular grid . The microparticles 6 according to Figure 10 are arranged in a peripheral region 8 of each droplet . In particular, the microparticles 6 sel f-arrange themselves at the peripheral region 8 of each droplet . The microparticles 6 are in particular arranged in the form of a ring, i . e . the microparticles 6 are sel f-arranged in a ring-shaped cluster . The ring can have a diameter in lateral directions of at most approximately 2 mm, approximately 1 mm as illustrated in Figure 10 .

[0080] The ring-shaped microsphere clusters remain deposited on the metal support 2 after the solution is evaporated from droplets . In particular, the ring-shaped microsphere clusters comprise the microspheres in a non-stacking sel f-arranging monolayer appearance .

[0081] Reference Signs

[0082] 1 power semiconductor device

[0083] 2 metal support 3 power semiconductor chip

[0084] 4 metal bonding layer

[0085] 5 filler metal

[0086] 6 microparticle

[0087] 7 uni form thickness 8 peripheral region

[0088] 9 central region

[0089] 10 suspension

[0090] 11 liquid

[0091] 12 pipette

Claims

Claims1. Method for producing a power semiconductor device (1) with at least one metal support (2) and at least one power semiconductor chip (3) which are connected to one another with at least one metal bonding layer (4) , comprising- providing the at least one metal support (2) ,- providing the at least one semiconductor chip (3) ,- applying at least one filler metal (5) on the at least one metal support (2) or the at least one power semiconductor chip ( 3 ) ,- applying a plurality of microparticles (6) on the at least one metal support (2) , the at least one power semiconductor chip (3) or the at least one filler metal (5) ,- arranging the at least one metal support (2) on the at least one power semiconductor chip (3) , and- generating the at least one metal bonding layer (4) by a thermal treatment of the at least one filler metal (5) , wherein- the at least one metal bonding layer (4) has a uniform thickness (2) , which is dependent on a size of the microparticles (6) .

2. Method according to claim 1, wherein- at least a part of the at least one metal support (2) and / or at least a part of the at least one power semiconductor chip (3) is removed after the generation of the at least one metal bonding layer (4) .

3. Method according to one of claims 1 or 2, wherein- the at least one filler metal (5) is a solder or a braze.

4. Method according to one of claims 1 to 3, wherein- the microparticles (6) are applied on a main surface of the at least one metal support (2) , the at least one metal support (2) or the at least one filler metal (5) in at least one predetermined region.

5. Method according to claim 4, wherein- the at least one predetermined region is located in a peripheral region (8) of the respective main surface.

6. Method according to one of the claims 1 to 5, wherein- the microparticles (6) each have the shape of a microsphere .

7. Method according to one of claims 1 to 6, wherein- the microparticles (6) are arranged in a monolayer, and / or- the microparticles (6) are monodisperse.

8. Method according to one of claims 1 to 7, wherein- the microparticles (6) are self-arranging.

9. Method according to one of claims 1 to 8, wherein- the microparticles (6) have the same diameters.

10. Method according to one of claims 1 to 9, wherein- the microparticles (6) each have a diameter of at least 10 pm and at most 50 pm.

11. Method according to one of claims 1 to 10, wherein- a melting temperature of the microparticles (6) is at least 450 °C.

12. Method according to one of claims 1 to 11, wherein- the microparticles (6) are electrically insulating or electrically conducting.

13. Method according to one of claims 1 to 12, when applying the plurality of microparticles (6) , wherein- a suspension (10) in which the plurality of microparticles (6) is included is applied on the at least one metal support (2) , the at least one power semiconductor chip (3) or the at least one filler metal (5) , and- a liquid (11) of the suspension (10) is removed after the application thereof.

14. Method according to claim 13, wherein when applying the plurality of microparticles (6)- the suspension (10) is applied in form of droplets.

15. Power semiconductor device (1) with- at least one metal support (2) ,- at least one power semiconductor chip (3) , and- at least one metal bonding layer (4) connecting the at least one metal support (2) to the at least one power semiconductor chip (3) , wherein- the metal bonding layer (4) has a uniform thickness (2) .

16. Power semiconductor device (1) according to claim 15, wherein- the uniform thickness (2) deviates from a mean thickness of the metal bonding by at most plus minus 20 %.

17. Power semiconductor device (1) according to one of the claims 15 or 16, wherein the at least one metal bonding layer (4) is produced depending on the size of microparticles (6) .

18. Power semiconductor device (1) according to one of claims 15 to 17, which is produced by the method according to one of claims 1 to 14.

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