Pixel sensing circuit and display device comprising same

Abstract

Provided, according to one embodiment of the present invention, are a pixel sensing circuit capable of reducing manufacturing costs by reducing the chip size of a source driver IC, and a display device comprising same.

Description

Pixel sensing circuit and display device including the same

[0001] The present invention relates to a pixel sensing circuit and a display device including the same.

[0002] In general, an OLED (Organic Light Emitting Diodes) display device is a display device that controls pixels by individually supplying data voltages according to image information to OLED pixels arranged in a matrix form to display a desired image.

[0003] The panel applied to OLED display devices, that is, the display panel on which OLED pixels are arranged, is expanding its range of applications due to its characteristics such as being lightweight, thin, and low-power operation.

[0004] Here, each pixel includes an organic light-emitting diode (OLED), a driving thin film transistor (TFT), etc. As the driving time of the pixels increases, the driving characteristics of the organic light-emitting diode or TFT, i.e., the electrical characteristics of the pixels, change. These changes in electrical characteristics can occur differently for each pixel, and if the electrical characteristics of the pixels change, a luminance difference occurs even among pixels that receive the same data voltage, which degrades the picture quality of the OLED display device.

[0005] To prevent image quality degradation in OLED display devices, variations in the electrical characteristics of pixels must be compensated for. To achieve this, pixel sensing circuits must be incorporated into the source driver ICs (Integrated Circuits) of OLED display devices. In other words, the source driver ICs of OLED display devices contain multiple sensing channels, and the pixel sensing circuits include multiple sensing channel circuits connected to each sensing channel, increasing their size. Consequently, the area occupied by the pixel sensing circuits within the source driver IC increases, which in turn increases the chip size and manufacturing cost of the source driver IC.

[0006] The purpose is to provide a pixel sensing circuit and a display device including the same, which can reduce manufacturing costs by reducing the chip size of a source driver IC.

[0007] According to an embodiment of the present invention for achieving the above-described technical problem, a pixel sensing circuit comprises: a first to m-th channel selection multiplexer electrically connected to i pixels among i (i is a natural number greater than 1)*m (m is a natural number greater than or equal to 1) pixels of a display panel, and selectively outputting first to m-th analog signals received from any one of the i pixels during each operation period; a first to m-th sample-and-hold scaler circuit for sampling, holding, and scaling the first to m-th analog signals during each operation period and outputting first to m-th characteristic voltages, respectively; a selection unit for sequentially selecting and outputting the first to m-th characteristic voltages; an analog-to-digital converter for converting each of the first to m-th characteristic voltages into digital data during each operation period; And a plurality of latches for storing the digital data; and for the one horizontal line, each of the first to m-th channel selection multiplexers, each of the first to m-th sample-and-hold scaler circuits, and the analog-to-digital converter repeats the operation section i times.

[0008] An embodiment of the present invention has the effect of reducing the size of a pixel sensing circuit by having a plurality of pixels share components of the pixel sensing circuit.

[0009] In addition, the embodiment of the present invention has the effect of reducing the chip size of the source driver IC and reducing the manufacturing cost of the source driver IC by reducing the size of the pixel sensing circuit.

[0010] In addition, the embodiment of the present invention can sense the characteristic voltage of a pixel more quickly by simultaneously performing analog signal sensing of a pixel and transmission of pixel sensing data.

[0011] Figure 1 is a configuration diagram of a display device according to one embodiment of the present invention.

[0012] FIG. 2 is a drawing showing the configuration of a display panel and a source driver IC according to one embodiment of the present invention.

[0013] FIG. 3 is a block diagram briefly showing the configuration of a pixel sensing circuit according to one embodiment of the present invention.

[0014] Figure 4 is a flow chart of a pixel sensing method according to one embodiment of the present invention.

[0015] FIG. 5 is a timing diagram of a pixel sensing circuit according to one embodiment of the present invention.

[0016] FIG. 6 is a block diagram briefly showing the configuration of a pixel sensing circuit according to another embodiment of the present invention.

[0017] Figure 7 is a flow chart of a pixel sensing process according to another embodiment of the present invention.

[0018] FIG. 8 is a timing diagram of a pixel sensing circuit according to another embodiment of the present invention.

[0019] FIG. 9 is a timing diagram of a pixel sensing circuit according to another embodiment of the present invention.

[0020] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0021] Throughout the specification, identical reference numbers refer to substantially identical components. In the following description, detailed descriptions of components and functions not related to the core components of the present invention and those known in the art may be omitted.

[0022] In this specification, when the terms "includes," "has," and "consists of," are used, other parts may be added, unless "only" is used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0023] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0024] While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0025] The term "at least one" should be understood to include all possible combinations of one or more associated items. For example, "at least one of the first, second, and third items" can mean any combination of items that can be represented by two or more of the first, second, and third items, as well as each of the first, second, and third items.

[0026] The individual features of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical linkages and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0027]

[0028] Hereinafter, with reference to FIGS. 1 and 2, a pixel sensing circuit and a display device according to one embodiment of the present invention will be described.

[0029] FIG. 1 is a configuration diagram of a display device according to one embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a display panel and a source driver IC according to one embodiment of the present invention.

[0030] Referring to FIG. 1, a display device (100) according to one embodiment of the present invention may include a display panel (110) and a panel driving device (120, 130, 140, 150) that drives the display panel (110).

[0031] The display panel (110) includes a plurality of data lines (DL), a plurality of gate lines (GL), and a plurality of pixel sensing lines (SL), and may include a plurality of pixels (P). Here, the plurality of pixels (P) may be arranged in a matrix form composed of a plurality of rows and a plurality of columns.

[0032] Devices (120, 130, 140, 150) that drive at least one component included in the display panel (110) may be panel driving devices. For example, a data driving circuit (120), a pixel sensing circuit (130), a gate driving circuit (140), a data processing circuit (150), etc. may be panel driving devices. At this time, each of the above-described devices (120, 130, 140, 150) may be a panel driving device, and all or at least one may be a panel driving device.

[0033] The gate driving circuit (140) can supply a scan signal of a turn-on voltage or a turn-off voltage to the gate line (GL). When the scan signal of the turn-on voltage is supplied to a pixel (P), the corresponding pixel (P) is connected to the data line (DL), and when the scan signal of the turn-off voltage is supplied to the pixel (P), the connection between the corresponding pixel (P) and the data line (DL) is released.

[0034] Here, the gate driving circuit (140) may be a gate driver IC (Integrated Circuit). In Fig. 1, only one gate driving circuit (140) is illustrated, but a general display device (100) may include one or more gate driving circuits (140).

[0035] The data driving circuit (120) supplies a data voltage to the data line (DL). The data voltage supplied to the data line (DL) is transmitted to the pixel (P) connected to the data line (DL) according to a scan signal.

[0036] The pixel sensing circuit (130) senses analog signals (Vsense / Isense), such as voltage and current, formed in each pixel (P). The pixel sensing circuit (130) may be connected to each pixel (P) according to a scan signal, or may be connected to each pixel (P) according to a separate sensing signal. In this case, the separate sensing signal may be generated by the gate driving circuit (140).

[0037] Pixels (P) may include organic light emitting diodes (OLEDs) and one or more transistors. The characteristics of the organic light emitting diodes (OLEDs) and transistors included in each pixel (P) may change over time or depending on the surrounding environment. A general pixel sensing circuit (130) may sense and process analog signals (Vsense / Isense) according to the characteristics of these components included in each pixel (P) and transmit pixel sensing data (S_DATA) to a data processing circuit (150).

[0038] Specifically, each pixel (P) may include an organic light-emitting diode (OLED), a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), and a storage capacitor (Cstg), as shown in FIG. 2.

[0039] An organic light-emitting diode (OLED) may be composed of an anode electrode, an organic layer, and a cathode electrode. Under the control of a driving transistor (DRT), the anode electrode is connected to a driving voltage (EVDD) and the cathode electrode is connected to a base voltage (EVSS), so that the organic light-emitting diode (OLED) emits light. In other words, when the driving transistor (DRT) is turned on, a driving current is supplied from the driving voltage (EVDD), so that the organic light-emitting diode (OLED) emits light, and a voltage is formed between the anode electrode and the cathode electrode according to the characteristics of the organic light-emitting diode (OLED).

[0040] A driver transistor (DRT) controls the brightness of an organic light-emitting diode (OLED) by controlling the driving current supplied to the OLED.

[0041] A first node (N1) of the driving transistor (DRT) may be electrically connected to an anode electrode of an organic light emitting diode (OLED) and may be a source node or a drain node of the driving transistor (DRT). A second node (N2) of the driving transistor (DRT) may be electrically connected to a source node or a drain node of a switching transistor (SWT) and may be a gate node of the driving transistor (DRT). A third node (N3) of the driving transistor (DRT) may be electrically connected to a driving voltage line (DVL) that supplies a driving voltage (EVDD) and may be a drain node or a source node of the driving transistor (DRT).

[0042] The switching transistor (SWT) is electrically connected between the data line (DL) and the second node (N2) of the driving transistor (DRT), and can be turned on by receiving a scan signal through the gate line (GL1).

[0043] When this switching transistor (SWT) is turned on, the data voltage (Vdata) supplied from the data driving circuit (120) through the data line (DL) is transmitted to the second node (N2) of the driving transistor (DRT).

[0044] A storage capacitor (Cstg) can be electrically connected between a first node (N1) and a second node (N2) of a driving transistor (DRT).

[0045] The storage capacitor (Cstg) may be a parasitic capacitor existing between the first node (N1) and the second node (N2) of the driving transistor (DRT), or may be an external capacitor intentionally designed outside the driving transistor (DRT).

[0046] The sensing transistor (SENT) connects the first node (N1) of the driving transistor (DRT) and the sensing line (SL), and the sensing line (SL) transmits a reference voltage (Vref) to the first node (N1) and transmits an analog signal (Vsense / Isense), which is a voltage or current formed at the first node (N1), to the pixel sensing circuit (130).

[0047] The pixel sensing circuit (130) measures the characteristics of the pixel (P) using an analog signal (Vsense or Isense) transmitted through a sensing line (SL). Specifically, by measuring the voltage of the first node (N1), the threshold voltage, mobility, current characteristics, etc. of the driving transistor (DRT) can be determined, and also the degree of deterioration of the organic light emitting diode (OLED), such as the parasitic capacitance and current characteristics of the organic light emitting diode (OLED), can be determined.

[0048] The pixel sensing circuit (130) can measure the voltage of the first node (N1), i.e., an analog signal (Vsense / Isense) according to the characteristics of the pixels (P), and transmit pixel sensing data (S_DATA), which is digital data, to the data processing circuit (150). And the data processing circuit (150) can determine the characteristics of each pixel (P) based on the pixel sensing data (S_DATA).

[0049] The pixel sensing circuit (130) will be described in more detail later with reference to FIG. 3.

[0050] The aforementioned data driving circuit (120) and pixel sensing circuit (130) can be included in one integrated circuit (125).

[0051] Additionally, one integrated circuit (125) may be a source driver IC. In FIG. 1, only one source driver IC (125) is illustrated, but a typical display device (100) may include one or more source driver ICs (125).

[0052] The data processing circuit (150) supplies various control signals to the gate driving circuit (140) and the data driving circuit (120). The data processing circuit (150) generates a gate control signal (GCS) for scanning pixels (P) according to the timing implemented in each frame and transmits the gate control signal (GCS) to the gate driving circuit (140). In addition, the data processing circuit (150) can convert image data (RGB) input from an external device into a data signal format used by the data driving circuit (120) and output image data (RGB`) to the data driving circuit (120). The data processing circuit (150) can transmit a data control signal (DCS) for controlling the data driving circuit (120) to supply a data voltage to each pixel (P) according to each timing.

[0053] In addition, the data processing circuit (150) can compensate and transmit the image data (RGB`) according to the characteristics of the pixel (P). At this time, the data processing circuit (150) can receive the pixel sensing data (S_DATA) from the pixel sensing circuit (130). Then, the pixel sensing data (S_DATA) can be used to generate compensation value data, and the image data (RGB`) can be compensated using the compensation value data. Here, the pixel sensing data (S_DATA) can include a characteristic value for the characteristic of the pixel (P). This data processing circuit (150) can be a timing controller.

[0054] Meanwhile, in a general display device (100), the source driver IC (125) includes at least one data driving circuit (120) and at least one pixel sensing circuit (130), so that the area of ​​the source driver IC (125) increases. In addition, since a general pixel sensing circuit (130) includes multiple identical components, the chip size of the source driver IC increases and the manufacturing cost increases. Accordingly, the present invention can reduce the number of identical components by sharing the components included in the pixel sensing circuit (130).

[0055]

[0056] Hereinafter, with reference to FIG. 3, a pixel sensing circuit according to one embodiment of the present invention will be described in more detail.

[0057] FIG. 3 is a block diagram briefly showing the configuration of a pixel sensing circuit according to one embodiment of the present invention.

[0058] The pixel sensing circuit (130) samples analog signals of a plurality of pixels (P) received through the first to nth sensing channels (SC1 to SCn) and scales the levels of the sampled voltages to generate characteristic voltages. In addition, the pixel sensing circuit (130) converts the scaled characteristic voltages into digital data through an analog-to-digital converter (134), stores the digital data in a plurality of latches (135-1 to 135-n), and then converts the stored digital data into pixel sensing data (S_DATA), which is serial digital data, and transmits the converted digital data to a data processing circuit (150).

[0059] Referring to FIG. 3, the pixel sensing circuit (130) includes first to n-th sensing channels (SC1 to SCn, n is a natural number greater than 1), first to m-th channel selection multiplexers (131-1 to 131-m, m is a natural number greater than or equal to 1), first to m-th sample-and-hold scaler circuits (132-1 to 132-m), a selection unit (133), an analog-to-digital converter (134), first to n-th latches (135-1 to 135-n), and a parallel-to-serial conversion unit (136).

[0060] The pixel sensing circuit (130) receives an analog signal (Vsense / Isense) from each of the first to nth pixels (P1 to Pn) through the first to nth sensing channels (SC1 to SCn). For example, the pixel sensing circuit (130) can receive an analog signal (Vsense / Isense) from each of the n pixels constituting one horizontal line of the display panel (110) through the first to nth sensing channels (SC1 to SCn).

[0061] Each of the first to m-th channel selection multiplexers (131-1 to 131-m) is an i (i is a natural number greater than 1):1 multiplexer. For example, as illustrated in FIG. 3, each of the first to m-th channel selection multiplexers (131-1 to 131-m) may be a 4 (i=4):1 multiplexer, but is not limited thereto.

[0062] Each of the first to m-th channel selection multiplexers (131-1 to 131-m) is electrically connected to i pixels among n pixels, i.e., i*m pixels, and outputs an analog signal (Vsense / Isense) of one pixel among the connected pixels. Specifically, the first to m-th channel selection multiplexers (131-1 to 131-m) are electrically connected to i pixels among i*m pixels during each operation period, and outputs an analog signal (Vsense / Isense) of one pixel among the connected pixels as the first to m-th analog signal to each of the first to m-th sample-and-hold scaler circuits (132-1 to 132-m). For example, during the first operation section, the first channel selection multiplexer (131-1) may transmit the first analog signal, which is an analog signal (Vsense / Isense) of the first pixel (P1) among the first to fourth pixels (P1 to P4), to the first sample-and-hold scaler circuit (132-1), and the m-th channel selection multiplexer (131-m) may transmit the m-th analog signal, which is an analog signal (Vsense / Isense) of the n-th pixel (Pn) among the n-3 to n-th pixels, to the m-th sample-and-hold scaler circuit (132-m).

[0063] According to one embodiment of the present invention, each of the first to mth channel selection multiplexers (131-1 to 131-m) can be sequentially connected to any one of the connected pixels during each operation period. For example, during the first operation period, the first channel selection multiplexer (131-1) may be connected to the first pixel (P1) among the first to fourth pixels (P1 to P4), the m-th channel selection multiplexer (131-m) may be connected to the n-3-th pixel (Pn-3) among the n-3-th to n-th pixels (Pn-3 to Pn), and during the second operation period, the first channel selection multiplexer (131-1) may be sequentially connected to the second pixel (P2) among the first to fourth pixels (P1 to P4), and the m-th channel selection multiplexer (131-m) may be connected to the n-2-th pixel (Pn-2) among the n-3-th to n-th pixels (Pn-3 to Pn).

[0064] The first to mth sample-and-hold scaler circuits (132-1 to 132-m) sequentially sample and hold the first to mth analog signals received from the first to mth channel selection multiplexers (131-1 to 131-m) according to the sampling signal received from the data processing circuit (150), and scale the level of the held voltage to generate and output the first to mth characteristic voltages.

[0065] To this end, each of the first to mth sample and hold scaler circuits (132-1 to 132-m) may include a sampling circuit, a holding circuit, and a scaling circuit.

[0066] The sampling circuit can sample the received analog signal (Vsense / Isense). The sampling circuit can include an analog front end (AFE) circuit for converting current into voltage. The analog front end circuit can be, for example, an integrator. The integrator can integrate the current, which is an analog signal received from a pixel (P), to generate an integrated voltage. The sampling circuit can then transfer the integrated voltage to a holding circuit based on the sampling signal.

[0067] In particular, according to one embodiment of the present invention, the sampling circuit can receive an analog signal (Vsense / Isense) according to a sampling signal.

[0068] Although not shown, the sampling circuit may be configured with a sampling switch. Accordingly, when the sampling switch is turned on, a voltage obtained by sampling an analog signal (Vsense / Isense) received from a pixel (P) may be transmitted to a holding circuit.

[0069] The holding circuit can hold the characteristic voltage transmitted from the sampling circuit. To this end, the holding circuit can include a holding element, which can be, for example, a capacitor. That is, the holding circuit can include a holding capacitor and hold the sampled voltage in the holding capacitor.

[0070] A scaling circuit can scale the level of a voltage held in a holding circuit. The scaling circuit can include a scaling capacitor, and can generate and output a characteristic voltage by scaling the level of the held voltage using the capacitance relationship between the holding capacitor and the scaling capacitor included in the holding circuit.

[0071] According to one embodiment of the present invention, since a sample-and-hold scaler circuit is shared between pixels connected to each channel selection multiplexer, a single sample-and-hold scaler circuit can process analog signals (Vsense / Isense) received from a plurality of pixels. Accordingly, the total number of sample-and-hold scaler circuits can be reduced, and the size of the pixel sensing circuit can be reduced, thereby reducing the chip size of the source driver IC and reducing manufacturing costs.

[0072] The selection unit (133) sequentially selects the first to mth characteristic voltages by each of the first to mth sample and holder scaler circuits (132-1 to 132-m) and outputs them to the analog-to-digital converter (134).

[0073] The analog-to-digital converter (134) converts the first to mth characteristic voltages into the first to mth digital data (P_DATA1 to P_DATAm) during each operating section and stores them in a latch.

[0074] For example, the analog-to-digital converter (134) can convert the first to mth characteristic voltages into first to mth digital data (P_DATA1 to P_DATAm) during each operating section and store them in a latch, respectively. That is, the analog-to-digital converter (145) can sequentially convert the first characteristic voltage corresponding to the first pixel (P1), the second characteristic voltage corresponding to the fifth pixel (P5), …, the mth characteristic voltage corresponding to the n-3th pixel (Pn-3) into first to mth digital data and store them in a latch, respectively.

[0075] According to one embodiment of the present invention, the plurality of latches may be n latches, and may be first to n-th latches (135-1 to 135-n). During one operation period, m digital data are stored in each latch, and when the operation periods of each of the first to m-th channel selection multiplexers (131-1 to 131-m), the first to m-th sample-and-hold scaler circuits (132-1 to 132-m), and the analog-to-digital converter (134) are repeated i times, n digital data are stored in the first to n-th latches (135-1 to 135-n).

[0076] According to one embodiment of the present invention, by sharing each latch between pixels connected to each channel selection multiplexer, the total number of latches can be reduced, the size of the pixel sensing circuit can be reduced, and the chip size of the source driver IC can be reduced, thereby reducing manufacturing costs.

[0077] The parallel-to-serial conversion unit (136) serially converts n digital data stored in each of the first to nth latches (135-1 to 135n) to generate pixel sensing data (S_DATA), and outputs the pixel sensing data (S_DATA) to the data processing circuit (150).

[0078] Specifically, the parallel-to-serial conversion unit (136) converts n digital data stored in each of the first to nth latches (135-1 to 135-n) into serial data to generate pixel sensing data (S_DATA), which is serial digital data, and outputs the generated pixel sensing data (S_DATA) to the data processing circuit (150).

[0079] According to one embodiment of the present invention, the parallel-to-serial conversion unit (136) generates pixel sensing data (S_DATA) by serially converting the n digital data stored in the first to nth latches (135-1 to 135-n) when the operation sections of the first to mth channel selection multiplexers (131-1 to 131-m), the first to mth sample-and-hold scaler circuits (132-1 to 132-m), and the analog-to-digital converter (134) are repeated i times and n digital data are stored in the first to nth latches (135-1 to 135-n).

[0080] According to one embodiment of the present invention, by sharing a sample-and-hold scaler circuit and a latch between pixels connected to each channel selection multiplexer, the size of the pixel sensing circuit can be reduced, the chip size of the source driver IC can be reduced, and manufacturing costs can be reduced.

[0081] Hereinafter, a pixel sensing method according to one embodiment of the present invention will be described with reference to FIGS. 4 and 5.

[0082] FIG. 4 is a flow chart of a pixel sensing process according to one embodiment of the present invention, and FIG. 5 is a timing diagram of a pixel sensing circuit according to one embodiment of the present invention.

[0083] As the analog signals (Vsense / Isense) of n pixels (P1 to Pn in FIG. 3) are transmitted to the pixel sensing circuit (130), sensing of the characteristic values ​​of the pixels begins.

[0084] Referring to FIGS. 4 and 5, the pixel sensing circuit (130) senses the first to mth analog signals, which are analog signals of the k, …, k+i(m-1)th pixels (Pk, …, Pk+i(m-1)), among the analog signals (Vsense / Isense) of n pixels, i.e., the first to nth pixels (P1 to Pn), during the sensing time (Ts) of the kth operation section (k is a natural number greater than 1 and less than or equal to i) (S401).

[0085] Specifically, during the sensing time (Ts) of the kth operation section, analog signals (Vsense / Isense) are received by the pixel sensing circuit (130) from the first to nth pixels (P1 to Pn) through the first to nth sensing channels (SC1 to SCn), and the first to mth channel selection multiplexers (131-1 to 131-m) output the first to mth analog signals, which are analog signals of the kth, …, k+i(m-1)th pixels (Pk, …, Pk+i(m-1)) among the first to nth pixels (P1 to Pn), to the first to mth sample-and-hold scaler circuits (132-1 to 132-m).

[0086] For example, during the sensing time (Ts) of the first operation section, the first analog signal, which is the analog signal (Vsense / Isense) of the first pixel (P1), is output to the first channel selection multiplexer (131-1) through the first sensing channel (SC1), and the first channel selection multiplexer (131-1) selectively outputs the first analog signal among the first to fourth pixels (P1 to P4) to the first sample-and-hold scaler circuit (132-1). At the same time, the second analog signal, which is the analog signal (Vsense / Isense) of the fifth pixel (P5), is output to the second channel selection multiplexer (131-2) through the fifth sensing channel (SC5), and the second channel selection multiplexer (131-2) can output the second analog signal among the fifth to eighth pixels (P5 to P8) to the second sample-and-hold scaler circuit (132-2).

[0087] Afterwards, the sampling time of the kth motion section (T SD ) during which the first to mth analog signals are sampled, held, and scaled in the first to mth sample-and-hold scaler circuits (132-1 to 132-m) (S402). Specifically, each of the first to mth sample-and-hold scaler circuits (132-1 to 132-m) samples, holds, and scales the kth operating section at the sampling time (T SD) samples and holds the first to mth analog signals according to the sampling signal, scales the level of the held voltage, and generates and outputs the first to mth characteristic voltages.

[0088] For example, the sampling time (T) of the kth motion interval SD ), the first analog signal is sampled and held in the first sample-and-hold scaler circuit (132-1), and the level of the held voltage is scaled, the second analog signal is sampled and held in the second sample-and-hold scaler circuit (132-2), and the level of the held voltage is scaled, and the m analog signal is sampled and held in the m sample-and-hold scaler circuit (132-m), and the level of the held voltage is scaled, thereby generating and outputting the first to m characteristic voltages.

[0089] Afterwards, each of the first to mth characteristic voltages is converted into the first to mth digital data (P_DATA1 to P_DATAm) in the analog-to-digital converter (134) (S403).

[0090] Specifically, the first to m-th characteristic voltages are sequentially selected by the selection unit (133) and transmitted to the analog-to-digital converter (134), and since, for one operation section, the pixels selected by each channel multiplexer among n pixels are 1 / i of n (n=i*m) pixels, i.e., m, the first to m-th characteristic voltages are converted into first to m-th digital data (P_DATA1 to P_DATAm) in the analog-to-digital converter (134) during 1 / i (Tc / i) of the conversion time (Tc) required to convert the characteristic voltages of the n pixels. Each of the first to m-th digital data (P_DATA1 to P_DATAm) is stored in at least some of the first to n-th latches (135-1 to 135-n).

[0091] Thereafter, if k is less than i (S410, Y), i.e., if it is not the i-th operation section, the next operation section (k=k+1, S411) is performed. Steps S401 to S403 are repeated. The value of k can be set by the data processing circuit (150).

[0092] Meanwhile, when k is i (S410, N), i.e., when it is the i-th operation section, the first to m-th channel selection multiplexers (131-1 to 131-m), the first to m-th sample-and-hold scaler circuits (132-1 to 132-m), and the analog-to-digital converter (134) execute the operation section i times, so that the sensing, sampling, holding, scaling, and conversion processes of analog signals for n pixels are completed, and the transmission time (T T ), the pixel sensing data, which is converted into digital data stored in each of the first to nth latches (135-1 to 135-n) corresponding to n pixels, is output to the data processing circuit (150) (S412).

[0093] Specifically, in the parallel-to-serial conversion unit (136), the transmission time (T T ), the digital data stored in each of the first to nth latches (135-1 to 135-n) are converted serially to generate pixel sensing data (S_DATA), and the generated pixel sensing data (S_DATA) is output to the data processing circuit (150).

[0094] Accordingly, to sample, hold, and scale the analog signals (Vsense / Isense) of n pixels and generate pixel sensing data (S_DATA), which is serial digital data, and send it to the data processing circuit (150), iTs+iT SD +Tc+T T It takes time. For example, if each of the first to mth channel selection multiplexers (131-1 to 131-m) is a 4 (i=4):1 multiplexer, as shown in Fig. 5, 4Ts+4T SD +Tc+TT It may take some time.

[0095]

[0096] Hereinafter, with reference to FIGS. 6 to 8, a pixel sensing circuit and a pixel sensing method according to another embodiment of the present invention will be described.

[0097] FIG. 6 is a block diagram briefly showing the configuration of a pixel sensing circuit according to another embodiment of the present invention, FIG. 7 is a flow chart of a pixel sensing process according to another embodiment of the present invention, and FIG. 8 is a timing diagram of a pixel sensing circuit according to another embodiment of the present invention.

[0098] A pixel sensing circuit and a pixel sensing method according to another embodiment of the present invention are identical to the pixel sensing circuit and the pixel sensing method according to the above-described embodiment of the present invention, except that they include m latches instead of n latches, that some of different operation sections are executed simultaneously, and that m digital data stored in the latches are transmitted to each operation section. Accordingly, the following describes another embodiment of the present invention, focusing on differences from the above-described embodiment of the present invention.

[0099] A pixel sensing circuit (130) according to another embodiment of the present invention, unlike the pixel sensing circuit (130) according to an embodiment of the present invention, includes m latches, first to m-th latches (135-1 to 135-m), as illustrated in FIG. 6.

[0100] According to another embodiment of the present invention, the first to mth latches (135-1 to 135-m) store the first to mth digital data sequentially output from the analog-to-digital converter (134), respectively.

[0101] A parallel-to-serial conversion unit (136) according to another embodiment of the present invention serially converts the first to mth digital data stored in the first to mth latches (135-1 to 135-m) in each operation section to generate and output pixel sensing data.

[0102] A parallel-to-serial conversion unit (136) according to another embodiment of the present invention, unlike the parallel-to-serial conversion unit (136) according to an embodiment of the present invention, does not serially convert and transmit n digital data at once, but serially converts m digital data in each operation section and transmits them in i operation sections, thereby dividing and transmitting n digital data corresponding to a total of n pixels over i operation sections.

[0103] As the analog signals (Vsense / Isense) of n pixels (P1 to Pn in FIG. 3) are transmitted to the pixel sensing circuit (130), sensing of the characteristic values ​​of the pixels begins.

[0104] Referring to FIGS. 7 and 8, the pixel sensing circuit (130) senses the first to mth analog signals, which are analog signals of the kth, …, k+i(m-1)th pixels (Pk, …, Pk+i(m-1)), among the analog signals (Vsense / Isense) of n pixels, i.e., the first to nth pixels (P1 to Pn), during the sensing time (Ts) of the kth operation section (S701).

[0105] Specifically, during the sensing time (Ts) of the kth operation section, analog signals (Vsense / Isense) are received by the pixel sensing circuit (130) from the first to nth pixels (P1 to Pn) through the first to nth sensing channels (SC1 to SCn), and the first to mth channel selection multiplexers (131-1 to 131-m) output the first to mth analog signals, which are analog signals of the kth, …, k+i(m-1)th pixels (Pk, …, Pk+i(m-1)) among the first to nth pixels (P1 to Pn), to the first to mth sample-and-hold scaler circuits (132-1 to 132-m).

[0106] Afterwards, the sampling time of the kth motion section (T SD ) During the first to mth sample and hold scaler circuits (132-1 to 132-m), the first to mth analog signals are sampled, held, and scaled (S702).

[0107] Specifically, each of the first to mth sample-and-hold scaler circuits (132-1 to 132-m) determines the sampling time (T) of the kth operating section. SD ) samples and holds the first to mth analog signals according to the sampling signal, scales the level of the held voltage, and generates and outputs the first to mth characteristic voltages.

[0108] Afterwards, each of the first to mth characteristic voltages is converted into the first to mth digital data (P_DATA1 to P_DATAm) in the analog-to-digital converter (134) (S703).

[0109] Specifically, the first to m-th characteristic voltages are sequentially selected by the selection unit (133) and transmitted to the analog-to-digital converter (134). At this time, since the pixels selected by each channel multiplexer among the n pixels for one operation section are 1 / i of the n (n=i*m) pixels, i.e., m, the first to m-th characteristic voltages are converted into the first to m-th digital data (P_DATA1 to P_DATAm) in the analog-to-digital converter (134) during 1 / i (Tc / i) of the conversion time (Tc) required to convert the characteristic voltages of the n pixels. The first to m-th digital data (P_DATA1 to P_DATAm) are respectively stored in the first to m-th latches (135-1 to 135-m).

[0110] Thereafter, the first to mth digital data (P_DATA1 to P_DATAm) stored in each of the first to mth latches (135-1 to 135-m) are converted serially in the parallel-to-serial conversion unit (136) to generate pixel sensing data (S_DATA), and the pixel sensing data (S_DATA) is transmitted to the data processing circuit (150) (S704).

[0111] As mentioned above, for one operation section, since the number of pixels selected by each channel multiplexer among n pixels is 1 / i of n (n=i*m) pixels, i.e., m, the transmission time (T) required to convert n digital data corresponding to n pixels T ) of 1 / i(T T / i), the first to mth digital data (P_DATA1 to P_DATAm) stored in each of the first to mth latches (135-1 to 135-m) are converted serially to generate pixel sensing data (S_DATA), and the generated pixel sensing data (S_DATA) is transmitted to the data processing circuit (150).

[0112] For example, as shown in Fig. 6, if each of the first to mth channel selection multiplexers (131-1 to 131-m) is a 4 (i=4):1 multiplexer, T is applied to each operating section. T / 4 may take time.

[0113] Afterwards, if k is less than i (S705, YES), i.e., if it is not the i-th operation section, the next operation section (k=k+1, S711) is performed and steps S701 to S704 are repeated.

[0114] Meanwhile, when k is i (S705, NO), i.e., when it is the i-th operation section, the first to m-th channel selection multiplexers (131-1 to 131-m), the first to m-th sample-and-hold scaler circuits (132-1 to 132-m), the analog-to-digital converter (134), and the parallel-to-serial conversion unit (136) execute the operation section i times, so that the sensing, sampling, holding, scaling, and conversion processes and transmission of analog signals for n pixels are completed, and thus the sensing of characteristic voltages for n pixels is completed (S712).

[0115] According to another embodiment of the present invention, the k-th operation section of the parallel-to-serial conversion unit (136) can be executed simultaneously with the k+1-th operation section of the first to m-th channel selection multiplexers (131-1 to 131-m). Specifically, in the k-th operation section, the parallel-to-serial conversion unit (136) generates pixel sensing data by serially converting the first to m-th digital data (P_DATA1 to P_DATAm) and transmits it to the data processing circuit (150) (T T / 4) The step of sensing (Ts) the first to m-th analog signals, which are analog signals of the k, …, k+i(m-1)-th pixels (Pk, …, Pk+i(m-1)), among the analog signals (Vsense / Isense) of the first to n-th pixels (P1 to Pn) in the first to m-th channel selection multiplexers (131-1 to 131-m), in the k+1-th operation section, can be executed simultaneously.

[0116] Accordingly, to sample, hold, and scale the analog signals (Vsense / Isense) of n pixels and generate pixel sensing data (S_DATA), which is serial digital data, and send it to the data processing circuit (150), iTs+iT SD +Tc+T T / i time is required. For example, if each of the first to mth channel selection multiplexers (131-1 to 131-m) is a 4 (i=4):1 multiplexer, as shown in Fig. 8, 4Ts+4TSD+Tc+T T / 4 may take time.

[0117] Accordingly, according to another embodiment of the present invention, by sharing components of the pixel sensing circuit between a plurality of pixels, the area of ​​the pixel sensing circuit can be reduced, and the time required for pixel sensing can be reduced by simultaneously executing different steps in different operating sections.

[0118]

[0119] Hereinafter, with reference to FIG. 9, a pixel sensing method according to another embodiment of the present invention will be described.

[0120] Below, FIG. 9 is a timing diagram of a pixel sensing circuit according to another embodiment of the present invention.

[0121] A pixel sensing method of a pixel sensing circuit according to another embodiment of the present invention is the same as the pixel sensing method (Fig. 7) according to another embodiment of the present invention described above, except that the sensing time of the k+1th operation section and the conversion time of the kth operation section are executed simultaneously, and the sampling time of the k+1th operation section and the transmission time of the kth operation section are executed simultaneously. Accordingly, the following describes another embodiment of the present invention, focusing on the differences from the other embodiment of the present invention.

[0122] According to another embodiment of the present invention, the k-th operation section of the analog-to-digital converter (134) can be executed simultaneously with the k+1-th operation section of the first to m-th channel selection multiplexers (131-1 to 131-m). Specifically, in the k-th operation section, the step of converting (Tc / 4) the first to m-th characteristic voltages into the first to m-th digital data (P_DATA1 to P_DATAm) in the analog-to-digital converter (134) can be executed simultaneously with the step of sensing (Ts) the first to m-th analog signals, which are analog signals of the k, …, k+i(m-1)-th pixels (Pk, …, Pk+i(m-1)) among the analog signals (Vsense / Isense) of the first to n-th pixels (P1 to Pn), in the first to m-th channel selection multiplexers (131-1 to 131-m), in the k+1-th operation section.

[0123] In addition, according to another embodiment of the present invention, the k-th operation section of the parallel-to-serial conversion unit (136) can be executed simultaneously with the k+1-th operation section of the first to m-th sample-and-hold scaler circuits (132-1 to 132-m). Specifically, in the k-th operation section, the parallel-to-serial conversion unit (136) generates pixel sensing data by serially converting the first to m-th digital data (P_DATA1 to P_DATAm) and transmits it to the data processing circuit (150) (T T / 4) can be executed simultaneously with the step of sampling, holding, and scaling the first to mth analog signals in the first to mth sample-and-hold scaler circuits (132-1 to 132-m) in the k+1th operation section to output the first to mth characteristic voltages (Ts / 4).

[0124] Accordingly, to sample, hold, and scale the analog signals (Vsense / Isense) of n pixels and generate pixel sensing data (S_DATA), which is serial digital data, and transmit it to the data processing circuit (150), iTs+iT SD +Tc / i+T T / i takes time. For example, if each of the first to mth channel selection multiplexers (131-1 to 131-m) is a 4 (i=4):1 multiplexer, as shown in Fig. 8, 4Ts+4T SD +Tc / 4+T T / 4 may take time.

[0125] Accordingly, according to another embodiment of the present invention, by sharing components of the pixel sensing circuit between a plurality of pixels, the area of ​​the pixel sensing circuit can be reduced, and the time required for pixel sensing can be reduced by simultaneously executing different steps in different operating sections.

[0126]

[0127] Those skilled in the art will appreciate that the present invention described above can be implemented in other specific forms without changing the technical idea or essential features thereof.

[0128] Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included within the scope of the present invention.

[0129] The present invention can be used to manufacture an integrated circuit and a display device including a pixel sensing circuit.

Claims

1. A first to m-th channel selection multiplexer electrically connected to i pixels among i (i is a natural number greater than 1)*m (m is a natural number greater than or equal to 1) pixels of a display panel, and selectively outputting first to m-th analog signals received from any one of the i pixels during each operation section; A first to mth sample-and-hold scaler circuit for sampling, holding, and scaling the first to mth analog signals during each of the above operation periods to output the first to mth characteristic voltages, respectively; A selection unit for sequentially selecting and outputting the first to mth characteristic voltages; An analog-to-digital converter that converts each of the first to mth characteristic voltages into digital data during each of the above operation sections; and comprising a plurality of latches storing the above digital data; For the above one horizontal line, each of the first to m-th channel selection multiplexers, each of the first to m-th sample-and-hold scaler circuits, and the analog-to-digital converter is a pixel sensing circuit that repeats the operation section i times.

2. In paragraph 1, The above plurality of latches are first to i*mth latches, When each of the first to mth channel selection multiplexers and each of the first to mth sample-and-hold scaler circuits repeats an operation section i times, digital data corresponding to each of the i*m pixels constituting the one horizontal line is stored in each of the first to i*mth latches, A pixel sensing circuit further comprising a parallel-to-serial conversion unit that converts digital data stored in each of the first to i*mth latches into pixel sensing data, which is serial digital data, and outputs the converted data.

3. In paragraph 1, The above plurality of latches are first to mth latches, When each of the first to mth channel selection multiplexers and each of the first to mth sample-and-hold scaler circuits performs one operation section, digital data corresponding to each of the first to mth analog signals is stored in each of the first to mth latches. A pixel sensing circuit further comprising a parallel-to-serial conversion unit that converts digital data stored in each of the first to mth latches during each of the above operation sections into pixel sensing data, which is serial digital data, and outputs the converted data.

4. In paragraph 3, A pixel sensing circuit in which the kth (k is a natural number greater than or equal to 1 and less than i) operation section of the above parallel-serial conversion unit is executed simultaneously with the k+1th operation section of the above first to mth channel selection multiplexers.

5. In paragraph 3, A pixel sensing circuit in which the kth operation section (k is a natural number greater than or equal to 1 and less than i) of the above analog-to-digital converter is executed simultaneously with the k+1th operation section of the above first to mth channel selection multiplexers.

6. In paragraph 3, A pixel sensing circuit in which the kth operation (k is a natural number greater than or equal to 1 and less than i) of the above parallel-serial conversion unit is performed simultaneously with the k+1th operation of the above first to mth sample-and-holder scaler circuits.

7. A display panel displaying an image through at least one pixel; and A panel driving device for driving the above display panel is included; The above panel driving device, A first to m-th channel selection multiplexer electrically connected to i pixels among i (i is a natural number greater than 1)*m (m is a natural number greater than or equal to 1) pixels of the display panel, and selectively outputting first to m-th analog signals received from any one of the i pixels during each operation section; A first to mth sample-and-hold scaler circuit for sampling, holding, and scaling analog signals output from the first to mth channel selection multiplexers during each of the above operation sections to output first to mth characteristic voltages, respectively; A selection unit for sequentially selecting and outputting the first to mth characteristic voltages; An analog-to-digital converter that converts each of the first to mth characteristic voltages into digital data during each of the above operation sections; and a plurality of latches storing the above digital data; and A display device in which, for the above one horizontal line, each of the first to m-th channel selection multiplexers, each of the first to m-th sample-and-hold scaler circuits, and the analog-to-digital converter repeats the operation section i times.

8. In paragraph 7, The above plurality of latches are first to i*mth latches, When each of the first to mth channel selection multiplexers and each of the first to mth sample-and-hold scaler circuits repeats an operation section i times, digital data corresponding to each of the i*m pixels constituting the one horizontal line is stored in each of the first to i*mth latches, A display device further comprising a parallel-to-serial conversion unit that converts digital data stored in each of the first to i*mth latches during each of the above operation sections into pixel sensing data, which is serial digital data, and outputs the converted data.

9. In paragraph 7, The above plurality of latches are first to mth latches, When each of the first to mth channel selection multiplexers and each of the first to mth sample-and-hold scaler circuits performs one operation section, digital data corresponding to each of the first to mth analog signals is stored in each of the first to mth latches. Further comprising a parallel-to-serial conversion unit that converts digital data stored in each of the first to mth latches during each of the above operation sections into pixel sensing data, which is serial digital data, and outputs the converted data; A display device in which the kth (k is a natural number greater than or equal to 1 and less than i) operation section of the parallel-to-serial conversion unit is performed simultaneously with the k+1th operation section of the first to mth channel selection multiplexers.

10. In paragraph 7, The above plurality of latches are first to mth latches, When each of the first to mth channel selection multiplexers and each of the first to mth sample-and-hold scaler circuits performs one operation section, digital data corresponding to each of the first to mth analog signals is stored in each of the first to mth latches. Further comprising a parallel-to-serial conversion unit that converts digital data stored in each of the first to mth latches during each of the above operation sections into pixel sensing data, which is serial digital data, and outputs the converted data; The kth operation section (k is a natural number greater than or equal to 1 and less than i) of the above analog converter is performed simultaneously with the k+1th operation of the first to mth channel selection multiplexers. A display device in which the kth operation (k is a natural number greater than or equal to 1 and less than i) of the parallel-serial conversion unit is performed simultaneously with the k+1th operation of the first to mth sample-and-holder scaler circuits.

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