Impedance compensation circuit

Abstract

An integrated circuit (IC) chip is disclosed. The IC chip includes receiver circuitry having an input pin, a first input circuit coupled to the input pin, and a T-coil compensation circuit to compensate for a first parasitic capacitance associated with the first input circuit. An on-die termination (ODT) circuit is included that is separate from the first input circuit. A circuit including a resistor and an inductor is coupled in series between the T-coil compensation circuit and the ODT circuit. The circuit compensates for a second parasitic capacitance associated with the ODT circuit.

Description

IMPEDANCE COMPENSATION CIRCUITTECHNICAL FIELD

[0001] The disclosure herein relates to impedance compensation circuits, related methods, systems and integrated circuit chips that employ such circuits.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0003] FIG. 1 illustrates one embodiment of an integrated circuit chip that incorporates a dynamic impedance compensation circuit.

[0004] FIG. 2 illustrates a high-level flowchart of steps for operating the dynamic impedance compensation circuit of FIG. 1.

[0005] FIG. 3 illustrates one embodiment of a memory module that employs the dynamic impedance compensation circuit of FIG. 1.DETAILED DESCRIPTION

[0006] Embodiments of impedance compensation circuits, methods, systems and associated integrated circuit devices are disclosed herein. For one embodiment, an integrated circuit (IC) chip is disclosed. The IC chip includes receiver circuitry having an input pin, a first input circuit coupled to the input pin, and a T-coil compensation circuit to compensate for a first parasitic capacitance associated with the first input circuit. An on-die termination (ODT) circuit is included that is separate from the first input circuit. A circuitincluding a resistor and an inductor is coupled in series between the T-coil compensation circuit and the ODT circuit. The circuit compensates for a second parasitic capacitance associated with the ODT circuit. By supplementing the T-coil compensation circuit with the circuit that compensates for the second parasitic capacitance associated with the ODT circuit, the input impedance of the receiver circuit may be maintained at a substantially constant value over a wide range of frequencies. Suppressing changes to the input impedance in this fashion may improve the signal integrity of the receiver.

[0007] Referring now to FIG. 1, one embodiment of an integrated circuit (IC) chip 100 includes receiver circuitry 102 that includes a receiver 104 that is coupled to an input pin 106 of the IC chip 100. For one embodiment, a first input circuit 108 is coupled to the input pin 106 and exhibits a parasitic capacitance Ci. One specific embodiment of the first input circuit 108 employs an electrostatic discharge (ESD) circuit to suppress the impact of ESD voltages at the input pin 106. The receiver circuitry 102 also includes a termination circuit 120 for establishing a termination impedance ZT (with a resistor load component RL). For one specific embodiment, the termination circuit 120 takes the form of a configurable on- die termination (ODT) circuit.

[0008] Further referring to FIG. 1, for one embodiment, the receiver circuitry 102 is configured such that a first input impedance Zini looking into the input pin 106 exhibits an impedance value that matches a characteristic impedance of a transmission line (not shown) that couples to the input pin 106. For one embodiment, the transmission line may be a single-ended transmission line with a characteristic impedance of fifty ohms. Thus, for impedance-matching purposes, the desired first input impedance Zini is fifty ohms, which also matches the termination impedance ZT. However, the parasitic capacitance Ci alters the first input impedance Zini as a function of frequency by introducing the capacitivecomponent Ci. Degrading the impedance matching may cause reflections and reduce the effective frequency response of the receiver circuitry.

[0009] With continued reference to FIG. 1, to compensate for the parasitic capacitance Ci that is coupled to the input pin 106, a first stage of impedance compensation is performed by a T-coil compensation circuit 110 that is employed at the input pin 106. The T-coil compensation circuit 110 includes a T-shaped network of components including a first inductor Li, a second inductor L2 that is disposed in series with and mutually coupled to the first inductor Li, and a component segment 112 that bisects the two inductor components at node 114 and includes the parasitic capacitance CL The parasitic capacitance Ci couples to alternating-current (AC) ground at 116. For some embodiments, a bridge capacitance CB is provided in parallel with the series-coupled inductors Li and L2. The bridge capacitance may be realized as a separate capacitive structure, or realized through an overlapping of the first and second inductors in adjacent metal layers (not shown) of the IC chip 100. For one embodiment, the inductors Li and L2 are of the same inductance values and are mutually coupled in a same polarity orientation, with a mutual coupling parameter M that is configured to a value of L / 3. In one specific embodiment, each inductor takes the value of (.375)RL2CI, with the value of the bridge capacitance CB being (.125)Ci . When looking into the input pin 106, the T-coil compensation circuit 110 provides an enhancement to the input impedance Zini that offsets the impact of the capacitive component CL The net result provided by the T-coil compensation circuit 110 allows the input impedance Zini to exhibit a relatively constant value through a wide range of frequencies that is equal to the termination impedance ZT.

[0010] For some embodiments, the termination circuit 120 employs a configurable resistance circuit represented by load resistance RL that is coupled to a power supply voltage VDD, and includes a network of selectable resistor sub-circuits. A givenprogrammable combination of one or more of the resistor sub-circuits may thus exhibit the desired termination resistance RL, such as fifty ohms, to match the transmission line impedance. However, due to the network of resistive elements involved in the resistor network, a second source of undesirable parasitic capacitance, referred to herein as a parasitic load capacitance CL, may impact the value of the termination impedance ZT by causing the termination impedance ZT to vary depending on frequency. Since the T-coil compensation circuit 110 generally functions to allow the input impedance Zini to exhibit a relatively constant value that is equal to the termination impedance ZT through a wide range of frequencies, maintaining the termination impedance ZT at a desired value through the wide range of frequencies is as important to successful impedance matching as maintaining the input impedance Zini constant through the wide range of frequencies.

[0011] Further referring to FIG. 1, to compensate for the parasitic load capacitance CL that arises from the resistor network of the termination circuit 120, a second stage of impedance compensation is performed by a supplemental compensation circuit 122 that is employed in series between the T-coil compensation circuit 112 and the termination circuit 120. The supplemental compensation circuit 122 includes a compensation resistor Rc disposed in parallel with a compensation inductor Lc. For one embodiment, the compensated termination impedance ZT may be made independent of frequency by configuring the compensation resistance Rc to be equal to the termination resistance RL, and setting the value of the compensation inductor Lc based on the values of the parasitic load capacitance CL and the termination resistance RL according to the relationship Lc = RL2CL.

[0012] Thus, during operation, as signals are being received by the input pin 106, a multi-stage impedance compensation process is performed by the receiver circuitry 102 to maintain the signal integrity of the input signals being received at the input pin 106 andpassed to the receiver 104. The multi-stage process involves compensating for parasitic input capacitance at the input pin 106 during a first stage of compensation that is performed by the T-coil compensation circuit 112, and also compensating for parasitic load capacitance at the termination circuit 120 during a second stage of compensation that is performed by the supplemental compensation circuit 122.

[0013] FIG. 2 illustrates a flowchart of steps for one embodiment of a method that may be performed to operate the IC chip 100 in a manner that improves the frequency response of the receiver circuitry 102. The method generally corresponds to how the IC chip 100 operates under typical circumstances and involves receiving a signal at the input pin 106 of the IC chip 100, at 202. At 204, ESD voltages are suppressed at the input pin 106 by the ESD circuit 108. Using the T-coil compensation circuit 112, the first parasitic capacitance Ci associated with the ESD circuit 108 is compensated-for, at 206. This first stage of compensation maintains the input impedance, as seen looking into the input pin, at a value that is independent of frequency, and thus relatively constant across a wide range of frequencies. At 208, the input pin 108 is terminated with the termination impedance circuit 120. The supplemental compensation circuit 122 compensates, at 210, using the compensation resistor RC and the compensation inductor LC, for the second parasitic capacitance CT associated with the termination impedance circuit 120. This second stage of compensation also maintains the termination impedance, as seen looking into the supplemental compensation circuit, at a value that is independent of frequency, and thus relatively constant across a wide range of frequencies. Configuring the input impedance and the termination impedance as impedance components that are each independent of frequency prevents undesirable impedance mismatches to degrade the signal integrity of signals received at the input pin 106.

[0014] Referring now to FIG. 3, for one embodiment, the receiver circuitry 102 lends itself well for use in a multiplexed registered clock driver (MRCD) integrated circuit chip 310 employed on a dynamic random access memory (DRAM) module 300. The memory module 300 generally includes a module substrate 302 that mounts one or more groups of memory devices 306. The MRCD IC chip 310 couples to the one or more groups of memory devices 306 via a secondary interface 312 and provides a buffering function for command and address (C / A) signals that are received via a primary interface 314 from a memory controller (not shown). C / A signals that are received by the primary interface 314 of the MRCD buffer chip 310 are then re-transmitted via the secondary interface 312 to the one or more groups of memory devices 306.

[0015] When received within a computer system via one or more computer-readable media, such data and / or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

[0016] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternativeembodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “ / ” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘ < signal name > ’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in responseto a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement.

[0017] While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMSWe Claim:

1. An integrated circuit (IC) chip, comprising: receiver circuitry including: an input pin; a first input circuit coupled to the input pin; a T-coil compensation circuit to compensate for a first parasitic capacitance associated with the first input circuit; an on-die termination (ODT) circuit separate from the first input circuit; and a circuit including a resistor and an inductor, the circuit coupled in series between the T-coil compensation circuit and the ODT circuit, the circuit to compensate for a second parasitic capacitance associated with the ODT circuit.

2. The IC chip of claim 1, wherein: the ODT circuit is to exhibit an impedance that includes a first resistance and the second parasitic capacitance; and the circuit is to compensate for changes in the impedance that are dependent on frequencies associated with signals received at the input pin.

3. The IC chip of claim 2, wherein: the inductor is coupled in parallel with the resistor.

4. The IC chip of claim 3, wherein: the resistor exhibits a second resistance; and the second resistance is set to match the first resistance.

5. The IC chip of claim 4, wherein: the ODT circuit further comprises a first programmable resistor network responsive to a mode register value to configure the first programmable resistor network to exhibit the first resistance; and the circuit further comprises a second programmable resistor network responsive to the mode register value to configure the second programmable resistor network to exhibit the first resistance.

6. The IC chip of claim 1, wherein the T-coil compensation circuit further comprises: a second inductor; and a third inductor mutually coupled with the second inductor to form a series- coupled node and disposed in a stacked relationship with the second inductor.

7. The IC chip of claim 6, wherein: a first inductance value of the second inductor matches a second inductance value of the third inductor; and wherein the first input circuit is coupled to the series-coupled node.

8. The IC chip of claim 1, wherein: the first input circuit comprises an electrostatic discharge (ESD) circuit.

9. The IC chip of claim 1, realized as an IC buffer chip.

10. An integrated circuit (IC) buffer chip, comprising: a primary interface including: an input pin for receiving signals from a memory controller; an electrostatic discharge (ESD) circuit coupled to the input pin; a T-coil compensation circuit to compensate for a first parasitic capacitance associated with the ESD circuit;an on-die termination (ODT) circuit; and a circuit including a resistor and an inductor, the circuit coupled in series between the T-coil compensation circuit and the ODT circuit, the circuit to compensate for a second parasitic capacitance associated with the ODT circuit.

11. The IC buffer chip of claim 10, wherein: the ODT circuit is to exhibit an impedance that includes a first resistance and the second parasitic capacitance; and the circuit is to compensate for changes in the impedance that are dependent on frequencies associated with signals received at the input pin.

12. The IC buffer chip of claim 10, wherein: the resistor exhibits a second resistance; and the inductor that is coupled in parallel with the resistor.

13. The IC buffer chip of claim 12, wherein: the second resistance is set to match the first resistance.

14. The IC buffer chip of claim 13, wherein: the ODT circuit further comprises a first programmable resistor network responsive to a mode register value to configure the first programmable resistor network to exhibit the first resistance; and the circuit further comprises a second programmable resistor network responsive to the mode register value to configure the second programmable resistor network to exhibit the first resistance.

15. The IC buffer chip of claim 10, wherein the T-coil compensation circuit further comprises: a second inductor; and a third inductor mutually coupled with the second inductor to form a series- coupled node and disposed in a stacked relationship with the second inductor.

16. The IC buffer chip of claim 15, wherein: a first inductance value of the second inductor matches a second inductance value of the third inductor; and wherein the first input circuit is coupled to the series-coupled node.

17. The IC buffer chip of claim 10, realized as a multiplexed registered clock driver (MRCD) IC chip.

18. A method of operation in an integrated circuit (IC) chip, comprising: receiving a signal at an input pin of the IC chip; suppressing electrostatic discharge (ESD) voltages at the input pin with an ESD circuit; compensating, using a T-coil, for a first parasitic capacitance associated with the ESD circuit; terminating the input pin with an on-die termination (ODT) circuit that is separate from the first input circuit; and compensating, using a circuit that includes a resistor and an inductor, the circuit disposed in series between the T-coil and the ODT circuit, for a second parasitic capacitance associated with the ODT circuit.

19. The method of claim 18, wherein: the terminating of the input pin with the ODT circuit includes establishing an impedance that includes a first resistance and the second parasitic capacitance; and wherein compensating, using the circuit, includes compensating for changes in the impedance that are dependent on frequencies associated with signals received at the input pin.

20. The method of claim 19, wherein: the terminating of the input pin with the ODT circuit further comprises setting a mode register value to configure a first programmable resistor network to exhibit the first resistance; and wherein the compensating, using the circuit, further comprises configuring a second programmable resistor network that is responsive to the mode register value to exhibit the first resistance.

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