Micro-electro-mechanical systems (MEMS) having vertical stops and anchor structures

Abstract

A semiconductor device having a single crystal substrate, a moving mass structure, and vertical stop(s) formed monolithically with the moving mass structure and configured to limit its movement. Manufacture of the device in reliance on global alignment key(s), with the use of an intermediate layer overlying the substrate and a device layer containing the moving mass structure and the stop(s) and overlying the intermediate layer. The device layer and the intermediate layer are single crystal materials substantially free from strain. The moving mass structure is mechanically coupled to at least one anchor rooted in the substrate and is freed to maneuver with respect to the substrate by removing portion(s) of the intermediate layer.

Description

MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) HAVING VERTICAL STOPS AND ANCHOR STRUCTURESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This International Patent Application claims priority from the benefit of the US Patent Application No. 18 / 533,820 filed on December 08, 2023, the disclosure of which is incorporated by reference herein.TECHNICAL FIELD

[0002] The present invention relates to semiconductor device manufacture and, in particular, to methods of manufacture of Micro-Electro-Mechanical Systems (MEMS) devices.RELATED ART

[0003] Micro-Electro-Mechanical Systems (MEMS) devices are, simply put, three- dimensional physical structures that generally combine both mechanical components (formed in or on a semiconductor substrate) and electronic components ( designed to produce electrical signals representing operation of the MEMS devices) and that are used in a wide variety of applications for various purposes such as optical or radio-frequency switches or relays, displays, atomic force microscopy, ultrasound transducers, or for performing various measurements. For example, sensors that measure physical parameters (such as acceleration, rotation, angular velocity, humidity, or pressure, for example) can be implemented in a form of MEMS device to produce an electrical signal representing a physical parameter being measured and to transfer such signal to an appropriate electronic circuitry to utilize the quantitative measurement. The MEMS device transduces the parameter being measured into an equivalent electrical parameter such as voltage, current, resistance, resonant frequency etc. The transduction principle used by the MEMs device may be capacitive, piezoresistive, piezoelectric, optical, magnetic among others.

[0004] Typically, a MEMS device has a moving component or element, the purpose of which is to change its position in relation to a static component of the MEMS device (such as the semiconductor substrate in which the MEMS device is formed, for example) during a given measurement performed with the use of the MEMS device. The moving element is often configured to be suspended from the semiconductor substrate with support of one or more so-called anchors incorporated in the MEMS device and attached to the carrying semiconductor substrate.

[0005] The supporting anchor(s) must be strong enough to not only support the moving element but also to withstand the stress exerted by the moving element under the forces applied by theparameter being measured. In addition, the anchors must also enable the electrical isolation of different elements of the MEMS device that are required to be at different potentials or voltages. As is often the case, the manufacture of the anchor can be ven complex, thereby increasing the cost of the overall MEMS device.

[0006] As a skilled artisan readily appreciates, the movement of the moving components of the MEMS device is necessarily limited by design. For example, in the situation when a given MEMS device is configured as a (part of) the measuring device, the spacing between the moving component (or element, or mass) of such MEMS device and the static carrying semiconductor substrate of the MEMS device is often determined by manufacturing constraints and a range required for a physical parameter being measured by the MEMS device.

[0007] In a situation when the value of the parameter being measured causes the response of the MEMS device to exceed its useful operational range (such as during shock), the moving mass can come in contact with the semiconductor substrate, often leading to damage of the MEMS device. Further, because of such undesired contact, the moving mass can also “stick” to the semiconductor substrate due to surface tension or adhesion forces and not return to a quiescent position (which effect is often referred to as stiction between the moving mass and the semiconductor substrate). A so-called stop structure (or simply “stop”) is often added to the moving mass (or portion) of the MEMS device to reduce the effects of stiction. A stop is a physical element designed to limit the movement of a movable part within the MEMS device, essentially acting as a mechanical barrier to prevent over-travel or damage by defining the maximum displacement allowed in a specific direction. As is well known in related art, MEMS devices employing stop structure (including stop structures themselves) are typically formed at the device level through judicious definition of areas and elements formed via multiple and differing materials deposition and removal steps in a laborious, complex, and rather costly multi-step fabrication process, which typically includes the formation of areas or elements of the overall MEMS structure dedicated to spatial alignment needed for various lithographic steps. The state-of-the-art dictates that, in the process of manufacture of a stop structure, several different materials be used and that, in some cases, the location of a stop structure substantially differ from the location of the moving MEMS mass. It is well recognized in related art that adding a stop - while often is critical for proper operation of a MEMS device - generally substantially complicates not only design but also practical implementation of the MEMS device.

[0008] The skilled person will appreciate, therefore, that a reconsideration of the conventional methodology / ies of such fabrication is, therefore, overdue, and that the need to devise the process of manufacture of the stop structure and the moving mass in a given MEMS device to be monolithic with one another in a fashion that necessarily simplifies manufacturability of such device incorporating themoving-mass-supporting anchors and allows to avoid multiple growth / re-growth / masking / bonding steps during the manufacturing process to improve reliability and performance of the resulting device.SUMMARY OF THE INVENTION

[0009] Embodiments of the invention provide a microelectromechanical system sensor that includes a substrate, an intermediate layer overlying and carried by the substrate, a device layer disposed above the intermediate layer, and an anchor structure that is rooted in the substrate, that protrudes away from the substrate, and that is electrically insulated from the substrate. The device layer includes a moving mass that is configured to move with respect to the substrate and that carries a stop structure (the stop structure being monolithic with the moving mass and that extending from the moving mass towards the substrate). Material of each of the substrate, the intermediate layer, and the device layer is a corresponding single crystal material, and the moving mass is structurally connected to the anchor with a spring structure. In at least one specific case, the spring structure is monolithic with the moving mass and with the stop structure and / or the substrate comprises single crystal silicon and / or the intermediate layer comprises single crystal silicon germanium. Optionally, and substantially in every implementation, each of the intermediate layer and the device layer may have a corresponding thickness greater than a respective critical thickness and / or the spring structure may have a spring force that exceeds a force of stiction between the stop structure and the substrate. Substantially in every embodiment, the sensor contains a global alignment key in at least one of the intermediate layer and the substrate, which key is dimensioned such that - during a formation of an overlying material layer carried by a layer containing the global alignment key - the overlying material layer substantially is not planarized above the global alignment key (but, instead, contains a visually-perceivable recess or indentation at a location above the global alignment key in the intermediate layer and the substrate. Alternatively or in addition - and substantially in every implementation of the sensor - the intermediate layer and the device layer may be epitaxial layers, that are substantially free from stress caused by dislocations. In at least one case, the sensor is devoid of a material of the intermediate layer between the moving mass and the substrate. (Here, in one specific arrangement, the sensor may be lacking the material of the intermediate layer between the moving mass and the substrate substantially at every point between two immediately neighboring anchor structures. Optionally, the sensor has a gap between a first surface of a portion of the device layer that is immediately affixed to a layer of material electrically insulating the anchor structure from the substrate and a second surface of the substrate, the first and second surfaces facing each other.) Alternatively or in addition, and substantially in every embodiment, the sensor may include a recess formed in the substrate and spatially aligned with an opening that is formed through the device layer (such recess and the opening containing the anchor structure in contact with each of the device layer and the substrate) and, optionally,the anchor structure may be dimensioned as a column extending transversely to the substrate, said column including a polycrystalline silicon core and a silicon nitride overlayer. (In the latter case, the sensor may be structured to be devoid of contact between the device layer and the polycrystalline silicon core and between the substrate and the polycrystallinc silicon core.)

[0010] Embodiments further provide a method that includes fabricating substantially every embodiment of the sensor alluded to above by taking at least the following steps: a step of covering a substrate of a first semiconductor material with an intermediate layer of a second semiconductor material containing dislocations to form a two-layer semiconductor structure in which the intermediate layer is substantially devoid of strain; a step of dimensioning a first recessed region in the intermediate layer to cause a material layer grown over the first recessed region substantially planarized over the first recessed region; a step of shaping the two-layer semiconductor structure to form a second recessed region therein (here, the second recessed region is dimensioned to have a material layer grown over the second recessed region to not be planarized above the second recessed region); a step of forming a device layer of a third semiconductor material over the intermediate layer to fill the first recessed region to produce a stop structure extending towards the substrate; a step of isolating a portion of the device layer configured as a moving mass from a stationary portion of the device layer by at least etching the device layer; and a step of releasing the moving mass that is monolithic with the stop structure by etching the intermediate layer to enable a combination of the moving mass and the stop structure to reposition by a predetermined distance with respect to the substrate. Here, material of each of the substrate, the intermediate layer, and the device layer is a respective single crystal material. In at least one specific implementation of the method, material of each of the semiconductor substrate and the device layer includes silicon, while the intermediate layer includes silicon germanium. Optionally, an embodiment of the method may additionally include the step of forming an anchor structure rooted in the substrate and having a core and a dielectric material electrically insulating the core from the substrate; and the step of forming a spring structure attached to the anchor structure and mechanically coupling the anchor structure and the moving mass. (In this latter case, the step of forming the anchor structure may incorporate forming the anchor structure that contains the dielectric material electrically insulating the core from the third semiconductor material.) Optionally , the step of forming the anchor structure may include the step of etching the device layer and the intermediate layer to form a void therethrough (which step of performed after the step of dimensioning the first recessed region and the step of shaping the two-layer semiconductor structure), as well as (i) the step of depositing a conformal dielectric material layer to cover a surface of the void and to be in contact with a first surface of the substrate, (ii) the step of filling at least a portion of the void with a material of the core of the anchor structure in contact with the conformal dielectric material, and the step of (iii) removing a portion of the conformal dielectric material and the material of the core to define asubstantially planar surface terminating the device layer, the conformal dielectric material, and the material of the core. Alternatively or in addition, and substantially in every implementation of the method, the step of forming a spring structure may include forming the spring structure having a spring force greater than a force of stiction between the stop structure and the substrate. Optionally, in an implementation of the method, the covering the substrate may include growing the intermediate layer in an epitaxial reactor beyond a corresponding critical thickness to form dislocations therein and / or the step of forming a device layer of a third semiconductor material may include epitaxially growing the device layer beyond a corresponding critical thickness to produce a grown device layer that is substantially strain free. Alternatively or in addition, and substantially in every implementation, the method may include a step of etching the one or more recessed regions in the intermediate layer of the second material during or with a timed etch to not expose the underlying substrate. Substantially in every embodiment of the method, the step of dimensioning a first recessed region in the intermediate layer may include etching the first recessed region to expose a surface of the substrate and / or the step of shaping the two-layer semiconductor structure to form a second recessed region may include etching both the intermediate layer and the substrate to form the second recessed region extending into the substrate. Optionally, an in every implementation, the method may contain a step of at least partially filling the first recessed region with a conformal auxiliary intermediate layer of a predetermined thickness that is substantially equal to the predetermined distance (in this case, the step of releasing the moving mass includes etching the conformal auxiliary intermediate layer that underlies the device layer.)BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The invention will be more fully understood by referring to the following Detailed Description of Specific Embodiments in conjunction with the not-to scale Drawings, of which:

[0012] FIG. 1 illustrates a semiconductor substrate;

[0013] FIG. 2 depicts an intermediate layer overlying the semiconductor substrate;

[0014] FIG. 3 provides a schematic of recessed regions formed in the intermediate layer and a global alignment key formed in the intermediate layer and the substrate, in accordance with an embodiment of the invention;

[0015] FIG. 4 depicts the layered structure in which the device layer includes one or more stops and is carried by the intermediate layer;

[0016] FIG. 5 is an illustration of the formation of the engineered substrate of an embodiment of the device of the invention in which the surface roughness of the device layer is reduced and / or removed with the use of Chemical Mechanical Polishing (CMP);

[0017] FIG. 6 shows a portion of the modified engineered substrate of FIG. 5 containing openings or voids formed in the device layer and the intermediate layer;

[0018] FIG. 7 illustrates the formation of anchor structure preform(s) by refilling the voids of the modified engineered substrate;

[0019] FIG. 8 illustrates the result of planarization of the upper surface of the overall semiconductor structure by removal of a predetermined upper portion thereof;

[0020] FIG. 9 depicts a processing step of preparation for selective modification of the intermediate layer of the overall semiconductor structure;

[0021] FIG. 10 is a portion of a cross-sectional view of a semiconductor device formed according to the idea of the present invention, in which the anchor structure preforms have been transformed to the anchor structures supporting a moving mass with monolithic stop structure(s);

[0022] FIG. 11 is a schematic top view of an embodiment of the MEMS device fabricated according to the idea of the invention;

[0023] FIGs. 12 and 13 illustrate a single-crystal semiconductor material substrate and such substrate carrying a first single-crystal intermediate layer, respectively;

[0024] FIG. 14 is an illustration of recessed regions formed in the first single-crystal intermediate layer;

[0025] FIG. 15 depicts the structure of FIG. 14, in which the recessed regions are filled by deposition with a second single-crystal intermediate layer;

[0026] FIG. 16 shows the structure of FIG. 15 overgrown with a single-crystal device layer the top of which contains roughness, while FIG. 17 depicts the same with the upper surface of which has been planarized by removing such roughness;

[0027] FIG. 18 depicts formation of anchor structure preforms in an embodiment of the invention;

[0028] FIG. 19 shown a modification of the structure of FIG. 18 in preparation to selective removal of intermediate layer(s) by etching through openings formed in such structure;

[0029] FIG. 20 is an illustration of an embodiment of the MEMS device formed according to the idea of the invention, in which the anchor structure preforms are transformed to anchor structure(s) supporting the moving mass carrying stop structure(s).

[0030] Generally, the sizes and relative scales of elements in Drawings may be set to be different from actual ones to appropriately facilitate simplicity, clarity, and understanding of the Drawings. For the same reason, not all elements present in one Drawing may necessarily be shown in another.DETAILED DESCRIPTION

[0031] Embodiments of the invention address the persisting in related art problem of complexity of manufacturing processes of a MEMS device employing a moving mass and a stop structure configured to limit the movement of such moving mass by devising a methodology of formation of such MEMS device (and, in particular, of the MEMS sensor device) in which material layer that is generated and / or modified with the purpose of forming such moving mass and the stop structure is a substantially single crystal material layer, while at the same time employing judiciously dimensioned anchor structures to suspend the moving mass with respect to substantially static (that is, not moving during the process of operation of the MEMS device) portions or elements. The judicious use of global alignment keys - the structural features permanently formed in the substrate layer of the device that are not modified throughout the process of manufacture - facilitate the simplification of the proposed methodology as compared with that of related art.

[0032] In particular, in at least one specific and non-limiting case (as the skilled person will understand from the discussion presented below), implementation of the methodology of the device results in formation of a MEMS sensorthat includes a substrate of a single crystal material (preferably but not necessarily silicon), a single crystal material intermediate layer overlying and carried by the substrate (and preferably but not necessarily containing silicon germanium, SiGe), a single crystal device layer disposed above the intermediate layer and including a moving mass (configured to move with respect to the substrate and carrying a stop structure that is monolithic with the moving mass and that extends from the moving mass towards the substrate), and an anchor structure rooted in the substrate and protruding away from the substrate and electrically insulated from the substrate. The moving mass is structurally connected to the anchor structure with the use of a spring structure. Preferably but not necessarily, at least one of the intermediate layer and the device layer has a corresponding thickness that is greater than a respective critical thickness (which, as is known in the art, depends on the properties of the device layer and intermediate layer and the growth conditions of these layers). Preferably but not necessarily, the spring structure is defined to have a spring force that exceeds a force of stiction between the stop structure and the substrate (that is, that exceeds a stiction force required to release the stop structure from the substrate when the stop structure abuts the substrate in static friction contact with the substrate). (In other words, the term "stiction force" - or, “force of stiction” - is defined in related at to refer to the minimumforce required to initiate movement between two stationary surfaces that are in contact with each other to essentially overcome the static friction that exists when objects are at rest.)

[0033] FIGs. 1 through 10 illustrate an example of the proposed fabrication methodology for fabrication of semiconductor devices such as MEMS sensors and actuators, microfluidic devices, optical devices, magnetic devices, to name just a few. As discussed below, an embodiment of such semiconductor device may be manufactured with the use of a single crystalline (or, single crystal) silicon wafer used as the semiconductor substrate, although other semiconductor substrates such as single-crystal SOI (Silicon on Insulator), single crystal GaAs (Gallium Arsenide), single crystal GaN (Gallium Nitride), single crystal SiC (Silicon Carbide), single crystal InP (Indium Phosphide) among other single crystal materials may optionally be used in related embodiments. The general flow of the methodology of fabrication of an embodiment of the invention is as follows: formation of the intermediate single-crystal material layer on a single-crystal substrate is followed by generation of a structural pattern that combines the appropriate recess(es) in the intermediate layer and the global alignment key(s) both in the intermediate layer and the substrate; growing of the single-crystal material device layer on top of the patterned combination of the substrate and the intermediate layer with transfer of the global alignment key(s) to an upper surface of the device layer; lithographic patterning of the features of the targeted MEMS device aligned to the so-transferred global alignment key(s) and etching of the device layer to identify the structure of the targeted MEMS device; and releasing a moving mass portion, of the targeted MEMS device, with stop structure(s) on such moving mass portion, by appropriate release etching procedure.

[0034] FIG. 1 schematically depicts a single crystal (or monocrystalline) semiconductor (such as silicon, in one case) substrate 100, which may be optionally doped to provide a bulk resistivity within a range from about 0.001 ohm-cm to about 10,000 ohm-cm. The n-type or p-type doping may be implemented with the use of arsenic, antimony, phosphorus, or boron, to name but a few.

[0035] FIG. 2 shows an intermediate layer 200 formed (for example, epitaxially grown) on the substrate 100 and carried by the substrate 100 in a processing step employing another single crystal material that is different from the material of the substrate 100 (for example, silicon germanium). The formation of the layer 200 that is overlying the substrate 100 is accomplished in such a fashion as to ensure that the layer 200 is substantially relaxed and substantially has no strain throughout the layer, in particular by appropriately varying or modulating the thickness of the layer being grown, gas precursors, temperatures, ramp rate, flow rates, and other process conditions. In particular, the structural relaxation of the intermediate layer 200 may be achieved with the specific variation of the growth conditions that lead to formation of dislocations by breaking of bonds due to the mismatch of the lattice parameters between the atoms of the semiconductor substrate 100 and the intermediate layer 200 being grown. Forexample, the intermediate layer 200 may be grown beyond the critical thickness that corresponds to the chosen growth conditions of temperature and other process parameters. (As is well known in the art, the term "critical thickness" of a material layer generally refers to the specific thickness at which a significant change in the behavior of such layer occurs (often related to the onset of plastic deformation, dislocation formation, or a shift in physical properties, usually due to accumulated strain within the layer, particularly when dealing with layers formed on a substrate with a different lattice structure. In a simple case, a critical thickness may be viewed as the limit of the thickness of the material layer at which the strain in the layer is still elastically accommodated. See, for example, www.sciencedirect.com / topics / en meerin / critical-thickness)

[0036] In one example, the relaxation of strain in the intermediate layer configured as the single crystal layer of SiGe may be achieved due to misfit dislocations and threading dislocations with the spatial density of these defects in the range of 109 / cm2.

[0037] In a related embodiment, the strain in the intermediate layer 200 may be relieved by introducing, into the layer 200, an atom of material that is different from the chosen single crystalline material of the layer 200. The intermediate layer 200 may be accomplished by epitaxially growing multiple (sub)layers of the chosen single crystal semiconductor material with each (sub)layer having a growth rate and / or temperature and / or gas precursor and / or flow rates and / or other process parameters that is / are different from the corresponding parameters used during the growth of another (sub)layer. In one example, the intermediate layer was formed by growing four (sub)layers of SiGe, each (sub)layer being about 250 nm thick, which resulted in an aggregate thickness of the intermediate layer 200 of about 1 mm. In various practical implementations, the intermediate layer was grown at various temperatures between about 850 °C and 1050 °C at atmospheric pressure, with a GeCU precursor flow rate between about 300 standard cubic centimeters per minute (seem) and 400 seem and a dichlorosilane (DCS) precursor flow rate between about 70 seem and 130 seem or between about 80 and 120 seem, with the use of hydrogen (H2) as the carrier gas flowing at a rate between about 40 standard liters per minute (slm)to 50 slm. In embodiments where multiple SiGe (sub)layers were used to form the overall intermediate layer, the flow rate of at least one precursor gas was optionally adjusted (e.g., GeC14 flow rate was increased from 300 seem for the first (sub)layerto 400 seem for the last (sub)layer, or varied between 300 seem and 400 seem for each (sub)layer, and / or the DCS flow rate was decreased from 120 seem for the first (sub)layer to 80 seem for the last (sub)layer or varied between 80 seem and 120 seem for each (sub)layer) to provide (sub)layers with differing compositions, or a composition gradient within the intermediate layer and to modify strain within each of the (sub)layers in the intermediate layer and to allow control of the propagation of threading dislocations that may be generated by strain relaxation in the overall SiGe intermediate layer.

[0038] In one example of the embodiment - and in further reference to FIG. 2 - the intermediate layer 200 is epitaxially grown as a single-crystal-sihcon germanium layer on top of the single-crystal-silicon substrate 100. The composition of silicon germanium (SiGe) may be represented by the formula Si(i.x)Gex, where;‘x” represents the mole fraction as a percentage of Germanium (Ge) in the Silicon Germanium (SiGe) alloy. The mole fraction percentage of Ge, represented by “x” may be chosen, depending on the specific implementation, between 1% and 100%. The fraction of Ge in the Si(i.X)Gexalloy may be modulated according to the particular application of intermediate layer 200 during the formation of a semiconductor device. In one embodiment, intermediate layer 200 comprises between 20% and 40% of Ge in the SiGe alloy, preferably between 25% and 35%, and most preferably about 30% of Ge in the SiGe alloy.

[0039] In one specific case, the intermediate layer 200 is configured as a composite layer formed by growing such multiple (sub)layers is relaxed by growing each (sub)layer of the composite beyond the corresponding critical thickness to ensure that the subsequently grown (sub)layer is formed under reduced internal strain. Alternatively or in addition, the intermediate layer 200 may be formed from multiple (sub)layers with thermal annealing employed between subsequent epitaxial growth (sub)steps such that the internal strain is relieved by formation of dislocations throughout the overall layer 200. Optionally, the intermediate layer 200 may be doped during the epitaxial growth process by introducing the n-t pe or p-type dopants to vary the properties of intermediate layer 200 for subsequent processes. The overall thickness of the intermediate layer 200 may be in the range from about 0.5 microns to about 10 microns and, optionally, of a value above the critical thickness for the chosen material to form dislocations such as misfit dislocations or threading dislocations or a combination of misfit / threading dislocations, to produce a substantially zero level strain in the layer 200.

[0040] The critical thickness for the composition of SiGe layer is the thickness below which intermediate layer 200 is strained with limited dislocations, while above the critical thickness the residual strain in the material is relieved by formation of density of dislocations by breaking of bonds in the single crystalline lattice structure leading to a relaxed layer. The critical thickness of the intermediate layer 200 is determined by the composition, growth temperature, gas precursors, flow rates etc., among other factors. In the example embodiment, intermediate layer 200 comprising SiGe may be grown by epitaxial growth of one or more layers of SiGe and by growing each layer beyond the corresponding critical thickness by relaxing the strain by formation of dislocations. In one specific embodiment, the intermediate layer 200 may contain about 30% of Ge in a single crystal SiGe that is strain free by formation of a density of dislocations to relieve the residual strain.

[0041] As a result of deposition of the layer 200 on top of the substrate 100, a two-layer semiconductor structure

[0042] In some embodiments, the composition of intermediate layer 200 may vary across the thickness of intermediate layer 200. In some embodiments, the composition of intermediate layer 200 may vary in a linear manner while in other embodiments, the composition of intermediate layer 200 may vary in a step wise manner.

[0043] Following the formation of a single crystal semiconductor material intermediate layer 200 on the single crystal semiconductor material substate 100, the layer 200 is judiciously patterned to form at least one first recess region 300 extending into the layer 200 without reaching the substrate 100 and at least one second recess region 310 (referred to herein as global alignment key(s)) dimensioned throughout the layer 200 and into the substrate 200, as is schematically indicated in FIG. 3 Recessed region(s) 300 are generated by removing a portion of the thickness of the intermediate layer 200 selectively, with the use of lithography and etching, for example, in one or more locations during the fabrication of a MEMS device that utilizes the two-layer structure 204. (As a result, an embodiment of the MEMS device structured according to the idea of the present invention includes at least one ridge or rib extending towards the substrate 100, as will be understood by the skilled person.)

[0044] Recessed region(s) 300 has(ve) a depth that is less than the thickness of the intermediate layer 200 and have a first lateral dimension in a first direction in the plane of the layer 200 and a second lateral dimension in a second (orthogonal) direction on the plane of the intermediate layer 200. The depth, first lateral dimension, and the second lateral dimension of recessed region(s) are not necessarily the same in the case of multiple recessed regions 300 but are chosen such that in a subsequent epitaxial growth step for a structural or device layer deposited on the top surface of intermediate layer 200, the top surface of the so subsequently deposited or grown structural or device layer is substantially planar - that is, the dimensions of recessed regions are chosen to allow planarization during a subsequent epitaxial growth step. In contradistinction with the parameters of the recessed region(s) 300, the dimensions of the global alignment key(s) 310 are judiciously chosen to ensure that, during the subsequent formation of a structural or device layer above the global alignment key(s) 310, such layer is not planarized in its portion that is above the global alignment key, thereby propagating the visibly- perceivable indentation to the top surface of a layered structure formed above the global key and thus establishing a spatial reference with respect to which the locations of other structural features or elements of a component of the MEMS device being fabricated can be substantially precisely identified. Such visibly-perceivable indentation (the example of which is identified in FIG. 4 with the numeral 430) may be used in the subsequent device fabrication steps. In the example of the embodiment of the MEMSsensor (discussed below), therefore, the presence of the global alignment key(s) 310 allows for registration of anchor structures to the global alignment key(s) and for ensuring that stop structures are spatially aligned with and corresponding to the moving MEMS mass to be formed. As shown in the specific but non-limiting example of FIG. 3, the location of the global alignment key 310 is at the periphery 320 of the substrate 100.

[0045] Thus, according to the idea of the invention, the formation of the recessed regions 300 was generally coupled with and was implemented in reliance on the definition of at least one global alignment key(s) 310 formed at the periphery of the substrate 100 to facilitate the fabrication of the desired MEMS device. In one specific case, however, the formation of the recessed regions was implemented in reliance of the definition of at least two global alignment keys generated at the periphery of the substrate 100, which, as the person of skill will readily appreciate, necessarily alleviates and reduces the possibility of making a rotational misalignment error. Global alignment key(s) 310 may be formed by etching - for example, with the use of Deep Reactive Ion Etching or, DRIE) - through the layer 200 and forming the appropriately dimensioned notches or trenches in the substrate 100 (for example at the perimeter of semiconductor substrate 100). Alternatively, in a related embodiment, the formation of the global alignment key(s) 310 as patterned trenches may be accomplished prior to the grow th of intermediate layer 200, with the subsequent removal of the portion of the layer 200 that is deposited onto such patterned trenches, as the skilled artisan will readily appreciate.

[0046] In a related embodiment, the at least one recessed region 300 may be formed after the trench(es) of global alignment key(s) 310 have been already generated, during a subsequent etching step of the intermediate layer 200 to be pre-determinately aligned to (or registered with respect to) the global alignment key(s) 310.

[0047] Overall, global alignment key(s) 310 has a depth that is greater than the depth of the one or more recessed regions 300 and that is equal to or greater than the thickness of the intermediate layer 200. In some embodiments, the depth of global alignment key(s) 310 is less than the depth of intermediate layer 200.

[0048] The size, shape, and depth of trenches representing global alignment key(s) 310 are generally defined by the requirements of subsequent processing steps as will be evident to those skilled in the art. In some embodiments, the first dimension of a global alignment key 310 in a first direction within the plane of the intermediate layer 200 is larger than the maximum lateral dimension of recessed region(s) 300 formed in the intermediate layer 200. In some embodiments, the first dimension of the global alignment key 310 is between about 10 mm and 2000 mm or approximately at least about 25 mm. The second dimension of a global alignment key 310 in a second (orthogonal) direction within the plane of theintermediate layer 200 is similarly and independently chosen. In some embodiments global alignment key(s) 310 are formed as rectangular trenches. In other embodiments, global alignment key(s) may be shaped as two orthogonal trenches that form a cross-like indent in the substrate 100 and / or the intermediate layer 200.

[0049] Depending on the specifics of a particular implementation of the proposed methodology, a recessed region 300 may be formed with the use of spm-coating the surface of intermediate layer 200 with a photo-resist and subsequent lithographic patterning steps with the use of a stepper or aligner and the following etching process(es) to transfer, to the intermediate layer 200, a pattern 300 with a square, round, rectangular, triangular, pentagonal, hexagonal, rhomboid, polygonal, or other shape(s).

[0050] The first dimension of recessed region 300 in a first direction within the plane of the intermediate layer 200 is in the range of approximately 0.5 to 20 mm or approximately between about 1 micron and about 10 microns. The second dimension of recessed region 300 in a second (substantially orthogonal to the first) direction within the plane of intermediate layer 200 is, independently, in the range of approximately 0.5 microns to about 20 microns or approximately between 1 micron and 10 microns.

[0051] The etching process(es) used to selectively remove a thickness of intermediate layer 200 and / or to form a recess 310 in the two-layer structure 204 may be wet, dry, vapor or a combination of wet, dry and vapor etching; such etching process(es) may be anisotropic, isotropic, or a combination of anisotropic and isotropic, as known in the art. In one embodiment, the selective removal of a thickness of intermediate layer 200 comprising silicon germanium uses RIE (Reactive Ion Etching) with fluorine chemistry (such as SF6). The depth of recessed regions 300 may be between (10% and 90% of the total thickness of the intermediate layer 200. In another embodiment, the etching process may employ the use of vapor HC1 to selectively remove a thickness of intermediate layer 200 comprising silicon germanium with a substantially isotropic spatial profile. Similarly, different combinations of gases and chemicals may be employed. In general, the etching process is configured to etch a predetermined distance into intermediate layer 200 such as to no not expose the substrate 100 when forming recessed regions 300.

[0052] FIG. 4 is an illustration of a device layer 400 with one or more stops 410 overlying intermediate layer 200 in accordance with an example embodiment. Device layer 400 and stops 410 comprises a single crystal semiconductor material and are epitaxially grown overlying the surface of intermediate layer 200. Device layer 400 can comprise a third material different from the material of intermediate layer 200 and semiconductor substrate 100. In one embodiment, device layer 400 comprises the same material as underlying semiconductor substrate 100. In the example embodiment, device layer 400 and semiconductor substrate 100 comprises single crystal silicon and intermediate layer 200comprises single crystal silicon germanium. The top surface of device (or structural) layer 400 is substantially planar above the region of the substrate where recessed regions 300 are formed. However, while the epitaxial growth of device layer 400 is planar above these regions, the surface above the global alignment keys (not shown) 310 is recessed with respect to the top surface of layer 400 in the region of a wafer or substrate where MEMS devices are to be formed.

[0053] According to the idea of the invention, the device layer 400 is a single-crystal semiconductor material - for example, silicon - is also grown to contain substantially zero strain, to be relaxed (for example, by being grown beyond the corresponding critical thickness due to the choice of the growth conditions of device layer 400. By growing device layer 400 above a relaxed layer comprising intermediate layer 200 with a density of dislocations to relieve the residual strain, the strain of device layer 400 is similarly relieved by formation of dislocations when the thickness of the layer 400 is greater than the corresponding critical thickness.

[0054] In one case, the single-crystal silicon device layer 400 is grown in an epitaxial reactor with precursor gases such as DCS (Dichlorosilane), TCS (Trichlorosilane), SiEE (Silane) among other precursor gases and at a temperature between about 400 °C and about 1200 °C to enable the formation of a single crystal overlying the relaxed surface of intermediate layer 200. The gas flow rates, temperatures and thickness of device layer 400 may be modulated or varied to grow the film thickness beyond the critical thickness and is accompanied by the formation of dislocations to form a relaxed device layer 400 with zero or very low strain.

[0055] Since the surface of intermediate layer 200 has been already patterned with one or more recessed regions 300, the epitaxial growth of device layer 400 is intentionally controlled such that single crystal material of the device layer 400 growing from the bottom surface in a recessed region 300 forms a single-crystal ndge or rib structure 410 extending towards the substrate 100 and monolithic with the remaining portion of the layer 400. At this step of the fabrication procedure, the spaces between neighboring ridge or rib structures 410 - referred herein as stop structures and operating as such by limiting the movement of the moving mass portion of the final embodiment of the targeted MEMS device, as discussed below in more detail - are filled by the single crystal semiconductor material (SiGe, in one example) of the intermediate layer 200.

[0056] Optionally, the device layer 400 may be grown as an undoped or doped layer depending on the specifics of a particular implementation. The doping of the device layer 400, if desired, may achieved by flowing through the chamber of the epitaxial reactor dopant gases such as arsine, phosphine, diborane along with precursor gases such as DCS and TCS to produce n-type or p-type depending on the doping type required for the formation of the semiconductor device. The sheetresistance of the doped layer forming device layer 400 is preferably in the range from about 0.001 ohm- cm to about 10,000 ohm -cm and may be, respectively, of n-type or p-type.

[0057] The thickness of the resulting substantially zero strain (due to the present density of dislocations) device layer 400 is generally chosen in the range of between about 1 micron to about 200 microns and - by analogy with the optional approach that may be chosen for formation of the intermediate layer 200 - may be formed in one or multiple epitaxial deposition steps such that the critical thickness of each of the (sub)layers of the resulting device layer 400 is exceeded for the particular growth conditions to produce each of the (sub)layers as a strain-free (sub)layer due to formation of corresponding dislocations. The growth conditions of the device layer 400 is controlled such that recessed regions 300 in intermediate layer 200 are filled with a single crystal material to form stops 412. The number of steps of epitaxial growth may vary in number from one to, for example, 100 steps. Alternatively or in addition - and similarly to the optional strategy of formation of the intermediate layer 200 alluded to above - in some embodiments, intermediate annealing steps may be used between deposition of individual (sub)layers of the layer 400 to further reduce residual strain in the respective material. The temperature and time of each deposition and annealing step may be varied to reduce the residual strain and also the surface roughness. Since dislocations are intentionally created in device layer 400 to relieve the residual strain, the misfit and threading dislocations that are created do contribute to formation of a surface roughness 420 on the surface of device layer 400, as indicated in FIG. 4. Surface roughness 420 on the upper surface of the device layer 400 has generally an average figure from about 2 nm and about 100 nm depending on the starting surface roughness of intermediate layer 200 and the growth conditions of device layer 400.

[0058] During the epitaxial growth of the device layer 400 on top of the intermediate layer 200 and the substrate 100, the global alignment key(s) 310) are filled with the single-crystal material of the layer 400 while naturally transferring these alignment keys to the upper surface of the layer 400, which transfer manifests as visually-perceivable indentation(s) 430 suitable for subsequent device processing steps as described below: since the regions of global alignment keys 310 are recessed due to the deep trenches which are etched, the epitaxial growth of device layer 400 necessarily defines a recess in the surface of the device layer 400.

[0059] FIG. 5 illustrates an embodiment of the following processing step of the proposed methodology, according to which the surface roughness 420 of the layer 400 is removed with polishing using Chemical Mechanical Polishing or Planarization (CMP) procedure in accordance with an example embodiment to arrive at the engineered substrate 510. In the specific case when the surface of device layer 400 has an average roughness 420 in a range between 10 nm and 100 nm, for example, the CMP step may be used to reduce the surface roughness to an average value that is substantially below 10Angstroms, thereby substantially planarizing the surface 500 of the device layer 400. In other words, the engineered planarized surface 500 is the result of the polishing CMP step described herein applied to the surface of device layer 400 after the epitaxial growth process. Such upper surface finish of the singlecrystal semiconductor material device layer 400 is, substantially, an optical finish suitable for implementation of lithographic processes discussed further below. (As understood in the art, the term “optical finish” refers to the level of smoothness and precision, achieved on a surface, that is specifically designed to minimize imperfections and irregularities that could distort light reflection or refraction, thereby substantially making the surface of such quality suitable for use in optical components like lenses and mirrors; essentially, it is a high-quality polish that ensures optimal light interaction with the surface, often described in related art with parameters such scratch-dig specifications and surface flatness.)

[0060] Overall, the engineered substrate 510 includes the substrate 100 (made of a first single crystal semiconductor material), the intermediate layer 200 (that is made of a second single crystal semiconductor material and is relaxed and strain free and has a density of dislocations due to its thickness being greater than the critical thickness), and the device layer 400 (that is made of a third single crystal semiconductor material and is relaxed and strain free and has a density of dislocations by growing the thickness of this layer beyond the critical thickness value). The device layer 400 further contains stops 412 of the third single crystal material monolithically integrated with the remaining portion of the device layer 400.

[0061] At the following processing step, as shown in FIG. 6, openings or voids 600 are formed in the engineered substrate 510 - for example, photolithographically, as will be understood by the skilled artisan - that penetrate through both the device layer 400 and the intermediate layer 200 and into the substrate 100 to form corresponding recesses in the substrate 100. An appropriately designed mask is used to ensure that the pattern for formation of voids 600 that may have a generally polygonal crosssection or a cross-section with a perimeter defined by a substantially differentiable function and that are judiciously aligned to the global alignment keys 430 (that has been transferred to the planarized surface of the device layer 400), At step of FIG. 6, the modified engineered substrate 604 is produced.

[0062] In one example, voids 600 formed in device layer 400 and intermediate layer 200 are patterned using high-aspect ratio etching techniques such as DRIE (Deep Reactive Ion Etching) and can be produced in one etching process or two separate etching processes using different etching methods and chemistries, depending on the material used for formation of device layer 400 and intermediate layer 200.

[0063] For example, the appropriately spatially aligned - with the global alignment key(s) - regions of the single crystal silicon device layer 400 (that have been exposed through a patterned photoresist layer) are etched to form high-aspect ratio trenches in the device layer 400 by using DRIEwith SFe chemistry and alternate cycles of etch utilizing SFe and passivation utilizing a polymer. The single-crystal SiGe intermediate layer 200 is then patterned using the same DRIE process to remove portions of intermediate layer 200 to expose or form a surface 610 in the single-cry stal silicon substrate 100. As shown, the surface 610 of voids 600 may be recessed into semiconductor substrate 100. When present, the depth of such recess into semiconductor substrate 100 corresponding to surface 610 of exposed regions of semiconductor substrate 100 may be in the range from about 0.5 micron to about 5 microns.

[0064] At the following processing step, indicated in FIG. 7, the voids 600 of the modified engineered substrate 604 of FIG. 6 are filled by depositing one or more material refill layers (depending on the choice of materials and the void dimensions). Considering the case when the surface 610 is a surface of a recess in the substrate 100, the voids 600 is refilled with the use of CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), reactive growth such as oxidation, and / or other deposition methods, in a preferably conformal fashion to refill the voids 600 at most with substantially insignificant internal voids or, preferably, substantially completely, to enable one or more refill layers to come in contact with surface (s) 610.

[0065] In one example, where the voids 600 of the modified engineered substrate 604 are etched through the single-crystal silicon device layer 400 and through the single-crystal SiGe intermediate layer 200, the voids may be refilled with multiple refill layers, for example the first layer 700 of a dielectric material and the second layer 710.

[0066] In one non-limitmg case, the first refill layer 700 includes LPCVD silicon nitride of the substantially dielectric nature deposited conformally with low stress and thickness in the range from about 0.5 micron to about 1.5 microns over the surface of device layer 400, sidewalls of voids 600, and surfaces 610 of exposed regions of the semiconductor substrate 100. The second refill layer 710 in this case may be structured as LPCVD polycrystallme silicon or polysilicon, conformally deposited over the surface of the first refill layer 700 to substantially completely fill the remaining portions of the voids 600. It is understood, therefore, that the first refill layer is substantially electrically insulating the material of the second refill layer from the substrate 10, the intermediate layer 200, and the device layer 400. The poly crystalline silicon used for formation of the layer 710 may be undoped or doped and, understandably, has a thickness that depends on the width and / or height of the voids 600 and the thickness of first refill layer 700. In a related embodiment, the second refill layer 710 may include LPCVD LTO (Low Temperature Oxide), HTO (High Temperature Oxide), TEOS (TetraEthylOrthoSilicate), among other oxide films. In yet another embodiment, the second refill layer 710 may contain SACVD (Sub Atmospheric Chemical Vapor Deposition) oxide. A greater than 2 number of refill layers for substantiallycompletely filling the voids 600 are within the scope of the invention (for example, 3 refill layers, 4 refill layers, etc.)

[0067] In a related embodiment, voids 600 may be completely refilled by depositing a single refill layer 700 made of a dielectric material (such as silicon nitride, for example).

[0068] The modified engineered substrate 604 with the voids 600 filled (as discussed, in reference to FIG. 7. with material(s) that are substantially electrically insulated from the materials of the substrate 100, the intermediate layer 200, and the device layer 400) then is additionally processed to form one or more anchor structure preforms shown in FIG. 8 as 810, 820. The anchor structure preforms 810 and 820 are completed by removing those portions of the refill layers 700 and 710 (in the example of the structure of FIG. 7) that are overlying the device layer 400, for example with the use of the Chemical Mechanical Polishing to expose a surface 800 of or in the device layer 400. (It is understood that during such polishing the excess of the refill layers, some predetermined thickness of the device layer 400 may also be removed.) The anchor structure preforms 810 and 820, substantially dimensioned as columns of material(s) with a chosen cross-section, are coupled to the surface 610 of substrate 100 (and rooted in the substrate 100, when the surface 61 is the surface of a recess formed in the substrate 100). The refill material 710 forms the core portion of such anchor structured while the refill material 700 is a wrapper material insulating the core at least from the material of the substrate 100.

[0069] As the result of the next processing step of the modified engineered substrate containing the anchor structure preforms, as shown in FIG. 9, openings 900 are formed in the device layer 400 with the use of lithographic techniques and etch processes employing appropriate photoresists, as known in the art, and in pre-determined spatial coordination with the global alignment keys(s) 430, thereby producing the semiconductor structure 904 in which the device layer 400 is now patterned to exhibit device layer portions 910, 915, 920, 925, 930, 935, 940, 945, and 950. In such structure 904, trenches / openings 900 are selectively etched to expose respective portions of the intermediate layer 200 at the bottom of the openings 900. In one example, DRIE was used to generate openings 900 organized in an array with high aspect ratio, such that the trench cross-sectional dimensions were smaller than the heights of the trenches. The aspect ratio (height to width) of openings 900 are preferably in the range from about 5: 1 to about 60: 1. In one practical case, the aspect ratio of the trenches / openings 900 were about in the range of 10: 1. As the skilled artisan will readily appreciate, the formation of the openings 900 now enables further structuring of the portions 910, 915, 920, 925, 930, 935, 940, 945, and 950 of the device layer 400 that leads to the definition of the stop-structure-containing moving mass of the target MEMS device (as discussed below). The presence of the stop structure(s) reduces stiction such that the moving mass (should it reposition beyond the practical limit and come in contact with the substrate 100 or another stationary portion of the MEMS device) could return to its quiescent position.

[0070] Further, it is understood that the continued structuring of the single crystal semiconductor material portions 910, 915, 920, 925, 930, 935, 940, 945, and 950 of the device layer 400 as discussed below enables the transformation of the formation of the anchor structure preforms 810, 820 to anchors or anchor structures carrying and supporting such moving mass.

[0071] FIG. 10 depicts the results of such continued structuring, which includes selective removal of pre -determined portions of the intermediate layer 200 through the openings 900 from under the portions 910, 915, 920, 925, 930, 935, 940, 945, and 950 of the device layer 400 while keeping the portions 915, 920, 940, 945 of the device layer 400 attached to the anchor structure preforms 810, 820. As a result of such processing, the MEMS device 1000 is formed, in which the anchor structure preforms 810, 820 are transformed into anchor structures 1060, 1065 that support - via the attached portions 920, 940 - at least a portion 1040 of the device layer 400 now enabled to move relatively at least to the substrate 100 and containing (as seen in the central part of the example of FIG. 10) the undercut portions 925, 930, 935 of the device layer and the stop structures 410.

[0072] In particular, in the considered above specific example, specific wet, dry, vapor, or gaseous etchant is introduced through the openings 900 in the single-crystal-silicon device layer 400 to selectively remove portions of the single-crystal SiGe intermediate layer 200 to form undercut regions 1010, 1015 and 1020 below the device layer 400. In the undercut region 1015, a portion of the intermediate layer 200 below stop structures 410 is removed to define the predetermined distance separating the stop structures 410 from the upper surface of the semiconductor substrate 100. An example of the etchant is provided by a vapor of hydrochloric acid (HC1). Such vapor HC1 may be diluted with a carrier gas (that may include, without limitations, hydrogen, nitrogen, argon among carrier gases) while the etching pressure may be an atmospheric pressure. Alternatively, etching may be performed at pressures below the atmospheric pressure (in one example, it was carried out at a pressure value between about 20 Ton and about 500 Ton; in another example - at a pressure value between about 200 Torr and about 400 Torr) and / or at a temperature in the range from about 250°C to about 1100°C (or in a range between about 600°C to about 850°C). The flow rate of the gases may be modified to achieve the desired etch rate and selectivity. In one specific example, the flow rate of HC1 gas in the chamber was about 5 slm and the hydrogen canier gas flow rate was also about 5 slm. However, other flow rates may be used for both HC1 and carrier gases, generally between about 1 slm and 10 slm.

[0073] In some embodiments, an HF -based pre-clean step was used prior to the HC1 selective etch, as a result of which step native oxides or other contaminants that may form on a surface are removed, thereby ensuring that the etchant can directly access the SiGe material result in a more controlled and consistent etch process. In one non-limiting examples, the pre-clean process was carriedout by immersing structure into a 100: 1 dilute HF solution at 15 °C (generally, preferably between about 10°C and 25°C) for about one minute. Optionally, HF dilutions between about 50: 1 and 200: 1 may also be used with pre-clean process times between about thirty seconds and five minutes. The sample was then rinsed at ambient or room temperature (approximately 20°C to 25°C) using high purity (deionized) water for between about one minute and three minutes (generally, for about two minutes) before undergoing a spin dry process as is known in the art. The sample was then baked in an H2environment for about tw o minutes at a temperature between about 850°C and about 1050°C. (Other temperatures as low as about 600°C may also be used, and other times between about thirty seconds and about ten minutes, or between about one minute and 5 minutes may also be used.)

[0074] As understood by the skilled person, as a result of such continued structuring, stops 410 in structured device layer are now separated from the underlying semiconductor substrate 100 by respective gaps that are smaller than the thickness of the intermediate layer 200 and that correspond to a pre-determined (target) distance of separation between the moving mass 1040 and the substrate 100.

[0075] The selective removal of the intermediate layer 200 in the undercut regions 1010, 1015 and 1020 also forms field regions 1030 and 1035 of the MEMS device 1000: the field region 1030 includes the portion 910 of the patterned device layer coupled to the portion of the intermediate layer 200 that is adjacent to the undercut region 1010, and the field region 1035 includes the portion 950 ofthe patterned device layer coupled to the portion of the intermediate layer 200 adjacent to the undercut region 1020.

[0076] In the example of FIG. 10, the resulting MEMS device 1000 is configured as an accelerometer sensor operable to detect acceleration due to inertial force in the z-axis with the use of the moving mass 1040 that is coupled with and attached - via the portion 935 configured as a suspension spring - to the anchor structure 1065 which, in turn, is rooted in and electrically insulated from the substrate 100. The structural coupling of a given anchor structure to the substrate 100 at a location recessed from the upper surface of the substrate increases the structural strength of such anchor structure.

[0077] The moving mass 1040 is substantially free to move under the stimulus of an inertial force such as acceleration force since the underlying portion of the intermediate layer 200 has been removed by formation of the undercut regions 1010, 1015 and 1020.

[0078] Different techniques for detection of the motion of moving mass may be used to detect the inertial stimulus. Transduction methods such as capacitance detection, piezoelectric, piezoresistive, resonant frequency, optical among other transduction techniques may be used for the accelerometer. In the considered example, the accelerometer sensor device 1000 is configured as a z-axis accelerometer that uses capacitive transduction to detect the input acceleration along the z-axis. The suspension springportion of the device 1000 enables the movement of moving mass 1040 (with which it is monolithic) and is coupled to a proof mass (that includes portions 925, 930 of the patterned device layer). The portions 920 and 925 of the MEMS device 1000 can be used as electrodes, in which case - when the input acceleration causes the repositioning of the moving mass 1040 along the z-axis - the overlap between an electrode represented by the portion 925 and an electrode represented by the portion 920 changes, thereby causing a change in the respective capacitance. The change in capacitance due to the change in the overlap represents a measure of the input acceleration and may be further converted to an output electrical signal representative of the input acceleration.

[0079] During the movement of the moving mass 1040 towards the substrate (caused by the acceleration force in the -z direction), the presence of the vertical stops 410 prevents the entire surface of the proof mass from coming into contact with underlying semiconductor substrate 100, thereby enabling the MEMS accelerometer sensor 100 to prevent, in operation, the stiction between the entire proof mass of the moving mass 1040 and the substrate 100. The stops 410 and the substrate 100 act as motion stops for the portion of proof mass of the moving mass 1040 and restrict the maximum distance of travel due to an input acceleration in the -z direction. Stop structures 410 also enable the MEMS accelerometer from sticking to the surface of the underlying substrate.

[0080] Generally, in a MEMS device such as a 3 -axis accelerometer or gyroscope, vertical stops 410 may be used to limit motion in the vertical axis due to acceleration, shock, vibration and other inertial forces. In another embodiment, the moving mass 1040 may be employed as an actuator that can move in the vertical direction (z-axis) due to an applied stimulus. In another related embodiment, the moving mass 1040 may be configured as a mirror that can move along or rotate about the z-axis.

[0081] FIG. 11 is a top view of a MEMS device 1100 formed in accordance with the idea of the invention and configured to operate, with the use of capacitive sensing, as a sensor of acceleration applied orthogonally to the plane of the device (that is, along the z-axis). Note that a single structure maybe identified on the figure directly, but it can be replicated multiple times and is understood to be labeled accordingly. The MEMS device 1100 contains a moving element and a static element formed in the device layer 1160, of a single-crystal silicon engineered substrate, that is relaxed and substantially strain free and overlying the single-crystal SiGe intermediate layer (that is also relaxed and substantially strain free and that is overlying a single-crystal silicon substrate). The moving element or mass includes a proof mass 1120 coupled to a spring suspension 1115, which is in turn coupled to the anchor 1110. Moving electrodes 1125 are coupled to the proof mass 1120, the spring suspension 1115, and the anchor 1110 to form the moving mass of the device 1100. To limit the motion of the proof mass 1120 along the z-axis, an array of stops 1130 is formed on the underside of the proof mass 1120 (as discussed above, in reference to FIGs. 1 through 10). The accelerometer sensor 1100 also comprises a static element that includes an arrayof static electrodes 1145 supported by an array of anchors 1140. Static electrodes of the array 1145 and moving electrodes 1125 are separated by small lateral gaps 1150 to form a capacitive sensor capable of measuring z-axis-directed acceleration. When an inertial force acts on the accelerometer in the -z direction, the proof mass 1120 moves in the -z direction due to the torsional rotation of the spring suspension 1115 supported by anchor 1110. The movement of the proof mass 1120 also causes movement of the array of moving electrodes 1125 in the -z direction, thereby causing a change in the spatial overlap between the moving electrodes 1125 and the static electrodes 1145 and, therefore a change in respective capacitance, which is a measure of the input (acting on the device 1100) vertical acceleration. The movement of the proof mass 1120 along the z-axis is limited by the stops 1130 since the gap spacings of the device layer 1150 from the underlying semiconductor substrate are smaller than the gap spacings between the moving electrodes 1125 and the surface of the underlying semiconductor substrate.

[0082] In the example of the embodiment 1100, the anchor 1110 that is coupled to the moving electrodes is also connected to a contact pad 1170. The anchor 1140 coupled to the array of static electrodes 1145 is connected to a contact pad 1175. The contact pad 1170 is electrically coupled to the capacitance plate of the moving electrodes 1125. The contact pad 1175 is electrically coupled to the capacitance plate of the static electrodes 1145. The differential capacitance is electrically read and analyzed by an external circuit (optionally, with the use of a programmable processor) - not shown for simplicity of illustration - such as ASIC (Application Specific Integrated Circuit) to convert the input acceleration to an external equivalent electrical signal such as voltage.

[0083] One alternative implementation of the stop structures in a target MEMS device (containing a moving mass monolithic with such stop structures and other elements, the definition of which requires judicious spatial coordination with and dimensional reference with respect to the global alignment key(s) that are formed in the device-carrying substrate and that are transferred to the upper surface of the device layer, as discussed above, see elements 320, 430) is schematically outlined below in reference to FIGs. 12 through 20. For simplicity of illustration, the respective global alignment keys are omitted in these drawings. Here, as the skilled artisan will readily appreciate, even if not explicitly mentioned or identified, the materials and processes and processing parameters used to devise such alternative implementation may be those already alluded to when discussing the previous embodiment in reference to FIGs. 1-10.

[0084] FIG. 12 - by analogy with FIG. 1 - illustrates a semiconductor substrate 1200, which is a single crystal material and may include silicon, SOI, germanium, GaN, SiC, and GaAs, to name just a few.

[0085] FIG. 13 shows a first intermediate layer 1300 formed with the use of epitaxial growth with a thickness above the critical thickness, for example, to contain dislocations and to be substantially strain free on top of a surface of the semiconductor substrate 1200, and includes comprises a material generally different from the material of the substrate 1200. In one example, the layer 1300 comprises SiGe with a germanium concentration between 10% - 80% and has a thickness in a range from about 0.2 micron to about 2 microns. In one specific embodiment, the layer 1300 is a single-crystal SiGe with 30% Germanium and has a thickness of about 0.5 micrometers.

[0086] FIG. 14 is an illustration of recessed regions 1400 formed (with the use of lithography and etching techniques, as known in the art) in the first intermediate layer 1300. In one case, recessed regions 1400 in the layer 1300 expose the surface of the underlying substrate 1200 (such as a singlecrystal silicon substrate 100).

[0087] FIG. 15 shows the results of deposition of the second intermediate layer 1500 over the recessed regions 1400 - for example, by growing beyond the critical thickness the single-crystal SiGe material in a conformal manner to be relaxed and substantially strain free with a density of dislocations The thickness of the second intermediate layer 1500 is preferably in the range from about 0.5 micron to about 2 microns The overall intermediate layer can be formed from multiple (sub)layers.

[0088] FIG. 16 is an illustration of a device layer 1600 of a third single -crystal semiconductor material (for example, silicon) grown overlying the surface of the intermediate layer in an epitaxial reactor under controlled conditions to be relaxed and substantially strain free with a density of dislocations and beyond the critical thickness for the particular growth conditions The thickness of device layer 1600 is preferably in the range of 2-200 microns; the layer 1600 may be formed in one or more growth steps and be doped with n-type or p-type dopant(s). In one specific case, the thickness of the layer 1600 is about 20 micrometers and it is doped n-type. The growth of device layer 1600 overlying second layer 1500 is earned out to fill the recessed regions of the previously formed intermediate layer form stops (or stop structures) 1620 that are separated from the surface of semiconductor substrate 1200 by a predetermined distance corresponding to the thickness of second layer 1500. Stops 1620 are also single crystal in nature and structure and are monolithic with the remaining portion of the layer 1600. The growth of device layer 1600 overlying second layer 1500 results in surface roughness 1610 on the surface of device layer 1600. As shown in the example of FIG 16, the surface roughness 1610 may be in the range from about 100 Angstrom to about 1 micrometer for the single-crystal silicon device layer 1600 comprising single crystal silicon.

[0089] FIG. 17 is an illustration of the semiconductor structure of FIG 16 from the top of which the surface roughness 1610 has been removed - for example, with the use of CMP to form asubstantially planarized surface 1700. configured to enable further process of lithography and etching to form semiconductor devices in subsequent fabrication steps. The thickness of device layer 1600 removed by CMP to produce the planarized surface 1700 is generally in the range from about 100 Angstrom to about 1 micrometer. The removal of the surface roughness leads to formation of the engineered substrate 1710

[0090] FIG. 18 is an illustration of formation of the anchor structure preforms 1810 and 1820 in the engineered substrate 1710, for example by etching one or more voids in device layer 1600 and intermediate layer 1630 such as to expose a surface of the underlying substrate 1200 (in a fashion analogous to that discussed in reference to FIG. 6). Alternatively, the voids can be extended or recessed into the semiconductor substrate 1200, and are subsequently refilled with one or more layers that are deposited conformally in the voids (by analogy with the process of formation of the anchor structure preforms 810, 820 discussed above).

[0091] FIG. 19 illustrates a semiconductor device preform 1980 - such as a preform of a MEMS device containing openings 1900 formed in the device layer 1600 to expose portions of the underlying intermediate layer 1630 with DRIE, for example, to provide access to the underlying portions of intermediate layer 1630. Formation of the openings 1900 in the device layer 1600 results in a patterned device layer containing portions 1930, 1935, 1940, 1945, 1950, 1955, 1960, 1965, and 1970. Openings 1900 enable the process of formation of anchor structures from the anchor structure preforms 1810, 1820.

[0092] FIG. 20 is an illustration of the MEMS device generated from the preform 1980 and configured to be a MEMS device that is responsive to inertial forces - such as, for example, an acceleration sensor or accelerometer that responds to acceleration in the z-axis.

[0093] As shown in FIG. 20, openings 1900 in the device layer 1600 of the preform 1980 have been used to selectively etch and remove portions of the intermediate layer 1630 to form undercut regions 2010, 2015 and 2020 to form the moving mass of the MEMS device and the anchor structures to which such moving mass is moveably attached. The anchor structure 2010 includes the patterned device layer portions 1935 and 1940 coupled to the layer 1800 of FIG. 18 and coupled to / rooted in the substrate 1200 and the refill layer 1810. The anchor structure 2020 includes the patterned device layer portions 1960 and 1965 coupled with the layer 1800 of FIG. 18 and coupled with / rooted in the semiconductor substrate 1200 and the refill layer 1810.

[0094] The etchants that are used for the selective removal of portions of intermediate layer 1630 may be liquid, gas or vapor. In the example when the device layer 1600 is single crystal silicon and the intermediate layer 1630 is single crystal SiGe, the vapor phase HC1 may be used as selective etchantThe formation of the undercut regions 2010 and 2020 also defines field regions 2040 and 2045. The field region 2040 includes patterned device layer portionl930 and the portion of intermediate layer 1630 adjacent to the undercut region 2010, and field region 2045 includes the patterned device layer portion 1970 and the portion of intermediate layer 1630 adjacent to undercut region 2020.

[0095] As a result of such selective etching, the anchor structure preforms 1810, 1820 are transformed into anchor structures 1910, 1920 along with the moving mass 2030 that defines the dynamic element of the MEMS device of FIG. 20 that can respond to an input acceleration. The moving mass 2030 includes the patterned device layer portion 1955 acting as a spring suspension and the patterned device layer portions 1945 and 1950 acting as a proof mass. The patterned device layer potions 1945 and 1950 have stops 1620 monolithic with the proof mass that limit the amount of movement of the proof mass to the gap between the stops 1620 and the surface of the substrate 1200.

[0096] The anchor structure 1910 acts as the static element of the MEMS device. The relative movement of the dynamic element of the accelerometer device containing moving mass 2030 with respect to the static anchor structure 1910 is used to detect the input acceleration having a vector component along the z-axis (by analogy with that of the embodiment of FIG. 20) - for example, with the use of capacitive transduction.

[0097] When an input acceleration acts on the moving mass of the device of FIG. 20, the proof mass moves in the -z direction due to the flexibility of spring suspension formed by the patterned device layer portion 1955 attached to the anchor structure 1920. The stop structures 1620, being closer to the surface of the substrate 1200, act as motion limiting stops for the moving mass 2030 that is repositioned in operation of the device due to acceleration being sensed. Since stop structures 1620 include the same single-crystal material as that of the device layer (of which the stop structures are part), the stop structures are strong and robust to withstand shock, vibration, acceleration, and other inertial forces. The restoring force of the spring suspension is higher than the attractive force of contact between the surfaces of the stop structure and the substrate 1200, thereby preventing catastrophic failure of the MEMS device due to shock or other operational conditions. Although the process of formation of the stop structures 1620 differs from that of formation of stop structures 410 of FIG. 10, the operation of the MEMS device of FIG. 11 and that of the MEMS device of FIG. 20 would be substantially identical as long as the stop structures 410 and stop structures 1620 have identical spacings from the respective semiconductor substrates 100 and 1200.

[0098] References throughout this specification to "one embodiment," "an embodiment," "a related embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the referred to "embodiment" is included in at least one embodiment of thepresent invention. Thus, appearances of the phrases "in one embodiment, “ "in an embodiment, “ and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment. It is to be understood that no portion of disclosure, taken on its own and in possible connection with a figure, is intended to provide a complete description of all features of the invention.

[0099] Within this specification, embodiments have been described in a way that enables a clear and concise specification to bet written, but it is intended and will be appreciated that embodiments may be variously combined or separated without parting from the scope of the invention. In particular, it will be appreciated that all features described herein at applicable to all aspects of the invention.

[0100] For the purposes of this disclosure and the appended claims, the use of the terms "substantially", "approximately", "about" and similar terms in reference to a descriptor of a value, element, property or characteristic at hand is intended to emphasize that the value, element, property, or characteristic referred to, while not necessarily being exactly as stated, would nevertheless be considered, for practical purposes, as stated by a person of skill in the art. These terms, as applied to a specified characteristic or quality descriptor means "mostly", "mainly", "considerably", "by and large", "essentially", "to great or significant extent", "largely but not necessarily wholly the same" such as to reasonably denote language of approximation and describe the specified characteristic or descriptor so that its scope would be understood by a person of ordinary skill in the art. In one specific case, the terms "approximately", "substantially", and "about", when used in reference to a numerical value, represent a range of plus or minus 20% with respect to the specified value, more preferably plus or minus 10%, even more preferably plus or minus 5%, most preferably plus or minus 2% with respect to the specified value. As a non-limiting example, two values being "substantially equal" to one another implies that the difference between the two values may be within the range of + / - 20% of the value itself, preferably within the + / - 10% range of the value itself, more preferably within the range of + / - 5% of the value itself, and even more preferably within the range of + / - 2% or less of the value itself.

[0101] The use of these terms in describing a chosen characteristic or concept neither implies nor provides any basis for indefiniteness and for adding a numerical limitation to the specified characteristic or descriptor. As understood by a skilled artisan, the practical deviation of the exact value or characteristic of such value, element, or property from that stated falls and may vary within a numerical range defined by an experimental measurement error that is typical when using a measurement method accepted in the art for such purposes.

[0102] Implementation of an embodiment of the invention - whether discussed expressly or not above - generally includes the use of electronic circuitry (for example, a computer processor) controlled by instructions stored in a memory', to perform specific data collection / processing andcalculation steps as disclosed above. The memory may be random access memory (RAM), read-only memory (ROM), flash memory or any other memory, or combination thereof, suitable for storing control software or other instructions and data. Those skilled in the art should would readily appreciate that instructions or programs defining the operation of the present embodiment(s) may be delivered to a processor in many forms, including, but not limited to, information permanently stored on non-writable storage media (e.g. read-only memory devices within a computer, such as ROM, or devices readable by a computer I / O attachment, such as CD-ROM or DVD disks), information alterably stored on writable storage media (e.g. floppy disks, removable flash memory and hard drives) or information conveyed to a computer through communication media, including wired or wireless computer networks. In addition, while the invention may be embodied in software, the functions necessary to implement a method of the invention may optionally or alternatively be embodied in part or in whole using firmware and / or hardware components, such as combinatorial logic, Application Specific Integrated Circuits (ASICs), Field- Programmable Gate Arrays (FPGAs) or other hardware or some combination of hardware, software and / or firmware components.

[0103] While the invention is described through the above-described exemplary' embodiments, it will be understood by those of ordinary skill in the art that modifications to, and variations of, the illustrated embodiments may be made without departing from the inventive concepts disclosed herein.

[0104] The term “and / or”, as used in connection with a recitation involving an element A and an element B, covers embodiments having element A alone, element B alone, or elements A and B taken together.

[0105] Disclosed aspects, or portions of these aspects, may be combined in ways not listed above. Accordingly, the invention should not be viewed as being limited to the disclosed embodiment(s).

Claims

CLAIMSWhat is claimed is:

1. A microelectromechanical system (MEMS) sensor comprising: a substrate; an intermediate layer overlying and carried by the substrate; a device layer disposed above the intermediate layer and including a moving mass that is configured to move with respect to the substrate and that carries a stop structure that is monolithic with the moving mass and that extends from the moving mass towards the substrate; and an anchor structure rooted in the substrate, protruding away from the substrate, and electrically insulated from the substrate, wherein each of the substrate, the intermediate layer, and the device layer is a corresponding single crystal material, wherein the moving mass is structurally connected to the anchor with a spring structure.

2. A MEMS sensor according to claim 1, wherein:(a) the spring structure is monolithic with the moving mass and with the stop structure; and / or(b) the substrate comprises single crystal silicon; and / or(c) the intermediate layer comprises single crystal silicon germanium.

3. A MEMS sensor according to one of claims 1 and 2, wherein:(a) wherein each of the intermediate layer and the device layer has a corresponding thickness greater than a respective critical thickness; and / or(b) wherein the spring structure has a spring force that exceeds a force of stiction between the stop structure and the substrate.

4. A MEMS sensor according to one of claims 1 to 3, further containing a global alignment key in at least one of the intermediate layer and the substrate, the global alignment key being dimensioned such that during a formation of an overlying material layer carried by a layer containing the global alignment key, the overlying material layer is substantially is not planarized above the global alignment key.

5. A MEMS sensor according to one of claims 1 to 4, wherein the intermediate layer and the device layer are epitaxial layers,wherein the intermediate layer and the device layer are substantially free from stress caused by dislocations.

6. A MEMS sensor according to one of claims 1 to 5, devoid of a material of the intermediate layer between the moving mass and the substrate.

7. A MEMS sensor according to claim 6, lacking the material of the intermediate layer between the moving mass and the substrate substantially at every point between two immediately neighboring anchor structures.

8. A MEMS sensor according to one of claims 6 and 7, having a gap between a first surface of a portion of the device layer that is immediately affixed to a layer of material electrically insulating the anchor structure from the substrate and a second surface of the substrate, the first and second surfaces facing each other.

9. A MEMS sensor according to one of claims 1 to 8, comprising a recess formed in the substrate and spatially aligned with an opening formed through the device layer, said recess and the opening containing the anchor structure in contact with each of the device layer and the substrate.

10. A MEMS sensor according to one of claims 1 to 9, wherein the anchor structure is dimensioned as a column extending transversely to the substrate, said column including a polycrystalline silicon core and a silicon nitride overlayer.

11. A MEMS sensor according to claim 10, devoid of contact between the device layer and the poly crystalline silicon core and between the substrate and the poly crystalline silicon core.

12. A method comprising: fabricating the MEMS sensor according to one of claims 1 to 11 by at least: covering a substrate of a first semiconductor material with an intermediate layer of a second semiconductor material containing dislocations to form a two-layer semiconductor structure in which the intermediate layer is substantially devoid of strain; dimensioning a first recessed region in the intermediate layer to cause a material layer grown over the first recessed region substantially planarized over the first recessed region;shaping the two-layer semiconductor structure to form a second recessed region therein, wherein the second recessed region is dimensioned to have a material layer grown over the second recessed region to not be planarized above the second recessed region; forming a device layer of a third semiconductor material over the intermediate layer to fill the first recessed region to produce a stop structure extending towards the substrate; isolating a portion of the device layer configured as a moving mass from a stationary portion of the device layer by at least etching the device layer; and releasing the moving mass that is monolithic with the stop structure by etching the intermediate layer to enable a combination of the moving mass and the stop structure to reposition by a predetermined distance with respect to the substrate, wherein a material of each of the substrate, the intermediate layer, and the device layer is a respective single crystal material.

13. A method according to claim 12, wherein each of the semiconductor substrate and the device layer comprises silicon, and wherein the intermediate layer comprises silicon germanium.

14. A method according to one of claims 12 and 13, further comprising: forming an anchor structure rooted in the substrate and having a core and a dielectric material electrically insulating the core from the substrate; and forming a spring structure attached to the anchor structure and mechanically coupling the anchor structure and the moving mass.

15. A method according to claim 14, wherein the forming the anchor structure includes forming the anchor structure having the dielectric material electrically insulating the core from the third semiconductor material.

16. A method according to one of claims 14 and 15, wherein the forming the anchor structure includes: after the dimensioning the first recessed region and the shaping the two-layer semiconductor structure, etching the device layer and the intermediate layer to form a void therethrough; depositing a conformal dielectric material layer to cover a surface of the void and to be in contact with a first surface of the substrate; filling at least a portion of the void with a material of the core of the anchor structure in contact with the conformal dielectric material; andremoving a portion of the conformal dielectric material and the material of the core to define a substantially planar surface terminating the device layer, the conformal dielectric material, and the material of the core.

17. A method according to one of claims 14 to 16, wherein the forming a spring structure includes forming the spring structure having a spring force greater than a force of stiction between the stop structure and the substrate.

18. A method according to one of claims 12 to 17, wherein said covering the substrate includes growing the intermediate layer in an epitaxial reactor beyond a corresponding critical thickness to form dislocations therein.

19. A method according to one of claims 12 to 18, wherein said forming a device layer of a third semiconductor material includes epitaxially growing the device layer beyond a corresponding critical thickness to produce a grown device layer that is substantially strain free.

20. A method according to one of claims 12 to 19, wherein of claim 1, further comprising etching the one or more recessed regions in the intermediate layer of the second material as a timed etch such that the underlying substrate is not exposed.

21. A method according to one of claims 12 to 20, wherein:(a) the dimensioning a first recessed region in the intermediate layer includes etching the first recessed region to expose a surface of the substrate; and / or(b) the shaping the two-layer semiconductor structure to form a second recessed region includes etching both the intermediate layer and the substrate to form the second recessed region extending into the substrate.

22. A method according to one of claims 12 to 21, further comprising: at least partially filling the first recessed region with a conformal auxiliary intermediate layer of a predetermined thickness that is substantially equal to the predetermined distance; and wherein the releasing the moving mass includes etching the conformal auxiliary intermediate layer that underlies the device layer.

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