Universal multi-band filtering embedded integrated interface and manufacturing method therefor

Abstract

A universal multi-band filtering embedded integrated interface and a manufacturing method therefor. An upper interface board, a middle interface board, and a lower interface board are aligned and soldered to form a three-dimensional interconnection structure. By implementing vertical interconnection by means of vias on the middle interface board, a universal, flexible and expandable multi-band filtering embedded integrated interface is manufactured, and the interface has remarkable characteristics of being miniaturized and integrated, achieving conformal filtering functionality, and reducing transmission and filtering loss.

Description

A universal multi-band filtering embedded integrated interface and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 14, 2023, with application number 202311736568.5 and invention name “A universal multi-band filtering embedded integrated interface and its manufacturing method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of multifunctional filtering integrated interfaces, and in particular to a universal multi-band filtering embedded integrated interface and a manufacturing method thereof. Background Art

[0003] In existing technology products, electromagnetic compatibility (EMC) has strict requirements for all electronic devices or systems. In addition, they must withstand interference from external artificial high-power input. The current main traditional solution is to add a multi-band filter group functional design to the input and output parts of the connector interface. Filters of multiple frequency bands are set on the circuit board, which has a connector interface, and the overall electromagnetic compatibility of the connector interface is achieved. However, with the development of technology, the above-mentioned multi-band filtering functional units all use packaged filters, which are implemented using traditional surface mounting technology, and thus occupy a large volume space, which seriously affects the miniaturization and lightweighting of electronic equipment, and thus cannot be applied to broader application scenarios such as micro-nano robots and smart Internet of Things. Advanced filtering integration technology must be used to achieve conformal miniaturization.

[0004] Summary of the Invention

[0005] This application provides a universal multi-band filtering embedded integrated interface and its manufacturing method. By vertically interconnecting through-holes in a mid-layer adapter board and filling them with solid metal, a universal, flexible, and scalable multi-band filtering embedded integrated interface is created. This interface features small-scale integration, conformal filtering functionality, and reduced transmission and filtering losses.

[0006] In a first aspect, a universal multi-band filtering embedded integrated interface is provided, comprising a plurality of filtering units and at least two external pins interconnected with the plurality of filtering units; the plurality of filtering units include first-type filtering units and / or second-type filtering units;

[0007] The first type of filtering unit includes a first type of substrate portion and a capacitor graphic circuit provided on the first type of substrate portion, wherein the first type of substrate material is a dielectric material used to form a capacitor;

[0008] The second type of filtering unit includes a second type of substrate portion and an inductor graphic circuit provided on the second type of substrate portion. The second type of substrate material is a dielectric material used to form an inductor.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the multiple filtering units include a first filtering unit and a second filtering unit, the first filtering unit and the second filtering unit belong to the same type of filtering units, the first substrate portion of the first filtering unit and the second substrate portion of the second filtering unit share a substrate, the first graphic circuit of the first filtering unit and the second graphic circuit of the second filtering unit are arranged on the surface of the same layer of substrate, and the first graphic circuit and the second graphic circuit are interconnected through the circuit on the surface of the same layer of substrate.

[0010] In combination with the first aspect, in certain implementations of the first aspect, the multiple filtering units include a third filtering unit and a fourth filtering unit, and the third filtering unit and the fourth filtering unit belong to different types of filtering units; the third substrate portion of the third filtering unit and the fourth substrate portion of the fourth filtering unit are fixedly connected by colloid; the third graphic circuit of the third filtering unit and the fourth graphic circuit of the fourth filtering unit are interconnected by a circuit across the colloid.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the multiple filtering units include a fifth filtering unit and a sixth filtering unit, and the fifth filtering unit and the sixth filtering unit belong to the same type or different types of filtering units; the fifth substrate portion of the fifth filtering unit belongs to the first layer substrate of the integrated interface, and the sixth substrate portion of the sixth filtering unit belongs to the second layer substrate of the integrated interface, the first layer substrate and the second layer substrate are welded together, and the fifth graphic circuit of the fifth filtering unit and the sixth graphic circuit of the sixth filtering unit are interconnected by solder.

[0012] In combination with the first aspect, in certain implementations of the first aspect, the integrated interface also includes a third type of substrate part, the third type of substrate part includes multiple conductive layers and multiple insulating layers arranged in a stacked manner, wherein an insulating layer is arranged between two adjacent conductive layers, and a conductive layer is arranged between two adjacent insulating layers, and the third type of substrate part is assembled with the first type of substrate part and / or the second type of substrate part by same-layer bonding or different-layer welding.

[0013] In combination with the first aspect, in certain implementations of the first aspect, devices other than filtering functions are provided on the first-type substrate portion and / or the second-type substrate portion that are bonded and assembled on the same layer as the third-type substrate portion.

[0014] In combination with the first aspect, in certain implementations of the first aspect, capacitive graphic circuits are provided on both sides of the first type of substrate portion, and the first type of substrate portion also includes a plurality of metallized blind holes arranged at intervals, with capacitive substrate material spaced between two adjacent metallized blind holes, and metal material is exposed on both sides of the first type of substrate portion respectively between two adjacent metallized blind holes.

[0015] In combination with the first aspect, in certain implementations of the first aspect, the second-type substrate portion includes a plurality of conductive holes arranged in an array, and inductor graphic circuits are provided on both sides of the second-type substrate portion for series connection between the plurality of conductive holes arranged in the array.

[0016] In conjunction with the first aspect, in certain implementations of the first aspect, on the first side of the second-type substrate portion, an inductor graphic circuit is disposed between the i-th via in the first row and the i+1-th via in the second row, an inductor graphic circuit is disposed between the last via in the first row and the last via in the third row, an inductor graphic circuit is disposed between the i-1-th via in the third row and the i-th via in the fourth row, and an inductor graphic circuit is disposed between the first via in the fourth row and the first via in the second row.

[0017] On the second side of the second type substrate portion, an inductor graphic circuit is provided between the ith via hole in the first row and the ith via hole in the second row, and an inductor graphic circuit is provided between the ith via hole in the third row and the ith via hole in the fourth row.

[0018] In combination with the first aspect, in certain implementations of the first aspect, the filter unit of the integrated circuit and the external pins on the same layer are transmitted through a graphic circuit and / or a via on the substrate where the filter unit is located.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the interconnection between the filter unit of the integrated circuit and the external pins of different layers is achieved through solder between the substrate where the filter unit is located and the substrate where the external pins are located, the graphic circuit on the substrate where the filter unit is located, the graphic circuit on the substrate where the external pins are located, and the conductive holes between the substrate where the filter unit is located and the substrate where the external pins are located.

[0020] In combination with the first aspect, in certain implementations of the first aspect, a shielding metal through-hole is further provided on the substrate of the integrated interface and a solder pad is provided on the shielding metal through-hole, which is used for signal shielding protection during the up and down transmission of signals and is located on both sides of the transmission line and around the transmission through-hole.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the integrated interface also includes a metal shell, which surrounds the outer periphery of the composite substrate; the metal shell is also provided with a step for mounting the composite substrate; the composite substrate composed of multiple substrate parts of the integrated interface has metallized material around it for welding connection with the step of the metal shell.

[0022] In conjunction with the first aspect, in certain implementations of the first aspect, the first type of substrate material is any one of the following dielectric non-magnetic materials: silicon, glass, microcrystalline glass, ceramic material, aluminum nitride, and lanthanum gallium silicate, and the first type of substrate material meets any one of the following conditions: a dielectric constant of greater than 1000 and an electric field strength resistance exceeding 50 kV / mm;

[0023] The second type of substrate material is any one of the following dielectric magnetic materials: nickel-zinc, manganese-zinc system ferrite, amorphous nanocrystalline magnetic core, and the second type of substrate material meets the saturation magnetic permeability of 500 or more.

[0024] In combination with the first aspect, in certain implementations of the first aspect, the multiple filtering units include at least one of the following: a microstrip filter, an LC filter, a MEMS filter, a cavity filter, a surface acoustic wave filter, and a body surface filter.

[0025] In a second aspect, a method for manufacturing a universal multi-band filtering embedded integrated interface as described in any one of the implementations of the first aspect is provided, characterized in that it includes:

[0026] Assembling and splicing a plurality of substrate parts to form a first layer of substrate, using colloid bonding to assemble heterogeneous substrate parts in the same layer, and using substrates of the same material in the same layer to serve as at least one homogeneous substrate part;

[0027] Processing a via hole on the first base substrate;

[0028] The first layer substrate is subjected to a coplanar polishing CMP process → PVD metallization → photolithography → etching → surface passivation to realize interconnection of graphic circuits on the first layer substrate;

[0029] Welding the first substrate and the second substrate together;

[0030] Inserting metal pins into the metal through holes of the first layer of substrate to form external pins of the integrated interface;

[0031] The composite substrate composed of the first substrate and the second substrate is installed in a metal shell and packaged.

[0032] In conjunction with the second aspect, in certain implementations of the second aspect, the conductive via on the first base substrate is prepared by:

[0033] In the copper sulfate solution, an inhibitor, an accelerator, and a leveler are added in a ratio of (0.5%-2%: 0.05%-0.2%: 0.5-2%, for example, 1%: 0.1%: 1%);

[0034] In a double-sided spraying, vacuuming, and constant temperature stirring equipment environment, a high pulse power supply is used to set a bidirectional pulse electroplating program with a current density of 0.1ASD to 10ASD and a pulse duty cycle of 0.1% to 99%. Deep hole electroplating is performed to achieve deep hole side wall metallization. The metal material is a single layer of metal or a multi-layer composite metal of TiW / Ti / NiCr / Ni / Al / Cu / Au, and the side wall metal thickness is 0.1 micron to 20 microns.

[0035] In conjunction with the second aspect, in certain implementations of the second aspect, the PVD metallization includes:

[0036] Physical deposition method PVD is used to achieve surface and hole wall metallization, and the back vacuum degree is less than 10 -4 Pa, for example, the back vacuum is 5×10 -5 Pa, filled with high-purity argon, control the ventilation volume, maintain the vacuum degree 0.01Pa ~ 10Pa, for example, maintain the vacuum degree 2Pa, the background temperature 25 ℃ ~ 400 ℃, for example, the background temperature is 100 ℃, the surface metal material is TiW / Ti / NiCr / Ni / Al / Cu / Au one layer of metal or multi-layer composite metal.

[0037] Traditionally, inductors (L) are made by winding a magnetic material through a wire, while traditional capacitors (C) are made by metallizing the upper and lower surfaces with a high-dielectric-constant material. The inductors and capacitors are then mounted and packaged to form a filter, resulting in a large volume and difficulty in integration. Compared to existing technologies, the solution provided by this application offers at least the following beneficial technical effects:

[0038] 1. Different from the traditional filter interface preparation method, the three-dimensional integration technology of the filter function is realized by using a composite substrate, which reduces the board area, has the advantages of smaller volume and higher integration, and is conducive to the future development trend of miniaturization.

[0039] 2. The present invention does not change the interface definition, position and size of the original connector, but adds a first-level filtering function adapter board to realize the interface filtering function.

[0040] 3. The present invention can change the filtering frequency range or add multi-stage filtering, which will make the system electromagnetic compatibility design more flexible and can be achieved by replacing the filter connector.

[0041] 4. The product has the advantages of miniaturization, high product integration and flexible configuration. It can adapt to various electrical filtering interconnection scenarios and can be easily installed on various modules and connectors inside and outside the chassis without considering additional fixation.

[0042] 5. Optional operating frequency bandwidth: 10~6000MHz (expandable to 40GHz); filter types: low-pass, band-pass, high-pass, band-stop; input / output impedance: 50Ω, 75Ω, customized. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic structural diagram of a universal multi-band filtering embedded integrated interface provided in an embodiment of the present application.

[0044] FIG2 is a schematic structural diagram of an assembly of multiple filter units provided in an embodiment of the present application.

[0045] FIG3 is a schematic structural diagram of another assembly of multiple filter units provided in an embodiment of the present application.

[0046] FIG4 is a schematic structural diagram of another assembly of multiple filter units provided in an embodiment of the present application.

[0047] FIG5 is a schematic structural diagram of a first type of filtering unit provided in an embodiment of the present application.

[0048] FIG6 is a schematic structural diagram of a second type of filtering unit provided in an embodiment of the present application.

[0049] FIG7 is a flow chart of a method for manufacturing a single filter unit provided in an embodiment of the present application.

[0050] FIG8 is a flowchart of a method for manufacturing multiple filter units provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The present application is described in further detail below with reference to the accompanying drawings and specific embodiments.

[0052] Figure 1 shows a schematic structural diagram of a universal multi-band filtering embedded integrated interface provided by an embodiment of the present application. The integrated interface may include multiple filtering units 1, and the multiple filtering units 1 include first-type filtering units and / or second-type filtering units. The first-type filtering unit includes a first-type substrate portion and a capacitor graphic circuit provided on the first-type substrate portion, and the first-type substrate material is a dielectric material for forming a capacitor. The second-type filtering unit includes a second-type substrate portion and an inductor graphic circuit provided on the second-type substrate portion, and the second-type substrate material is a dielectric material for forming an inductor.

[0053] The multiple filter units 1 of the integrated interface can correspond to multiple frequency bands, and the multiple frequency bands can be designed in sections according to the required filtering functions of each frequency band. The multiple filter units 1 include but are not limited to microstrip filters, LC filters, MEMS filters, cavity filters, surface acoustic wave filters, and surface filters.

[0054] In this application, the graphic circuit can be an interconnected metal microstrip line used to implement a key circuit design for interconnecting upper and lower interfaces. The metal material can be commonly used interconnected metals such as copper / nickel / gold / silver or a combination thereof or an alloy thereof.

[0055] The first type of filter unit can be understood as a capacitive C fabricated on a first type of specific substrate material (materials may include, but are not limited to, silicon, glass, glass-ceramic, high-dielectric-constant ceramics, aluminum nitride, lanthanum gallium silicate, and other dielectric non-magnetic materials). The first type of specific substrate material can meet any of the following requirements: a dielectric constant of 1000 or greater and an electric field strength resistance exceeding 50kV / mm.

[0056] The second type of filter unit can be understood as an inductive L fabricated on a second type of specific substrate material (e.g., dielectric magnetic materials such as nickel-zinc, manganese-zinc ferrites, and amorphous nanocrystalline cores). The dielectric constant of the second type of specific substrate material has a wider range of values ​​than that of the first type of specific substrate material; the second type of specific substrate material can meet a saturation permeability of 500 or above, and the permeability is related to the filtering frequency band.

[0057] In some embodiments provided herein, the integrated interface may utilize metal pins as external pins 3 of the integrated interface to conduct signals with relatively high current values. As shown in Figure 1 , the metal pins may be disposed on the substrate 2 of the integrated interface and interconnected with the surface image circuitry of substrate 2. The integrated interface includes at least two external pins 3. The processing techniques for the metal pins include, for example, sintering the metal pins with solder, which may be, but is not limited to, tin-lead, gold-tin, gold-germanium, or silver-tin. The metal pins may be made of commonly used metal materials such as copper alloys and nickel alloys.

[0058] 1 to 3 , the plurality of filter units 1 include a filter unit A and a filter unit B. The substrate portion A of the filter unit A and the substrate portion B of the filter unit B belong to the same substrate layer.

[0059] In one embodiment, filter unit A and filter unit B belong to the same type of filter unit. Substrate portion A and substrate portion B can share a substrate 2, as shown in a partial form in FIG2 . That is, the graphic circuit A of filter unit A and the graphic circuit B of filter unit B are set on the surface of the same layer of substrate 2, for example, by photolithography. Filter unit A and filter unit B can be interconnected through the circuit on the surface of substrate 2. Filter unit A and filter unit B can also be interconnected through the conductive holes of the upper substrate 2 of the interface. The conductive holes are mainly interconnected metal pillars filled with metal after the through holes, which are used to realize three-dimensional vertical interconnection between various embedded filters. The metal material is mainly copper or copper alloy.

[0060] In another embodiment, filter unit A and filter unit B belong to the first and second categories, respectively. Substrate portion A and substrate portion B can be securely connected via a colloid. Specifically, a colloid is provided between substrate portion A and substrate portion B, as shown in a partial form in FIG3 . Graphic circuit A of filter unit A and graphic circuit B of filter unit B can be interconnected via a circuit spanning the colloid. Graphic circuit A and graphic circuit B can also be interconnected via conductive vias in substrate 2 on the integrated interface.

[0061] The material of the colloid is, for example, a high-strength and tough thermosetting epoxy resin. After the filter unit A and the filter unit B are bonded, excess thermosetting epoxy resin may overflow near the bonding position. Mechanical grinding and polishing are used for surface treatment so that the bonding position is flush with the substrates on both sides, which is convenient for subsequent metallization on the substrate surface. The form of splicing and curing substrates of different materials is not limited to side-by-side splicing and stacking to form a composite substrate. Substrates of different materials are first spliced ​​and composited, and then subjected to coplanar CMP treatment → PVD metallization → photolithography → etching → surface passivation to achieve interconnection.

[0062] In other embodiments, filter unit A and filter unit B are not arranged on the same layer, as shown in a partial form in Figure 4. Filter unit A and filter unit B can be of the same type or different types. Substrate portion A of filter unit A belongs to the A-layer substrate of the integrated interface, and substrate portion B of filter unit B belongs to the B-layer substrate of the integrated interface. The A-layer substrate and the B-layer substrate can be connected by soldering. Graphic circuit A of filter unit A is arranged on the surface of the A-layer substrate. Graphic circuit B of filter unit B is arranged on the surface of the B-layer substrate. Filter unit A and filter unit B can be interconnected by solder.

[0063] In some embodiments, the processing technology for interconnecting the above-mentioned graphic circuit is as follows:

[0064] Interconnection is achieved by performing coplanar CMP treatment on the same substrate layer, followed by PVD metallization, photolithography, etching, and surface passivation. Functional thin films are deposited on the surface of structural substrate materials with through-hole metallization using PVD, or thick-film functional materials are prepared using screen printing. These materials can be temperature-sensitive materials such as platinum and ruthenium pastes, and temperature signals are transmitted through the metal of multiple through-holes.

[0065] In some embodiments, the processing technology of the interconnected via holes is as follows:

[0066] Using high-power pulsed laser for drilling, in one possible case, the substrate thickness can be 100 to 1000 μm and the hole diameter can be 10 to 500 μm;

[0067] Physical vapor deposition (PVD) methods, such as magnetron sputtering and plasma evaporation, are used to metallize the surface and inner sidewalls of the cavity as a seed layer. The seed layer material usually has two layers. The thickness of the first seed layer is 10nm to 2μm, and the material is usually one or more of titanium, titanium tungsten, nickel chromium or aluminum; the thickness of the second seed layer is 10nm to 10μm, and the material is usually one or more of nickel or copper and their alloys;

[0068] Deep hole electroplating is used for metal filling, and the metal material is usually copper or its alloy;

[0069] The surface is flattened using the chemical mechanical polishing (CMP) method to remove the surface metal so that the metal in the hole and the substrate material are on the same plane.

[0070] In some embodiments, referring to Figures 2 to 4, shielding metal through holes and metal-filled pads can also be provided on the substrate for signal shielding protection during up and down signal transmission. The pads are located on both sides of the transmission line and around the transmission through holes, and the aperture size is related to a quarter wavelength corresponding to the transmission frequency.

[0071] 1 , a universal multi-band filtering embedded integrated interface provided in an embodiment of the present application may include multiple types of substrate materials. The substrate materials may cooperate with each other in structure, and the graphic circuits on the substrate materials may be interconnected, so that the integrated interface with filtering function is more streamlined in size and structure. The embodiment shown in FIG1 is illustrated using a three-layer substrate as an example. In other embodiments provided in the present application, the integrated interface may include a substrate with fewer layers (e.g., 1 or 2 layers), and may also include a substrate with more layers (more than 3 layers).

[0072] The integrated interface may include a first substrate, a second substrate 2-2, and a third substrate. The first substrate includes a substrate portion 2-1a, a substrate portion 2-1b, and a substrate portion 2-1c. The third substrate includes a substrate portion 2-3a, a substrate portion 2-3b, and a substrate portion 2-3c. The second substrate 2-2 is disposed between the first and third substrates and includes vias. Solder is provided between the substrate layers to achieve interconnection between the substrate layers.

[0073] The substrate portion 2-1a may be provided with external pins 3-1 of the integrated circuit. The substrate portion 2-1b may be the substrate portion of the filter unit 1, which may be a first-type filter unit or a second-type filter unit. The substrate portion 2-1c may be provided with external pins 3-2 of the integrated circuit. The specific structure of the filter unit 1 may refer to the filter unit A or filter unit B shown in Figure 2-4.

[0074] The substrate portion 2-3a may be provided with external pins 3-3 of the integrated circuit. The substrate portion 2-3b may be the substrate portion of the filter unit 2, which may be a first-type filter unit or a second-type filter unit. The substrate portion 2-3c may be provided with external pins 3-4 of the integrated circuit. The specific structure of the filter unit 2 may refer to the filter unit A or filter unit B shown in Figure 2-4.

[0075] In one embodiment, when the filter unit-1 is connected to the external pin 3-1 on the same layer for filtering the signal transmitted by the external pin 3-1, the signal between the filter unit-1 and the external pin 3-1 can be transmitted through the graphic circuit and / or conductive hole on the first substrate.

[0076] In one embodiment, when the filtering unit-1 is connected to the external pin 3-3 of a different layer for filtering the signal transmitted by the external pin 3-3, the transmission between the filtering unit-1 and the external pin 3-3 can be through the solder between the first substrate and the second substrate 2-2, the conductive hole of the second substrate 2-2, the solder between the second substrate 2-2 and the third substrate, the graphic circuit on the first substrate, the second substrate 2-2 and / or the third substrate.

[0077] In one embodiment, when the filter unit-1 is connected to the filter unit-2 of a different layer to perform multi-band filtering, the filter unit-1 and the filter unit-2 can be interconnected through the solder between the first substrate and the second substrate 2-2, the second substrate 2-2, the solder between the second substrate 2-2 and the third substrate, and the conductive hole of the second substrate 2-2.

[0078] In some embodiments, in addition to the substrate portion of the first type of filter unit (i.e., the first type of substrate portion) and the substrate portion of the second type of filter unit (i.e., the second type of substrate portion), the integrated interface may also include a third type of substrate portion. Compared with the first type of substrate portion and the second type of substrate portion, the material selection range of the third type of substrate portion is relatively wider. In one possible case, in order to ensure that the integrated interface accommodates as large an area as possible for the graphic circuit, the third type of substrate portion may include multiple conductive layers and multiple insulating layers stacked together, wherein an insulating layer is provided between two adjacent conductive layers, and a conductive layer is provided between two adjacent insulating layers.

[0079] Taking Figure 1 as an example, in one possible scenario, when substrate portion 2-1a belongs to the third type of substrate portion, substrate portion 2-1a and substrate portion 2-1b can be structurally bonded together using a colloid (e.g., a thermosetting epoxy resin). The graphic circuits on substrate portion 2-1a and the graphic circuits on substrate portion 2-1b can be interconnected using a graphic circuit that spans the bonded portion.

[0080] Taking FIG. 1 as an example, in one possible case, when the second substrate 2-2 includes a third type substrate portion, the substrate portion 2-1b and the second substrate 2-2 can be structurally bonded and fixed and electrically interconnected through pads and solder.

[0081] In one possible scenario, to fully utilize the height space available for the integrated interface, components are further provided on the first and second type substrate portions. In other words, the first and second type substrate portions can be used to carry not only the graphic circuitry of the filter unit itself but also components other than filtering functions.

[0082] In some embodiments, referring to FIG5 , in order to integrate a capacitive filtering unit (i.e., a first type of filtering unit) with better performance on an integrated interface in a limited space, the first type of substrate portion may include a plurality of metallized blind holes that are spaced apart. Capacitive substrate material is spaced apart between two adjacent metallized blind holes. Two adjacent metallized blind holes expose metal material on both sides of the first type of substrate portion, respectively. Therefore, two adjacent metallized blind holes and the substrate material therebetween can form a capacitive unit, and a capacitive unit can be formed between the bottom surface of the metallized blind hole and the relatively arranged graphic circuit, which is conducive to increasing the capacity in a limited space. The design of the capacity of the capacitive filtering unit is related to the dielectric constant of the substrate material, the aperture of the metallized blind hole, the spacing between the metallized blind holes, and the depth-to-diameter ratio of the metallized blind holes.

[0083] In some embodiments, referring to FIG6 , in order to integrate a more highly performing inductive filter unit (i.e., a second type of filter unit) on an integrated interface with limited space, the second type of substrate portion may include a plurality of vias arranged in an array. Graphic circuits are provided on both sides of the second type of substrate portion for realizing series connection between the plurality of vias arranged in an array. The design of the inductance of the inductive filter unit is related to the magnetic permeability of the substrate material, the aperture of the vias, the spacing between the vias, and the aspect ratio of the vias.

[0084] For example, as shown in FIG6 , on the first side of the second type of substrate portion, a pattern circuit is disposed between the i-th via in the first row and the i+1-th via in the second row, a pattern circuit is disposed between the last via in the first row and the last via in the third row, a pattern circuit is disposed between the i-1-th via in the third row and the i-th via in the fourth row, and a pattern circuit is disposed between the first via in the fourth row and the first via in the second row. On the second side of the second type of substrate portion, a pattern circuit is disposed between the i-th via in the first row and the i-th via in the second row, and a pattern circuit is disposed between the i-th via in the third row and the i-th via in the fourth row.

[0085] In some embodiments, as shown in FIG1 , the integrated interface may further include a metal housing. The metal housing surrounds the outer periphery of the composite substrate. The metal housing may also be provided with a step for mounting the composite substrate. Since the substrate used on the periphery of the composite substrate may be the first type of substrate portion or the second type of substrate portion described above, direct welding is difficult. Therefore, the portion of the composite substrate surrounding the step for fixing to the step may be metallized for laser welding to the step of the metal housing. In effect, the composite substrate is mounted in the metal housing and laser-sealed to ensure airtightness.

[0086] The process for implementing the graphic circuits on the multiple substrate sections 2 described above, for example, repeats the following steps: coplanar CMP treatment → PVD metallization → photolithography → etching → insulation layer coating (using BCB or PI) → photolithography → metal filling. Furthermore, the integrated interface can be encapsulated as a whole to protect the filter, metal wires, surface wiring pads, etc. The potting compound can be silicone rubber, epoxy resin, polyimide, etc.

[0087] In conjunction with Figure 1, the embodiment provided in the embodiment of the present application can reserve the position of the filter and the interconnection pads by stacking the upper, middle and lower three-layer substrate according to different filter types and design selections. The three-layer substrate material can be different materials according to the use requirements, such as high dielectric ceramics, special glass, silicon, lithium niobate and other special functional materials. On the one hand, the role of the substrate is vertical interconnection structuring, which can realize the electrical interconnection of the functions at both ends of the connector interface. At the same time, another more important aspect is to select the filter substrate itself as the upper and lower substrates to realize the filtering function.

[0088] In one embodiment, if a plurality of MEMS filters of different frequency bands are to be integrated, the discrete devices are implemented using a silicon substrate, and a monolithic integration design is performed based on the substrate. The peripheral area of ​​the filter itself is increased for preparing through-hole metallization and interconnecting with the underlying circuit, thereby realizing the integration of the adapter board and the filter.

[0089] In one embodiment, if a plurality of microstrip filters of different frequency bands are to be integrated, the discrete devices are implemented using ceramic substrate materials, a monolithic integration design is performed based on the substrate, and the peripheral area of ​​the filter itself is increased for preparing through-hole metallization and interconnecting with the lower-layer circuit, thereby realizing the integration of the adapter board and the filter.

[0090] The advantage of this integration approach is that it allows the filter to be integrated with the substrate, with only holes in the peripheral expansion area for soldering connectors to form external interconnections. This allows the filter to function as both a filter and an adapter board. The method for manufacturing a universal multi-band filtering embedded integrated interface can include the following steps.

[0091] Assembling and splicing a plurality of substrate parts to form a first layer of substrate, using colloid bonding to assemble heterogeneous substrate parts in the same layer, and using substrates of the same material in the same layer to serve as at least one homogeneous substrate part;

[0092] Processing a via hole on the first base substrate;

[0093] The first layer of substrate is polished and processed with coplanar CMP → PVD metallization → photolithography → etching → surface passivation to achieve interconnection of graphic circuits on the first layer of substrate;

[0094] Welding the first substrate and the second substrate together;

[0095] Inserting metal pins into the metal through-holes of the first layer substrate to form external pins of the integrated interface;

[0096] The composite substrate composed of the first substrate and the second substrate is installed in a metal housing and packaged.

[0097] In some embodiments, the vias on the substrate can be prepared by adding an inhibitor, an accelerator, and a leveler to a copper sulfate solution in a ratio of (0.5% to 2%: 0.05% to 0.2%: 0.5% to 2%, for example, 1%: 0.1%: 1%). In a double-sided spraying, vacuuming, and constant temperature stirring environment, a high pulse power source is used to set a bidirectional pulse electroplating process, with a current density of 0.1 ASD to 10 ASD (for example, 2 ASD) and a pulse duty cycle of 0.1% to 99% (for example, 10%). Deep hole electroplating is performed to metallize the deep hole sidewalls. The metal material can be a single layer or multilayer composite metal such as TiW / Ti / NiCr / Ni / Al / Cu / Au, with a sidewall metal thickness of 0.1 micron to 20 microns (for example, 10 microns). After deep hole electroplating, the surface copper thickness is relatively thick (typically tens of microns). The adapter plate is then rough ground on both sides using a single-side grinding method, followed by double-side polishing to remove the surface metal.

[0098] In some embodiments, PVD metallization is specifically as follows: physical deposition methods (PVD) such as magnetron sputtering and electron beam evaporation are used to achieve surface and hole inner wall metallization (background vacuum degree <10 -4 Pa, for example, the back vacuum is 5×10 -5Pa, high-purity argon is filled, the ventilation volume is controlled, and the vacuum degree is maintained at 0.01Pa~10Pa, for example, the vacuum degree is maintained at 2Pa, and the background temperature is 25℃~400℃, for example, the background temperature is 100℃). The surface metal material can be a layer of metal or a multi-layer composite metal such as TiW / Ti / NiCr / Ni / Al / Cu / Au. After the PVD metallization process, a mask (including alignment marks) is used to perform the process of spraying, exposure, development, and etching according to the design pattern to achieve metal patterning, and local electroplating thickening is performed according to the design requirements, so that the upper surface of the adapter plate is electrically interconnected with the lower surface through the metal in the hole, providing an important three-dimensional interconnection structural foundation for the interconnection with the filter. The electroplated metal can be one or more composite metals such as Ni / Cu / Au.

[0099] In some embodiments, the first substrate and the second substrate are welded together, including: metal welding interconnection and alignment of the first substrate and the second substrate, which can be soldering with solder such as tin-lead, tin-bismuth, silver-tin, or eutectic welding with gold-tin, gold-germanium, etc. The specific size and position of the punching holes shall be based on actual design needs.

[0100] In some embodiments, the preparation of the metal needle includes: first implanting an elastic metal ring into the through hole of the first layer substrate to ensure contact with the metal inner wall of the hole, and then welding the metal needle to realize a functional integrated interface.

[0101] In some embodiments, a single filter unit is fabricated as shown in FIG7 , and a plurality of filter units are fabricated as shown in FIG8 .

[0102] Typical performance indicators:

[0103] Integration size: Only the length of the connector interface without the filtering function unit is increased by no more than 10mm, and other conditions such as appearance and interface position remain unchanged.

[0104] Operating frequency: DC-400MHz

[0105] Out-of-band suppression: ≥40dB@900-1200MHz

[0106] In-band insertion loss: ≤0.6dB

[0107] Standing wave coefficient: ≤1.5

[0108] Working temperature: -40℃~+75℃;

[0109] Storage temperature: -50℃~+85℃.

[0110] Maximum passing power: 10W;

[0111] Storage environment: temperature -10~40℃, relative humidity not more than 80%, no acidic, alkaline or other harmful gases around.

[0112] The above-mentioned integrated interface integrates LC filters, cables and adapter connectors, has good filtering characteristics and large passing power, and reduces the conventional filter and cable and connector assembly and matching problems.

[0113] These integrated interfaces are suitable for a variety of applications, including internal and external electrical filtering interconnection, RF interconnection with integrated filtering functions, and inter-board signal transmission filtering. They meet the relevant testing requirements of GJB150 and offer user-defined options for low-pass, band-pass, high-pass, and band-stop filters. They also offer a variety of connector options. Operating frequencies reach up to 6 GHz, with out-of-band rejection reaching 70 dB. These products offer outstanding advantages, including low loss, high integration, flexibility, and adaptability to specific application scenarios.

[0114] By selecting various miniaturized filter circuits, the product can be further miniaturized and its operating frequency can be extended to 18GHz or even higher. It is also possible to achieve circuit characteristics close to those of EMI filters by integrating miniaturized inductors, capacitors, resistors, or high-performance inductive and capacitive materials into the product.

[0115] Although the present invention is disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A general multi - band filtering embedded integrated interface, characterized in that, It includes a plurality of filtering units and at least two external pins interconnected with the plurality of filtering units; the plurality of filtering units include first - type filtering units and / or second - type filtering units; The first - type filtering units include a first - type substrate portion and a capacitive graphic circuit provided on the first - type substrate portion, and the first - type substrate material is a dielectric material for forming a capacitor; The second - type filtering units include a second - type substrate portion and an inductive graphic circuit provided on the second - type substrate portion, and the second - type substrate material is a dielectric material for forming an inductor.

2. The integrated interface according to claim 1, characterized in that, The plurality of filtering units include a first filtering unit and a second filtering unit. The first filtering unit and the second filtering unit belong to the same type of filtering unit. The first substrate portion of the first filtering unit and the second substrate portion of the second filtering unit share a substrate. The first graphic circuit of the first filtering unit and the second graphic circuit of the second filtering unit are provided on the surface of the same - layer substrate, and the first graphic circuit and the second graphic circuit are interconnected through a circuit on the surface of the same - layer substrate.

3. The integrated interface according to claim 1 or 2, characterized in that, The plurality of filtering units include a third filtering unit and a fourth filtering unit. The third filtering unit and the fourth filtering unit belong to different types of filtering units; the third substrate portion of the third filtering unit and the fourth substrate portion of the fourth filtering unit are fixedly connected by glue; the third graphic circuit of the third filtering unit and the fourth graphic circuit of the fourth filtering unit are interconnected through a circuit across the glue.

4. The integrated interface according to any one of claims 1 to 3, characterized in that, The plurality of filtering units include a fifth filtering unit and a sixth filtering unit. The fifth filtering unit and the sixth filtering unit belong to the same type or different types of filtering units; the fifth substrate portion of the fifth filtering unit belongs to the first - layer substrate of the integrated interface, the sixth substrate portion of the sixth filtering unit belongs to the second - layer substrate of the integrated interface, the first - layer substrate and the second - layer substrate are welded together, and the fifth graphic circuit of the fifth filtering unit and the sixth graphic circuit of the sixth filtering unit are interconnected through solder.

5. The integrated interface according to any one of claims 1 to 4, characterized in that, The integrated interface further includes a third - type substrate portion. The third - type substrate portion includes a plurality of conductive layers and a plurality of insulating layers stacked. An insulating layer is provided between two adjacent conductive layers, and a conductive layer is provided between two adjacent insulating layers. The third - type substrate portion is assembled with the first - type substrate portion and / or the second - type substrate portion by the same - layer bonding or different - layer welding method.

6. The integrated interface according to claim 5, characterized in that, Devices other than filtering functions are provided on the first - type substrate portion and / or the second - type substrate portion assembled by the same - layer bonding with the third - type substrate portion.

7. The integrated interface according to any one of claims 1 to 6, characterized in that, Capacitive graphic circuits are provided on both sides of the first - type substrate portion. The first - type substrate portion further includes a plurality of metallized blind holes arranged at intervals. A capacitive substrate material is spaced between two adjacent metallized blind holes, and two adjacent metallized blind holes expose metal materials on both sides of the first - type substrate portion respectively.

8. The integrated interface according to any one of claims 1 to 7, characterized in that, The second type of substrate portion includes a plurality of via holes arranged in an array, and inductive graphic circuits are arranged on both sides of the second type of substrate portion for series connection between the plurality of via holes arranged in the array.

9. The integrated interface according to claim 8, characterized in that, On the first side of the second type of substrate portion, an inductive graphic circuit is arranged between the i-th via hole in the first row and the (i + 1)-th via hole in the second row, an inductive graphic circuit is arranged between the last via hole in the first row and the last via hole in the third row, an inductive graphic circuit is arranged between the (i - 1)-th via hole in the third row and the i-th via hole in the fourth row, and an inductive graphic circuit is arranged between the first via hole in the fourth row and the first via hole in the second row; On the second side of the second type of substrate portion, an inductive graphic circuit is arranged between the i-th via hole in the first row and the i-th via hole in the second row, and an inductive graphic circuit is arranged between the i-th via hole in the third row and the i-th via hole in the fourth row.

10. The integrated interface according to any one of claims 1 to 9, characterized in that, The filtering unit of the integrated circuit is transmitted to the external pins on the same layer through the graphic circuit and / or via holes on the substrate where the filtering unit is located.

11. The integrated interface according to any one of claims 1 to 10, characterized in that, The interconnection of the filtering unit of the integrated circuit with external pins on different layers is realized through solder between the substrate where the filtering unit is located and the substrate where the external pins are located, the graphic circuit on the substrate where the filtering unit is located, the graphic circuit on the substrate where the external pins are located, and the via holes between the substrate where the filtering unit is located and the substrate where the external pins are located.

12. The integrated interface according to any one of claims 1 to 11, characterized in that, Metal via holes for shielding are also arranged on the substrate of the integrated interface, and pads are arranged on the metal via holes for signal shielding protection during the up and down signal transmission, located on both sides of the transmission line and around the transmission via holes.

13. The integrated interface according to any one of claims 1 to 12, characterized in that, The integrated interface further includes a metal housing, and the metal housing surrounds the outer periphery of the composite substrate; the metal housing is also provided with a step for mounting the composite substrate; the periphery of the composite substrate formed by multiple substrate portions of the integrated interface has metallized materials for welding connection with the step of the metal housing.

14. The integrated interface according to any one of claims 1 to 13, characterized in that, The first type of substrate material is any one of the following dielectric non-magnetic materials: silicon, glass, glass-ceramics, ceramic materials, aluminum nitride, lanthanum gallium silicate, and the first type of substrate material satisfies any one of the following: the dielectric constant is above 1000, and the withstand electric field strength exceeds 50 kV / mm; The second type of substrate material is any one of the following dielectric magnetic materials: nickel-zinc, manganese-zinc system ferrite, amorphous nanocrystalline magnetic core, and the second type of substrate material satisfies that the saturation magnetic permeability is above 500.

15. The integrated interface according to any one of claims 1 to 14, characterized in that, The forms of the multiple filtering units include at least one of the following: microstrip filter, LC filter, MEMS filter, cavity filter, surface acoustic wave filter, body surface filter.

16. A manufacturing method of a general multi - band filtering embedded integrated interface according to any one of claims 1 to 15, characterized in that, Including: Assembling and splicing multiple substrate portions to form a first-layer substrate, using colloid bonding for assembling different types of substrate portions on the same layer, and the substrate of the same material on the same layer serves as at least one same-type substrate portion; Processing the via holes on the first-layer substrate; Performing polishing coplanar CMP treatment → PVD metallization → lithography → etching → Surface passivation to realize the interconnection of the graphic circuits on the first-layer substrate; Welding and connecting the first-layer substrate and the second-layer substrate; Inserting metal pins into the metal via holes on the first-layer substrate to form the external pins of the integrated interface; Mount the composite substrate composed of the first-layer substrate and the second-layer substrate in a metal housing and encapsulate it.

17. The manufacturing method according to claim 16, wherein, The via holes on the first base substrate are prepared by the following method: In a copper sulfate solution, add an inhibitor, an accelerator, and a leveling agent, and configure them according to the ratio of (0.5% - 2%: 0.05% - 0.2%: 0.5 - 2%, for example, 1%: 0.1%: 1%). In an equipment environment with double-sided spraying, vacuum pumping, and constant-temperature stirring, use a high-pulse power supply to set a bidirectional pulse electroplating program, with a current density of 0.1 ASD - 10 ASD and a pulse duty cycle of 0.1% - 99%, to perform deep-hole electroplating to achieve metallization of the deep-hole sidewalls. The metal material is a single-layer metal or a multi-layer composite metal of TiW / Ti / NiCr / Ni / Al / Cu / Au, and the sidewall metal thickness is 0.1 μm - 20 μm.

18. The manufacturing method according to claim 16 or 17, wherein, PVD metallization includes: The surface and the inner wall of the holes are metallized by physical vapor deposition (PVD). The background vacuum degree is < 10 -4 Pa. For example, the background vacuum degree is 5×10 -5 Pa. High-purity argon gas is filled, the gas flow rate is controlled, and the vacuum degree is maintained at 0.01 Pa to 10 Pa. For example, the vacuum degree is maintained at 2 Pa, and the background temperature is 25°C to 400°C. For example, the background temperature is 100°C. The surface metal material is a single-layer metal or a multi-layer composite metal such as TiW / Ti / NiCr / Ni / Al / Cu / Au.

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