Word line control circuit and magnetic random access memory

Abstract

A word line control circuit and a magnetic random access memory. The word line control circuit comprises: a control circuit suitable for receiving a read-write enable signal and a row decoding signal and generating a first boost control signal and a second boost control signal which are opposite in logic; a boost circuit suitable for adjusting the voltage of a first output end and the voltage of a second output end on the basis of the first boost control signal and the second boost control signal when different operations are carried out; and a voltage selection circuit suitable for: during a write operation, applying a write voltage to a corresponding word line, and under the control of the voltage of the second output end, disconnecting a path connected to the second output end; and during a read operation, applying a read voltage to a corresponding word line, and under the control of the voltage of the first output end, disconnecting a path connected to the first output end. Use of the present solution can avoid affecting normal writing of data and reduce power consumption of the read operation.

Description

Word line control circuit and magnetic random access memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 11, 2023, with application number 202311701862.2 and invention name “Word line control circuit and magnetic random access memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of memory, and in particular to a word line control circuit and a magnetic random access memory. Background Art

[0003] As a new type of non-volatile memory, magnetic random access memory (MRAM) has the advantages of low power consumption, high reliability, sustainable miniaturization, and compatibility with complementary metal oxide semiconductor (CMOS) processes. It combines the high-speed read and write capabilities of static random access memory (SRAM) and the high integration of dynamic random access memory (DRAM), and is considered to be one of the most promising next-generation memories.

[0004] In practical applications, the write current of MRAM is very large, while the read current is very small. Therefore, the word line control circuit of MRAM needs to be able to output dual voltage waveforms to provide different operating voltages during read / write operations.

[0005] However, in the existing MRAM word line control circuit, the word line voltage cannot reach the required high voltage during a write operation, thereby affecting the normal writing of data and causing power consumption waste during a read operation.

[0006] Summary of the Invention

[0007] The problem to be solved by the present invention is: how to avoid affecting the normal writing of data and reduce the power consumption of the read operation.

[0008] To solve the above problem, an embodiment of the present invention provides a word line control circuit, the word line control circuit comprising:

[0009] The control circuit is adapted to receive a read / write enable signal and a row decoding signal and generate a first boost control signal and a second boost control signal having opposite logics;

[0010] a boost circuit connected to the control circuit, having a first output terminal and a second output terminal; the boost circuit is adapted to adjust the voltages of the first output terminal and the second output terminal based on the first boost control signal and the second boost control signal when performing different operations;

[0011] and a voltage selection circuit connected to the control circuit and the boost circuit, adapted to apply a write voltage to the corresponding word line during a write operation, and disconnect the path connected to the second output terminal under the control of the second output terminal voltage; and to apply a read voltage to the corresponding word line during a read operation, and disconnect the path connected to the first output terminal under the control of the first output terminal voltage.

[0012] Optionally, the boost circuit is suitable for setting the voltage of the first output terminal to a low level and increasing the voltage of the second output terminal to a write voltage under the control of the first boost control signal and the second boost control signal when performing a write operation, and for increasing the voltage of the first output terminal to the write voltage and setting the voltage of the second output terminal to a low level when performing a read operation or not performing a read or write operation.

[0013] Optionally, the boost circuit includes:

[0014] a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0015] Among them, the first PMOS transistor, the third PMOS transistor and the first NMOS transistor are connected in series, and the second PMOS transistor, the fourth PMOS transistor and the second NMOS transistor are connected in series; the source electrodes of the first PMOS transistor and the second PMOS transistor are connected to the write voltage output terminal; the gate electrode of the first PMOS transistor and the gate electrode of the first NMOS transistor are connected to the second boost control signal; the gate electrode of the second PMOS transistor and the gate electrode of the second NMOS transistor are connected to the first boost control signal; the gate electrode of the third PMOS transistor is connected to the drain electrode of the fourth PMOS transistor and serves as the first output terminal; the gate electrode of the fourth PMOS transistor is connected to the drain electrode of the third PMOS transistor and serves as the second output terminal.

[0016] Optionally, the voltage selection circuit includes:

[0017] a first voltage selection subcircuit, one end of which is connected to the second output terminal and the other end of which is connected to the word line, and adapted to apply the read voltage to the corresponding word line during a read operation and disconnect the path connected to the first output terminal under the control of the voltage of the first output terminal;

[0018] a second voltage selection subcircuit, one end of which is connected to the first output terminal and the other end of which is connected to the word line, and adapted to apply a write voltage to the corresponding word line during a write operation and disconnect a path connected to the second output terminal under the control of the voltage of the second output terminal;

[0019] The word line closing sub-circuit is connected to the first voltage selection sub-circuit and the second voltage selection sub-circuit, and is suitable for closing the word line.

[0020] Optionally, the first voltage selection sub-circuit includes: a fifth PMOS transistor and a sixth PMOS transistor connected in series; the source of the fifth PMOS transistor and the read voltage output end; the gate of the fifth PMOS transistor is connected to the inverted signal of the row decoding signal; and the gate of the sixth PMOS transistor is connected to the second output end.

[0021] Optionally, the second voltage selection sub-circuit includes: a seventh PMOS transistor, wherein the gate of the seventh PMOS transistor is connected to the first output end, the source is connected to the write voltage output end, and the drain is connected to the word line.

[0022] Optionally, the word line shutdown circuit includes: a third NMOS transistor and a fourth NMOS transistor connected in series; the gate of the third NMOS transistor is connected to the second boost control signal, and the gate of the fourth NMOS transistor is connected to the inverted signal of the row decoding signal; the source of the fourth NMOS transistor is grounded.

[0023] Optionally, the control circuit includes: a first AND gate circuit, a first inverter and a second inverter;

[0024] Among them, the input end of the first AND gate circuit is connected to the read and write enable signal and the row decoding signal; the output end of the first AND gate circuit generates the first boost control signal; the output end of the first AND gate circuit is connected to the input end of the first inverter, and the output end of the first inverter generates the second boost control signal; the input end of the second inverter is connected to the row decoding signal, and the output end of the second inverter is connected to the voltage selection circuit.

[0025] Optionally, the control circuit is further adapted to receive a read drive control signal, and generate the voltage selection circuit control signal based on the read drive control signal, a read / write enable signal and a row decoding signal, so as to turn off the word line after reading out the data.

[0026] Optionally, the control circuit includes: a first AND gate circuit, a second AND gate circuit, a first inverter, a second inverter and a third inverter;

[0027] Among them, the input end of the third inverter is connected to the read drive control signal; the input end of the second AND gate circuit is connected to the row decoding signal and the output signal of the third inverter; the input end of the first AND gate circuit is connected to the read and write enable signal and the output signal of the second AND gate circuit; the output end of the first AND gate circuit generates the first boost control signal; the output end of the first AND gate circuit is connected to the input end of the first inverter, and the output end of the first inverter generates the second boost control signal; the input end of the second inverter is connected to the output signal of the second AND gate circuit, and the output end of the second inverter is connected to the voltage selection circuit.

[0028] An embodiment of the present invention further provides a magnetic random access memory, which includes any one of the above-mentioned word line control circuits.

[0029] Optionally, the magnetic random access memory further includes:

[0030] A clock control circuit, adapted to receive a clock signal and the read / write enable signal, and generate a read drive precharge signal and a read drive control signal;

[0031] a read drive circuit connected to the clock control circuit and adapted to perform a read operation under the control of the read drive precharge signal and the read drive control signal;

[0032] a precharge circuit, connected to the read drive circuit, adapted to precharge the bit line and the source line;

[0033] a write driver circuit connected to the precharge circuit and adapted to control the voltages of the bit line and the source line to perform a write operation;

[0034] a row decoder connected to the word line control circuit and adapted to generate a row decoding signal;

[0035] a memory array connected to the word line control circuit;

[0036] The word line control circuit is connected to the row decoder and the clock control circuit, and is adapted to control the word line voltage based on the read / write enable signal, the row decoding signal and the read drive control signal to meet operation requirements.

[0037] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0038] By applying the solution of the present invention, the boost circuit can adjust the voltages of its first and second output terminals during different operations. During a write operation, the voltage selection circuit can apply the write voltage to the corresponding word line and, under control of the voltage at the second output terminal, disconnect the path connected to the second output terminal. This prevents the write voltage on the word line from being affected by an incomplete disconnection of the path connecting the voltage selection circuit to the second output terminal of the boost circuit, thereby preventing the normal writing of data. The voltage selection circuit can also apply the read voltage to the corresponding word line during a read operation and, under control of the voltage at the first output terminal, disconnect the path connected to the first output terminal. This prevents power consumption caused by an incomplete disconnection of the path connecting the voltage selection circuit to the first output terminal of the boost circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic structural diagram of an existing row decoding driver;

[0040] FIG2 is a schematic structural diagram of a word line control circuit according to an embodiment of the present invention;

[0041] 3 is a schematic diagram of the circuit structure of a word line control circuit according to an embodiment of the present invention;

[0042] 4 is a schematic diagram of the circuit structure of another word line control circuit according to an embodiment of the present invention;

[0043] FIG5 is a schematic structural diagram of a magnetic random access memory according to an embodiment of the present invention;

[0044] FIG6 is a schematic diagram of the structure of a sensitive amplifier. DETAILED DESCRIPTION

[0045] Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a new type of MRAM that uses spin current to write information. Taking STT-MRAM as an example, an STT-MRAM memory cell typically consists of an access transistor (1T) and a magnetic tunnel junction (1MTJ). During an STT-MRAM write operation, currents in different directions must be applied to the magnetic tunnel junction (MTJ) depending on the data being written. Specifically, when writing to a high-resistance state, a current must be applied from the source line to the bit line of the 1T-1MTJ; when writing to a low-resistance state, a current must be applied from the bit line to the source line of the 1T-1MTJ.

[0046] The write current needs to reach the critical flip current for writing high resistance or low resistance, which is usually very high. In advanced processes, increasing the size of the access transistor or overvoltage of the word line is usually adopted to achieve the corresponding critical flip current.

[0047] Both approaches have drawbacks. Increasing the size of the access transistor increases the area of ​​the memory array, and thus the area of ​​the entire MRAM circuit. Overvoltage on the word line affects circuit reliability, but to prevent erroneous writes during read operations, STT-MRAM has a very low read current and does not require overvoltage on the word line.

[0048] To this end, the word line control circuit of the MRAM needs to be able to output dual voltage waveforms to provide different operating voltages during read / write operations.

[0049] To enable the MRAM wordline control circuit to output dual voltages, a current method uses charge sharing to switch between read and write voltages. Specifically, a capacitor can be included in the wordline control circuit. During a write operation, the wordline voltage is raised to the write voltage. During a read operation, the capacitor is charged, lowering the wordline voltage to the read voltage.

[0050] This solution, on the one hand, increases the delay in charging the capacitor during read operations, resulting in a longer switching time for the power supply voltage of the word line control circuit. This causes the switching transistors in the MRAM to be overvoltage for a considerable period of time during read operations, affecting transistor reliability. On the other hand, the capacitors occupy a large circuit area.

[0051] In order to reduce delay and circuit area, a word line voltage scheme as shown in FIG1 is currently proposed. Specifically, referring to FIG1 , a row decoding driver 10 may include: a power selection circuit 110 and a plurality of decoding driving circuits 120. Among them:

[0052] The power selection circuit 110 receives a read / write select signal VPPSW at one input and an address select signal AIN at the other. The read / write select signal VPPSW and the address select signal AIN are ANDed together and then inverted to generate a read enable signal REN. This signal controls the on / off switching of the read voltage control transistor M2. The inverted read enable signal REN generates a write enable signal WEN, which controls the on / off switching of the write voltage control transistor M1.

[0053] The output terminal of the power selection circuit 110 is connected to the common node VPP. When the read / write selection signal VPPSW is in the read state and the address selection signal AIN is valid, the power selection circuit 110 sets the voltage of the common node VPP to the read voltage, otherwise it is the write voltage.

[0054] One input terminal of the decoding driving circuit 120 is connected to the driving selection signal BIN, and the other input terminal is connected to the address selection signal AIN, so that the voltage of the common node VPP can be applied to the corresponding word line.

[0055] With the above solution, the word line voltage is selected through simple read and write enable logic control. However, when the first voltage VDD1 and the second voltage VDD2 differ greatly, when the write enable signal WEN is valid, the write voltage control tube M1 is turned on and the read voltage control tube M2 cannot be completely turned off, which will cause a voltage drop, resulting in the voltage of the common node VPP being unable to be pulled up to the first voltage VDD1, which may affect the normal writing of data; when the read enable is valid, the read voltage control tube M2 is turned on and the write voltage control tube M1 cannot be completely turned off, which will charge the common node VPP, causing the voltage of the common node VPP to be higher than the second voltage VDD2, resulting in waste of power consumption.

[0056] To address this problem, the present invention provides a word line control circuit, in which a boost circuit and a voltage selection circuit are provided. The boost circuit can adjust the voltages of its first output terminal and second output terminal when performing different operations. On the one hand, the voltage selection circuit can apply the write voltage to the corresponding word line when performing a write operation, and under the control of the voltage of the second output terminal, disconnect the path connected to the second output terminal, thereby avoiding the normal writing of data being affected by the path connecting the voltage selection circuit and the second output terminal of the boost circuit not being completely shut down. On the other hand, the read voltage can be applied to the corresponding word line when performing a read operation, and under the control of the voltage of the first output terminal, disconnect the path connected to the first output terminal, thereby avoiding the waste of power consumption caused by the path connecting the voltage selection circuit and the first output terminal of the boost circuit not being completely shut down.

[0057] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0058] 2 , an embodiment of the present invention provides a word line control circuit 20 , which may include: a control circuit 21 , a boost circuit 22 , and a voltage selection circuit 23 .

[0059] The control circuit 21 is used to receive the read / write enable signal and the row decoding signal, and generate a first boost control signal and a second boost control signal with opposite logics;

[0060] The boost circuit 22 is connected to the control circuit 21 and has a first output terminal and a second output terminal. The boost circuit 22 is adapted to adjust the voltage of the first output terminal and the second output terminal based on the first boost control signal and the second boost control signal when performing different operations.

[0061] The voltage selection circuit 23 is connected to the control circuit 21 and the boost circuit 22, and is suitable for applying the write voltage to the corresponding word line during a write operation, and disconnecting the path connected to the second output terminal under the control of the second output terminal voltage; and applying the read voltage to the corresponding word line during a read operation, and disconnecting the path connected to the first output terminal under the control of the first output terminal voltage.

[0062] During a write operation, the path connecting the voltage selection circuit 23 to the second output terminal is disconnected. This prevents the second output terminal of the boost circuit from discharging the word line through this path, thereby lowering the word line voltage and affecting normal data writing. Furthermore, during a read operation, the path connecting the voltage selection circuit 23 to the first output terminal is disconnected, thereby preventing wasted power consumption.

[0063] In a specific implementation, the boost circuit 22 can, under the control of the first boost control signal and the second boost control signal, set the voltage of the first output terminal to a low level and increase the voltage of the second output terminal to a write voltage when performing a write operation, and when performing a read operation or not performing a read or write operation, increase the voltage of the first output terminal to the write voltage and set the voltage of the second output terminal to a low level.

[0064] In a specific implementation, the boost circuit 22 may have various circuit structures, which are not limited here, as long as it can boost the word line voltage to the write voltage.

[0065] In one embodiment of the present invention, referring to FIG. 2 , the boost circuit 22 includes:

[0066] a first PMOS transistor MP1 , a second PMOS transistor MP2 , a third PMOS transistor MP3 , a fourth PMOS transistor MP4 , a first NMOS transistor MN1 , and a second NMOS transistor MN2 .

[0067] Among them, the first PMOS transistor MP1, the third PMOS transistor MP3 and the first NMOS transistor MN1 are connected in series, and the second PMOS transistor MP2, the fourth PMOS transistor MP4 and the second NMOS transistor MN2 are connected in series; the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the write voltage output terminal; the gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are connected to the second boost control signal xan; the gate of the second PMOS transistor MP2 and the gate of the second NMOS transistor MN2 are connected to the first boost control signal xa; the gate of the third PMOS transistor MP3 is connected to the drain of the fourth PMOS transistor MP4 and serves as the first output terminal Z; the gate of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3 and serves as the second output terminal ZN.

[0068] In a specific implementation, the first boost control signal xa is logically opposite to the second boost control signal xan, that is, when the first boost control signal xa is high, the second boost control signal xan is low, and when the first boost control signal xa is low, the second boost control signal xan is high.

[0069] In a specific implementation, the write voltage outputted by the write voltage output terminal is V WL When performing a write operation, the first boost control signal xa is set to a high level, and the second boost control signal xan is set to a low level. At this time, the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, the first output terminal Z is set to a low level, and then the third PMOS transistor MP3 is turned on, and the voltage of the second output terminal ZN rises to the write voltage V WL When a read operation is performed or a read / write operation is not performed, the first boost control signal xa is set to a low level, and the second boost control signal xan is set to a high level. At this time, the second PMOS transistor MP2 and the first NMOS transistor MN1 are turned on, the second output terminal ZN is set to a low level, and the fourth PMOS transistor MP4 is turned on. Finally, the voltage of the first output terminal Z rises to the write voltage V WL .

[0070] In a specific implementation, the voltage selection circuit 23 may have various circuit structures, which are not limited here.

[0071] In one embodiment of the present invention, referring to FIG2 , the voltage selection circuit 23 may include: a first voltage selection sub-circuit 231 , a second voltage selection sub-circuit 232 and a first voltage selection sub-circuit 233 .

[0072] The first voltage selection subcircuit 231 has one end connected to the second output end and the other end connected to the word line, and is adapted to apply the read voltage to the corresponding word line during a read operation and disconnect the path connected to the first output end under the control of the voltage of the first output end;

[0073] The second voltage selection subcircuit 232 has one end connected to the first output end and the other end connected to the word line, and is adapted to apply a write voltage to the corresponding word line during a write operation and disconnect the path connected to the second output end under the control of the voltage of the second output end;

[0074] The word line closing sub-circuit 233 is connected to the first voltage selection sub-circuit and the second voltage selection sub-circuit, and is suitable for closing the word line.

[0075] In a specific implementation, the write voltage is higher than the read voltage.

[0076] In one embodiment of the present invention, referring to FIG. 3 , the first voltage selection subcircuit 231 may include: a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6 connected in series; a source of the fifth PMOS transistor MP5 and a read voltage output terminal; a gate of the fifth PMOS transistor MP5 connected to an inverted signal EN of the row decoding signal A; and a gate of the sixth PMOS transistor MP6 connected to the second output terminal ZN.

[0077] 3 , the second voltage selection subcircuit 232 may include a seventh PMOS transistor MP7 having a gate connected to the first output terminal Z, a source connected to the write voltage output terminal, and a drain connected to the word line WL.

[0078] During the write operation, the row decoding signal A is valid, and the inverted signal EN of the row decoding signal A turns on the fifth PMOS transistor MP5. At the same time, the first output terminal Z of the boost circuit 23 is at a low level, and the voltage of the second output terminal ZN is the write voltage V WL At this time, the sixth PMOS transistor MP6 is disconnected, that is, the path connected to the second output terminal ZN is disconnected. The seventh PMOS transistor MP7 is turned on, so that the write voltage V WL is applied to the corresponding word line WL.

[0079] During a read operation, row decode signal A is active, and its inverted counterpart, signal EN, turns on the fifth PMOS transistor MP5. Simultaneously, the voltage at the first output terminal Z of the boost circuit 23 becomes the write voltage, and the voltage at the second output terminal ZN is low. At this point, the sixth PMOS transistor MP6 turns on, applying the read voltage Vcore to the word line WL. Simultaneously, the seventh PMOS transistor MP7 turns off, disconnecting the path to the first output terminal.

[0080] The voltage fed back from the output end of the boost circuit 23 can clamp the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 in different states, thereby preventing the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 from entering the triode region, ensuring that the voltage of the word line WL can maintain the required potential in both reading and writing.

[0081] In a specific implementation, the first to seventh PMOS transistors MP1 to MP7 and the first to fourth NMOS transistors may all be high-voltage MOS transistors, thereby avoiding the overvoltage problem.

[0082] In one embodiment of the present invention, referring to FIG. 3 , the word line shut-down circuit 233 may include: a third NMOS transistor MN3 and a fourth NMOS transistor MN4 connected in series; a gate of the third NMOS transistor MN3 is connected to the second boost control signal xan, a gate of the fourth NMOS transistor MN4 is connected to the inverted signal EN of the row decoding signal A; and a source of the fourth NMOS transistor MN4 is grounded.

[0083] Specifically, when the second boost control signal xan is at a high level, the third NMOS transistor MN3 is turned on, otherwise it is turned off. When the row decoding signal A is valid, the fourth NMOS transistor MN4 is turned on, otherwise it is turned off. Thus, the word line shutdown circuit 23 can ground the word line WL when no read or write operations are being performed, forming a ground path and thereby shutting down the word line.

[0084] In a specific implementation, the control circuit 21 may have a variety of circuit structures, which are not limited here.

[0085] In one embodiment of the present invention, referring to FIG3 , the control circuit includes: a first AND gate circuit Y1, a first inverter f1, and a second inverter f2. The input of the first AND gate circuit Y1 is connected to the read / write enable signal WREN and the row decoding signal A; the output of the first AND gate circuit Y1 generates the first boost control signal xa; the output of the first AND gate circuit Y1 is connected to the input of the first inverter f1, and the output of the first inverter f1 generates the second boost control signal xan; the input of the second inverter f2 is connected to the row decoding signal A, and the output of the second inverter f2 is connected to the voltage selection circuit.

[0086] Specifically, when no read or write operation is performed, the row decoding signal A is set to a low level. At this time, the inverted signal EN of the row decoding signal A is set to a high level, the first boost control signal xa is set to a low level, and the second boost control signal xan is set to a high level, thereby turning on the fourth NMOS transistor MN4, the second PMOS transistor MP2, and the first NMOS transistor MN1, setting the second output terminal ZN to a low level, and turning on the fourth PMOS transistor MP4. Finally, the voltage of the first output terminal Z rises to the write voltage V WL , the seventh PMOS transistor MP7 is turned off, and the second boost control signal xan is at a high level, so that the third NMOS transistor MN3 is turned on, and the voltage of the word line WL is set to a low level.

[0087] When a read operation is performed, the row decoding signal A is valid, the read / write enable signal WREN is set to a low level, the first boost control signal xa is set to a low level, the second boost control signal xan is set to a high level, the fifth PMOS tube MP5 is turned on, and the voltage of the first output terminal Z rises to the write voltage V WL , the seventh PMOS transistor MP7 is turned off, the second output terminal ZN is set to a low level, the sixth PMOS transistor MP6 is turned on, and the voltage of the word line WL is set to the read voltage V CORE .

[0088] When a write operation is performed, the row decoding signal A is valid, the read / write enable signal WREN is set to a high level, the first boost control signal xa is set to a high level, and the second boost control signal xan is set to a low level. At this time, the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, the voltage of the first output terminal Z is low, and then the third PMOS transistor MP3 is turned on, and the voltage of the second output terminal ZN rises to the write voltage V WL , the seventh PMOS tube MP7 is turned on, and the voltage of the word line WL is set to the write voltage V WL , the high potential of the second output terminal ZN further disconnects the sixth PMOS transistor MP6.

[0089] In practical applications, the read time of magnetic random access memory is usually much faster than the write time. The same external clock is used in the synchronous circuit to control the reading and writing of the circuit, and the reading and writing maintain the same cycle. For magnetic random access memory, the word line remains open for a long time after the data is read out, resulting in a waste of power consumption and an increased probability of erroneous writing.

[0090] In one embodiment of the present invention, in order to reduce power consumption and lower the probability of erroneous writing, the control circuit is further adapted to receive a read drive control signal SE, and based on the read drive control signal SE, a read / write enable signal WREN and a row decoding signal A, jointly generate a control signal for the voltage selection circuit so as to close the word line WL after completing data reading, thereby effectively shortening the word line opening time during the read operation.

[0091] Specifically, referring to FIG4 , the control circuit may include: a first AND gate circuit Y1, a second AND gate circuit Y2, a first inverter f1, a second inverter f2, and a third inverter f3.

[0092] The input end of the third inverter f3 is connected to the read drive control signal SE; the input end of the second AND gate circuit Y2 is connected to the row decoding signal A and the output signal of the third inverter f3; the input end of the first AND gate circuit Y1 is connected to the read and write enable signal WREN and the output signal of the second AND gate circuit Y2; the output end of the first AND gate circuit Y1 generates the first boost control signal xa; the output end of the first AND gate circuit Y1 is connected to the input end of the first inverter f1, and the output end of the first inverter f1 generates the second boost control signal xan; the input end of the second inverter f2 is connected to the output end A_wr of the second AND gate circuit Y2, and the output end of the second inverter f2 is connected to the voltage selection circuit.

[0093] Compared to the control circuit shown in FIG2 , a second AND gate circuit Y2 and a third inverter f3 are added, and a read drive control signal SE is introduced. The read drive control signal SE is used to control the read drive circuit to perform a read operation. When the read drive control signal SE is high, data is quickly read. At this time, the voltage selection circuit can shut down the word line, thereby reducing power consumption.

[0094] The wordline control circuit of the present invention eliminates the need for capacitor charging and discharging, enabling rapid switching of wordline voltages and read operation timing control through simple logic control. The wordline control circuit is simple in design and easy to implement, while ensuring wordline voltage stability. Furthermore, by adding a read drive control signal to the wordline control circuit, the wordline is turned off after data is read, effectively shortening the wordline open time during read operations.

[0095] An embodiment of the present invention further provides a magnetic random access memory, which may include the word line control circuit described in the above embodiment.

[0096] In one embodiment of the present invention, referring to FIG5 , the magnetic random access memory further includes: a clock control circuit 51 , a read driver circuit 52 , a precharge circuit 53 , a write driver circuit 54 , a row decoder 55 and a storage array 56 .

[0097] The clock control circuit 51 is adapted to receive the clock signal CLK and the read / write enable signal WREN, and generate a read drive precharge signal SAE and a read drive control signal SE;

[0098] The read drive circuit 52 is connected to the clock control circuit 51 and is adapted to perform a read operation under the control of the read drive precharge signal SAE and the read drive control signal SE;

[0099] The precharge circuit 53 is connected to the read drive circuit 52 and is suitable for precharging the bit line BL and the source line SL;

[0100] The write driver circuit 54 is connected to the precharge circuit 53 and is adapted to control the voltages of the bit line BL and the source line SL to perform a write operation;

[0101] The row decoder 55 is connected to the word line control circuit 20 and is adapted to generate a row decoding signal A;

[0102] The memory array is connected to the word line control circuit 20;

[0103] The word line control circuit 20 is connected to the row decoder 55 and the clock control circuit 51 and is adapted to control the voltage of the word line WL based on the read / write enable signal WREN, the row decoding signal A and the read drive control signal SE to meet operation requirements.

[0104] Assuming that the memory cells in the memory array are m rows and n columns and there are s reference cells, then the row decoding signal A output by the row decoder is m bits and can be expressed as A<m-1:0> ; The number of memory cell bit lines is n, which can be expressed as BL<n-1:0> ; The number of memory cell source lines is also n, which can be expressed as SL<n-1:0> ; The number of memory cell word lines is m, which can be expressed as WL<m-1:0> , the number of reference cell bit lines is s, which can be expressed as ref-BL<s-1:0> ; The number of reference unit source lines is s, which can be expressed as ref-SL<s-1:0> .

[0105] In a specific implementation, the clock signal CLK and the read / write enable signal WREN generate a read driver pre-charge signal SAE and a read driver control signal SE via the clock control circuit 51. The read driver pre-charge signal SAE and the read driver control signal SE are input to the sense amplifier of the read driver circuit 52. The read driver pre-charge signal SAE is set to a high level during a read operation, and the read driver control signal SE is subsequently set to a high level. After the read operation is completed and in other stages such as a write operation, the signal is set to a low level.

[0106] Read drive control signal SE and row decoder output signal A<m-1:0> , the read and write enable signal WREN generates the word line potential required for different operations through the word line control circuit 20. Specifically, when performing a write operation, the corresponding word line is set to a high voltage V WL , the memory cell is opened, the precharge circuit 54 releases the bit line BL and the source line SL, and the write data is controlled by the write drive circuit 53 to control the voltage of the bit line BL and the source line SL, thereby realizing the writing of the corresponding memory cell. When performing a read operation, the corresponding word line is set to a high voltage V CORE , the memory cell is opened, the precharge circuit releases the bit line BL, source line SL, reference cell bit line ref-BL, and reference cell source line ref-SL, and the data of the corresponding memory cell is read through the read driver circuit 52. When the read driver control signal SE is set high, the data is quickly read out, and at this time the word line control circuit 20 turns off the corresponding word line, thereby reducing power consumption.

[0107] In a specific implementation, the read drive circuit may be provided with a plurality of sense amplifiers, each sense amplifier being connected to a plurality of storage cells and a reference cell for reading data from the connected storage cells.

[0108] Figure 6 is a schematic diagram of the circuit structure of a conventional sense amplifier. Referring to Figure 6 , the sense amplifier may include: first to eleventh switches Q1 to Q11. The gates of the first and second switches Q1 and Q2 are connected to the clamping signal CLAMP, forming a clamping circuit. The gates of the third and fourth switches Q3 and Q4 are connected to the read drive control signal SE, forming the switch control circuit of the sense amplifier. The fifth to eighth switches Q5 to Q8 form a crossover inverter. The gates of the ninth to eleventh switches Q9 to Q11 are connected to the read drive precharge signal SAE, forming a precharge circuit.

[0109] The memory cell 61 is connected to one end of the first switching transistor Q1 via a pair of column select transistors, while the reference cell 62 is connected to one end of the second switching transistor Q2 via a pair of column select transistors. The gate of one column select transistor is connected to the column select signal cs, while the gate of the other column select transistor is connected to the inverted column select signal csn. The memory cell 61 includes a MTJ and an access transistor, while the reference cell 62 includes one or more MTJs and an access transistor. The memory cell 61 is connected to the word line WL and the bit line BL, while the reference cell 62 is connected to the reference word line ref-WL and the reference bit line ref-BL.

[0110] When a read operation begins, the read-drive precharge signal SAE is set high before the read-drive control signal SE. The sense amplifier generates different currents based on the resistance difference between the storage cell 61 and the reference cell 62, creating a potential difference at the drains of the third and fourth switches Q3 and Q4. Subsequently, the read-drive control signal SE is set high, and the output terminals OUT and OUT_b are quickly pulled to their corresponding high and low potentials due to feedback, enabling fast data readout.

[0111] By adopting the magnetic random access memory architecture and word line control circuit thereof, the overall architecture design is simple and easy to implement, and can realize fast switching of word line voltage during different operations, thereby reducing read power consumption.

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A word line control circuit, characterized in that, Comprising: A control circuit, adapted to receive a read / write enable signal and a row decoding signal, and generate a first boost control signal and a second boost control signal that are logically opposite; A boost circuit, connected to the control circuit, having a first output terminal and a second output terminal; the boost circuit is adapted to adjust the voltages of the first output terminal and the second output terminal based on the first boost control signal and the second boost control signal during different operations; And a voltage selection circuit, connected to the control circuit and the boost circuit, adapted to apply a write voltage to a corresponding word line during a write operation, and disconnect a path connected to the second output terminal under the control of the voltage of the second output terminal; During a read operation, apply a read voltage to a corresponding word line, and disconnect a path connected to the first output terminal under the control of the voltage of the first output terminal.

2. The word line control circuit according to claim 1, characterized in that, The boost circuit is adapted to set the voltage of the first output terminal to a low level under the control of the first boost control signal and the second boost control signal during a write operation, raise the voltage of the second output terminal to the write voltage, and during a read operation or when no read / write operation is performed, raise the voltage of the first output terminal to the write voltage and set the voltage of the second output terminal to a low level.

3. The word line control circuit according to claim 2, characterized in that, The boost circuit includes: A first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor and a second NMOS transistor; Wherein, the first PMOS transistor, the third PMOS transistor and the first NMOS transistor are connected in series, and the second PMOS transistor, the fourth PMOS transistor and the second NMOS transistor are connected in series; the sources of the first PMOS transistor and the second PMOS transistor are connected to a write voltage output terminal; the gates of the first PMOS transistor and the first NMOS transistor are connected to receive The second boost control signal; the gates of the second PMOS transistor and the second NMOS transistor are connected to receive the first boost control signal; the gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor and serves as the first output terminal; the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor and serves as the second output terminal.

4. The word line control circuit according to any one of claims 1 to 3, characterized in that, The voltage selection circuit includes: A first voltage selection sub-circuit, one end connected to the second output terminal and the other end connected to the word line, adapted to apply the read voltage to a corresponding word line during a read operation, and disconnect a path connected to the first output terminal under the control of the voltage of the first output terminal; A second voltage selection sub-circuit, one end connected to the first output terminal and the other end connected to the word line, adapted to apply the write voltage to a corresponding word line during a write operation, and disconnect a path connected to the second output terminal under the control of the voltage of the second output terminal; A word line closing sub-circuit, connected to the first voltage selection sub-circuit and the second voltage selection sub-circuit, adapted to close the word line.

5. The word line control circuit according to claim 4, characterized in that, The first voltage selection sub-circuit includes: a fifth PMOS transistor and a sixth PMOS transistor connected in series; the source of the fifth PMOS transistor is connected to the read voltage output terminal; the gate of the fifth PMOS transistor is connected to the inverted signal of the row decoding signal; the gate of the sixth PMOS transistor is connected to the second output terminal, and the drain of the sixth PMOS transistor is connected to the word line.

6. The word line control circuit according to claim 4, characterized in that, The second voltage selection sub-circuit includes: a seventh PMOS transistor, the gate of the seventh PMOS transistor is connected to the first output terminal, the source is connected to the write voltage output terminal, and the drain is connected to the word line.

7. The word line control circuit according to claim 4, characterized in that, The word line shutdown circuit includes: a third NMOS transistor and a fourth NMOS transistor connected in series; the gate of the third NMOS transistor is connected to the second boost control signal, the gate of the fourth NMOS transistor is connected to the inverted signal of the row decoding signal; the source of the fourth NMOS transistor is grounded.

8. The word line control circuit according to claim 1, characterized in that, The control circuit includes: a first AND gate circuit, a first inverter and a second inverter; Wherein, the input terminal of the first AND gate circuit is connected to the read / write enable signal and the row decoding signal; the output terminal of the first AND gate circuit generates the first boost control signal; the output terminal of the first AND gate circuit is connected to the input terminal of the first inverter, and the output terminal of the first inverter generates the second boost control signal; the input terminal of the second inverter is connected to the row decoding signal, and the output terminal of the second inverter is connected to the voltage selection circuit.

9. The word line control circuit according to claim 1, characterized in that, The control circuit is further adapted to receive a read drive control signal, and jointly generate a control signal for the voltage selection circuit based on the read drive control signal, the read / write enable signal and the row decoding signal, so as to turn off the word line after reading data.

10. The word line control circuit according to claim 9, characterized in that, The control circuit includes: a first AND gate circuit, a second AND gate circuit, a first inverter, a second inverter and a third inverter; Wherein, the input terminal of the third inverter is connected to the read drive control signal; the input terminal of the second AND gate circuit is connected to the row decoding signal and the output signal of the third inverter; the input terminal of the first AND gate circuit is connected to the read / write enable signal and the output signal of the second AND gate circuit; the output terminal of the first AND gate circuit generates the first boost control signal; the output terminal of the first AND gate circuit is connected to the input terminal of the first inverter, and the output terminal of the first inverter generates the second boost control signal; the input terminal of the second inverter is connected to the output signal of the second AND gate circuit, and the output terminal of the second inverter is connected to the voltage selection circuit.

11. A magnetic random access memory, characterized in that, Including the word line control circuit according to any one of claims 1 to 10.

12. The magnetic random access memory according to claim 11, characterized in that, The magnetic random access memory further includes: A clock control circuit, adapted to receive a clock signal and the read / write enable signal, and generate a read drive precharge signal and a read drive control signal; A read drive circuit, connected to the clock control circuit, adapted to perform a read operation under the control of the read drive precharge signal and the read drive control signal; A precharge circuit, connected to the read drive circuit, adapted to precharge the bit line and the source line; A write driver circuit, connected to the precharge circuit, adapted to control the voltages of the bit lines and the source lines to perform a write operation; A row decoder, connected to the word line control circuit, adapted to generate a row decoding signal; A memory array, connected to the word line control circuit; The word line control circuit, connected to the row decoder and the clock control circuit, adapted to control the word line voltage based on the read / write enable signal, the row decoding signal, and the read drive control signal to meet the operation requirements.

Images