Data transmission system and automatic delay value acquisition method

Abstract

A data transmission system and an automatic delay value acquisition method. For an interface to be tested, an AD chip determines a first delay test value of a clock line relative to a data line on the basis of a preset delay set, sends first test data to an SOC chip by means of the data line, uses a delay-locked loop module to generate a clock signal on the basis of the first delay test value, and sends the clock signal to the SOC chip by means of the clock line; the SOC chip receives, on the basis of the clock signal, the first test data sent by the AD chip to obtain second test data, and returns the second test data to the AD chip; the AD chip compares the received test data with the first test data sent by the AD chip, and when the received test data and the first test data are the same, determines that the first delay test value is a target delay test value. In this way, when using the AD chip, the delay value of the clock line relative to the data line can be automatically determined, and because the delay value is obtained by automatic testing conducted by the device, the test efficiency is significantly enhanced, and the test accuracy is improved.

Description

A data transmission system and a method for automatically obtaining a delay value

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 11, 2023, with application number 202311690397.7 and invention name “A data transmission system and method for automatically obtaining delay values”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a data transmission system and a method for automatically obtaining a delay value. Background Art

[0003] In the case of serial synchronous communication, the clock line of the communication bus has a delay relative to the data line. Taking rising edge acquisition as an example: rising edge acquisition includes setup time (Tsu) and hold time (Thd), as shown in Figure 1. In Figure 1, clk1 is the clock signal, D1 is the data signal, and bit0 is the actual transmitted data, where:

[0004] Tsu is the time interval during which the data at the input terminal has arrived and remains stable before the rising edge of the clock.

[0005] Thd is the time interval during which the input data remains stable after the rising edge of the clock.

[0006] Simply put, the build time means "preparation in advance" and the hold time means "remaining unchanged afterwards".

[0007] At the receiving end, if data remains stable for a period of time before and after the rising edge of the clock, the data is considered to have been correctly collected on that rising edge. The delay between the rising edge of the clock at the receiving end and the location of the data center is the delay between the clock line and the data line in the communication interface, known as clkdelay. Because the clkdelay value affects the accuracy of data collected at the receiving end, a significant deviation between the rising edge position and the location of the collected data center may result in erroneous data.

[0008] In the prior art, a clkdelay value is tested before a device leaves the factory, and the tested clkdelay value is set as the unique and non-adjustable clkdelay value of the device. After the device leaves the factory, if the device circuit changes, the clkdelay value set before the device leaves the factory may be unreasonable. If this clkdelay value continues to be used as the final value for all motherboards, data transmission errors will occur.

[0009] Therefore, how to determine the clkdelay value becomes an urgent problem to be solved. Summary of the Invention

[0010] The purpose of the embodiments of the present application is to provide a data transmission system and a method for automatically obtaining a delay value, so as to automatically determine the delay value of a clock line relative to a data line when using a device. The specific technical solution is as follows:

[0011] In a first aspect, an embodiment of the present application provides a data transmission system, the system comprising:

[0012] An AD chip, a SOC chip, and at least one data communication bus; the AD chip includes a delay-locked loop module; the AD chip includes at least one interface, each interface corresponding to a data communication bus; wherein the data communication bus includes a clock line and a data line, and the AD chip and the SOC chip are communicatively connected via the interface and the data communication bus;

[0013] The AD chip is configured to: select, for an interface to be tested, a delay test value from a preset delay set as a first delay test value of the interface to be tested, the first delay test value representing a communication delay of a clock line relative to the data line in the same data communication bus, wherein the interface to be tested is an interface of the AD chip;

[0014] The AD chip is configured to: send first test data to the SOC chip through the interface to be tested and a data line in a data communication bus corresponding to the interface to be tested, generate a clock signal based on the first delay test value using the delay locked loop module, and send the clock signal to the SOC chip through a clock line in the data communication bus corresponding to the interface to be tested;

[0015] The SOC chip is configured to: receive first test data sent by the AD chip based on the received clock signal to obtain second test data; send the clock signal to the AD chip through the clock line, and return the second test data to the AD chip through the data line via the interface to be tested;

[0016] The AD chip is configured to: receive the second test data returned by the SOC chip based on the received clock signal, obtain third test data, and compare the third test data with the first test data; if the third test data is the same as the first test data, determine that the first delay test value is the target delay test value of the interface to be tested; if the third test data is different from the first test data, determine that the first delay test value is not the target delay test value of the interface to be tested.

[0017] In a possible implementation manner, the AD chip is further configured as follows:

[0018] In the case where the third test data is identical to the first test data, after the step of determining that the first delay test value is the target delay test value of the interface to be tested, selecting a delay test value that has not been selected from the preset delay set as the first delay test value of the interface to be tested, and returning to the step of the AD chip sending the first test data to the SOC chip through the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, generating a clock signal based on the first delay test value by using the delay phase-locked loop module, and sending the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested to continue execution until the preset delay set is traversed and one or more target delay test values ​​are obtained;

[0019] The AD chip determines an optimal target delay test value from a plurality of target delay test values ​​based on a preset first rule, and configures the optimal target delay test value as the delay value of the clock line of the interface to be tested relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0020] In a possible implementation, the AD chip is specifically configured as follows:

[0021] Determining an optimal target delay test value from the plurality of target delay test values ​​based on a preset first rule includes:

[0022] The median of the plurality of target delay test values ​​is taken as the optimal target delay test value.

[0023] In one possible implementation, when the AD chip is powered on and before sending the first test data to the SOC chip through the data line, the AD chip is configured to select a delay test value from a preset delay set as the first delay test value of the interface to be tested.

[0024] In a possible implementation manner, the AD chip is further configured to: when the third test data is the same as the first test data, after determining that the first delay test value is the target delay test value of the interface to be tested; select another delay test value from the preset delay set as the first delay test value of the interface to be tested, and return to the step of the AD chip sending the first test data to the SOC chip through the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, using the delay phase-locked loop module to generate a clock signal based on the first delay test value, sending the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested, and continue executing until the preset delay set is traversed and a set of target delay test values ​​is obtained;

[0025] Repeat the above traversal process to obtain a preset number of target delay test values;

[0026] The AD chip determines an optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, and uses the optimal target delay test value as the delay value of the clock line relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0027] In a possible implementation, the AD chip is specifically configured as follows:

[0028] Determining an optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule includes:

[0029] Taking the intersection of the preset number of groups of target delay test values;

[0030] A target delay test value is selected from the intersection as the optimal target delay test value.

[0031] In a possible implementation, the AD chip includes at least one high-definition signal interface and / or at least one ultra-high-definition signal interface.

[0032] In a second aspect, an embodiment of the present application provides a method for automatically acquiring a delay value, which is applied to a data transmission system, wherein the data transmission system includes an AD chip, a SOC chip, and at least one data communication bus, wherein the AD chip includes at least one interface, and each interface corresponds to a data communication bus; wherein the data communication bus includes a clock line and a data line, and the AD chip and the SOC chip are communicatively connected through the interface and the data communication bus; the AD chip includes a delay phase-locked loop module; and the method includes:

[0033] The AD chip selects, for an interface to be tested, a delay test value from a preset delay set as a first delay test value of the interface to be tested, the first delay test value representing a communication delay of a clock line relative to the data line in the same data communication bus, wherein the interface to be tested is an interface of the AD chip;

[0034] The AD chip sends first test data to the SOC chip through the interface to be tested and a data line in the data communication bus corresponding to the interface to be tested, generates a clock signal based on the first delay test value using the delay locked loop module, and sends the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested;

[0035] The SOC chip receives the first test data sent by the AD chip based on the received clock signal to obtain second test data; sends the clock signal to the AD chip through the clock line, and returns the second test data to the AD chip through the interface to be tested through the data line;

[0036] The AD chip receives the second test data returned by the SOC chip based on the received clock signal, obtains third test data, and compares the third test data with the first test data. When the third test data is the same as the first test data, it is determined that the first delay test value is the target delay test value of the interface to be tested. When the third test data is different from the first test data, it is determined that the first delay test value is not the target delay test value of the interface to be tested.

[0037] In one possible implementation, the method further includes:

[0038] After the step of determining that the first delay test value is the target delay test value of the interface to be tested when the third test data is the same as the first test data, the AD chip selects another delay test value from the preset delay set as the first delay test value of the interface to be tested, and returns to the step of sending the first test data to the SOC chip through the interface to be tested and a data line in a data communication bus corresponding to the interface to be tested, generating a clock signal based on the first delay test value by using the delay-locked loop module, sending the clock signal to the SOC chip through a clock line in the data communication bus corresponding to the interface to be tested, and continuing the execution until the preset delay set is traversed and one or more target delay test values ​​are obtained;

[0039] The AD chip determines an optimal target delay test value from a plurality of target delay test values ​​based on a preset first rule, and uses the optimal target delay test value as the delay value of the clock line of the interface to be tested relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0040] In a possible implementation, the AD chip determines the optimal target delay test value from the plurality of target delay test values ​​based on a preset first rule, including:

[0041] The median of the plurality of target delay test values ​​is taken as the optimal target delay test value.

[0042] In a possible implementation manner, the AD chip selects, for the interface to be tested, a delay test value from a preset delay set as a first delay test value of the interface to be tested, including:

[0043] The AD chip is powered on and before sending first test data to the SOC chip through the data line, a delay test value is selected from a preset delay set as a first delay test value of the interface to be tested.

[0044] In one possible implementation, the method further includes:

[0045] After the step of, the AD chip determining, when the third test data is identical to the first test data, that the first delay test value is the target delay test value of the interface to be tested;

[0046] Select another delay test value from the preset delay set as the first delay test value of the interface to be tested, and return to step, wherein the AD chip sends first test data to the SOC chip through the interface to be tested and a data line in the data communication bus corresponding to the interface to be tested, generates a clock signal based on the first delay test value by using the delay phase-locked loop module, and sends the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested, and continues to execute until the preset delay set is traversed to obtain a set of target delay test values;

[0047] Repeat the above traversal process to obtain a preset number of target delay test values;

[0048] The AD chip determines an optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, and uses the optimal target delay test value as the delay value of the clock line relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0049] In a possible implementation, the AD chip determines the optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, including:

[0050] Taking the intersection of the preset number of groups of target delay test values;

[0051] A target delay test value is selected from the intersection as the optimal target delay test value.

[0052] Another aspect of an embodiment of the present application provides a method for automatically obtaining a delay value, which is applied to a first chip. The method includes:

[0053] Selecting a delay test value from a preset delay set to obtain a first delay test value of the interface to be tested in the first chip, wherein the first delay test value represents a communication delay of a clock line relative to a data line in a data communication bus corresponding to the interface to be tested;

[0054] generating a clock signal based on the first delay test value, sending the clock signal to the second chip through the interface to be tested and the clock line, and sending first test data to the second chip using the interface to be tested and the data line, so that the second chip receives the first test data based on the clock signal to obtain second test data, sends the clock signal to the first chip through the clock line, and returns the second test data to the first chip through the interface to be tested through the data line;

[0055] receiving second test data returned by the second chip based on the received clock signal to obtain third test data;

[0056] The third test data is compared with the first test data. If the third test data is the same as the first test data, it is determined that the first delay test value is the target delay test value of the interface to be tested. If the third test data is different from the first test data, it is determined that the first delay test value is not the target delay test value of the interface to be tested.

[0057] In a possible implementation manner, the first chip is an AD chip, and the second chip is a SOC chip; or, the first chip is a SOC chip, and the second chip is an AD chip.

[0058] In a possible implementation, after comparing the third test data with the first test data and, if the third test data is identical to the first test data, determining that the first delay test value is the target delay test value of the interface to be tested, and if the third test data is different from the first test data, determining that the first delay test value is not the target delay test value of the interface to be tested, the method further includes:

[0059] Selecting a delay test value that has not been selected from the preset delay set as the first delay test value of the interface to be tested, and returning to the step of generating a clock signal based on the first delay test value, sending the clock signal to the second chip through the interface to be tested and the clock line, and sending first test data to the second chip using the interface to be tested and the data line, and continuing the process until the preset delay set is traversed and one or more target delay test values ​​are obtained;

[0060] An optimal target delay test value is determined from the multiple target delay test values, and the optimal target delay test value is used as the delay value of the clock line of the interface to be tested relative to the data line, so that the first chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0061] In a possible implementation manner, determining an optimal target delay test value from the multiple target delay test values ​​includes:

[0062] The median of the plurality of target delay test values ​​is taken as the optimal target delay test value.

[0063] In a possible implementation manner, selecting a delay test value from a preset delay set to obtain a first delay test value of the interface to be tested in the first chip includes:

[0064] When the first chip is powered on and before first test data is sent to the second chip through the data line, a delay test value is selected from a preset delay set as a first delay test value of the interface to be tested.

[0065] In a possible implementation, after comparing the third test data with the first test data and, if the third test data is identical to the first test data, determining that the first delay test value is the target delay test value of the interface to be tested, and if the third test data is different from the first test data, determining that the first delay test value is not the target delay test value of the interface to be tested, the method further includes:

[0066] Selecting a delay test value that has not been selected from the preset delay set as the first delay test value of the interface to be tested, and returning to the step of generating a clock signal based on the first delay test value, sending the clock signal to the second chip through the interface to be tested and the clock line, and sending first test data to the second chip using the interface to be tested and the data line, and continuing the process until the preset delay set is traversed to obtain a set of target delay test values;

[0067] Repeat the above traversal process to obtain a preset number of target delay test values;

[0068] An optimal target delay test value is determined from the preset number of groups of target delay test values, and the optimal target delay test value is used as the delay value of the clock line relative to the data line, so that the first chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0069] In a possible implementation manner, determining the optimal target delay test value from the preset number of groups of target delay test values ​​includes:

[0070] Taking the intersection of the preset number of groups of target delay test values;

[0071] A target delay test value is selected from the intersection as the optimal target delay test value.

[0072] Another aspect of the present application provides an electronic device, including:

[0073] a memory configured to store a computer program;

[0074] The processor is configured to implement any of the above-mentioned steps of the method for automatically obtaining the delay value when executing the program stored in the memory.

[0075] In another aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above-mentioned methods for automatically obtaining a delay value is implemented.

[0076] Another aspect of an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the above-mentioned methods for automatically obtaining a delay value.

[0077] Beneficial effects of the embodiments of the present application:

[0078] The present invention provides a method and data transmission system for automatically acquiring a delay value. For an interface to be tested, an AD chip determines a first delay test value of a clock line relative to a data line based on a preset delay set. The AD chip then sends first test data to a SOC chip via the data line. A delay-locked loop (DLL) module generates a clock signal based on the first delay test value and sends the clock signal to the SOC chip via the clock line. The SOC chip receives the first test data sent by the AD chip based on the received clock signal, obtains second test data, and returns the second test data to the AD chip via the data line. The AD chip compares the received test data with the first test data it sent. If the two are the same, the first delay test value is determined to be the target delay test value. In this way, when using the AD chip, the delay value of the clock line relative to the data line of the interface to be tested can be automatically determined. Furthermore, because the delay value is automatically determined by the device, not only is test efficiency greatly improved, the tedious steps of manual testing are eliminated, and accuracy is also increased. This target delay test value can offset the delay between the clock line and the data line caused by hardware routing and other factors, thereby improving the accuracy of the collected data.

[0079] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0081] FIG1 is a schematic diagram of setup time and hold time in the related art;

[0082] FIG2-1 is a schematic diagram of a first structure of a data transmission system provided in an embodiment of the present application;

[0083] FIG2-2 is a schematic diagram of a second structure of a data transmission system provided in an embodiment of the present application;

[0084] FIG3 is a schematic diagram of a first flow chart of a method for automatically obtaining a delay value provided in an embodiment of the present application;

[0085] FIG4 is a schematic diagram of a second flow chart of the method for automatically obtaining a delay value provided in an embodiment of the present application. DETAILED DESCRIPTION

[0086] To make the objectives, technical solutions, and advantages of this application more clearly understood, the present application is further described below with reference to the accompanying drawings and examples. It is apparent that the described examples are only a portion of the embodiments of this application, and not all of them. All other embodiments derived by persons of ordinary skill in the art based on the examples in this application are intended to fall within the scope of protection of this application.

[0087] First, the terms involved in the embodiments of this application are explained:

[0088] BT656: A data transmission protocol that includes a data line and a clock line.

[0089] clkdelay: The delay of the clock line relative to the data line in a data communication bus.

[0090] AD chip: In this article, it refers to the chip on the DVR that is configured to convert analog signals into digital signals.

[0091] SOC chip: In this article, it refers to the main chip on the DVR that connects to the AD chip.

[0092] The length of the data communication bus between the AD chip and the SOC chip on the PCB (Printed Circuit Board) and the peripheral circuits of the data communication bus may affect the signal transmission on the data line, resulting in a deviation between the data received by the receiving end and the data sent by the sending end. Therefore, as long as there is a modification to the hardware circuit, the delay value of the clock line of the data communication bus relative to the data line needs to be re-determined to ensure that the receiving end can accurately receive the data sent by the sending end.

[0093] To this end, embodiments of the present application disclose a data transmission system and a method for automatically obtaining a delay value, which are described below respectively.

[0094] First, an embodiment of the present application provides a data transmission system. Referring to FIG. 2-1 , FIG. 2-1 is a schematic diagram of a first embodiment of the data transmission system of the present application. The system includes:

[0095] An AD chip 110, a SOC chip 120, and at least one data communication bus 130; the AD chip 110 includes a delay-locked loop module; the AD chip 110 includes an interface, each interface corresponding to a data communication bus; wherein the data communication bus 130 includes a clock line 131 and a data line 132, and the AD chip 110 and the SOC chip 120 are communicatively connected via the interface and the data communication bus 130;

[0096] The AD chip 110 is configured to select, for an interface to be tested, a delay test value from a preset delay set as a first delay test value of the interface to be tested, wherein the first delay test value represents a communication delay of a clock line relative to the data line in the same data communication bus, wherein the interface to be tested is an interface of the AD chip;

[0097] The AD chip 110 is configured to send first test data to the SOC chip 120 via the interface to be tested and a data line in the data communication bus corresponding to the interface to be tested, generate a clock signal based on the first delay test value using the delay-locked loop module, and send the clock signal to the SOC chip 120 via a clock line in the data communication bus corresponding to the interface to be tested;

[0098] The SOC chip 120 is configured to receive the first test data sent by the AD chip 110 based on the received clock signal, obtain second test data, return the second test data to the AD chip 110 via the test interface through the data line, and send the clock signal to the AD chip 110 through the clock line;

[0099] The above-mentioned AD chip 110 is configured to receive the second test data returned by the above-mentioned SOC chip based on the received clock signal, obtain third test data, and compare the above-mentioned third test data with the above-mentioned first test data. When the above-mentioned third test data is the same as the above-mentioned first test data, it is determined that the above-mentioned first delay test value is the target delay test value of the above-mentioned interface to be tested. When the above-mentioned third test data is different from the above-mentioned first test data, it is determined that the above-mentioned first delay test value is not the target delay test value of the above-mentioned interface to be tested.

[0100] The delay-locked loop module is a clock generation circuit that adjusts the output of the voltage-controlled delay line according to the phase difference between the input clock and the output clock, so that the phase of the output clock remains consistent with the input clock.

[0101] AD chips generally include multiple different interfaces. For example, AD chips include multiple high-definition interfaces and multiple ultra-high-definition interfaces. A high-definition interface refers to an interface that supports high-definition resolution image transmission. High-definition resolution includes 1280×720 resolution and 1920×1080 resolution. The high-definition interface can be HDMI (High Definition Multimedia) or the like. An ultra-high-definition interface refers to an interface that supports ultra-high-definition resolution image transmission. Ultra-high-definition resolution includes 3840×2160 resolution. The ultra-high-definition interface can be HDBaseT (projector interface). Exemplarily, the AD chip includes 2 high-definition interfaces and 4 ultra-high-definition interfaces, or the AD chip includes 2 high-definition interfaces, or the AD chip includes 4 ultra-high-definition interfaces.

[0102] The interface of the AD chip is configured to communicate with the outside. Specifically, the interface of the AD chip is communicatively connected to the interface of the SOC chip via a data communication bus. The data communication bus to which the interface of the AD chip is connected is referred to as the data communication bus corresponding to the interface. The data communication bus includes a clock line and a data line. The interface is configured to connect to the data communication bus. The AD chip and the SOC chip are communicatively connected via the data communication bus. Exemplarily, one end of the data communication bus is connected to the interface of the AD chip, and the other end of the data communication bus is connected to the interface of the SOC chip. The data communication bus connects the SOC chip and the AD chip via interfaces corresponding to each other, wherein the interfaces corresponding to each other refer to interfaces that support the same communication protocol and communicate between the two. Exemplarily, the AD chip includes a first-end communication port, and the SOC chip includes a second-end communication port. The second-end communication port is an interface corresponding to the first-end communication port. One end of the data communication bus is connected to the first-end communication port, and the other end of the data communication bus is connected to the second-end communication port.

[0103] A clock line is a line used to transmit clock signals, and a data line is a line used to transmit data. A data communication bus includes a clock line and at least one data line. The interface of an AD chip includes at least one clock line sub-interface and at least one data line sub-interface, with the clock line of the data communication bus connected via the clock line sub-interface and the data line of the data communication bus connected via the data line. Similarly, the interface of an SOC chip also includes at least one clock line sub-interface and at least one data line sub-interface, with the clock line of the data communication bus connected via the clock line sub-interface and the data line of the data communication bus connected via the data line.

[0104] The preset delay set can be configured based on actual conditions. In one example, the delay test values ​​in the preset delay set are all integers. For example, the preset delay set may be integers ranging from 0-100 or 0-200. Increasing the delay test value by one will cause the delay of the AD clock line relative to the data line to change by a preset number of picoseconds. For example, a delay test value of ±1 will cause the delay of the AD clock line relative to the data line to change by ±1 picosecond.

[0105] The interface to be tested is an interface configured for data transmission during this data transmission process, or an interface manually designated and configured for testing.

[0106] If it is determined that data is transmitted through an interface, the interface for transmitting data is the interface to be tested. The method for determining the interface to be tested can be determined by the AD chip based on the format of the data to be sent, or it can be specified by the user through a preset interface, which is not specifically limited.

[0107] Exemplarily, if the format of the data to be sent is HDMI format, then the interface to be tested is a high-definition interface. When the AD chip has multiple high-definition interfaces, any one of the multiple high-definition interfaces can be designated as the interface to be tested.

[0108] The delay value of the interface to be tested must first be determined. The delay value refers to the communication delay of the clock line relative to the data line, or in other words, the delay value refers to the communication time difference between the clock line and the data line. The AD chip can determine a value from a preset delay set as the first delay test value of the clock line relative to the data line. For example, the AD chip can randomly select a value from the preset delay set as the first delay test value of the clock line relative to the data line, or it can select values ​​according to a preset rule, for example, selecting values ​​in ascending order or descending order. The specific selection can be determined based on actual conditions.

[0109] After determining a first delay test value of the clock line relative to the data line, the AD chip sends first test data to the SOC chip via the data line, where the first test data can be data in any format, for example, the first test data is an alternating high and low level signal of 1010101010101010..., and a DLL (Delay Locked Loop) module is used to generate a clock signal based on the first delay test value. The AD chip then sends a clock signal to the SOC chip via the clock line. The SOC chip receives the first test data sent by the AD chip based on the received clock signal to obtain second test data, and returns the second test data to the AD chip via the data line via the interface to be tested. The clock signal is then sent to the AD chip via the clock line. The AD chip receives the second test data returned by the SOC chip based on the received clock signal to obtain third test data, and compares the third test data with the first test data. If the third test data is the same as the first test data, it is determined that the first delay test value is the target delay test value. If the third test data is different from the first test data, it is determined that the first delay test value is not the target delay test value.

[0110] Furthermore, when the third test data is different from the first test data and it is determined that the first delay test value is not the target delay test value, the AD chip redetermines the first delay test value of the clock line relative to the above-mentioned data line based on the preset delay set, that is, selects another delay test value from the preset delay set as the first delay test value of the interface to be tested, and returns to the step. The AD chip sends the first test data to the SOC chip through the interface to be tested and the data line, uses the delay phase-locked loop module to generate a clock signal based on the first delay test value, and sends the clock signal to the SOC chip through the clock line. After obtaining the target delay test value, when the AD chip determines to transmit the data to be transmitted through the interface to be tested, it can transmit the data to be transmitted through the interface to be tested based on the target delay test value.

[0111] For the interface to be tested, the AD chip determines a first delay test value of the clock line relative to the data line based on a preset delay set. The AD chip then sends first test data to the SOC chip via the data line. A delay-locked loop module generates a clock signal based on the first delay test value and sends the clock signal to the SOC chip via the clock line. The SOC chip receives the first test data sent by the AD chip based on the received clock signal, obtains second test data, and returns the second test data to the AD chip via the data line. The AD chip compares the received test data with the first test data it sent. If the two are the same, it determines that the first delay test value is the target delay test value. In this way, when using the AD chip, the delay value of the clock line relative to the data line of the interface to be tested can be automatically determined. Furthermore, because the delay value is automatically determined by the device, it not only greatly improves test efficiency and eliminates the tedious steps of manual testing, but also increases accuracy. Based on this target delay test value, the delay between the clock line and the data line caused by hardware routing and other factors can be offset, improving the accuracy of the collected data.

[0112] In a possible implementation manner, the AD chip is further configured as follows:

[0113] In the case that the third test data is the same as the first test data, after the step of determining that the first delay test value is the target delay test value of the interface to be tested, a delay test value that has not been selected is selected from the preset delay set as the first delay test value of the interface to be tested, and returning to the step of the AD chip sending the first test data to the SOC chip through the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, using the delay phase-locked loop module to generate a clock signal based on the first delay test value, and sending the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested, and continuing the execution until the preset delay set is traversed and one or more target delay test values ​​are obtained;

[0114] The above-mentioned AD chip determines the optimal target delay test value from the multiple target delay test values ​​based on a preset first rule, and uses the above-mentioned optimal target delay test value as the delay value of the clock line of the above-mentioned interface to be tested relative to the data line, so that the above-mentioned AD chip sends the data to be sent through the above-mentioned interface to be tested based on the above-mentioned optimal target delay test value.

[0115] When the two are the same, after determining that the first delay test value is the target delay test value, a new first delay test value of the clock line relative to the data line can be determined from the preset delay set, wherein other delay test values ​​can be randomly updated to the first delay test value based on the preset delay set, or the first delay test value can be determined according to a preset traversal rule. For example, the next value of the first delay test value can be updated to the first delay test value, or the previous value of the first delay test value can be updated to the first delay test value. The specific setting is based on actual conditions and is not limited here.

[0116] After traversing the preset delay set, all target delay test values ​​are obtained, and then an optimal target delay test value is determined from all target delay test values. For example, the median of all target delay test values ​​can be used as the optimal target delay test value. The AD chip is then caused to send data to be sent through the interface to be tested based on the target delay test value.

[0117] In a possible implementation, the AD chip is specifically configured as follows:

[0118] When the AD chip is powered on and before sending the first test data to the SOC chip through the data line, the AD chip is configured to select a delay test value from a preset delay set as the first delay test value of the interface to be tested.

[0119] Whenever the device is restarted, the target delay test value is re-determined, so that the delay value used after each device startup is accurate.

[0120] In a possible implementation manner, the AD chip is specifically configured to, when the third test data is the same as the first test data, determine that the first delay test value is the target delay test value, and record the target delay test value.

[0121] Every time the AD chip tests a reasonable value, the value can be recorded, and the first delay test value can be updated after recording until all target delay test values ​​are obtained.

[0122] In a possible implementation, the data communication bus may be any bus that supports serial synchronous communication, such as a BT601 communication bus, a BT656 communication bus, a BT709 communication bus, a BT1120 communication bus, and the like.

[0123] See Figure 2-2, which is a second schematic diagram of the data transmission system according to an embodiment of the present application.

[0124] The AD chip includes a hardware module and a software module. The AD chip and the SOC chip are connected via the BT656 interface. The SOC chip then returns the received data to the AD chip's hardware module via the BT656 interface. The hardware module can be a DLL module, which is a circuit module that uses an external clock signal to generate a signal with the required phase. The AD chip's hardware module receives this data and sends it to the software module inside the AD chip. The software module parses the data and matches the parsed data with the sent data.

[0125] In a possible implementation, the AD chip is specifically configured as follows:

[0126] The AD chip determines the next value of the first delay test value as the first delay test value based on the preset delay set.

[0127] The values ​​of the preset delay set can be discrete set points. When the first delay test value is re-determined, the next value of the first delay test value can be determined as the first delay test value, where, for two endpoint values ​​in the preset delay set, the smaller endpoint value is the next value of the larger endpoint value. For example, if the preset delay set is 1-100, where the delay test value is an integer, when the first delay test value is 40, 41 can be determined as the first delay test value. When the first delay test value is 100, 1 can be determined as the first delay test value.

[0128] In a possible implementation, the AD chip is specifically configured as follows:

[0129] The AD chip determines a previous value of the first delay test value as the first delay test value based on the preset delay set.

[0130] The values ​​of the preset delay set can be discrete set points. When determining the first delay test value, the previous value of the first delay test value can be determined as the first delay test value, where, for two endpoint values ​​in the preset delay set, the larger endpoint value is the value next to the smaller endpoint value. For example, if the preset delay set is 1-100, where the delay test value is an integer, when the first delay test value is 40, 39 can be determined as the first delay test value. When the first delay test value is 1, 100 can be determined as the first delay test value.

[0131] In a possible implementation, the AD chip is specifically configured as follows:

[0132] The above-mentioned AD chip randomly extracts a value as the delay test value to be determined based on the above-mentioned preset delay set, and determines whether the delay test value to be determined is the same as the first delay test value. If different, the delay test value to be determined is determined as the first delay test value. If the same, continue to randomly extract a value as the delay test value to be determined.

[0133] In a possible implementation, the AD chip is specifically configured as follows:

[0134] Determining an optimal target delay test value from the plurality of target delay test values ​​based on a preset first rule includes:

[0135] The median of the multiple target delay test values ​​is taken as the optimal target delay test value.

[0136] After obtaining all the target delay test values, the median of the multiple target delay test values ​​is used as the optimal target delay test value. The optimal target delay test value is used to act on the clock line by setting the register, so as to offset the delay between the clock line and the data line caused by hardware routing and other reasons, thereby improving the accuracy of the collected data.

[0137] In a possible implementation manner, the AD chip is further configured as follows:

[0138] The AD chip is further configured to: after the step of determining that the first delay test value is the target delay test value of the interface to be tested when the third test data is the same as the first test data; select another delay test value from the preset delay set as the first delay test value of the interface to be tested, and return to the step of the AD chip sending the first test data to the SOC chip via the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, generating a clock signal based on the first delay test value by using the delay phase-locked loop module, sending the clock signal to the SOC chip via the clock line in the data communication bus corresponding to the interface to be tested, and continuing the execution until the preset delay set is traversed and a set of target delay test values ​​is obtained;

[0139] Repeat the above traversal process to obtain a preset number of target delay test values;

[0140] The above-mentioned AD chip determines the optimal target delay test value from the above-mentioned preset number of groups of target delay test values ​​based on the preset second rule, and uses the above-mentioned optimal target delay test value as the delay value of the above-mentioned clock line relative to the above-mentioned data line, so that the above-mentioned AD chip sends the data to be sent through the above-mentioned interface to be tested based on the above-mentioned optimal target delay test value.

[0141] A set of target delay test values ​​includes at least one target delay test value. The AD chip can repeatedly traverse the preset delay set multiple times to obtain multiple sets of traversal results. That is, each traversal results in at least one target delay test value. Finally, the multiple sets of traversal results can be compared based on preset rules to determine an optimal target delay test value from the multiple sets of results. The optimal target delay test value is used as the target delay test value for the data line to ensure the accuracy and consistency of the determined target delay test value. This allows the AD chip to send data to be sent through the interface to be tested based on the accurate target delay test value.

[0142] In a possible implementation, the AD chip is specifically configured as follows:

[0143] Determining the optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule includes:

[0144] Taking the intersection of the above preset number of groups of target delay test values;

[0145] A target delay test value is selected from the above intersection as the optimal target delay test value.

[0146] After obtaining a preset number of groups of target delay test values, an intersection of the preset number of groups of target delay test values ​​may be taken, and then a target delay test value may be selected from the intersection as an optimal target delay test value.

[0147] Alternatively, after the intersection is determined, the median of the target delay test values ​​in the intersection is determined as the optimal target delay test value, to ensure the accuracy and consistency of the determined target delay test value.

[0148] In a possible implementation, the AD chip is specifically configured as follows:

[0149] If the above intersection is an empty set, a reminder message is generated, so that the user can detect the AD chip based on the reminder message.

[0150] Based on the above embodiment, referring to FIG3 , FIG3 is a first flow chart of a method for automatically obtaining a delay value provided in an embodiment of the present application, which is applied to a data transmission system. The data transmission system includes an AD chip, an SOC chip, and at least one data communication bus. The AD chip includes at least one interface, and each interface corresponds to a data communication bus; wherein the data communication bus includes a clock line and a data line, and the AD chip and the SOC chip are communicatively connected through the interface and the data communication bus; the AD chip includes a delay phase-locked loop module; the method includes:

[0151] S310: The AD chip selects a delay test value from a preset delay set for an interface to be tested as a first delay test value of the interface to be tested, wherein the first delay test value represents a communication delay of a clock line relative to the data line in the same data communication bus, wherein the interface to be tested is an interface of the AD chip.

[0152] S320, the AD chip sends first test data to the SOC chip through the interface to be tested and a data line in the data communication bus corresponding to the interface to be tested, generates a clock signal based on the first delay test value using the delay-locked loop module, and sends the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested;

[0153] S330, the SOC chip receives the first test data sent by the AD chip based on the received clock signal, obtains second test data, returns the second test data to the AD chip via the test interface through the data line, and sends the clock signal to the AD chip via the clock line;

[0154] S340, the AD chip receives the second test data returned by the SOC chip based on the received clock signal, obtains the third test data, and compares the third test data with the first test data. When the third test data is the same as the first test data, it is determined that the first delay test value is the target delay test value of the interface to be tested. When the third test data is different from the first test data, it is determined that the first delay test value is not the target delay test value of the interface to be tested.

[0155] In a possible implementation manner, when the matching is successful, the method further includes:

[0156] After the step of determining that the first delay test value is the target delay test value of the interface to be tested when the third test data is the same as the first test data, the AD chip selects another delay test value from the preset delay set as the first delay test value of the interface to be tested, and returns to the step of sending the first test data to the SOC chip via the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, generating a clock signal based on the first delay test value by using the delay phase-locked loop module, and sending the clock signal to the SOC chip via the clock line in the data communication bus corresponding to the interface to be tested, and continuing the execution until the preset delay set is traversed and one or more target delay test values ​​are obtained;

[0157] The above-mentioned AD chip determines the optimal target delay test value from the multiple target delay test values ​​based on a preset first rule, and uses the above-mentioned optimal target delay test value as the delay value of the clock line of the above-mentioned interface to be tested relative to the data line, so that the above-mentioned AD chip sends the data to be sent through the above-mentioned interface to be tested based on the above-mentioned optimal target delay test value.

[0158] The specific process can be seen in FIG4 , which is a schematic diagram of a second process of the method for automatically obtaining the delay value provided in an embodiment of the present application.

[0159] S410, the AD chip selects a delay test value from a preset delay set for the interface to be tested as a first delay test value of the interface to be tested;

[0160] S420: The AD chip sends first test data to the SOC chip through the interface to be tested and the data line, generates a clock signal based on the first delay test value using the delay-locked loop module, and sends the clock signal to the SOC chip through the clock line.

[0161] S430: The SOC chip receives the first test data sent by the AD chip based on the received clock signal, obtains second test data, returns the second test data to the AD chip via the test interface through the data line, and sends the clock signal to the AD chip via the clock line.

[0162] S440, the AD chip receives the second test data returned by the SOC chip based on the received clock signal, obtains third test data, and compares the third test data with the first test data;

[0163] S450, determine whether the comparison is successful; if so, execute step S460, if not, execute step S470.

[0164] S460, determining that the first delay test value is a target delay test value;

[0165] S470, determine whether the preset delay set has been traversed; if so, execute step S490, if not, execute step S480.

[0166] S480, selecting another delay test value from the preset delay set as the first delay test value of the interface to be tested, and returning to step S420 to continue execution;

[0167] S490, obtaining one or more target delay test values;

[0168] S400, the AD chip determines the optimal target delay test value from the multiple target delay test values ​​based on a preset first rule, and uses the optimal target delay test value as the delay value of the clock line of the interface to be tested relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0169] In a possible implementation, the AD chip determines the optimal target delay test value from the plurality of target delay test values ​​based on a preset first rule, including:

[0170] The median of the multiple target delay test values ​​is taken as the optimal target delay test value.

[0171] In a possible implementation manner, the AD chip selects, for the interface to be tested, a delay test value from a preset delay set as the first delay test value of the interface to be tested, including:

[0172] When the AD chip is powered on and starts up, and before sending the first test data to the SOC chip through the data line, the AD chip selects a delay test value from a preset delay set as the first delay test value of the interface to be tested.

[0173] In a possible implementation, the above method further includes:

[0174] After the step of the AD chip determining that the first delay test value is the target delay test value of the interface to be tested when the third test data is the same as the first test data;

[0175] Select another delay test value from the above-mentioned preset delay set as the first delay test value of the above-mentioned interface to be tested, and return to the step. The above-mentioned AD chip sends the first test data to the above-mentioned SOC chip through the above-mentioned interface to be tested and the data line in the data communication bus corresponding to the above-mentioned interface to be tested, uses the above-mentioned delay phase-locked loop module to generate a clock signal based on the above-mentioned first delay test value, and sends the above-mentioned clock signal to the above-mentioned SOC chip through the clock line in the data communication bus corresponding to the above-mentioned interface to be tested. Continue to execute until the above-mentioned preset delay set is traversed and a set of target delay test values ​​is obtained;

[0176] Repeat the above traversal process to obtain a preset number of target delay test values;

[0177] The above-mentioned AD chip determines the optimal target delay test value from the above-mentioned preset number of groups of target delay test values ​​based on the preset second rule, and uses the above-mentioned optimal target delay test value as the delay value of the above-mentioned clock line relative to the above-mentioned data line, so that the above-mentioned AD chip sends the data to be sent through the above-mentioned interface to be tested based on the above-mentioned optimal target delay test value.

[0178] In a possible implementation manner, the AD chip determines the optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, including:

[0179] Taking the intersection of the above preset number of groups of target delay test values;

[0180] A target delay test value is selected from the above intersection as the optimal target delay test value.

[0181] Another aspect of an embodiment of the present application provides a method for automatically obtaining a delay value, which is applied to a first chip. The method includes:

[0182] Selecting a delay test value from a preset delay set to obtain a first delay test value of the interface to be tested in the first chip, where the first delay test value represents a communication delay of a clock line relative to a data line in a data communication bus corresponding to the interface to be tested;

[0183] generating a clock signal based on the first delay test value using a delay-locked loop module of the first chip, sending the clock signal to the second chip via the clock line, and sending first test data to the second chip using the interface to be tested and the data line, so that the second chip receives the first test data based on the clock signal to obtain second test data; sending the clock signal to the first chip via the clock line, and returning the second test data to the first chip via the interface to be tested via the data line;

[0184] receiving second test data returned by the second chip based on the received clock signal to obtain third test data;

[0185] The third test data is compared with the first test data. If the third test data is the same as the first test data, it is determined that the first delay test value is the target delay test value of the interface to be tested. If the third test data is different from the first test data, it is determined that the first delay test value is not the target delay test value of the interface to be tested.

[0186] The first chip can be any type of integrated circuit, for example, an AD chip, a SOC chip, an MCU (Microcontroller Unit) chip, or an FPGA (Field Programmable Gate Array), and similarly, the second chip can also be any type of integrated circuit, for example, an AD chip, a SOC chip, an MCU chip, or an FPGA. The types of the first chip and the second chip can be the same or different. In one possible embodiment, the first chip is an AD chip and the second chip is an SOC chip; or, the first chip is an SOC chip and the second chip is an AD chip.

[0187] In one possible implementation, the method further includes:

[0188] After the step of determining that the first delay test value is the target delay test value of the interface to be tested when the third test data is the same as the first test data, the first chip selects another delay test value from the preset delay set as the first delay test value of the interface to be tested, and returns to the step of generating a clock signal based on the first delay test value using the delay-locked loop module of the first chip, sending the clock signal to the second chip through the clock line, and sending the first test data to the second chip using the interface to be tested and the data line, and continues executing until the preset delay set is traversed and one or more target delay test values ​​are obtained;

[0189] The first chip determines an optimal target delay test value from a plurality of target delay test values ​​based on a preset first rule, and uses the optimal target delay test value as the delay value of the clock line of the interface to be tested relative to the data line, so that the first chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0190] In a possible implementation manner, the first chip determines an optimal target delay test value from the plurality of target delay test values ​​based on a preset first rule, including:

[0191] The median of the plurality of target delay test values ​​is taken as the optimal target delay test value.

[0192] In a possible implementation manner, the first chip selects, for the interface to be tested, a delay test value from a preset delay set as a first delay test value of the interface to be tested, including:

[0193] When the first chip is powered on and before sending first test data to the second chip through the data line, the first chip selects a delay test value from a preset delay set as a first delay test value of the interface to be tested.

[0194] In one possible implementation, the method further includes:

[0195] After the step of, the first chip determining, when the third test data is identical to the first test data, that the first delay test value is the target delay test value of the interface to be tested;

[0196] Selecting another delay test value from the preset delay set as the first delay test value of the interface to be tested, and returning to step 1 to generate a clock signal based on the first delay test value using the delay-locked loop module of the first chip, sending the clock signal to the second chip via the clock line, and sending first test data to the second chip using the interface to be tested and the data line, and continuing the process until the preset delay set is traversed to obtain a set of target delay test values;

[0197] Repeat the above traversal process to obtain a preset number of target delay test values;

[0198] The first chip determines an optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, and uses the optimal target delay test value as the delay value of the clock line relative to the data line, so that the first chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

[0199] In a possible implementation, the first chip determines the optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, including:

[0200] Taking the intersection of the preset number of groups of target delay test values;

[0201] A target delay test value is selected from the intersection as the optimal target delay test value.

[0202] An embodiment of the present application further provides an electronic device, including:

[0203] a memory configured to store a computer program;

[0204] The processor, when configured to execute a program stored in the memory, implements the following steps:

[0205] The AD chip selects, for an interface to be tested, a delay test value from a preset delay set as a first delay test value of the interface to be tested, the first delay test value representing a communication delay of a clock line relative to the data line in the same data communication bus, wherein the interface to be tested is an interface of the AD chip;

[0206] The AD chip sends first test data to the SOC chip through the interface to be tested and a data line in the data communication bus corresponding to the interface to be tested, generates a clock signal based on the first delay test value using the delay-locked loop module, and sends the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested;

[0207] The SOC chip receives the first test data sent by the AD chip based on the received clock signal, obtains second test data, sends the clock signal to the AD chip through the clock line, and returns the second test data to the AD chip through the data line via the interface to be tested;

[0208] The above-mentioned AD chip receives the second test data returned by the above-mentioned SOC chip based on the received clock signal, obtains the third test data, and compares the above-mentioned third test data with the above-mentioned first test data. When the above-mentioned third test data is the same as the above-mentioned first test data, it is determined that the above-mentioned first delay test value is the target delay test value of the above-mentioned interface to be tested. When the above-mentioned third test data is different from the above-mentioned first test data, it is determined that the above-mentioned first delay test value is not the target delay test value of the above-mentioned interface to be tested.

[0209] Furthermore, the electronic device may further include a communication bus and / or a communication interface, and the processor, the communication interface, and the memory communicate with each other via the communication bus.

[0210] The communication bus mentioned in the electronic device mentioned above may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0211] The communication interface is configured for communication between the electronic device and other devices.

[0212] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0213] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0214] In another embodiment provided in the present application, a computer-readable storage medium is further provided, wherein a computer program is stored in the computer-readable storage medium. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for automatically obtaining delay values ​​are implemented.

[0215] In another embodiment provided by the present application, a computer program product including instructions is further provided, which, when executed on a computer, enables the computer to execute any one of the methods for automatically obtaining a delay value in the above embodiments.

[0216] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The above-mentioned computer program product includes one or more computer instructions. When the above-mentioned computer program instructions are loaded and executed on a computer, the above-mentioned process or function according to the embodiment of the present application is generated in whole or in part. The above-mentioned computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The above-mentioned computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the above-mentioned computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium, (such as a floppy disk, hard disk, tape), an optical medium (such as a DVD), or a solid-state drive (SSD).

[0217] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0218] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0219] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A data transmission system, the system comprising: An AD chip, a SOC chip, and at least one data communication bus; the AD chip includes a delay-locked loop module; The AD chip includes at least one interface, each interface corresponds to a data communication bus; wherein the data communication bus includes a clock line and a data line, and the AD chip is communicatively connected with the SOC chip through the interface and the data communication bus; The AD chip is configured to: for an interface to be tested, select a delay test value from a preset delay set as a first delay test value of the interface to be tested, the first delay test value representing a communication delay of a clock line relative to the data line in the same data communication bus, wherein the interface to be tested is an interface of the AD chip; The AD chip is configured to: send first test data to the SOC chip through the interface to be tested and a data line in a data communication bus corresponding to the interface to be tested, generate a clock signal based on the first delay test value using the delay locked loop module, and send the clock signal to the SOC chip through a clock line in the data communication bus corresponding to the interface to be tested; The SOC chip is configured to: receive the first test data sent by the AD chip based on the received clock signal to obtain the second test data; send the clock signal to the AD chip through the clock line, and return the second test data to the AD chip through the data line via the interface to be tested; The AD chip is configured to: receive the second test data returned by the SOC chip based on the received clock signal, obtain third test data, and compare the third test data with the first test data; when the third test data is the same as the first test data, determine that the first delay test value is the target delay test value of the interface to be tested; when the third test data is different from the first test data, determine that the first delay test value is not the target delay test value of the interface to be tested.

2. The system according to claim 1, wherein: The AD chip is also configured as: In the case where the third test data is the same as the first test data, after the step of determining that the first delay test value is the target delay test value of the interface to be tested, selecting a delay test value that has not been selected from the preset delay set as the first delay test value of the interface to be tested, and returning to the step of the AD chip sending the first test data to the SOC chip through the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, using the delay phase-locked loop module to generate a clock signal based on the first delay test value, and sending the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested to continue execution until the preset delay set is traversed and one or more of the target delay test values ​​are obtained; The AD chip determines an optimal target delay test value from multiple target delay test values ​​based on a preset first rule, and configures the optimal target delay test value as a delay value of the clock line of the interface to be tested relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

3. The system according to claim 2, wherein: The AD chip is specifically configured as follows: Determining an optimal target delay test value from a plurality of the target delay test values ​​based on a preset first rule comprises: The median of the multiple target delay test values ​​is taken as the optimal target delay test value.

4. The system according to claim 1, wherein: When the AD chip is powered on and before sending the first test data to the SOC chip through the data line, the AD chip is configured to select a delay test value from a preset delay set as a first delay test value of the interface to be tested.

5. The system according to claim 1, wherein: The AD chip is also configured to: when the third test data is the same as the first test data, after determining that the first delay test value is the target delay test value of the interface to be tested; select another delay test value from the preset delay set as the first delay test value of the interface to be tested, and return to the step of the AD chip sending the first test data to the SOC chip through the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, using the delay phase-locked loop module to generate a clock signal based on the first delay test value, sending the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested, and continue to execute until the preset delay set is traversed to obtain a set of target delay test values; Repeat the above traversal process to obtain a preset number of groups of target delay test values; The AD chip determines an optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, and uses the optimal target delay test value as the delay value of the clock line relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

6. The system according to claim 5, wherein: The AD chip is specifically configured as follows: Determining the optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule includes: Taking the intersection of the preset number of groups of target delay test values; A target delay test value is selected from the intersection as the optimal target delay test value.

7. The system according to claim 1, wherein: The AD chip includes at least one high-definition signal interface and / or at least one ultra-high-definition signal interface.

8. A method for automatically acquiring a delay value, applied to a data transmission system, wherein the data transmission system comprises an AD chip, a SOC chip, and at least one data communication bus, wherein the AD chip comprises at least one interface, and each interface corresponds to a data communication bus; wherein: The data communication bus includes a clock line and a data line, and the AD chip is communicatively connected with the SOC chip through the interface and the data communication bus; the AD chip includes a delay-locked loop module; and the method includes: The AD chip selects a delay test value from a preset delay set for the interface to be tested as a first delay test value of the interface to be tested, wherein the first delay test value represents a communication delay of a clock line relative to the data line in the same data communication bus, wherein the interface to be tested is an interface of the AD chip; The AD chip sends first test data to the SOC chip through the interface to be tested and a data line in a data communication bus corresponding to the interface to be tested, generates a clock signal based on the first delay test value using the delay locked loop module, and sends the clock signal to the SOC chip through a clock line in the data communication bus corresponding to the interface to be tested; The SOC chip receives the first test data sent by the AD chip based on the received clock signal to obtain second test data; sends the clock signal to the AD chip through the clock line, and returns the second test data to the AD chip through the data line via the interface to be tested; The AD chip receives the second test data returned by the SOC chip based on the received clock signal, obtains third test data, and compares the third test data with the first test data. When the third test data is the same as the first test data, it is determined that the first delay test value is the target delay test value of the interface to be tested. When the third test data is different from the first test data, it is determined that the first delay test value is not the target delay test value of the interface to be tested.

9. The method according to claim 8, wherein: The method further comprises: After the step of determining that the first delay test value is the target delay test value of the interface to be tested when the third test data is the same as the first test data, the AD chip selects another delay test value from the preset delay set as the first delay test value of the interface to be tested, and returns to the step of sending the first test data to the SOC chip through the interface to be tested and a data line in a data communication bus corresponding to the interface to be tested, generating a clock signal based on the first delay test value by using the delay phase-locked loop module, sending the clock signal to the SOC chip through a clock line in the data communication bus corresponding to the interface to be tested, and continuing to execute until the preset delay set is traversed to obtain one or more of the target delay test values; The AD chip determines an optimal target delay test value from multiple target delay test values ​​based on a preset first rule, and uses the optimal target delay test value as the delay value of the clock line of the interface to be tested relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

10. The method according to claim 9, wherein: The AD chip determines an optimal target delay test value from a plurality of target delay test values ​​based on a preset first rule, including: The median of the multiple target delay test values ​​is taken as the optimal target delay test value.

11. The method according to claim 8, wherein: The AD chip selects a delay test value from a preset delay set for the interface to be tested as a first delay test value of the interface to be tested, including: The AD chip is powered on and before sending the first test data to the SOC chip through the data line, a delay test value is selected from a preset delay set as a first delay test value of the interface to be tested.

12. The method according to claim 8, wherein: The method further comprises: After the step of, the AD chip determining, when the third test data is the same as the first test data, that the first delay test value is the target delay test value of the interface to be tested; Select another delay test value from the preset delay set as the first delay test value of the interface to be tested, and return to the step wherein the AD chip sends the first test data to the SOC chip through the interface to be tested and the data line in the data communication bus corresponding to the interface to be tested, and use the delay phase-locked loop module to generate a clock signal based on the first delay test value, and send the clock signal to the SOC chip through the clock line in the data communication bus corresponding to the interface to be tested, and continue to execute until the preset delay set is traversed to obtain a set of target delay test values; Repeat the above traversal process to obtain a preset number of groups of target delay test values; The AD chip determines an optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, and uses the optimal target delay test value as the delay value of the clock line relative to the data line, so that the AD chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

13. The method according to claim 12, wherein: The AD chip determines the optimal target delay test value from the preset number of groups of target delay test values ​​based on a preset second rule, including: Taking the intersection of the preset number of groups of target delay test values; A target delay test value is selected from the intersection as the optimal target delay test value.

14. A method for automatically acquiring a delay value, applied to a first chip, the method comprising: Selecting a delay test value from a preset delay set to obtain a first delay test value of the interface to be tested in the first chip, wherein the first delay test value represents a communication delay of a clock line relative to a data line in a data communication bus corresponding to the interface to be tested; Generate a clock signal based on the first delay test value, send the clock signal to the second chip through the interface to be tested and the clock line, and send first test data to the second chip using the interface to be tested and the data line, so that the second chip receives the first test data based on the clock signal to obtain second test data, sends the clock signal to the first chip through the clock line, and returns the second test data to the first chip through the interface to be tested through the data line; receiving second test data returned by the second chip based on the received clock signal to obtain third test data; The third test data is compared with the first test data. When the third test data is the same as the first test data, it is determined that the first delay test value is the target delay test value of the interface to be tested. When the third test data is different from the first test data, it is determined that the first delay test value is not the target delay test value of the interface to be tested.

15. The method according to claim 14, wherein: The first chip is an AD chip, and the second chip is a SOC chip; or, the first chip is a SOC chip, and the second chip is an AD chip.

16. The method according to claim 14, wherein: After comparing the third test data with the first test data, and determining that the first delay test value is a target delay test value of the interface to be tested when the third test data is the same as the first test data, and determining that the first delay test value is not a target delay test value of the interface to be tested when the third test data is different from the first test data, the method further includes: Select a delay test value that has not been selected from the preset delay set as the first delay test value of the interface to be tested, and return to the step of generating a clock signal based on the first delay test value, sending the clock signal to the second chip through the interface to be tested and the clock line, and sending the first test data to the second chip using the interface to be tested and the data line, and continue to execute until the preset delay set is traversed to obtain one or more target delay test values; An optimal target delay test value is determined from the multiple target delay test values, and the optimal target delay test value is used as the delay value of the clock line of the interface to be tested relative to the data line, so that the first chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

17. The method according to claim 16, wherein: Determining an optimal target delay test value from a plurality of the target delay test values ​​comprises: The median of the multiple target delay test values ​​is taken as the optimal target delay test value.

18. The method according to claim 14, wherein: The step of selecting a delay test value from a preset delay set to obtain a first delay test value of the interface to be tested in the first chip includes: When the first chip is powered on and before first test data is sent to the second chip through the data line, a delay test value is selected from a preset delay set as a first delay test value of the interface to be tested.

19. The method according to claim 14, wherein: After comparing the third test data with the first test data, and determining that the first delay test value is a target delay test value of the interface to be tested when the third test data is the same as the first test data, and determining that the first delay test value is not a target delay test value of the interface to be tested when the third test data is different from the first test data, the method further includes: Select a delay test value that has not been selected from the preset delay set as the first delay test value of the interface to be tested, and return to the step of generating a clock signal based on the first delay test value, sending the clock signal to the second chip through the interface to be tested and the clock line, and sending the first test data to the second chip using the interface to be tested and the data line, and continue to execute until the preset delay set is traversed to obtain a set of target delay test values; Repeat the above traversal process to obtain a preset number of groups of target delay test values; An optimal target delay test value is determined from the preset number of groups of target delay test values, and the optimal target delay test value is used as the delay value of the clock line relative to the data line, so that the first chip sends the data to be sent through the interface to be tested based on the optimal target delay test value.

20. The method according to claim 19, wherein: The determining the optimal target delay test value from the preset number of groups of target delay test values ​​comprises: Taking the intersection of the preset number of groups of target delay test values; A target delay test value is selected from the intersection as the optimal target delay test value.

21. An electronic device comprising: a memory configured to store a computer program; The processor, when configured to execute a program stored in the memory, implements the method steps described in any one of claims 8-13 or 14-20.

22. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method steps described in any one of claims 8 to 13 or 14 to 20 are implemented.

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