Flexible circuit board, cof module and electronic device comprising same

Abstract

The present invention provides a flexible circuit board comprising: a substrate; a plurality of circuit patterns arranged on the substrate; and a protective layer arranged on the circuit patterns, wherein: the thickness of each of the plurality of circuit patterns is 25 μm or less and greater than 8 μm; and the thickness deviation between the plurality of circuit patterns is 0.5-3 μm. When the flexible circuit board is connected to a display panel, the display panel can have high performance and enables high current to flow therethrough. Circuit patterns having the features according to the present invention are prevented from being damaged by the high current.

Description

Flexible circuit boards, COF modules and electronic devices including the same

[0001] The present invention relates to a flexible circuit board, a COF module and an electronic device including the same.

[0002] Recently, various electronic products are becoming thinner and smaller. Consequently, there is a growing demand for high-density semiconductor chips to be mounted within the narrow spaces of these electronic products.

[0003] A COF (Chip-On-Film) comprises a substrate and a chip on the substrate. The substrate is flexible, meaning the COF is a flexible circuit board. Accordingly, the COF is applicable to flexible displays. For example, the COF can be applied to various wearable electronic devices. Furthermore, the COF has a fine pitch, meaning that the COF is applicable to high-resolution displays.

[0004] The chip includes a semiconductor chip. For example, the chip may be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.

[0005] The chip is connected to an external circuit board and display panel via a circuit pattern. For example, pads are arranged at one end and the other end of the circuit pattern, respectively. One pad is electrically connected to a terminal of the chip. The other pad is connected to a terminal of the circuit board and the display panel. Accordingly, the chip, the circuit board, and the display panel are electrically connected via the COF. As a result, a signal is transmitted to the display panel via the circuit pattern.

[0006] As the performance of the display panel increases, the current drawn by the display panel also increases. Consequently, the flexible circuit board is connected to the display panel. Consequently, the circuit pattern may be damaged by the high current. This may reduce the reliability of the COF module.

[0007] Therefore, a new structure of flexible circuit board, COF module and electronic device including the same that can solve the above problems are required.

[0008] As a patent related to the above flexible circuit board, Korean registered patent KR10-0618898 (2006.09.01) is disclosed.

[0009] The present invention provides a flexible circuit board having improved reliability and a COF module including the same.

[0010] A flexible circuit board according to an embodiment includes a substrate; a plurality of circuit patterns arranged on the substrate; and a protective layer arranged on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness exceeding 8 μm and not greater than 25 μm, and a thickness deviation between the plurality of circuit patterns is 0.5 μm to 3 μm.

[0011] Additionally, each of the plurality of circuit patterns includes a buffer layer disposed on the substrate, a metal layer disposed on the buffer layer, and a bonding layer disposed on the metal layer.

[0012] Additionally, the bonding layer is arranged to cover the side surface of the buffer layer, the side surface of the metal layer, and the upper surface of the metal layer.

[0013] Additionally, the thickness deviation between the metal layers of the plurality of circuit patterns is 0.5 µm to 3 µm.

[0014] Additionally, the metal layer includes a first metal layer and a second metal layer on the first metal layer, and a thickness of the second metal layer is greater than a thickness of the first metal layer.

[0015] Additionally, the thickness deviation between the second metal layers of the plurality of circuit patterns is 0.5 μm to 3 μm.

[0016] In addition, the substrate includes a first side end and a second side end, and the protective layer includes a first open area overlapping an area between the first side end and the second side end along a thickness direction, a second open area spaced apart from the first open area and closest to the first side end, and a third open area spaced apart from the first open area and the second open area and closest to the second side end.

[0017] In addition, the circuit pattern includes a first circuit pattern including a first pad portion arranged in the first open area; a second pad portion arranged in the second open area, and a first wiring portion connecting between the first pad portion and the second pad portion; and a second circuit pattern including a third pad portion arranged in the first open area; a fourth pad portion arranged in the third open area, and a second wiring portion connecting between the third pad portion and the fourth pad portion.

[0018] Additionally, the thickness deviation of the first circuit pattern is 0.3 µm to 2.5 µm.

[0019] Additionally, the thickness deviation of the second circuit pattern is 0.3 µm to 5 µm.

[0020] Additionally, the thickness deviation between the first pad portion and the third pad portion is 0.3 µm to 0.9 µm.

[0021] Additionally, the thickness deviation of the second pad portion is 0.5 µm to 3 µm.

[0022] Additionally, the thickness deviation of the fourth pad portion is 1 µm to 5 µm.

[0023] Additionally, the circuit pattern further includes a third circuit pattern including a fifth pad portion arranged in the second open area, a sixth pad portion arranged in the third open area, and a third wiring portion connecting the fifth pad portion and the sixth pad portion.

[0024] Additionally, the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern is 1 µm to 5 µm.

[0025] In addition, the first circuit pattern is arranged on one surface of the substrate, the third circuit pattern is arranged on the other surface of the substrate, and the second circuit pattern is arranged on the one surface and the other surface of the substrate, respectively, and is connected through a via.

[0026] A flexible circuit board according to an embodiment includes a plurality of circuit patterns. The circuit patterns have a set thickness. Specifically, the circuit patterns have a thickness exceeding 8 μm. In addition, the circuit patterns have a uniform line width.

[0027] The above flexible circuit board is connected to a display panel. The display panel may have high performance. Accordingly, a high current may flow through the display panel.

[0028] The high current is transmitted to the flexible circuit board. Since the circuit pattern is formed within a set thickness range, the circuit pattern can be prevented from being damaged by the high current.

[0029] The above circuit pattern has a uniform thickness. That is, the thickness deviation of the circuit pattern is small.

[0030] In detail, the plating process for forming the circuit pattern is controlled. In detail, during the plating process, a shielding layer can be placed in an area with a thick plating thickness to control the plating thickness to be uniform with that of other areas.

[0031] Accordingly, the thickness deviation of the circuit pattern is reduced. In addition, the thickness deviation of each circuit pattern is reduced. In addition, the thickness deviation of each pad portion is reduced.

[0032] Therefore, the signals or currents moving through each circuit pattern become uniform. Consequently, the electrical characteristics of the flexible circuit board and COF module are improved.

[0033] Fig. 1 is a top view of a flexible circuit board according to an embodiment.

[0034] Figures 2 and 3 are cross-sectional views taken along the AA' area of ​​Figure 1.

[0035] Figure 4 is a cross-sectional view taken along the BB' area of ​​Figure 1.

[0036] Figures 5 and 6 are drawings illustrating the first process of forming a circuit pattern.

[0037] Figure 7 is a scanning electron microscope (SEM) photograph of a circuit pattern formed by the first process.

[0038] Figures 8 to 16 are drawings illustrating a second process for forming a circuit pattern.

[0039] Figure 17 is a scanning electron microscope (SEM) photograph of a circuit pattern formed by the second process.

[0040] Fig. 18 is a drawing for explaining the connection of a COF module and other members according to an embodiment.

[0041] FIGS. 19 to 21 are drawings of electronic devices including flexible circuit boards according to embodiments.

[0042] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0043] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0044] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0045] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0046] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0047] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0048] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0049] In the following description, the first direction (1D) is the direction in which the pad portion of the display panel and the pad portion of the circuit board face each other. In addition, the second direction (2D) is the direction perpendicular to the first direction (1D).

[0050]

[0051] Below, with reference to the drawings, a flexible circuit board and a COF module including the same according to an embodiment are described.

[0052] Referring to FIG. 1, a flexible circuit board (1000) according to an embodiment includes a substrate (100), a circuit pattern, and a protective layer (300).

[0053] The above-mentioned substrate (100) includes a first surface (1S) and a second surface (2S) opposite to the first surface (1S). The circuit pattern and the protective layer (300) are arranged on the first surface (1S).

[0054] The substrate (100) includes a cutting line (CL). The flexible circuit board (1000) is cut along the cutting line (CL). For example, the circuit pattern, the metal pattern, the protective layer, and the chip are placed on the substrate (100). Thereafter, the substrate (100) is cut along the cutting line (CL). Accordingly, a COF module is manufactured. Accordingly, the edge of the COF module becomes the cutting line (CL).

[0055] The above-mentioned substrate (100) includes an effective area (AA) and an ineffective area (UA). In detail, the first surface (1S) includes the effective area (AA) and the ineffective area (UA).

[0056] The above valid area (AA) and the non-valid area (UA) are separated by the cutting line (CL). The valid area (AA) is an area inside the cutting line (CL). In addition, the non-valid area (UA) is an area outside the cutting line (CL).

[0057] The circuit pattern, the protective layer, and the chip are arranged on the effective area (AA). In addition, a dummy pattern and a sprocket hole (SH) are arranged on the ineffective area (UA). The dummy pattern increases the strength of the substrate (100). In addition, the flexible circuit board (1000) is rolled or unrolled in a roll-to-roll manner by the sprocket hole (SH).

[0058] The above substrate (100) includes a chip mounting area (CHA). The chip mounting area (CHA) is disposed on the first surface (1S). The chip mounting area (CHA) is disposed on the effective area (AA). The chip (CH) is disposed on the chip mounting area (CHA). In addition, the pad portions of the circuit pattern are disposed inside the chip mounting area (CHA). In addition, the protective layer (300) is not disposed on the chip mounting area (CHA).

[0059] The substrate (100) includes a flexible material. For example, the substrate (100) may include polyimide (PI). However, the embodiment is not limited thereto. The substrate (100) may include a polymer material including polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board can be applied to various electronic devices, including curved display devices.

[0060] The substrate (100) may have a thickness of 20 μm to 100 μm. For example, the substrate (100) may have a thickness of 25 μm to 50 μm. For example, the substrate (100) may have a thickness of 30 μm to 40 μm. When the thickness of the substrate (100) exceeds 100 μm, the overall thickness of the flexible circuit board increases. As a result, the flexible characteristics of the flexible circuit board may be reduced. In addition, when the thickness of the substrate (100) is less than 20 μm, the substrate (100) may be damaged by heat and pressure applied to the substrate when the chip is mounted on the flexible circuit board.

[0061]

[0062] The circuit pattern and the protective layer (300) are disposed on the substrate (100). In detail, the circuit pattern and the protective layer (300) are disposed on the first surface (1S). In detail, the circuit pattern and the protective layer (300) are disposed on at least one of the effective area (AA) and the non-effective area (UA).

[0063] The above circuit pattern includes a first circuit pattern (210), a second circuit pattern (220), and a third circuit pattern (230).

[0064] Referring to Fig. 1, the first circuit pattern (210) includes a first wiring portion (211), a first pad portion (212a), and a second pad portion (212b). The first wiring portion (211), the first pad portion (212a), and the second pad portion (212b) may include the same material. In addition, the first wiring portion (211), the first pad portion (212a), and the second pad portion (212b) may be formed integrally.

[0065] The first pad portion (212a) is positioned within the chip mounting area (CHA). Accordingly, the first pad portion (212a) is connected to the terminal of the chip. As a result, the first circuit pattern (210) and the chip are connected.

[0066] The second pad portion (212b) is positioned outside the chip mounting area (CHA). The second pad portion (212b) is connected to the pad portion of the circuit board (3000). As a result, the first circuit pattern (210) and the circuit board (3000) are connected.

[0067] The first wiring portion (211) is arranged between the first pad portion (212a) and the second pad portion (212b). The first wiring portion (211) connects the first pad portion (212a) and the second pad portion (212b). Accordingly, the chip (CH) and the circuit board (3000) are connected. Accordingly, a signal generated from the chip (CH) is transmitted to the circuit board (3000).

[0068] The first circuit pattern (210) may further include a test pad portion. Specifically, a first test pad portion (TP1) is arranged in the non-effective area (UA). The first wiring portion (211), the first pad portion (212a), the second pad portion (212b), and the first test pad portion (TP1) may be formed integrally.

[0069] Before connecting the circuit board and the second pad portion (212b), the first circuit pattern (210) can be tested by the first test pad portion (TP1). For example, whether the first circuit pattern is open or shorted can be checked through the first test pad portion (TP1).

[0070]

[0071] The second circuit pattern (220) includes a second wiring portion (221), a third pad portion (222a), and a fourth pad portion (222b). The second wiring portion (221), the third pad portion (222a), and the fourth pad portion (222b) may include the same material. In addition, the second wiring portion (221), the third pad portion (222a), and the fourth pad portion (222b) may be formed integrally.

[0072] The third pad portion (222a) is positioned within the chip mounting area (CHA). Accordingly, the third pad portion (222a) is connected to the terminal of the chip. As a result, the second circuit pattern (220) and the chip (CH) are connected.

[0073] The fourth pad portion (222b) is positioned outside the chip mounting area (CHA). The fourth pad portion (222b) is connected to the pad portion of the external display panel (4000). As a result, the second circuit pattern (220) and the display panel (4000) are connected.

[0074] The second wiring portion (221) is arranged between the third pad portion (222a) and the fourth pad portion (222b). The second wiring portion (221) connects the third pad portion (222a) and the fourth pad portion (222b). Accordingly, the chip (CH) and the display panel (4000) are connected. Accordingly, a signal generated from the chip (CH) is transmitted to the display panel (4000).

[0075] The second circuit pattern (220) may further include a test pad portion. In detail, a second test pad portion (TP2) is arranged in the non-effective area (UA). The second test pad portion (TP2) is arranged outside the cutting line (CL). The second test pad portion (TP2) is arranged on the non-effective area (UA). The second wiring portion (221), the third pad portion (222a), the fourth pad portion (222b), and the second test pad portion (TP2) may be formed integrally.

[0076] Before connecting the circuit board and the fourth pad portion (222b), the second circuit pattern (220) can be tested by the second test pad portion (TP2). For example, whether the second circuit pattern is open or shorted can be checked through the second test pad portion (TP2).

[0077]

[0078] The third circuit pattern (230) includes a third wiring portion (231), a fifth pad portion (232a), and a sixth pad portion (232b). The third wiring portion (231), the fifth pad portion (232a), and the sixth pad portion (232b) may include the same material. In addition, the third wiring portion (231), the fifth pad portion (232a), and the sixth pad portion (232b) may be formed integrally.

[0079] The fifth pad portion (232a) and the sixth pad portion (232b) are positioned outside the chip mounting area (CHA). The fifth pad portion (232a) may be connected to the pad portion of the circuit board (2000). In addition, the sixth pad portion (232b) may be connected to the pad portion of the display panel (4000).

[0080] The third wiring portion (231) is positioned between the fifth pad portion (232a) and the sixth pad portion (232b). The third wiring portion (231) connects the fifth pad portion (232a) and the sixth pad portion (232b). Accordingly, the circuit board (3000) and the display panel (4000) are connected.

[0081] The third circuit pattern (230) may be a bypass circuit. For example, the third circuit pattern (230) may be a power supply pattern. Accordingly, the circuit board and the display panel may be supplied with power by the third circuit pattern (230).

[0082] The third circuit pattern (230) may include a plurality of third circuit patterns spaced apart in the second direction (2D). The line width and spacing of the third circuit pattern (230) may be larger than the line width and spacing of the first circuit pattern (210). In addition, the line width and spacing of the third circuit pattern (230) may be larger than the line width and spacing of the second circuit pattern (220).

[0083] Although not shown in the drawing, at least one dummy pattern may be placed on the effective area (AA).

[0084] The above dummy pattern can prevent the flexible circuit board (1000) from bending. In addition, the spacing and line width of the circuit pattern can be made uniform by the dummy pattern.

[0085] The dummy pattern may include the same material as the circuit pattern. The line width of the dummy pattern may be the same as or different from the circuit pattern. The dummy pattern is not connected to the chip (CH), the circuit board (3000), and the display panel (4000).

[0086] At least one of the third circuit pattern and the dummy pattern may be an outermost pattern. In detail, the outermost pattern in the second direction (2D) of the substrate (100) may be at least one of the third circuit pattern and the dummy pattern.

[0087]

[0088] The protective layer (300) is disposed on the first surface (1S). Accordingly, the protective layer (300) is disposed on the first circuit pattern (210), the second circuit pattern (220), and the third circuit pattern (230). The protective layer (300) is disposed on the first wiring portion (211), the second wiring portion (221), and the third wiring portion (231). The protective layer (300) is not disposed on the first pad portion (212a), the second pad portion (212b), the third pad portion (222a), the fourth pad portion (222b), the fifth pad portion (232a), and the sixth pad portion (232b). In addition, the protective layer (300) is not disposed on the chip mounting area (CHA).

[0089]

[0090] Referring to FIGS. 2 and 3, the circuit pattern is formed in a multilayer structure. FIGS. 2 and 3 are described focusing on the first circuit pattern. The following description applies equally to the second and third circuit patterns.

[0091] Referring to Fig. 2, the first circuit pattern is formed in multiple layers. In detail, the first wiring portion (211), the first pad portion (212a), and the second pad portion (212b) include a buffer layer (205), a metal layer (201), and a bonding layer (203).

[0092] The buffer layer (205) may include multiple layers. Specifically, the buffer layer (205) includes a first buffer layer (205a) and a second buffer layer (205b). The first buffer layer (205a) is disposed on the substrate (100). The second buffer layer (205b) is disposed on the first buffer layer (205a).

[0093] The first buffer layer (205a) includes a material having good adhesion to the substrate (100). For example, the first buffer layer (205a) may include nickel (Ni). In addition, the second buffer layer (205b) includes a material having good adhesion to the circuit pattern. For example, the second buffer layer (205b) may include chromium (Cr).

[0094] The above buffer layer (205) may have a thin film thickness in nanometer units. For example, the above buffer layer (205) may have a thickness of 20 nm or less.

[0095] The adhesion between the substrate (100) and the circuit pattern is improved by the buffer layer (205).

[0096] The metal layer (201) is disposed on the buffer layer (205). Specifically, the metal layer (201) is disposed on the second buffer layer (205b). The metal layer (201) includes a metal material. For example, the metal layer (201) may include copper (Cu).

[0097] The above metal layer (201) can be formed by electroplating using the buffer layer as a seed layer. That is, the above metal layer (201) can be a plating layer.

[0098] The thickness of the above metal layer (201) may be 10 µm to 30 µm.

[0099] The above bonding layer (203) is placed on the above metal layer (201).

[0100] The above bonding layer (203) is arranged on the side and upper surface of the metal layer (201). For example, the bonding layer (203) may be arranged to surround the metal layer (201).

[0101] The above bonding layer (203) includes a metal. For example, the bonding layer (203) may include tin (Sn). The bonding layer (203) is formed by a plating process. In detail, the bonding layer (203) may be a plating layer.

[0102] The thickness of the above bonding layer (203) may be 0.3 μm to 0.7 μm. The tin content may increase as it extends from the lower surface to the upper surface of the above bonding layer (203).

[0103] That is, the bonding layer (203) is in contact with the metal layer (201). Therefore, the tin content increases from the lower surface of the bonding layer (203) toward the upper surface. In addition, the copper content decreases from the lower surface of the bonding layer (203) toward the upper surface.

[0104] Accordingly, pure tin may remain in a thickness range of 0.1 µm to 0.3 µm from the upper surface of the bonding layer (203).

[0105] The pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel by the bonding layer (203). For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel.

[0106]

[0107] Referring to FIG. 3, the metal layer (201) may include a first metal layer (201a) and a second metal layer (201b). The first metal layer (201a) is disposed on the buffer layer (205). The second metal layer (201b) is disposed on the first metal layer (201a). The second metal layer (201b) may be formed by electroplating using the first metal layer (201a) as a seed layer. That is, the second metal layer (201b) may be a plating layer.

[0108] The thickness of the first metal layer (201a) may be smaller than the thickness of the second metal layer (201b).

[0109] For example, the thickness of the first metal layer (201a) may be 0.7 µm to 2 µm, and the thickness of the second metal layer (201b) may be 6 µm to 25 µm.

[0110] The first metal layer (201a) and the second metal layer (201b) may include the same metal material. For example, the first metal layer (201a) and the second metal layer (201b) may include copper (Cu).

[0111] The above bonding layer (203) may include a first bonding layer (203a) and a second bonding layer (203b).

[0112] The first bonding layer (203a) is disposed on the metal layer (201). In detail, the first bonding layer (203a) is disposed on the second wiring portion (221), the third pad portion (222a), and the fourth pad portion (222b).

[0113] The second bonding layer (203b) is disposed on the first bonding layer (203a). In detail, the second bonding layer (203b) is disposed on the third pad portion (222a) and the fourth pad portion (222b).

[0114] Accordingly, the second wiring portion (221) includes the buffer layer (205), the metal layer (201), and the first bonding layer (203a). In addition, the third pad portion (222a) and the fourth pad portion (222b) include the buffer layer (205), the metal layer (201), the first bonding layer (203a), and the second bonding layer (203b).

[0115] Accordingly, the layer structure of the second wiring portion (221) is different from the layer structures of the first pad portion (212a) and the second pad portion (212b).

[0116] The first bonding layer (203a) and the second bonding layer (203b) contain metal. In detail, the first bonding layer (203a) and the second bonding layer (203b) may contain tin (Sn).

[0117] The first bonding layer (203a) and the second bonding layer (203b) are arranged with different thicknesses. Specifically, the thickness of the second bonding layer (203b) is greater than the thickness of the first bonding layer (203a).

[0118] For example, the first bonding layer (203a) has a thickness of 0.02 μm to 0.06 μm. In addition, the second bonding layer (203b) has a thickness of 0.2 μm to 0.6 μm.

[0119] Accordingly, the thickness of the first wiring portion (211) is reduced. The flexible circuit board includes a bending area (BA) that is bent in one area. The wiring portion is arranged on the bending area (BA). Accordingly, the thickness of the bonding layer on the wiring portion is formed to be small. Accordingly, when the flexible circuit board is bent, cracks can be prevented from forming in the first wiring portion (211).

[0120] The thickness of the circuit pattern may be greater than 8 μm and less than or equal to 25 μm. Specifically, the thickness of the circuit pattern may be from 9 μm to 20 μm. Specifically, the thickness of the circuit pattern may be from 10 μm to 15 μm.

[0121] If the thickness of the circuit pattern is less than 8 μm, the resistance of the circuit pattern may increase. Furthermore, when a high current flows through the display panel, the circuit pattern may be damaged. If the thickness of the circuit pattern exceeds 25 μm, it becomes difficult to implement a fine pattern.

[0122]

[0123] Figure 4 is a cross-sectional view taken along the BB' area of ​​Figure 1.

[0124] The first wiring portion (211) includes a buffer layer (205), a first metal layer (201a), a second metal layer (201b), and a bonding layer (203). The buffer layer (205) and the bonding layer (203) are formed with a thin film thickness. Accordingly, the total thickness (T3) of the first wiring portion (211) is determined by the thickness (T2) of the metal layers (201a, 201b) or the thickness (T2) of the second metal layer (201b).

[0125] The above metal layer may be formed as one metal layer as shown in Fig. 2. Alternatively, the metal layer may be formed as two metal layers as shown in Fig. 3.

[0126] Figures 5 to 7 are drawings for explaining the first process of forming a circuit pattern. The first process is a process of forming a circuit pattern using a single metal layer, as shown in Figure 2.

[0127] Referring to Fig. 5, a buffer layer (205) is disposed on the substrate (100). The metal layer (201) is disposed on the buffer layer (205).

[0128] Next, a photosensitive layer (400) is placed on the metal layer (201). The photosensitive layer (400) forms a plurality of photosensitive patterns (DP) through exposure and development processes. The photosensitive patterns (DP) are placed on an area where the circuit pattern is formed. Accordingly, the area between the photosensitive patterns (DP) becomes an etching area.

[0129] Referring to Fig. 6, the etching area is etched. For example, the etching area is etched by spraying an etchant.

[0130] After etching the above etching area, a bonding layer (205) is formed on the metal layer (201) to form a circuit pattern.

[0131] However, if the thickness of the metal layer (201) increases, the etching uniformity of the circuit pattern may decrease. For example, if the thickness of the metal layer (201) exceeds 8 μm, the uniformity of the line width of the circuit pattern may decrease. That is, although the thickness of the metal layer (201) is uniform, the line width may be uneven.

[0132] Referring to Fig. 7, it can be seen that the line width (W) of the circuit pattern (210) is uneven. That is, as shown in Fig. 7(a), the line width of the circuit pattern (210) increases as it approaches the substrate (100). Accordingly, the line widths of the upper and lower surfaces of the circuit pattern (210) become different. As the thickness of the circuit pattern (210) increases, the line width difference between the upper and lower surfaces of the circuit pattern increases. Therefore, the line width (W) of the circuit pattern (210) becomes uneven at each position. Therefore, it becomes difficult to form a circuit pattern with a fine line width.

[0133]

[0134] Therefore, the embodiment forms a circuit pattern by a second process different from the first process.

[0135] Figures 8 to 17 are drawings illustrating the second process.

[0136] Referring to Fig. 8, the buffer layer (205) is disposed on the substrate (100). The first metal layer (201a) is disposed on the buffer layer (205). The first metal layer (201a) may be formed by electrolytic or electroless plating.

[0137] Referring to FIGS. 9 and 10, the photosensitive layer (400) is disposed on the first metal layer (201a). The photosensitive layer (400) forms a plurality of photosensitive patterns (DP) through exposure and development processes. The photosensitive patterns (DP) are disposed on an area where the circuit pattern is not formed. Accordingly, the circuit pattern is formed on an area between the photosensitive patterns (DP). Accordingly, the area between the photosensitive patterns (DP) becomes a plating area. Accordingly, a plurality of plating areas are formed.

[0138] Referring to FIGS. 11 to 14, a second metal layer (201b) is plated on the plating area. For example, a plating solution is sprayed onto the plating area. As the thickness of the second metal layer (201b) increases, the plating thickness of the plating areas may vary. Accordingly, the thickness deviation of multiple circuit patterns may increase.

[0139] For example, as shown in Fig. 12, the thickness of one plating layer may be greater than that of the plating layer in another region. Therefore, a shielding layer (500) may be placed on a plating region with a large plating layer thickness. The plating layer may have a large thickness in a wide region (W2). Therefore, a shielding layer (500) may be formed on a plating region with a large plating layer thickness. Plating is not performed on a plating region overlapping with the shielding layer (500). In addition, plating is performed on a plating region that does not overlap with the shielding layer (500). Therefore, the plating thicknesses of regions with large and small plating layer thicknesses can be uniformly controlled.

[0140] As shown in Fig. 13, the shielding layer (500) is placed until the thickness of the plating layer in multiple plating areas becomes uniform. Once the thickness of the plating layer in multiple plating areas becomes uniform, the chip layer is removed.

[0141] Next, as shown in Fig. 14, when the plating layer on the plating area is plated to a set thickness, the plating process is completed.

[0142] Referring to FIGS. 15 and 16, the photosensitive pattern (DP) is removed. Subsequently, the first metal layer (201a) and the buffer layer (205) disposed under the photosensitive pattern (DP) are etched to separate a plurality of circuit patterns. When the first metal layer (201a) and the buffer layer (205) are etched, the second metal layer (201b) is etched together. Therefore, the thickness of the second metal layer (201b) can be slightly reduced compared to the thickness after the plating process is completed. Therefore, the plating process can be performed to a thickness slightly higher than the set circuit pattern thickness.

[0143] The second process plates a second metal layer on the plating area. Accordingly, the line widths of the circuit patterns can be made uniform.

[0144] As shown in Fig. 17, the widths of the upper and lower portions of the circuit pattern may be similar. Accordingly, the line width (W) of the circuit pattern may be uniform. In addition, the line width deviation of multiple circuit patterns may be reduced.

[0145] Additionally, the second process controls the plating thickness. Specifically, the thickness variation of multiple plating areas is controlled by the shielding layer (500). Accordingly, the thickness of the circuit pattern can be made uniform. Furthermore, the thickness variation of the multiple circuit patterns can be reduced.

[0146]

[0147] Measurement location 1, 3 Pad section 2 Pad section 4 Pad section Average thickness (㎛) 12.2 13.4 13.8 Thickness deviation (㎛) 0.6 3.2 5.9 Maximum thickness (㎛) 12.5 15.7 17.9 Minimum thickness (㎛) 11.9 12.5 12.0

[0148] Measurement location Pad 1, 3 Pad 2 Pad 4 Average thickness (㎛) 11.8 12.3 12.0 Thickness deviation (㎛) 0.8 1.2 1.6 Maximum thickness (㎛) 12.3 12.9 12.9 Minimum thickness (㎛) 11.5 11.7 11.3

[0149] Tables 1 and 2 show data on the thickness of the circuit pattern formed by the second process. Tables 1 and 2 above show results after the plating process was performed with a set thickness of 12 μm. Table 1 shows comparative example data for plating without using the shielding layer. Table 2 shows example data for plating using the shielding layer.

[0150] Referring to Table 1, the average thickness of the circuit pattern exceeds the set thickness. Furthermore, it can be seen that the thickness variation of the circuit pattern is large. In particular, it can be seen that the thickness variation of the second pad portion and the fourth pad portion is large. Accordingly, the thickness variation of the first pad portion, the second pad portion, the third pad portion, and the fourth pad portion also increases.

[0151] Referring to Table 2, the average thickness of the circuit pattern is similar to the set thickness. Furthermore, it can be seen that the thickness variation of the circuit pattern is small. Specifically, the first to fourth pad portions have a thickness variation of 3 μm or less. Accordingly, the thickness variation of the first, second, third, and fourth pad portions is also reduced.

[0152] The thickness of the above circuit pattern is determined by the thickness of the second metal layer. In an embodiment, the thickness of the second metal layer is controlled by the shielding layer.

[0153] Accordingly, the thickness deviation of the second metal layer of the circuit patterns is reduced. In detail, the thickness deviation of the second metal layer may be 3 μm or less. In detail, the thickness deviation of the second metal layer may be 0.5 μm to 3 μm, 0.6 μm to 2.5 μm, or 0.5 μm to 2 μm.

[0154] In addition, the thickness deviation of the metal layer of the circuit patterns is reduced. Specifically, the thickness deviation of the metal layer may be 3 μm or less. Specifically, the thickness deviation of the metal layer may be 0.5 μm to 3 μm, 0.6 μm to 2.5 μm, or 0.5 μm to 2 μm.

[0155] Additionally, the thickness deviation of the circuit patterns is reduced. Specifically, the thickness deviation of the circuit pattern may be 3 μm or less. Specifically, the thickness deviation of the circuit pattern may be 0.5 μm to 3 μm, 0.6 μm to 2.5 μm, or 0.5 μm to 2 μm.

[0156] Additionally, the thickness deviation of each circuit pattern is reduced.

[0157] In detail, the thickness deviation of the first circuit pattern may be 0.3 µm to 2.5 µm, 0.4 µm to 2 µm, or 0.5 µm to 1.5 µm.

[0158] The thickness deviation of the second circuit pattern may be 0.3 µm to 5 µm, 0.4 µm to 4 µm, or 0.5 µm to 2 µm.

[0159] Additionally, the thickness deviation of each pad portion is reduced.

[0160] In detail, the thickness deviation between the first pad portion and the third pad portion may be 0.3 µm to 0.9 µm.

[0161] Additionally, the thickness deviation of the second pad portion may be 0.5 µm to 3 µm, 0.8 µm to 2 µm, or 1 µm to 1.5 µm.

[0162] Additionally, the thickness deviation of the fourth pad portion may be 1 µm to 5 µm, 1.2 µm to 3 µm, or 1.5 µm to 2 µm.

[0163] In addition, the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern is reduced. The thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern is the difference between the largest thickness and the smallest thickness of the circuit patterns. The thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern may be 5 μm or less. In detail, the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern may be 1 μm to 5 μm, 1.2 μm to 4 μm, or 1.4 μm to 2 μm.

[0164]

[0165] Accordingly, the flexible circuit board according to the embodiment includes circuit patterns having uniform thickness and width. In addition, the circuit patterns have a thickness exceeding 8 μm.

[0166] Accordingly, the circuit pattern can be prevented from being damaged by the high current of the display panel. Furthermore, since the line width and thickness of the circuit patterns are uniform, the current and signals moving through each channel can be uniform. Consequently, the electrical characteristics of the flexible circuit board and COF module are improved.

[0167]

[0168] Referring to FIG. 18, one end of the COF module (2000) is connected to the display panel (4000), and the other end is connected to the circuit board (3000). For example, the display panel (4000) and the circuit board (3000) are disposed on one surface of the COF module (2000). However, the embodiment is not limited thereto. The display panel (4000) and the circuit board (3000) may be disposed on different surfaces of the COF module (2000). In this case, the COF module (2000) may have circuit patterns disposed on each of both surfaces. For example, the COF module (2000) may include a first circuit pattern and a second circuit pattern disposed on a first surface, and a second circuit pattern and a third circuit pattern disposed on the second surface. The second circuit patterns may be connected to each other through vias.

[0169] Since the COF module (2000) includes a flexible substrate, it has a rigid shape and a bent shape between the display panel (3000) and the circuit board (4000). That is, the COF module (2000) may include a bending area (BA).

[0170] The COF module (2000) connects the display panel (4000) and the circuit board (3000), which are arranged opposite each other, in a curved manner. Therefore, the thickness of the electronic device is reduced. Furthermore, the design freedom of the electronic device is enhanced. Furthermore, the COF module (2000) prevents wiring from breaking even when in a curved configuration. Consequently, the reliability of the electronic device is enhanced.

[0171]

[0172] Since the above COF module is flexible, it can be used in various electronic devices.

[0173] For example, referring to FIG. 19, the COF module can be applied to a flexible touch window. Accordingly, a touch device device including the COF module can be a flexible touch device. Accordingly, the user can bend or fold it by hand. Such a flexible touch window can be applied to a wearable touch, etc.

[0174] Referring to FIG. 20, the COF module can be applied to various wearable touch devices including curved displays. Accordingly, an electronic device including the COF module can be slimmed down or made lighter.

[0175] Referring to Fig. 21, the COF module can be used in various electronic devices having a display portion, such as a TV, monitor, or laptop. In this case, the COF module can also be used in an electronic device having a curved display portion.

[0176]

[0177] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0178] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. Description; A plurality of circuit patterns arranged on the above description; and Including a protective layer arranged on the above circuit pattern, The thickness of each of the above multiple circuit patterns exceeds 8㎛ and is 25㎛ or less, A flexible circuit board having a thickness deviation between the plurality of circuit patterns of 0.5 ㎛ to 3 ㎛.

2. In paragraph 1, Each of the above multiple circuit patterns, A buffer layer disposed on the above-mentioned substrate, A metal layer disposed on the above buffer layer, and A flexible circuit board comprising a bonding layer disposed on the metal layer.

3. In paragraph 2, A flexible circuit board, wherein the bonding layer is arranged to cover a side surface of the buffer layer, a side surface of the metal layer, and an upper surface of the metal layer.

4. In paragraph 2, A flexible circuit board having a thickness deviation between metal layers of the above-mentioned plurality of circuit patterns of 0.5 ㎛ to 3 ㎛.

5. In paragraph 2, The metal layer comprises a first metal layer and a second metal layer on the first metal layer, A flexible circuit board, wherein the thickness of the second metal layer is greater than the thickness of the first metal layer.

6. In paragraph 5, A flexible circuit board wherein the thickness deviation between the second metal layers of the plurality of circuit patterns is 0.5 ㎛ to 3 ㎛.

7. In paragraph 2, The above description includes a first side section and a second side section, A flexible circuit board, wherein the protective layer includes a first open area overlapping a region between the first side end and the second side end along a thickness direction, a second open area spaced apart from the first open area and closest to the first side end, and a third open area spaced apart from the first open area and the second open area and closest to the second side end.

8. In paragraph 7, The above multiple circuit patterns are, A first circuit pattern including a first pad portion arranged in the first open area, a second pad portion arranged in the second open area, and a first wiring portion connecting the first pad portion and the second pad portion, and A flexible circuit board comprising a second circuit pattern including a third pad portion arranged in the first open area, a fourth pad portion arranged in the third open area, and a second wiring portion connecting the third pad portion and the fourth pad portion.

9. In paragraph 8, A flexible circuit board, wherein the thickness deviation of the first circuit pattern is 0.3 ㎛ to 2.5 ㎛.

10. In paragraph 9, A flexible circuit board having a thickness deviation of the second circuit pattern of 0.3 ㎛ to 5 ㎛.

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