Array substrate and manufacturing method therefor, and display device

Abstract

An array substrate and a manufacturing method therefor, and a display device. The array substrate comprises: a base; a plurality of first wires (50) and a plurality of second wires (60), which are provided on one side of the base, the first wires (50) extending in a first direction, the second wires (60) extending in a second direction, the first wires (50) and the second wires (60) intersecting each other to define a plurality of sub-pixels arranged in an array, each sub-pixel comprising at least one transistor (20), and the first direction and the second direction intersecting each other; and a color filter layer (30) provided on one side of the transistors (20), the color filter layer (30) comprising color filter patterns corresponding to the sub-pixels, and the orthographic projections of the color filter patterns on the base covering the orthographic projections of the transistors (20) on the base.

Description

Array substrate, manufacturing method thereof, and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) have rapidly developed due to their small size, low power consumption, and zero radiation. An LCD panel consists of a cell-aligned thin-film transistor (TFT) array substrate and a color filter (CF) substrate. Liquid crystal (LC) molecules are positioned between the array and CF substrates. By controlling the second and first electrodes, an electric field is generated to drive the liquid crystal deflection, achieving grayscale display.

[0003] During the assembly process of the array substrate and color filter substrate, if there is any misalignment between the two substrates, it can easily lead to poor display. In addition, when the display device is bent, the spacers between the array substrate and the color filter substrate can easily slide and shift, which can easily cause problems such as light leakage and display abnormalities in the display device.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In one aspect, the present disclosure provides an array substrate, comprising:

[0007] substrate;

[0008] a plurality of first routing lines and a plurality of second routing lines disposed on one side of the substrate, wherein the first routing lines extend along a first direction, and the second routing lines extend along a second direction, the first routing lines and the second routing lines intersect with each other to define a plurality of sub-pixels arranged in an array, each of the sub-pixels comprising at least one transistor, and the first direction and the second direction intersect with each other;

[0009] A color filter layer is provided on one side of the transistor; the color filter layer comprises a color filter pattern corresponding to the sub-pixel, and the orthographic projection of the color filter pattern on the substrate covers the orthographic projection of the transistor on the substrate.

[0010] In an exemplary embodiment, along the first direction, a portion of an orthographic projection of the color filter pattern corresponding to one of the adjacent sub-pixels on the substrate falls within the other sub-pixel.

[0011] In an exemplary embodiment, the second wirings between adjacent sub-pixels overlap with orthographic projections of the color filter patterns of the two adjacent sub-pixels on the substrate.

[0012] In an exemplary embodiment, a center line of the second wiring overlaps with an orthographic projection of overlapping boundaries of the color filter patterns of the two adjacent sub-pixels on the substrate.

[0013] In an exemplary embodiment, a ratio of a distance between the second routing line, which is perpendicular to the center line of the substrate, and an extension line, in the first direction, of the overlapping boundary of the color filter patterns of the two adjacent sub-pixels, which is perpendicular to the substrate, to a length of the second routing line in the first direction is greater than 0 and less than or equal to 0.33.

[0014] In an exemplary embodiment, the color filter pattern corresponding to one of the adjacent sub-pixels is provided with a protrusion on at least one side of the first direction, and the orthographic projection of the protrusion on the substrate is located in the orthographic projection of the other of the adjacent sub-pixels on the substrate.

[0015] In an exemplary embodiment, the shape of the bump includes a trapezoid.

[0016] In an exemplary embodiment, the color filter layer is disposed on a side of the transistor close to the substrate; or, the color filter layer is disposed on a side of the transistor far from the substrate.

[0017] In an exemplary embodiment, each of the sub-pixels further comprises a connecting electrode connected to the at least one transistor, a first electrode disposed on a side of the connecting electrode away from the substrate, and a contact hole exposing at least a portion of the connecting electrode, the first electrode being connected to the connecting electrode through the contact hole; the color filter layer being disposed between the first electrode and the connecting electrode, the color filter pattern comprising a hollow area, and the orthographic projection of the contact hole on the substrate being located in the orthographic projection of the hollow area on the substrate.

[0018] In an exemplary embodiment, the hollow region of the color filter pattern corresponding to one of the adjacent sub-pixels is connected to the color filter pattern corresponding to the other sub-pixel.

[0019] In an exemplary embodiment, the color filter pattern corresponding to one of the adjacent sub-pixels is provided with a protrusion on at least one side of the first direction, and the protrusion extends into the hollow region of the color filter pattern corresponding to the other sub-pixel.

[0020] In an exemplary embodiment, the contact hole of one of the adjacent sub-pixels has a first side and a second side, the first side is adjacent to the protrusion of the color filter pattern corresponding to the other sub-pixel, and the second side is adjacent to the other side of the hollow area, the distance between the first side and the edge of the protrusion in the first direction is L1, and the minimum vertical distance between the second side and the other side of the hollow area is L2, and L1 is greater than or equal to L2.

[0021] In an exemplary embodiment, the ratio of L1 to L2 is less than or equal to 2 and greater than or equal to 1.

[0022] In an exemplary embodiment, a planarization layer is provided on a side of the color filter layer close to the first electrode, and an insulating layer is provided on a side of the planarization layer close to the first electrode. The contact hole includes at least a first via hole provided in the planarization layer and a second via hole provided in the insulating layer. The orthographic projection of the first via hole on the substrate is located in the orthographic projection of the second via hole on the substrate, and the orthographic projection of the second via hole on the substrate is located in the orthographic projection of the connecting electrode on the substrate.

[0023] In an exemplary embodiment, a minimum vertical distance between an edge of an orthographic projection of the first via hole on the substrate and an edge of an orthographic projection of the second via hole on the substrate is L3, and a minimum vertical distance between an edge of an orthographic projection of the first via hole on the substrate and an edge of an orthographic projection of the connecting electrode on the substrate is L4, and L4 is greater than L3.

[0024] In an exemplary embodiment, the ratio of L4 to L3 is less than or equal to 2 and greater than or equal to 1.1.

[0025] In an exemplary embodiment, the invention further includes a second electrode disposed on a side of the color filter layer close to the first electrode, an insulating layer disposed on a side of the second electrode close to the first electrode, and the first electrode is in direct contact with the insulating layer.

[0026] In an exemplary embodiment, a spacer layer is further included and is disposed on a side of the insulating layer away from the substrate. The spacer layer is in direct contact with the insulating layer, and the first electrode and the orthographic projection of the spacer layer on the substrate do not overlap.

[0027] In an exemplary embodiment, a cross-section of the spacer layer in a direction perpendicular to the substrate includes at least one of a rectangle, a regular trapezoid, and an inverted trapezoid.

[0028] In an exemplary embodiment, the transistor includes a gate disposed on the substrate, a gate insulating layer disposed on a side of the gate away from the substrate, an active layer disposed on a side of the gate insulating layer away from the substrate, a first electrode and a second electrode disposed on a side of the active layer away from the substrate, and the first electrode and the second electrode are connected through the active layer.

[0029] On the other hand, the present disclosure further provides a display device comprising the aforementioned array substrate.

[0030] In an exemplary embodiment, a color filter substrate is further included, which is arranged opposite to the array substrate. The color filter substrate includes a black matrix, and the black matrix does not overlap with the orthographic projection of at least part of the second trace on the substrate.

[0031] In an exemplary embodiment, a first spacer layer is further included. A side of the first spacer layer close to the array substrate is connected to the array substrate. A side of the first spacer layer close to the color filter substrate is connected to the color filter substrate.

[0032] In an exemplary embodiment, a first spacer layer and a second spacer layer are further included, wherein a side of the first spacer layer close to the array substrate is connected to the array substrate, a side of the first spacer layer away from the array substrate is connected to the second spacer layer, and a side of the second spacer layer away from the array substrate is connected to the color filter substrate, the first spacer layer includes a regular trapezoid in a cross section perpendicular to the substrate direction, and the second spacer layer includes an inverted trapezoid in a cross section perpendicular to the substrate direction.

[0033] In another aspect, the present disclosure further provides a method for preparing an array substrate, comprising:

[0034] A plurality of first wirings and a plurality of second wirings are formed on a substrate, wherein the first wirings extend along a first direction, and the second wirings extend along a second direction, the first wirings and the second wirings intersect with each other to define a plurality of sub-pixels arranged in an array, each of the sub-pixels comprising at least one transistor, and the first direction and the second direction intersect with each other;

[0035] A color filter layer is formed on one side of the transistor, wherein the color filter layer includes a color filter pattern corresponding to the sub-pixel, and an orthographic projection of the color filter pattern on the substrate covers an orthographic projection of the transistor on the substrate.

[0036] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0038] FIG1 is a schematic diagram of a cross-sectional structure of a display device;

[0039] FIG2 is a schematic diagram of a planar structure of a display device;

[0040] FIG3 is a schematic diagram of a planar structure of an array substrate;

[0041] FIG4 is a schematic diagram of a planar structure of a display device according to an exemplary embodiment of the present disclosure;

[0042] FIG5 is a schematic diagram of a planar structure of an array substrate after forming a first conductive layer in a preparation process of an exemplary embodiment of the present disclosure;

[0043] 6a and 6b are schematic diagrams of a planar structure of an array substrate after an active layer is formed in a preparation process of an exemplary embodiment of the present disclosure;

[0044] 7a and 7b are schematic diagrams of a planar structure of an array substrate after forming a second conductive layer in a preparation process of an exemplary embodiment of the present disclosure;

[0045] 8a and 8b are schematic diagrams of a planar structure of an array substrate after forming a color filter layer in a preparation process of an exemplary embodiment of the present disclosure;

[0046] 9a and 9b are schematic diagrams of a planar structure of an array substrate after forming a third conductive layer in a preparation process of an exemplary embodiment of the present disclosure;

[0047] FIG10 is a schematic diagram of a planar structure of an array substrate after forming a fourth conductive layer in a preparation process of an exemplary embodiment of the present disclosure;

[0048] FIG11 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0049] FIG12 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0050] FIG13 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0051] FIG14 is a partial plan view of a display device according to an exemplary embodiment of the present disclosure;

[0052] FIG15 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0054] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0055] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0056] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is merely to facilitate the description of this specification and simplify the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of the components may be appropriately changed depending on the direction in which each component is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced as appropriate.

[0057] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0058] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a gate electrode (source electrode terminal, drain region, or source electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the source electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0059] In this specification, the first electrode can be referred to as the source electrode, the second electrode can be referred to as the source electrode, or vice versa. The functions of "source electrode" and "source electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "source electrode" may be interchanged, and "source terminal" and "drain terminal" may be interchanged.

[0060] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0061] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0062] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0063] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0064] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0065] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In the ADS mode, the first electrode and the second electrode are both located on one side of the array substrate. In the TN and VA modes, the first electrode and the second electrode are respectively arranged on opposite sides of the liquid crystal layer, with the first electrode located on one side of the array substrate and the second electrode located on the opposite substrate.

[0066] The ADS mode operates on the principle that liquid crystal molecules lie in a plane parallel to the glass substrate. When no voltage is applied, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from exiting. When voltage is applied, a transverse electric field forms on the liquid crystal, aligning the liquid crystal molecules along the direction of the electric field. After passing through the lower polarizer and the liquid crystal layer, the light becomes elliptically polarized, allowing it to pass through the upper polarizer and exit.

[0067] The TN mode operates under the principle that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and the liquid crystal molecules before exiting through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the upper and lower polarizers, align vertically. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. However, since its polarization axis is parallel to the upper polarizer, the light is absorbed and cannot be emitted.

[0068] The VA mode operates on the principle that liquid crystal molecules are aligned perpendicular to the glass substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from being emitted. When voltage is applied, the liquid crystal molecules are deflected in the direction of the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0069] The structure of the array substrate is described below by taking the ADS display mode array substrate structure as an example.

[0070] Figure 1 is a schematic cross-sectional view of a display device. As shown in Figure 1 , the display device may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, as well as a liquid crystal layer 300 and a spacer layer disposed between the array substrate 100 and the color filter substrate 200. The array substrate 100 may include a first structure layer 102 disposed on the side of a first substrate 101 facing the color filter substrate 200, and the color filter substrate 200 may include a second structure layer 202 disposed on the side of a second substrate 201 facing the array substrate 100. In an exemplary embodiment, the first structure layer 102 may include first and second traces, thin-film transistors, a color filter layer, first and second electrodes, and the second structure layer 202 may include a black matrix. The liquid crystal layer 300 may include a plurality of liquid crystal molecules having dielectric anisotropy. In response to an electric field applied between the array substrate 100 and the color filter substrate 200, the liquid crystal molecules may rotate in a predetermined direction between the array substrate 100 and the color filter substrate 200, thereby allowing or blocking light transmission.

[0071] Figure 2 is a schematic diagram of a planar structure of a display device. The display device may include a display area and a border area located around the display area. As shown in Figure 2, the display area of ​​the display device may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels includes a thin film transistor, a first electrode, and a second electrode.

[0072] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel that emits red (R) light, the second sub-pixel P2 can be a green sub-pixel that emits green (G) light, and the third sub-pixel P3 can be a blue sub-pixel that emits blue (B) light. The shape of the sub-pixels in the pixel unit can be rectangular, diamond, pentagonal or hexagonal, etc. The sub-pixels in the pixel unit can be arranged horizontally in parallel, vertically in parallel or in a herringbone manner, which is not limited in the present disclosure.

[0073] In an exemplary embodiment, a pixel unit may include four sub-pixels, which is not limited in the present disclosure.

[0074] In an exemplary embodiment, the display device includes a display area having a rectangular shape. In some embodiments, the display area may also have a circular shape, an elliptical shape, or a polygonal shape such as a triangle, a pentagon, or the like.

[0075] In an exemplary embodiment, the display device may be a flat panel display device. In some embodiments, the display device may also be other types of display devices, such as a flexible display device, a foldable display device, a rollable display device, etc.

[0076] Figure 3 is a schematic diagram of a planar structure of an array substrate. As shown in Figure 3, in an exemplary embodiment, the array substrate may include a plurality of first lines (S1 to Sm) and a plurality of second lines (D1 to Dn). The plurality of first lines may extend horizontally and be arranged sequentially along the vertical direction, and the plurality of second lines may extend vertically and be arranged sequentially along the horizontal direction. The plurality of intersecting first lines and the plurality of second lines define a plurality of regularly arranged sub-pixels Pxij, where i and j may be natural numbers. In an exemplary embodiment, the sub-pixel Pxij may include a thin film transistor, a color filter layer, a second electrode, and a first electrode, and the thin film transistor is connected to the first line, the second line, and the first electrode, respectively.

[0077] In an exemplary embodiment, a plurality of first traces are led out to the border area and connected to the scan driver, a plurality of second traces are led out to the border area and connected to the data driver, and at least a portion of the scan driver and the data driver can be formed on the array substrate.

[0078] In an exemplary embodiment, an external control device (such as a timing controller) may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver. The data driver may use the received grayscale values ​​and control signals to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may use a clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel row basis, where n may be a natural number. The external control device may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The scan driver may use the clock signal, the scan start signal, etc. to generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm. For example, the scan driver may sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm, where m may be a natural number. For example, the scan driver may be configured as a shift register and may generate scan signals by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of the clock signal.

[0079] An exemplary embodiment of the present disclosure provides an array substrate, comprising:

[0080] substrate;

[0081] a plurality of first routing lines and a plurality of second routing lines disposed on one side of the substrate, wherein the first routing lines extend along a first direction, and the second routing lines extend along a second direction, the first routing lines and the second routing lines intersect with each other to define a plurality of sub-pixels arranged in an array, each of the sub-pixels comprising at least one transistor, and the first direction and the second direction intersect with each other;

[0082] A color filter layer is provided on one side of the transistor; the color filter layer comprises a color filter pattern corresponding to the sub-pixel, and the orthographic projection of the color filter pattern on the substrate covers the orthographic projection of the transistor on the substrate.

[0083] In an exemplary embodiment, along the first direction, a portion of an orthographic projection of the color filter pattern corresponding to one of the adjacent sub-pixels on the substrate falls within the other sub-pixel.

[0084] In an exemplary embodiment, the second wirings between adjacent sub-pixels overlap with orthographic projections of the color filter patterns of the two adjacent sub-pixels on the substrate.

[0085] In an exemplary embodiment, a center line of the second wiring overlaps with an orthographic projection of overlapping boundaries of the color filter patterns of the two adjacent sub-pixels on the substrate.

[0086] In an exemplary embodiment, a ratio of a distance between the second routing line, which is perpendicular to the center line of the substrate, and an extension line, in the first direction, of the overlapping boundary of the color filter patterns of the two adjacent sub-pixels, which is perpendicular to the substrate, to a length of the second routing line in the first direction is greater than 0 and less than or equal to 0.33.

[0087] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0088] In the following, the display device of this embodiment is taken as a liquid crystal display device (LCD) as an example. The display device of this embodiment can adopt a curved screen design, that is, the edge area or other area of ​​the array substrate and the color film substrate in the display device forms a curved surface, but the display panel of this embodiment is not limited to this.

[0089] Figure 4 is a schematic diagram of the planar structure of a display device according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display device according to the present disclosure includes an array substrate and a color filter substrate disposed opposite each other in a plane parallel to the display device, and a liquid crystal layer and a spacer layer disposed between the array substrate and the color filter substrate. As shown in Figure 4, the array substrate includes a plurality of first traces 50 and a plurality of second traces 60 disposed on a first substrate in a direction parallel to the array substrate. The first traces 50 extend along a first direction D1 and are spaced apart along a second direction D2. The first traces 50 are connected to the second gate electrode of the transistor 20. The second traces 60 extend along the second direction and are connected to the electrode of the transistor 20. The first traces 50 and the second traces 60 intersect to define a plurality of sub-pixels arranged in an array, each of which includes at least one transistor 20. The first direction D1 and the second direction D2 are both parallel to the array substrate and intersect with each other. For example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0090] In an exemplary embodiment, the first trace 50 may be integrally connected to the gate of the transistor 20 and may include the same conductive material. The gate of the transistor 20 may be a portion of the first trace 50 protruding in the opposite direction of the second direction D2.

[0091] In an exemplary embodiment, the second wiring 60 may be bent periodically to improve the transmittance of the display device. For example, in one sub-pixel, the second wiring 60 may be bent into a V-shape, as shown in FIG4 , to maximize the transmittance of the display device.

[0092] In an exemplary embodiment, the second trace 60 may be integrally connected to the second electrode 220 of the transistor 20 and include the same conductive material. The second electrode 220 of the transistor 20 may be a portion of the second trace 60 .

[0093] In an exemplary embodiment, the first substrate 101 may be an insulating substrate and may be transparent. For example, the first substrate 101 may be a glass substrate, a quartz substrate, a transparent resin substrate, or the like. The first substrate 101 may include a polymer or plastic material having high heat resistance. In some embodiments, the first substrate 101 may be flexible. In other words, the first substrate 101 may be a substrate that can be deformed by rolling, folding, bending, or the like.

[0094] In an exemplary embodiment, the array substrate further includes a color filter layer 30, which is located on one side of the transistor 20. For example, the color filter layer 30 may be located on the side of the transistor 20 closer to the first substrate; alternatively, the color filter layer 30 may be located on the side of the transistor 20 farther from the first substrate. The color filter layer 30 includes a color filter pattern corresponding to the sub-pixel, with the orthographic projection of the color filter pattern on the substrate overlapping the orthographic projection of the transistor on the substrate.

[0095] In an exemplary embodiment, the array substrate further includes a second electrode 33 disposed on a side of the transistor 20 away from the first substrate, and a first electrode 40 disposed on a side of the second electrode 22 away from the first substrate. The first electrode 40 and the second electrode 22 overlap in orthographic projection on the substrate, and the first electrode 40 can be connected to the first electrode of the transistor 20.

[0096] In an exemplary embodiment, the display device of the embodiment of the present disclosure further includes a contact hole 70 and a connecting electrode 80. The connecting electrode 80 is connected to the first electrode of the transistor 20. The contact hole 70 extends in a direction perpendicular to the first substrate. The contact hole 70 overlaps with the orthographic projection of the connecting electrode 80 on the first substrate. For example, the orthographic projection of the contact hole 70 on the first substrate is located within the orthographic projection of the connecting electrode 80 on the first substrate. The contact hole 70 exposes at least a portion of the surface of the connecting electrode 80. At least a portion of the first electrode 40 extends to the area where the contact hole 70 is located, overlapping with the orthographic projection of the contact hole 70 on the first substrate. The first electrode 40 is connected to the exposed connecting electrode 80 through the contact hole 70, so that the first electrode 40 can be connected to the first electrode of the transistor 20 through the connecting electrode 80, so that the first electrode 40 can receive a voltage from the first electrode of the transistor 20.

[0097] In an exemplary embodiment, the orthographic projection of the contact hole 70 on the first substrate may include a rectangle. In some embodiments, the orthographic projection of the contact hole on the first substrate may include a rounded rectangle, circle, ellipse, triangle, rhombus, trapezoid, pentagon, hexagon, etc.

[0098] The following is an exemplary description of the preparation process of the array substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the array substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0099] In an exemplary embodiment, the preparation process of the array substrate of this embodiment may include the following operations.

[0100] (11) Forming a first conductive layer. In an exemplary embodiment, forming the first conductive layer may include: depositing a first conductive film on a first substrate, patterning the first conductive film through a patterning process to form the first conductive layer, wherein the first conductive layer includes a plurality of first traces 50 and a plurality of gates 204, as shown in FIG5 .

[0101] In an exemplary embodiment, the first traces 50 extend along the first direction D1 and are arranged at intervals along the second direction D2.

[0102] In an exemplary embodiment, the gate 204 is block-shaped. Multiple gates 204 are disposed on a side of the first trace 50 opposite the second direction D2. The gates 204 are spaced apart in the first direction D1. The gates 204 are integrally connected to the first trace 50 and comprise the same conductive material. The gates 204 may be a portion of the first trace 50 that protrudes in the direction opposite the second direction D2.

[0103] (12) Forming an active layer. In an exemplary embodiment, forming the active layer may include: depositing a semiconductor thin film on a side of the first conductive layer away from the first substrate on the substrate on which the aforementioned pattern is formed, and patterning the semiconductor thin film through a patterning process to form a plurality of active layers 203, as shown in FIG6a and FIG6b.

[0104] In an exemplary embodiment, the active layer 203 is in a block shape, for example, a rectangular block shape. The active layer 203 overlaps with the orthographic projection of the gate 204 on the first substrate. For example, the orthographic projection of the active layer 203 on the first substrate is located in the orthographic projection of the gate 204 on the first substrate.

[0105] (13) Forming a second conductive layer. In an exemplary embodiment, forming the second conductive layer may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, on a side of the active layer away from the first substrate, and patterning the second conductive film through a patterning process to form a second conductive layer, wherein the second conductive layer includes a plurality of second traces 60, a plurality of connecting electrodes 80, and a first electrode 210, as shown in FIG7a and FIG7b.

[0106] In an exemplary embodiment, the second lines 60 extend along the second direction D2. A plurality of second lines 60 are arranged at intervals along the first direction D1. The second lines 60 intersect with the first lines 50 to define a plurality of sub-pixels arranged in an array. The second lines 60 may be periodically curved to improve the transmittance of the display device.

[0107] In an exemplary embodiment, at least a portion of the second trace 60 overlaps with an orthographic projection of the active layer 203 on the first substrate, and the region where the second trace 60 overlaps with the active layer 203 forms the second pole 220 .

[0108] In an exemplary embodiment, the connection electrode 80 is block-shaped, such as a rectangular block, and is located on a side of the second trace 60 opposite to the first direction D1. The connection electrode 80 does not overlap with the orthographic projections of the first trace 50 and the second trace 60 on the first substrate.

[0109] In some embodiments, the shape of the orthographic projection of the connection electrode on the first substrate may include a rounded rectangle, a circle, an ellipse, a triangle, a rhombus, a trapezoid, a pentagon, a hexagon, etc.

[0110] In an exemplary embodiment, the first electrode 210 is L-shaped. A first end of the first electrode 210 is connected to the connection electrode 80 , and a second end of the first electrode 210 overlaps with an orthographic projection of the active layer 203 on the first substrate.

[0111] In an exemplary embodiment, the first electrode 210 , the second electrode 220 , the active layer 203 , and the gate electrode 204 form a transistor of a sub-pixel.

[0112] (14) Forming a color filter layer. In an exemplary embodiment, forming the color filter layer may include: depositing a color filter thin film on the substrate on which the aforementioned pattern is formed, on a side of the second conductive layer away from the first substrate, patterning the color filter thin film through a patterning process to form a color filter layer 30, wherein the color filter layer 30 includes a color filter pattern corresponding to the sub-pixel, wherein the orthographic projection of the color filter pattern on the substrate covers the orthographic projection of the transistor on the substrate, as shown in FIG8a and FIG8b.

[0113] In an exemplary embodiment, the color filter layer 30 includes a first color filter pattern 301 that transmits a first color, a second color filter pattern 302 that transmits a second color, and a third color filter pattern 303 that transmits a third color. The first color filter pattern 301, the second color filter pattern 302, and the third color filter pattern 303 are arranged in sequence along a first direction D1. The first color filter pattern 301 is adjacent to the second color filter pattern 302, and at least a portion of an edge of the first color filter pattern 301 is connected to at least a portion of an edge of the second color filter pattern 302; the second color filter pattern 302 is adjacent to the third color filter pattern 303, and at least a portion of an edge of the second color filter pattern 302 is connected to at least a portion of an edge of the third color filter pattern 303.

[0114] In an exemplary embodiment, the color filter pattern includes a hollow region 304, and the connection electrode 80 overlaps with the orthographic projection of the hollow region 304 on the first substrate. The hollow region 304 of the color filter pattern is connected to the edge of the adjacent color filter pattern in the opposite direction of the first direction D1.

[0115] In an exemplary embodiment, the color filter pattern corresponding to one of the adjacent sub-pixels is provided with a protrusion 306 on one side of the first direction D1, the orthographic projection of the protrusion 306 on the substrate is located in the orthographic projection of the other of the adjacent sub-pixels on the substrate, and the protrusion 306 extends into the hollow area 304 of the color filter pattern corresponding to the adjacent sub-pixel.

[0116] In an exemplary embodiment, the shape of the bump 306 comprises a trapezoid.

[0117] (15) Forming a third conductive layer. In an exemplary embodiment, forming the second conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, on a side of the second conductive layer away from the first substrate, patterning the third conductive film shown in Figures 9a and 9b by a patterning process to form a third conductive layer, wherein the third conductive layer includes a second electrode 33, as shown.

[0118] In an exemplary embodiment, the second electrode 33 may cover a plurality of sub-pixels and has a relief hole 331 disposed therein. The relief hole 331 has an orthographic projection on the first substrate including an orthographic projection of the connection electrode 80 on the first substrate 101 , and the relief hole 331 exposes the connection electrode 80 .

[0119] (16) Forming a fourth conductive layer. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, on a side of the third conductive layer away from the first substrate, and patterning the fourth conductive film through a patterning process to form the fourth conductive layer, wherein the fourth conductive layer includes the first electrode 40, as shown in FIG. 4A and FIG. 10 .

[0120] In an exemplary embodiment, the first electrode 40 may be a slit electrode. The first electrode 40 may include a plurality of branch electrodes 401 that overlap with the orthographic projection of the second electrode 33 on the first substrate, and slits 402 formed between the branch electrodes 401. The branch electrodes 401 may be substantially parallel to the second trace 60 and may extend along the contour of the second trace 60. For example, the second trace 60 may be bent into a V-shape, and each branch electrode 401 may be formed to have a V-shaped edge. The direction in which the slits 402 of the first electrode 40 extend is not specifically limited and may extend along the second direction D2 or at a certain angle to the second direction D2.

[0121] In an exemplary embodiment, the first electrode 40 may be made of a transparent conductive material, such as ITO, IZO, ITZO, or AZO.

[0122] In an exemplary embodiment, the first electrode 40 is provided with an extension portion 403 on one side of the second direction D2, the first end of the extension portion 403 is connected to the first electrode 40, the second end of the extension portion 403 extends along the second direction D2, at least a portion of the extension portion 403 overlaps with the positive projection of the connecting electrode 80 on the first substrate, and the extension portion 403 can be connected to the connecting electrode 80.

[0123] Figure 11 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 11 may be a cross-sectional view taken along the AA' line in Figure 4. In an exemplary embodiment, as shown in Figure 11 , the display device according to an exemplary embodiment of the present disclosure may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, as well as a liquid crystal layer and a spacer layer (not shown) disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may include a second base 201. The array substrate 100 may include a first substrate 101, a first insulating layer 21 arranged on the first substrate 101, a second conductive layer 32 arranged on a side of the first insulating layer 21 away from the first substrate 101, a second insulating layer 22 arranged on a side of the second conductive layer 32 away from the first substrate 101, a color filter layer 30 arranged on a side of the second insulating layer 22 away from the first substrate 101, an organic dielectric layer 90 arranged on a side of the color filter layer 30 away from the first substrate 101, a third conductive layer arranged on a side of the organic dielectric layer 90 away from the first substrate 101, a third insulating layer 23 arranged on a side of the third conductive layer away from the first substrate 101, and a fourth conductive layer 34 arranged on a side of the third insulating layer 23 away from the first substrate 101.

[0124] In an exemplary embodiment, the second substrate 201 may be an insulating substrate and may be transparent. For example, the second substrate 201 may be a glass substrate, a quartz substrate, a transparent resin substrate, or the like. The second substrate 201 may include a polymer or plastic material with high heat resistance. In some embodiments, the second substrate 201 may be flexible. In other words, the first substrate 101 may be a substrate that can be deformed by rolling, folding, bending, or the like.

[0125] In exemplary embodiments, the first insulating layer 21 , the second insulating layer 22 , and the third insulating layer 23 may employ an inorganic material, for example, silicon nitride or silicon oxide.

[0126] In an exemplary embodiment, the second conductive layer 32 may include a second trace 60 . The second trace 60 does not overlap with an orthographic projection of the first electrode 40 on the first substrate 101 .

[0127] In an exemplary embodiment, the color filter layer 30 may include a plurality of color filter patterns that may transmit light of different colors.

[0128] In an exemplary embodiment, the second wirings 60 between adjacent sub-pixels overlap with the orthographic projections of the color filter patterns of the two adjacent sub-pixels on the first substrate.

[0129] In an exemplary embodiment, the second routing line 60 is perpendicular to the center line O of the first substrate, and the distance d1 from the overlapping boundary of the color filter patterns of the two adjacent sub-pixels in the first direction D1 is the same as that in the first direction D1, and the length of the second routing line 60 in the first direction D1 is the same as that in the first direction D1, and the ratio of d1 to d2 is greater than 0 and less than or equal to 0.33.

[0130] In some embodiments, the second trace 60 overlaps with the orthographic projection of the substrate on the overlapping boundaries of the color filter patterns of the two adjacent sub-pixels at a point perpendicular to the center line O of the first substrate.

[0131] In an exemplary embodiment, the orthographic projections of the organic dielectric layer 90 and the color filter layer 30 on the first substrate 101 overlap. The organic dielectric layer 90 covers multiple color filter patterns that transmit light of different colors. The surface of the organic dielectric layer 90 on the side closest to the first substrate 101 is in contact with the color filter layer 30, while the surface of the organic dielectric layer 90 on the side away from the first substrate 101 is flattened. The color filter patterns that transmit light of different colors have different thicknesses. The organic dielectric layer 90 can flatten the surface of the color filter layer 30, compensating for the step difference between adjacent color filter patterns and ensuring planarization during subsequent film fabrication.

[0132] In an exemplary embodiment, the third conductive layer includes a second electrode 33 , and the second electrode 33 overlaps with an orthographic projection of the color filter layer 30 on the first substrate 101 .

[0133] In an exemplary embodiment, the fourth conductive layer 34 includes a first electrode 40. The first electrode 40 may be in direct contact with the third insulating layer 23. The first electrode 40 overlaps with the orthographic projection of the color filter layer 30 on the first substrate 101. The first electrode 40 overlaps with the orthographic projection of the second electrode on the first substrate 101.

[0134] Figure 12 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 12 may be a cross-sectional view taken along the C-C' line in Figure 4. In an exemplary embodiment, as shown in Figure 12, on a plane perpendicular to the display device, the display device according to the present embodiment may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, and a liquid crystal layer and a spacer layer 400 disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may include a second substrate 201 and a black matrix 202 disposed on a side of the second substrate 201 proximal to the array substrate 100. The array substrate 100 may include a first substrate 101, a first conductive layer 31 arranged on the first substrate 101, a first insulating layer 21 arranged on a side of the first conductive layer 31 away from the first substrate 101, a semiconductor layer arranged on a side of the first insulating layer 21 away from the first substrate 101, a second conductive layer arranged on a side of the semiconductor layer away from the first substrate 101, a second insulating layer 22 arranged on a side of the second conductive layer away from the first substrate 101, a color filter layer 30 arranged on a side of the second insulating layer 22 away from the first substrate 101, an organic dielectric layer 90 arranged on a side of the color filter layer 30 away from the first substrate 101, a third conductive layer arranged on a side of the organic dielectric layer 90 away from the first substrate 101, and a third insulating layer 23 arranged on a side of the third conductive layer away from the first substrate 101.

[0135] In an exemplary embodiment, the first conductive layer 31 may include a first wiring and a gate, and the first wiring and the gate may be connected as a whole and include the same conductive material. The first wiring and the gate may be formed of an aluminum (Al)-based metal such as Al or an Al alloy, a silver (Ag)-based metal such as Ag or an Ag alloy, a copper (Cu)-based metal such as Cu or a Cu alloy, a molybdenum (Mo)-based metal such as Mo or a Mo alloy, chromium (Cr), tantalum (Ta), titanium (Ti), etc. At least one of the first wiring and the gate may have a single-layer structure or a multilayer structure including two conductive films with different physical properties. For example, one of the two conductive films may be formed of a low-resistance metal (e.g., an Al-based metal, an Ag-based metal, a Cu-based metal, etc.) to reduce signal delay or voltage drop in the first wiring, and the other conductive film may be formed of a material having excellent contact properties similar to indium tin oxide (ITO) and indium zinc oxide (IZO) (such as a Mo-based metal, Cr, Ti, Ta, or the like). For example, the multi-layer structure of the first wiring and the gate includes a combination of a Cr lower film and an Al upper film or a combination of an Al lower film and a Mo upper film, but the present disclosure is not limited thereto.

[0136] In some embodiments, the first trace and the gate may be located in different film layers and connected through a via, and the first trace and the gate may include different conductive materials.

[0137] In an exemplary embodiment, the first insulating layer 21 may serve as a gate insulating layer of a transistor, for isolating a gate electrode from an active layer. The first insulating layer 21 may have a single-layer structure or a multi-layer structure.

[0138] In an exemplary embodiment, the semiconductor layer includes an active layer 203 , and the active layer 203 overlaps with an orthographic projection of the gate on the first substrate 101 . For example, the orthographic projection of the active layer 203 on the first substrate 101 is located in the orthographic projection of the gate on the first substrate 101 .

[0139] In an exemplary embodiment, the active layer 203 may include a metal oxide, for example, Indium Gallium Zinc Oxide (IGZO).

[0140] In an exemplary embodiment, the second conductive layer includes a first electrode 210 and a second electrode 220, which are connected via the active layer 203. The first electrode 210 can serve as the drain electrode of the transistor and is connected to the first electrode via a contact hole; the second electrode 220 can serve as the source electrode of the transistor and is integrally connected to the second trace. The gate electrode, active layer 203, first electrode 210, and second electrode 220 together form the transistor of the array substrate.

[0141] In an exemplary embodiment, the second conductive layer may be formed of Al, Cu, Ag, Mo, Cr, Ti, Ta, or an alloy thereof, and may have a single-layer structure or a multi-layer structure. The multi-layer structure includes a lower film formed of a refractory metal and a low-resistance upper film formed on the lower film, but the present disclosure is not limited thereto.

[0142] According to the capacitance calculation formula c=εs / d, where c is the capacitance value, ε is the dielectric constant of the medium between the capacitor plates, s is the relative area of ​​the capacitor plates, and d is the vertical distance between the capacitor plates, the display device of the embodiment of the present disclosure increases the film thickness between the second conductive layer and the third conductive layer by setting a color filter layer between the second conductive layer and the third conductive layer, and reduces the capacitance value between the first electrode and the second electrode and the second electrode in the second conductive layer, thereby reducing the load of the display device and further reducing the power consumption of the display device.

[0143] The display device of the embodiment of the present disclosure increases the film thickness between the first conductive layer and the third conductive layer by setting a color filter layer between the first conductive layer and the third conductive layer, reduces the capacitance value between the gate and the second electrode in the first conductive layer, thereby reducing the load of the display device and further reducing the power consumption of the display device.

[0144] The display device of the embodiment of the present disclosure improves the performance of the display device, increases the aperture ratio, improves the transmittance, and alleviates problems such as poor display by disposing a color filter layer in the array substrate.

[0145] In an exemplary embodiment, the spacer layer 400 is disposed on the third insulating layer 23 and is in direct contact with the third insulating layer 23. The spacer layer 400 is used to support the array substrate 100 and the color filter substrate 200, separate the array substrate 100 and the color filter substrate 200, and maintain a distance between the array substrate 100 and the color filter substrate 200.

[0146] The display device disclosed herein arranges the spacer layer 400 on the array substrate 100, so that during the alignment process of the array substrate 100 and the color filter substrate 200, only the spacer layer 400 of the array substrate 100 and the black matrix 202 of the color filter substrate 200 need to be aligned, thereby reducing the difficulty of alignment. In addition, the surface of the black matrix is ​​flat, and after the spacer layer 400 and the black matrix 202 are aligned, the height of the spacer layer 400 can be ensured to be consistent, thereby avoiding display differences caused by inconsistent heights of the spacer layer 400 and ensuring the display effect.

[0147] In an exemplary embodiment, a cross-section of the spacer layer 400 in a direction perpendicular to the first substrate includes at least one of a rectangle, a regular trapezoid, and an inverted trapezoid.

[0148] In an exemplary embodiment, the black matrix 202 of the color filter substrate 200 can extend along a first direction D1, overlapping with the orthographic projection of at least a portion of the first traces of the array substrate 100 on the first substrate, and not overlapping with the orthographic projection of at least a portion of the second traces of the array substrate 100 on the first substrate. For example, the black matrix 202 extends in the same direction as the first traces and overlaps with the orthographic projection of the first traces on the first substrate, while not overlapping with the orthographic projection of the second traces on the first substrate. The display device disclosed herein can use the second traces as the black matrix to block light, thereby simplifying the production process and reducing production costs.

[0149] Figure 13 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 13 may be a cross-sectional view taken along the BB' line in Figure 4. In an exemplary embodiment, as shown in Figure 13, on a plane perpendicular to the display device, the display device according to the present embodiment may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, and a liquid crystal layer and a spacer layer disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may include a second substrate 201 and a black matrix 202 disposed on a side of the second substrate 201 proximal to the array substrate 100. The array substrate 100 may include a first substrate 101, a first conductive layer arranged on the first substrate 101, a first insulating layer 21 arranged on a side of the first conductive layer away from the first substrate 101, a second conductive layer arranged on a side of the first insulating layer 21 away from the first substrate 101, a second insulating layer 22 arranged on a side of the second conductive layer away from the first substrate 101, a color filter layer 30 arranged on a side of the second insulating layer 22 away from the first substrate 101, an organic dielectric layer 90 arranged on a side of the color filter layer 30 away from the first substrate 101, a third conductive layer arranged on a side of the organic dielectric layer 90 away from the first substrate 101, a third insulating layer 23 arranged on a side of the third conductive layer away from the first substrate 101, and a fourth conductive layer arranged on a side of the third insulating layer 23 away from the first substrate 101.

[0150] In an exemplary embodiment, the first conductive layer includes a first trace 50 extending along the first square, the first trace 50 being connected to the gate of the transistor. The second conductive layer includes a connecting electrode 80, which is connected to the first electrode of the transistor. The third conductive layer includes a second electrode 33. The fourth conductive layer includes a first electrode 40.

[0151] In an exemplary embodiment, the connecting electrode 80 and the first electrode of the transistor are located in the same film layer and are integrally connected. The connecting electrode 80 and the first electrode of the transistor may comprise the same conductive material. In some embodiments, the connecting electrode and the first electrode of the transistor may be located in different film layers and connected via a via.

[0152] In an exemplary embodiment, the display device of the disclosed embodiment may further include a contact hole 70. The contact hole 70 extends from the surface of the third insulating layer 23 away from the first substrate 101, sequentially passes through the third insulating layer 23, the organic dielectric layer 90, and a portion of the second insulating layer 22, to the surface of the connecting electrode 80 away from the first substrate 101, exposing at least a portion of the surface of the connecting electrode 80. The contact hole 70 does not overlap with the orthographic projection of the second electrode on the first substrate 101. The first electrode 40 covers at least a portion of the inner wall of the contact hole 70, for example, the first electrode 40 covers the sidewalls and bottom wall of the contact hole 70. The first electrode 40 directly contacts the exposed connecting electrode 80 through the contact hole 70.

[0153] In an exemplary embodiment, the orthographic projection of the side of the contact hole 70 away from the first substrate 101 on the first substrate 101 is located in the orthographic projection of the side of the contact hole 70 close to the first substrate 101 on the first substrate 101. The contact hole 70 has an inverted trapezoidal shape with a larger top and a smaller bottom in a cross section perpendicular to the first substrate 101.

[0154] In an exemplary embodiment, the contact hole 70 includes at least a first via hole 701 disposed in the organic dielectric layer 90 and a second via hole 702 disposed in the third insulating layer 23. The first via hole 701 penetrates the organic dielectric layer 90 in a direction perpendicular to the first substrate 101, and the second via hole 702 penetrates the third insulating layer 23 in a direction perpendicular to the first substrate 101. The first via hole 701 and the second via hole 702 are connected and can be formed simultaneously through a single etching process. The orthographic projection of the first via hole 701 on the first substrate 101 is located within the orthographic projection of the second via hole 702 on the first substrate 101, and the orthographic projection of the second via hole 702 on the first substrate 101 is located within the orthographic projection of the connecting electrode 80 on the first substrate 101.

[0155] In an exemplary embodiment, the color filter layer 30 includes a color filter pattern, which includes a hollow region 304. The color resist material in the hollow region 304 is etched away, and a portion of the material of the organic dielectric layer 90 is filled into the hollow region 304. The orthographic projection of the contact hole 70 on the first substrate 101 is located within the orthographic projection of the hollow region 304 on the first substrate 101, so that the contact hole 70 does not overlap with the orthographic projection of the color filter layer 30 on the first substrate 101.

[0156] In the display device of the disclosed embodiment, the orthographic projection of the contact hole 70 on the first substrate 101 is positioned within the orthographic projection of the hollowed-out region 304 on the first substrate 101. This prevents penetration of the color filter layer 30 during the contact hole formation process, thereby preventing breakage of the color filter layer 30 during the contact hole formation process. Furthermore, the number of film layers penetrated during contact hole formation is reduced, thereby lowering the risk of significant deviation between the contact hole 70 aperture and the designed dimensions and resolving issues such as residual color filter material within the contact hole 70.

[0157] Figure 14 is a partial plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 14 may be an enlarged view of point a in Figure 4 . In an exemplary embodiment, as shown in Figure 14 , the color filter pattern includes a hollow region 304. The first and second via holes 701 and 702 connecting the electrode 80 and the contact hole are located within the hollow region 304, overlapping with the orthographic projection of the hollow region 304 on the first substrate. The hollow region 304 has an opening 305 on one side opposite to the first direction D1. The other sides of the hollow region 304 surround the contact hole. The other sides of the hollow region 304 may include one side of the hollow region 304 in the first direction D1 and two opposite sides in the second direction D2. The opening 305 of the hollow region 304 of the color filter pattern is adjacent to the edge of an adjacent color filter pattern. For example, the opening 305 of the hollow region 304 of the color filter pattern is connected to the edge of an adjacent color filter pattern. In some embodiments, the hollow region has openings on both opposite sides of the first direction, which will not be further described in detail in this embodiment.

[0158] In an exemplary embodiment, a bump 306 is provided on one side edge of the color filter pattern in the first direction D1. The bump 306 extends into the opening 305 of the hollow region of the adjacent color filter pattern, so that at least part of the bump 306 is located in the hollow region of the adjacent color filter pattern.

[0159] In an exemplary embodiment, the orthographic projection of the second via hole 702 of the contact hole onto the first substrate is a rounded rectangle. The second via hole 702 has a first side 7021 and a second side 7022. The first side 7021 is adjacent to the bump 306 of the adjacent color filter pattern, and the second side 7022 is adjacent to the other side of the hollow region 304. The minimum vertical distance between the first side 7021 and the edge of the bump 306 of the adjacent color filter pattern is L1, and the minimum vertical distance between the second side 7022 and the other side of the hollow region is L2, where L1 is greater than or equal to L2.

[0160] The display device of the embodiment of the present disclosure makes the slope of the contact hole gentle by making the minimum vertical distance between the first side 7021 and the edge of the protrusion 306 of the adjacent color filter pattern greater than or equal to the minimum vertical distance between the second side 7022 and the other sides of the hollow area, thereby preventing the contact hole from having a steep slope, resulting in residual color resist material in the contact hole and failure of the electrical connection.

[0161] In an exemplary embodiment, the ratio of L1 to L2 is less than or equal to 4 and greater than or equal to 1. For example, the ratio of L1 to L2 is less than or equal to 2 and greater than or equal to 1, thereby making the contact hole slope gentle, avoiding color resist material residue, and ensuring electrical connection.

[0162] In an exemplary embodiment, L1 is greater than or equal to 7 micrometers. For example, L1 is greater than or equal to 10 micrometers and less than or equal to 15 micrometers, so as to make the slope of the contact hole gentle, avoid color resist material residue, and ensure electrical connection.

[0163] In an exemplary embodiment, L2 is greater than or equal to 5.5 micrometers. For example, L2 is greater than or equal to 7 micrometers and less than or equal to 10 micrometers, so as to make the slope of the contact hole gentle, avoid color resist material residue, and ensure electrical connection.

[0164] In an exemplary embodiment, the orthographic projection of the second via 702 on the first substrate is located in the orthographic projection of the connecting electrode 80 on the first substrate, the minimum vertical distance between the edge of the orthographic projection of the first via 701 on the first substrate and the edge of the orthographic projection of the second via 702 on the first substrate is L3, and the minimum vertical distance between the edge of the orthographic projection of the first via 701 on the first substrate and the edge of the orthographic projection of the connecting electrode 80 on the first substrate is L4, and L4 is greater than L3, so that the exposed area of ​​the contact hole is the connecting electrode 80, thereby ensuring the electrical connection between the first electrode and the connecting electrode.

[0165] In an exemplary embodiment, the ratio of L4 to L3 is less than or equal to 4 and greater than or equal to 1.1. For example, the ratio of L4 to L3 is less than or equal to 2 and greater than or equal to 1.1, thereby ensuring electrical connection between the first electrode and the connection electrode.

[0166] In an exemplary embodiment, L3 is greater than or equal to 3.5 micrometers. For example, L3 is greater than or equal to 5 micrometers and less than or equal to 7.5 micrometers, thereby ensuring electrical connection between the first electrode and the connection electrode.

[0167] In an exemplary embodiment, L4 is greater than or equal to 4.5 micrometers. For example, L3 is greater than or equal to 8 micrometers and less than or equal to 10 micrometers, thereby ensuring electrical connection between the first electrode and the connection electrode.

[0168] Figure 15 is a schematic diagram of the cross-sectional structure of a display device according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the structure of the display device according to this exemplary embodiment is substantially the same as that of the aforementioned embodiment in a plane perpendicular to the display device, except that, as shown in Figure 15 , a first spacer layer 410 is provided on the side of the third insulating layer 23 of the array substrate 100 of the display device according to this embodiment, which is close to the color filter substrate 200. The color filter substrate 200 may include a second substrate 201 and a black matrix 202 provided on the side of the second substrate 201 close to the array substrate 100. A second spacer layer 420 is provided on the side of the black matrix 202 of the color filter substrate 200 close to the array substrate 100, and the second spacer layer 420 may be in direct contact with the black matrix 202. The first spacer layer 410 of the array substrate 100 is connected to the second spacer layer 420 of the color filter substrate 200.

[0169] In an exemplary embodiment, the cross-section of the first spacer layer 410 in a direction perpendicular to the first substrate includes a regular trapezoidal shape, and the cross-section of the second spacer layer 420 in a direction perpendicular to the first substrate includes an inverted trapezoidal shape.

[0170] An embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned array substrates.

[0171] The present disclosure also provides a method for preparing an array substrate, including:

[0172] A plurality of first wirings and a plurality of second wirings are formed on a substrate, wherein the first wirings extend along a first direction, and the second wirings extend along a second direction, the first wirings and the second wirings intersect with each other to define a plurality of sub-pixels arranged in an array, each of the sub-pixels comprising at least one transistor, and the first direction and the second direction intersect with each other;

[0173] A color filter layer is formed on one side of the transistor, wherein the color filter layer includes a color filter pattern corresponding to the sub-pixel, and an orthographic projection of the color filter pattern on the substrate covers an orthographic projection of the transistor on the substrate.

[0174] The present disclosure further provides a display device including the aforementioned array substrate. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0175] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. An array substrate, comprising: a substrate; a plurality of first wirings and a plurality of second wirings disposed on one side of the substrate, the first wirings extending along a first direction, the second wirings extending along a second direction, the first wirings and the second wirings intersecting each other to define a plurality of sub-pixels arranged in an array, each sub-pixel including at least one transistor, and the first direction and the second direction intersecting each other; a color filter layer disposed on one side of the transistor; the color filter layer includes color filter patterns corresponding to the sub-pixels, and a positive projection of the color filter patterns on the substrate covers a positive projection of the transistor on the substrate.

2. The array substrate according to claim 1, wherein, Along the first direction, a part of a positive projection of the color filter pattern corresponding to one of the adjacent sub-pixels falls within another sub-pixel.

3. The array substrate according to claim 2, wherein, The second wirings between the adjacent sub-pixels all overlap with positive projections of the color filter patterns of the adjacent two sub-pixels on the substrate.

4. The array substrate according to claim 3, wherein, A center line of the second wiring overlaps with a positive projection of an overlapping boundary of the color filter patterns of the adjacent two sub-pixels on the substrate.

5. The array substrate according to claim 3, wherein, A ratio of a distance in the first direction between a center line of the second wiring perpendicular to the substrate and the overlapping boundary of the color filter patterns of the adjacent two sub-pixels to a length of the second wiring in the first direction is greater than 0 and less than or equal to 0.

33.

6. The array substrate according to claim 2, wherein, A bump is disposed on at least one side in the first direction of the color filter pattern corresponding to one of the adjacent sub-pixels, and a positive projection of the bump on the substrate is located in a positive projection of another sub-pixel among the adjacent sub-pixels on the substrate.

7. The array substrate according to claim 6, wherein, The shape of the bump includes a trapezoid.

8. The array substrate according to any one of claims 1 to 7, wherein The color filter layer is disposed on a side of the transistor close to the substrate; or, the color filter layer is disposed on a side of the transistor away from the substrate.

9. The array substrate according to any one of claims 1 to 7, each sub-pixel further includes a connection electrode connected to the at least one transistor, a first electrode disposed on a side of the connection electrode away from the substrate, and a contact hole exposing at least a part of the connection electrode, the first electrode being connected to the connection electrode through the contact hole; the color filter layer is disposed between the first electrode and the connection electrode, the color filter pattern includes a hollowed-out area, and a positive projection of the contact hole on the substrate is located in a positive projection of the hollowed-out area on the substrate.

10. The array substrate according to claim 9, wherein, The hollowed-out area of the color filter pattern corresponding to one of the adjacent sub-pixels is connected to the color filter pattern corresponding to another sub-pixel.

11. The array substrate according to claim 10, wherein, A bump is disposed on at least one side in the first direction of the color filter pattern corresponding to one of the adjacent sub-pixels, and the bump extends into the hollowed-out area of the color filter pattern corresponding to another sub-pixel.

12. The array substrate according to claim 11, wherein, The contact hole of one of the adjacent sub-pixels has a first side and a second side. The first side is adjacent to the bump of the color filter pattern corresponding to the other sub-pixel, and the second side is adjacent to the other side of the hollowed-out area. The distance between the first side and the edge of the bump in the first direction is L1, and the minimum vertical distance between the second side and the other side of the hollowed-out area is L2. L1 is greater than or equal to L2.

13. The array substrate according to claim 12, wherein, The ratio of L1 to L2 is less than or equal to 2 and greater than or equal to 1.

14. The array substrate according to claim 9 further includes a planarization layer disposed on the side of the color filter layer close to the first electrode and an insulating layer disposed on the side of the planarization layer close to the first electrode. The contact hole at least includes a first via hole disposed in the planarization layer and a second via hole disposed in the insulating layer. The orthographic projection of the first via hole on the substrate is located within the orthographic projection of the second via hole on the substrate, and the orthographic projection of the second via hole on the substrate is located within the orthographic projection of the connection electrode on the substrate.

15. The array substrate according to claim 14, wherein, The minimum vertical distance between the edge of the orthographic projection of the first via hole on the substrate and the edge of the orthographic projection of the second via hole on the substrate is L3, and the minimum vertical distance between the edge of the orthographic projection of the first via hole on the substrate and the edge of the orthographic projection of the connection electrode on the substrate is L4. L4 is greater than L3.

16. The array substrate according to claim 15, wherein, The ratio of L4 to L3 is less than or equal to 2 and greater than or equal to 1.

1.

17. The array substrate according to claim 9 further includes a second electrode disposed on the side of the color filter layer close to the first electrode and an insulating layer disposed on the side of the second electrode close to the first electrode. The first electrode is in direct contact with the insulating layer.

18. The array substrate according to claim 17 further includes a spacer layer disposed on the side of the insulating layer away from the substrate. The spacer layer is in direct contact with the insulating layer, and the orthographic projection of the first electrode on the substrate does not overlap with the orthographic projection of the spacer layer on the substrate.

19. For the array substrate according to claim 18, the cross-section of the spacer layer in the direction perpendicular to the substrate includes at least one of a rectangle, a regular trapezoid, and an inverted trapezoid.

20. The array substrate according to any one of claims 1 to 7, wherein, The transistor includes a gate disposed on the substrate, a gate insulating layer disposed on the side of the gate away from the substrate, an active layer disposed on the side of the gate insulating layer away from the substrate, a first pole and a second pole disposed on the side of the active layer away from the substrate. The first pole and the second pole are connected through the active layer.

21. A display device includes the array substrate according to any one of claims 1 to 20.

22. The display device according to claim 21 further includes a color filter substrate disposed opposite to the array substrate. The color filter substrate includes a black matrix, and the black matrix does not overlap with the orthographic projection of at least part of the second trace on the substrate.

23. The display device according to claim 22, further comprising a first spacer layer, one side of the first spacer layer close to the array substrate is connected to the array substrate, and one side of the first spacer layer close to the color filter substrate is connected to the color filter substrate.

24. The display device according to claim 22, further comprising a first spacer layer and a second spacer layer. One side of the first spacer layer close to the array substrate is connected to the array substrate. The side of the first spacer layer away from the array substrate is connected to the second spacer layer. The side of the second spacer layer away from the array substrate is connected to the color filter substrate. The cross-section of the first spacer layer in the direction perpendicular to the substrate includes a regular trapezoid, and the cross-section of the second spacer layer in the direction perpendicular to the substrate includes an inverted trapezoid.

25. A method for manufacturing an array substrate, comprising: forming a plurality of first wirings and a plurality of second wirings on a substrate, the first wirings extending along a first direction, the second wirings extending along a second direction, the first wirings and the second wirings intersecting each other to define a plurality of sub-pixels arranged in an array, each sub-pixel including at least one transistor, and the first direction and the second direction intersecting each other; forming a color filter layer on one side of the transistor, the color filter layer including a color filter pattern corresponding to the sub-pixels, and the orthographic projection of the color filter pattern on the substrate covering the orthographic projection of the transistor on the substrate.

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