Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a first base, a first electrode layer, a second electrode layer, a first insulating layer, a second insulating layer and sub-pixels. The sub-pixels comprise: a first electrode, which is arranged in the first electrode layer and comprises a first connecting portion; a first adapter portion, which is arranged in the second electrode layer; and a first hollowed-out portion. The first hollowed-out portion comprises: a first via hole, which is provided in the first insulating layer and by means of which the first connecting portion is exposed; a second via hole, which is provided in the second insulating layer and is in communication with the first via hole; a first insulating portion, which is arranged in the first insulating layer and a side wall of which is formed as a first inner wall of the first via hole; and a filling portion, which is arranged on the side of the first insulating portion away from the first base, wherein the first adapter portion is, in the first via hole, connected to the first connecting portion, and the first adapter portion, from the first inner wall, passes through the filling portion and continuously extends into the second via hole.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] With the development and advancement of the display panel industry, market requirements for display panel functionality and quality are becoming increasingly stringent. Based on their structural principles, the mainstream display modes of existing LCD panels include: Vertical Alignment (VA), Twisted Nematic (TN), and Advanced Super Dimension Switch (ADS) display panels. Advanced Super Dimension Switch (ADS) display panels offer advantages such as wide viewing angles, high aperture ratios, low color shading, and fast response times, and are being adopted in an increasing number of products.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] According to a first aspect of the present disclosure, there is provided a display substrate, comprising:

[0006] first base;

[0007] a first electrode layer disposed on the first substrate;

[0008] a second electrode layer disposed on a side of the first electrode layer facing away from the first substrate;

[0009] a first insulating layer and a second insulating layer disposed between the first electrode layer and the second electrode layer, wherein the second insulating layer is located on a side of the first insulating layer facing away from the first substrate; and

[0010] A sub-pixel disposed on the first substrate, wherein the sub-pixel comprises:

[0011] a first electrode provided in the first electrode layer, the first electrode including a first connecting portion;

[0012] a first transition portion provided in the second electrode layer; and

[0013] The first empty space, wherein the first empty space comprises:

[0014] a first via hole provided in the first insulating layer, wherein the first via hole exposes the first connecting portion;

[0015] a second via hole provided in the second insulating layer, the second via hole being connected to the first via hole;

[0016] a first insulating portion provided in the first insulating layer, wherein a sidewall of the first insulating portion is formed as a first inner wall of the first via hole; and

[0017] a filling portion provided on a side of the first insulating portion facing away from the first substrate;

[0018] Among them, the first transition part includes a first transition sub-part and a second transition sub-part connected to the first transition sub-part, the first transition sub-part is connected to the first connecting part in the first via, and the second transition sub-part extends continuously from the first inner wall through the filling part to the second via.

[0019] According to an embodiment of the present disclosure, the display substrate further includes:

[0020] a metal conductive layer disposed between the first insulating layer and the second insulating layer; and

[0021] a first signal line electrically connected to the sub-pixel;

[0022] The sub-pixel further includes:

[0023] a second transfer portion located in the metal conductive layer, the second transfer portion being electrically connected to the first signal line;

[0024] The second via hole includes a first half hole and a second half hole arranged in a first direction and opposite to each other, the first half hole is connected to the first via hole, and the second half hole exposes the second connecting portion;

[0025] The second adapter portion extends continuously into the second half hole through the filling portion and is connected to the exposed second adapter portion.

[0026] According to an embodiment of the present disclosure, the orthographic projection of the connection area of ​​the first half hole and the second half hole on the first substrate defines a first pattern, and the orthographic projection of the filling portion on the first substrate is located within the orthographic projection of the second via hole on the first substrate and overlaps with the first pattern.

[0027] According to an embodiment of the present disclosure, the first insulating portion includes a first sub-portion, the first sub-portion extends along a second direction, and the second direction intersects the first direction;

[0028] The connection area between the first half hole and the second half hole exposes the first sub-portion, the second transition portion covers a portion of the first sub-portion, and the filling portion at least partially covers a portion of the first sub-portion not covered by the second transition portion.

[0029] According to an embodiment of the present disclosure, the side wall of the first sub-portion, the side wall of the filling portion, and the side wall of the second transition portion form a first step surface.

[0030] According to an embodiment of the present disclosure, the first half hole includes a second inner wall, and the second half hole includes a third inner wall;

[0031] In a connection area between the first half hole and the second half hole, the second inner wall is located on a side of the third inner wall close to a first reference line and has a first spacing therebetween, wherein the first reference line includes: a straight line passing through the center of the first half hole and the center of the second half hole;

[0032] The first spacing is less than or equal to the maximum thickness of the first transition portion.

[0033] According to an embodiment of the present disclosure, the filling portion is located in the second insulating layer, and the filling portion includes a first end and a second end oppositely arranged along the second direction, and the first end and the second end are respectively in contact with the inner wall of the second via hole.

[0034] According to an embodiment of the present disclosure, the display substrate further includes:

[0035] a metal conductive layer disposed between the first insulating layer and the second insulating layer; and

[0036] a first signal line electrically connected to the sub-pixel;

[0037] The sub-pixel further includes:

[0038] a second transfer portion located in the metal conductive layer, the second transfer portion being electrically connected to the first signal line;

[0039] The first floor also includes:

[0040] a third via hole penetrating the second insulating layer, the third via hole being spaced apart from the second via hole, and the third via hole exposing the second transition portion;

[0041] The first transfer portion further includes a third transfer sub-portion and a fourth transfer sub-portion connected to the third transfer sub-portion, the third transfer sub-portion being located on a side of the second insulating layer facing away from the first substrate, and the fourth transfer sub-portion being connected to the exposed second transfer portion at the bottom of the third via hole;

[0042] The second transfer sub-portion extends continuously through the filling portion to the inner wall of the second via hole and is connected to the third transfer sub-portion.

[0043] According to an embodiment of the present disclosure, an orthographic projection of the first via hole on the first substrate defines a third pattern, an orthographic projection of the second via hole on the first substrate defines a fourth pattern, an orthographic projection of the third via hole on the first substrate defines a fifth pattern, and an orthographic projection of the filling portion on the first substrate defines a sixth pattern;

[0044] The sixth pattern at least partially surrounds the third pattern, the fourth pattern covers the sixth pattern, and the fifth pattern at least partially surrounds the fourth pattern.

[0045] According to an embodiment of the present disclosure, the fifth pattern includes a continuous square ring pattern.

[0046] According to an embodiment of the present disclosure, the sidewall of the second transition portion is covered by the second insulating layer;

[0047] The sidewall of the first insulating portion, the sidewall of the filling portion, and the sidewall of the second insulating portion form a continuous first inclined surface, and the second transition sub-portion at least partially covers the first inclined surface; or

[0048] The first insulating portion, the filling portion, and the second insulating portion form a second step surface, and the second transfer sub-portion at least partially covers the second step surface.

[0049] According to an embodiment of the present disclosure, the display substrate further includes:

[0050] A first semiconductor layer is provided between the metal conductive layer and the second electrode layer, the filling portion is located in the first semiconductor layer, a portion of the filling portion is connected to the second transition sub-portion, and another portion is connected to the second transition portion.

[0051] According to an embodiment of the present disclosure, the display substrate further includes a gate metal layer disposed between the first electrode layer and the first insulating layer;

[0052] The sub-pixel further includes:

[0053] a third transition portion provided in the gate metal layer, the third transition portion being located in the first via hole and covering the first connection portion;

[0054] The first adapter portion is connected to the first connecting portion through the third adapter portion.

[0055] According to an embodiment of the present disclosure, the orthographic projection of the first insulating portion on the first substrate overlaps with the orthographic projection of the third transition portion on the first substrate, and in this overlapping area, the orthographic projection of the filling portion on the first substrate overlaps with the orthographic projection of the third transition portion on the first substrate.

[0056] According to an embodiment of the present disclosure, the orthographic projection of the first insulating portion on the first substrate overlaps with the orthographic projection of the third transition portion on the first substrate, and the orthographic projection of the filling portion on the first substrate does not overlap with the orthographic projection of the third transition portion on the first substrate.

[0057] According to an embodiment of the present disclosure, the orthographic projection of the second transition portion on the first substrate defines a seventh pattern, the seventh pattern has a first size in the first direction, the seventh pattern has a second size in the second direction, and the first direction and the second direction intersect;

[0058] The ratio of the first size to the second size is greater than or equal to 1:2.5.

[0059] According to an embodiment of the present disclosure, an etching rate of the filling portion is lower than an etching rate of the first insulating portion.

[0060] According to a second aspect of the present disclosure, a display device is provided, comprising the above-mentioned display substrate.

[0061] According to a third aspect of the present disclosure, a method for preparing a display substrate is provided, wherein the display substrate includes the above-mentioned display substrate, and the preparation method includes:

[0062] providing a first substrate;

[0063] forming a first insulating material on the first substrate;

[0064] forming a second insulating material on a side of the first insulating material facing away from the first substrate;

[0065] patterning the first insulating material and the second insulating material to form a first insulating layer having the first via hole, a second insulating layer having the second via hole, and the filling portion;

[0066] Wherein, the filling part is prepared by the following steps:

[0067] forming a first sacrificial material on a side of the second insulating material facing away from the first substrate, wherein the first sacrificial material includes a first sacrificial portion, and the first sacrificial portion covers a portion of the second insulating material;

[0068] The second insulating material and the first sacrificial material are etched, and the first sacrificial portion is configured such that during etching, the second insulating material covered by the first sacrificial portion is etched first, so that after etching is completed, a portion of the second insulating material can be retained to form the filling portion.

[0069] According to an embodiment of the present disclosure, the preparation method further includes:

[0070] Before forming the second insulating material, forming a metal conductive material on a side of the first insulating material facing away from the first substrate;

[0071] patterning the metal conductive material to form a second transfer portion;

[0072] The forming of a first sacrificial material on a side of the second insulating material facing away from the first substrate comprises:

[0073] Using a first mask to pattern the first sacrificial material, wherein the first mask includes a third half hole and a fourth half hole arranged opposite to each other along a first direction, and a first light shielding portion located between the third half hole and the fourth half hole;

[0074] The third half hole is configured such that: the first sacrificial material directly opposite to the third half hole is removed to form a fifth half hole, the first sacrificial material directly opposite to the fourth half hole is removed to form a sixth half hole, and the first sacrificial material directly opposite to the first light shielding portion is retained to form the first sacrificial portion;

[0075] The fifth half hole is configured such that, when etching the second insulating material, the second insulating material directly opposite the fifth half hole is removed to form a first half hole, and the first insulating material directly opposite the fifth half hole is removed to form a first via hole;

[0076] The sixth half hole is configured such that when the second insulating material is etched, the second insulating material opposite to the sixth half hole is removed to form a second half hole, where the second half hole exposes the second transition portion.

[0077] According to an embodiment of the present disclosure, the third half hole and the fourth half hole have the same size; or,

[0078] The third half hole includes a fourth inner wall, and the fourth half hole includes a fifth inner wall. In the connection area between the third half hole and the fourth half hole, the fifth inner wall is located on a side of the fourth inner wall close to a second reference line and has a second spacing, wherein the second reference line includes: a straight line passing through the center of the third half hole and the center of the fourth half hole.

[0079] According to an embodiment of the present disclosure, the first light shielding portion includes a strip structure, and the width of the first light shielding portion is greater than or equal to the average value of the first etching offset and the second etching offset;

[0080] The first etching offset includes: a deviation between an expected aperture and an actual aperture when forming the first via hole and the first half hole; the second etching offset includes: a deviation between an expected aperture and an actual aperture when forming the second half hole.

[0081] According to a fourth aspect of the present disclosure, a method for preparing a display substrate is provided, wherein the display substrate includes the above-mentioned display substrate, and the preparation method includes:

[0082] providing a first substrate;

[0083] forming a first insulating material on the first substrate;

[0084] Using a second mask, forming a first semiconductor material on a side of the first insulating material facing away from the first substrate, wherein the first semiconductor material includes a first covering portion, and the first covering portion covers a portion of the first insulating material;

[0085] forming a second insulating material on a side of the first semiconductor material facing away from the first substrate;

[0086] patterning the first insulating material, the second insulating material, and the first semiconductor material to form a first insulating layer having the first via hole, a second insulating layer having the second via hole, and the filling portion;

[0087] Wherein, the filling part is prepared by the following steps:

[0088] Using a third mask, forming a first barrier material on a side of the second insulating material facing away from the first substrate, wherein the first barrier material exposes a portion of the second insulating material;

[0089] Using the first barrier material as a fourth mask, etching the first insulating material, the first semiconductor material, and the second insulating material, wherein the first barrier material is configured to remove portions of the first insulating material, the first semiconductor material, and the second insulating material that are exposed by the first barrier material;

[0090] The first covering portion is configured such that when the first insulating material, the first semiconductor material and the second insulating material are etched, the first insulating material covered by the first covering portion is etched first, and after the etching is completed, the portion of the first covering portion not exposed by the first barrier material is retained to form the filling portion.

[0091] According to an embodiment of the present disclosure, the step of using a second mask to form a first semiconductor material on a side of the first insulating material facing away from the first substrate includes:

[0092] forming a second semiconductor material on a side of the first insulating material facing away from the first substrate;

[0093] forming a metal conductive material on a side of the second semiconductor material facing away from the first substrate;

[0094] patterning the second semiconductor material and the metal conductive material using the second mask, wherein the second mask includes a first area and a second area surrounding the first area;

[0095] The first region is configured such that, when the second semiconductor material and the metal conductive material are patterned, the metal conductive material directly facing the first region is removed, and the second semiconductor material directly facing the first region is retained, thereby forming the first covering portion;

[0096] The second region is configured as follows: when the second semiconductor material and the metal conductive material are composed, the metal conductive material directly opposite the second region is retained to form a second transition portion, and the second semiconductor material directly opposite the second region is retained to electrically connect the second transition portion to the first covering portion.

[0097] According to an embodiment of the present disclosure, the first area includes a circle or a square.

[0098] According to an embodiment of the present disclosure, the third mask includes a third region and a fourth region surrounding the third region;

[0099] The third region is configured to: form a fourth via hole on the first barrier material, wherein the fourth via hole exposes a first portion of the second insulating material;

[0100] The fourth region is configured to: form a fifth via hole on the first barrier material, the fifth via hole at least partially surrounding the fourth via hole, and the fifth via hole exposing the second portion of the second insulating material;

[0101] The etching of the first insulating material, the first semiconductor material and the second insulating material using the first barrier material as a fourth mask comprises:

[0102] The first portion is removed to form the second via hole, and the second portion is removed to form the third via hole, wherein the third via hole exposes the second transfer portion.

[0103] According to an embodiment of the present disclosure, the fourth area includes a circular ring or a square ring.

[0104] According to an embodiment of the present disclosure, the preparation method further includes:

[0105] Before forming the first insulating material, forming a first electrode material on the first substrate;

[0106] forming a gate metal material on a side of the first electrode material facing away from the first substrate;

[0107] patterning the first electrode material and the gate metal material using a fifth mask, wherein the fifth mask includes a fifth region and a sixth region surrounding the fifth region;

[0108] The fifth region is configured such that, when patterning the first electrode material and the gate metal material, the first electrode material directly opposite the fifth region is retained to form a first connecting portion, and the gate metal material directly opposite the fifth region is retained to form a third transition portion on the first connecting portion.

[0109] The sixth region is configured such that, when the first electrode material and the gate metal material are patterned, the first electrode material facing the sixth region is retained, and the gate metal material facing the sixth region is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0110] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0111] FIG1 schematically shows a diagram of a display panel in a pair of ratios;

[0112] FIG2 schematically shows a partial cross-sectional view of a pair of proportional sub-pixels;

[0113] FIG3 schematically shows a schematic diagram of a pair of ratios in which the first electrode is a pixel electrode and is connected to a data line;

[0114] FIG4 schematically shows a schematic diagram of a first electrode being switched through a switching via in a pair of ratios;

[0115] FIG5 schematically shows a cross-sectional view of FIG4 along the section line AA′;

[0116] FIG6 schematically shows a plan view of a display substrate according to an embodiment of the present disclosure;

[0117] FIG7A schematically shows one of the schematic diagrams of the first electrode being switched through the switching via in an embodiment of the present disclosure;

[0118] FIG7B schematically shows a plan view of a second via hole and a filling portion in an embodiment of the present disclosure;

[0119] 8A to 8C schematically illustrate cross-sectional views of FIG. 7A along section line BB′;

[0120] FIG9 schematically shows a schematic diagram of preparing a filling portion in an embodiment of the present disclosure;

[0121] FIG10 schematically shows a flow chart of a method for preparing a display substrate according to an embodiment of the present disclosure;

[0122] FIG11 schematically shows a schematic diagram of a first mask in an embodiment of the present disclosure;

[0123] FIG12 schematically shows a schematic diagram of a second via hole in an embodiment of the present disclosure;

[0124] FIG13 schematically shows a second schematic diagram of the first electrode being switched through the switching via in an embodiment of the present disclosure;

[0125] 14A to 14C schematically illustrate cross-sectional views of FIG. 13 along section line CC′;

[0126] FIG15 schematically shows a schematic diagram of a third via hole in an embodiment of the present disclosure;

[0127] FIG16 schematically shows one of the schematic diagrams of the third adapter in the embodiment of the present disclosure;

[0128] FIG17 schematically shows a second schematic diagram of the third adapter in an embodiment of the present disclosure;

[0129] FIG18 schematically shows a second flow chart of the method for preparing a display substrate according to an embodiment of the present disclosure;

[0130] 19A to 19C schematically illustrate a process for preparing a display substrate according to an embodiment of the present disclosure;

[0131] 20A to 20E schematically illustrate schematic diagrams of a mask in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0132] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0133] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0134] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0135] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0136] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0137] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0138] It should be noted that, in this article, the term "same layer" refers to a layer structure formed by patterning a film layer for forming a specific pattern using the same film-forming process and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. Multiple elements, components, structures, and / or parts of the "same layer and the same material" are composed of the same material and are formed through the same single patterning process. Generally, multiple elements, components, structures, and / or parts of the "same layer and the same material" have approximately the same thickness.

[0139] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display panel, that is, the dimension along the light emitting direction of the display panel, or the dimension along the normal direction of the display device.

[0140] FIG1 schematically shows a diagram of a display panel in a pair of scales.

[0141] Referring to FIG1 , a comparative example shows a display panel, which may be a liquid crystal display panel, specifically an Advanced Super Dimension Switch (ADS) liquid crystal display panel. For example, the display panel in this comparative example includes a base substrate 110, a plurality of sub-pixels PX10 disposed on the base substrate 110, and a data line DL10 and a gate line GL10 connected to each sub-pixel PX10.

[0142] FIG2 schematically shows a partial cross-sectional view of a pair of scaled sub-pixels.

[0143] Referring to Figure 2 , subpixel PX10 includes a first electrode D11, a second electrode D12, and a liquid crystal layer LC10 disposed between the first and second electrodes D11 and D12. One of the first and second electrodes D11 and D12 is a pixel electrode, and the other is a common electrode. The first and second electrodes D11 and D12 apply a first electric field in response to a drive signal, causing liquid crystal molecules LC11 in the liquid crystal layer LC10 to deflect in response to the first electric field, thereby achieving a display effect.

[0144] In this example, the first electrode D11 is connected to the corresponding signal line. For example, FIG3 schematically illustrates a schematic diagram of a pair of proportions in which the first electrode is a pixel electrode and is connected to a data line. Referring to FIG3 , the subpixel PX10 further includes a first transistor T10. If the first electrode D11 is a pixel electrode, the first electrode D11 is first connected to the first transistor T10, and then connected to the data line DL10 through the first transistor T10. Thus, the first transistor T10 can control the connection between the first electrode D11 and the data line DL10. When the first electrode D11 and the data line DL10 are conductive, the data voltage signal on the data line DL10 is transmitted to the first electrode D11. This process is also referred to as charging the subpixel PX. If the first electrode D11 is a common electrode, the first electrode D11 can be directly connected to the common signal line, thereby providing a constant common voltage signal to the first electrode D11.

[0145] FIG4 schematically shows a schematic diagram of a first electrode being switched through a switching via hole in a pair of ratios, and FIG5 schematically shows a cross-sectional view along the section line AA′ of FIG4 .

[0146] 4 and 5 , in this example, no matter whether the first electrode D11 is connected to the first transistor T10 or the common signal line, both connections need to be made through the switching via ZJV10 .

[0147] In this comparative example, the display panel also includes: a first electrode layer 120, a gate metal layer (not shown in the figure), a gate insulating layer 130, a semiconductor layer 140, a metal conductive layer 150, a passivation layer 160 and a second electrode layer 170 arranged on the base substrate 110, wherein the first electrode layer 120, the gate metal layer 130, the gate insulating layer 130, the metal conductive layer 150, the passivation layer 160 and the second electrode layer 170 are arranged in sequence in a direction away from the base substrate 110, and the first electrode D11 is arranged in the first electrode layer 120.

[0148] Taking the connection between the first electrode D11 and the first transistor T10 as an example, each sub-pixel PX10 also includes a first transfer portion ZJ11 disposed in the second electrode layer 170 and a second transfer portion ZJ12 disposed in the metal conductive layer 150. The second transfer portion ZJ12 is connected to the data line DL10. For example, the second transfer portion ZJ12 is connected to the drain of the first transistor T10, and the source of the first transistor T10 is connected to the data line DL10. When the first transistor T10 is turned on, the source and drain of the first transistor T10 are conductive, and the second transfer portion ZJ12 is conductive to the data line DL10. Each sub-pixel PX10 also includes a first transfer hole V11 that penetrates the gate insulating layer 130 and the passivation layer 160, and a second transfer hole V12 that penetrates the passivation layer 160. The first transfer hole V11 exposes the first electrode D11, and the second transfer hole V12 exposes the second transfer portion ZJ12. One end of the first transition portion ZJ11 connects to the first electrode D11 at the bottom of the first transition hole V11, and the other end rises upward and connects to the second transition portion ZJ12 in the second transition hole V12. However, the inventors discovered that during the formation of the first transition portion ZJ11, it is prone to breakage.

[0149] Specifically, in this comparative example, the first transfer hole V11 and the second transfer hole V12 are two interconnected half-holes. A dry etching process is used to form the first transfer hole V11 and the second transfer hole V12. The dry etching process is isotropic, specifically, the dry etching gas etches the gate insulating layer 130 not only vertically but also horizontally. This phenomenon is also known as the drilling phenomenon. The drilling phenomenon can cause over-etching of the gate insulating layer 130, resulting in an undercut phenomenon DQ10. When forming the first transfer portion ZJ11, the undercut phenomenon DQ10 causes a discontinuous climbing path of the first transfer portion ZJ11, resulting in a break in the first transfer portion ZJ11, as shown in FIG5 . The break in the first transfer portion ZJ11 can result in a poor connection between the first electrode D11 and the second transfer portion ZJ12. If the first electrode D11 is a pixel electrode, this poor connection can lead to charging failure of the subpixel PX10. If the first electrode D11 is a common electrode, the poor connection may cause the sub-pixel PX10 to flicker.

[0150] In view of this, an embodiment of the present disclosure provides a display substrate, which includes: a first substrate, a first electrode layer arranged on the first substrate, a second electrode layer arranged on the side of the first electrode layer away from the first substrate, and a first insulating layer and a second insulating layer arranged between the first electrode layer and the second electrode layer, and the second insulating layer is located on the side of the first insulating layer away from the first substrate.

[0151] The display substrate further includes a subpixel disposed on the first substrate, wherein the subpixel includes a first electrode disposed in the first electrode layer and a first transition portion disposed in the second electrode layer. The first electrode includes a first connecting portion. The subpixel further includes a first hollow portion, which includes a first via hole disposed in the first insulating layer, a second via hole disposed in the second insulating layer, a first insulating portion disposed in the first insulating layer, and a filling portion disposed on a side of the first insulating portion facing away from the first substrate.

[0152] The first via exposes the first connecting portion, the second via communicates with the first via, and the sidewall of the first insulating portion forms the first inner wall of the first via. The first transition portion includes a first transition sub-portion and a second transition sub-portion connected to the first transition sub-portion. The first transition sub-portion connects to the first connecting portion in the first via, and the second transition sub-portion extends continuously from the first inner wall, through the filling portion, and into the second via.

[0153] In an embodiment of the present disclosure, the first via and the second via are connected, so that they can be formed simultaneously in a single etching step. In addition, when forming the first via and the second via, the filling portion will protect the material used to form the first insulating portion to reduce the etching intensity of this portion of the material, thereby reducing the drilling phenomenon. In addition, as long as it is ensured that the filling portion can be formed, the portion of the first insulating material used to form the first via will not be over-etched, and the undercut phenomenon will not occur. In this way, in the first via and the second via that are finally formed, a more continuous and gentle climbing path can be formed for the first transition portion, which is beneficial to reduce the risk of fracture of the first transition portion, and further improve the problems such as poor overlap caused thereby.

[0154] The display substrate in the embodiment of the present disclosure will be described in detail below with reference to FIG. 6 to FIG. 20E .

[0155] FIG6 schematically shows a plan view of a display substrate in an embodiment of the present disclosure.

[0156] 6 , the display substrate in the embodiment of the present disclosure includes: a display area AA and a peripheral area NA located on at least one side of the display area AA. The display area AA can have various shapes. For example, the display area AA can be provided in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or an ellipse with curved edges, and a semicircle or a semi-ellipse with straight and curved edges. In the embodiment of the present disclosure, the display area AA is provided as an area having a quadrilateral shape with straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0157] The display substrate may further include a first substrate 210 and a plurality of pixel units P disposed on the first substrate 210 and located in the display area AA. The plurality of pixel units P may be arranged in an array along a third direction Z1 and a fourth direction Z2. The third direction Z1 intersects the fourth direction Z2. For example, the third direction Z1 may include the vertical direction in FIG. 6 , and the fourth direction Z2 may include the horizontal direction in FIG. 6 . That is, the third direction Z1 and the fourth direction Z2 are perpendicular to each other.

[0158] Each pixel unit P may include multiple sub-pixels PX. For example, the pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. Exemplarily, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0159] The plurality of sub-pixels PX may be arranged in an array along the third direction Z1 and the fourth direction Z2, but the embodiments of the present disclosure are not limited thereto. For ease of description, the embodiments of the present disclosure refer to the plurality of sub-pixels PX arranged along the third direction Z1 as a column of sub-pixels PX, and the plurality of sub-pixels PX arranged along the fourth direction Z2 as a row of sub-pixels PX.

[0160] The display substrate further includes a plurality of gate lines GL and a plurality of data lines DL disposed on the first substrate 210 and located at least in the display area AA. The plurality of data lines DL extend along a third direction Z1, and the plurality of gate lines GL extend along a fourth direction Z2. Each subpixel PX is connected to a corresponding data line DL and a corresponding gate line GL. For example, subpixels PX in the same row are connected to the same gate line GL, while subpixels PX in different rows are connected to different gate lines GL. Subpixels PX in the same column are connected to the same data line DL, while subpixels PX in different columns are connected to different data lines DL.

[0161] The peripheral area NA may be disposed on at least one side of the display area AA. For example, the peripheral area NA may surround the display area AA. In an embodiment of the present disclosure, the peripheral area NA may include a vertical portion extending in the third direction Z1 and a horizontal portion extending in the fourth direction Z2.

[0162] The display substrate may further include a gate drive circuit 220 and a display binding end 230 arranged on the first substrate 210 and located in the peripheral area NA. For example, the gate drive circuit 220 may be located on at least one side of the display area AA. In the embodiment shown in Figure 6, the gate drive circuit 220 is located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides may refer to: "the left and right sides of the display substrate (screen) viewed by the human eye when displaying". For example, the display binding end 230 may be located on at least one side of the display area AA. In the embodiment shown in Figure 6, the display binding end 230 is located on the lower side of the display area AA. It should be noted that the lower side may refer to: "the lower side of the display substrate (screen) viewed by the human eye when displaying". The display binding end 230 is used to bind to the display driver component. For example, the display driver component may include devices such as a flexible circuit board and a display driver chip. The display binding end 230 can be connected to devices such as a printed circuit board located on the back side of the display substrate through the display driver component. The display binding end 230 is also connected to the signal line in the display area AA (such as the data line DL mentioned above), and thus the electrical signal on the printed circuit board can be transmitted to the corresponding signal line in the display area AA through the display binding end 230, thereby realizing the display function.

[0163] It should be noted that although Figure 6 shows that the gate driving circuit 220 is located on the left and right sides of the display area AA and the display binding terminal 230 is located on the lower side of the display area AA, the embodiments of the present disclosure are not limited to this. The gate driving circuit 220 and the display binding terminal 230 can be located at any suitable position in the peripheral area NA.

[0164] In an embodiment of the present disclosure, the gate driver circuit 220 can utilize GOA technology, also known as Gate Driver on Array (GOA). In GOA technology, the gate driver circuit 220 is directly disposed on the array substrate, replacing an external chip. Each GOA unit functions as a first-level shift register, with each shift register level connected to a gate line GL. Each level of shift register sequentially outputs scan signals in turn, achieving progressive scanning of the sub-pixels PX. In some embodiments, each shift register level can also be connected to multiple gate lines GL. This adapts to the development trend of high-resolution and narrow-frame display substrates.

[0165] Similar to the aforementioned comparative example, the subpixel PX in the embodiment of the present disclosure also includes a first transistor, a first electrode, and a second electrode. Accordingly, the first electrode is also connected to the corresponding device via a transfer via. However, the embodiment of the present disclosure differs from the aforementioned comparative example in that at least the transfer via is improved.

[0166] Figure 7A schematically illustrates one schematic diagram of a first electrode being connected via a transfer via in an embodiment of the present disclosure. Figure 7B schematically illustrates a plan view of a second via and a filling portion in an embodiment of the present disclosure. Figures 8A to 8C schematically illustrate a cross-sectional view of Figure 7A taken along line BB′. Figure 13 schematically illustrates another schematic diagram of a first electrode being connected via a transfer via in an embodiment of the present disclosure. Figures 14A to 14C schematically illustrate a cross-sectional view of Figure 13 taken along line CC′.

[0167] 7A to 8C and 13 to 14C, the display substrate in the embodiment of the present disclosure includes: a first electrode layer 220 arranged on a first substrate 210, a second electrode layer 230 arranged on the side of the first electrode layer 220 away from the first substrate 210, a first insulating layer 240 and a second insulating layer 250 arranged between the first electrode layer 220 and the second electrode layer 230, and the second insulating layer 250 is located on the side of the first insulating layer 240 away from the first substrate 210.

[0168] In an embodiment of the present disclosure, the materials of the first electrode layer 220 and the second electrode layer 230 may include a transparent conductive material. For example, the materials of the first electrode layer 220 and the second electrode layer 230 may include indium tin oxide (ITO).

[0169] The display substrate in the embodiment of the present disclosure may further include a gate metal layer for setting the gate line GL and a metal conductive layer 260 for setting the data line DL, etc., wherein the first insulating layer 240 may refer to a gate insulating layer arranged between the gate metal layer and the metal conductive layer 260, and the second insulating layer 250 may refer to a passivation layer arranged between the metal conductive layer 260 and the second electrode layer 230.

[0170] The sub-pixel PX10 includes a first electrode D21 disposed in the first electrode layer 220 and a first transition portion ZJ21 disposed in the second electrode layer 230 .

[0171] In the embodiment of the present disclosure, the first electrode D21 can be either a pixel electrode or a common electrode. For example, when the first electrode D21 is a pixel electrode, the common electrode can be located in the second electrode layer 230. When the first electrode D21 is a common electrode, the pixel electrode can be located in the second electrode layer 230. The specific method can be determined according to actual needs and is not limited in the embodiment of the present disclosure.

[0172] In the embodiment of the present disclosure, the first transition portion ZJ21 is connected between the first electrode D21 and the corresponding signal line, thereby forming a conductive path between the first electrode D21 and the corresponding signal line. For clarity, unless otherwise specified, the following description assumes that the first electrode D21 is a pixel electrode. In this embodiment, the signal line corresponding to the first electrode D21 is a data line DL.

[0173] Exemplarily, the sub-pixel PX10 further includes a first transistor, the first electrode D21 is connected to the first transition portion ZJ21, and the first transition portion ZJ21 is electrically connected to the data line DL through the first transistor.

[0174] Exemplarily, the first transistor includes a source, a drain, and a gate. At least one of the source and the drain is located in the metal conductive layer 260, and the gate is located in the gate metal layer. In the first transistor, the gate is connected to the gate line GL, one of the source and the drain (e.g., the source) is connected to the data line DL, and the other (e.g., the drain) is connected to the first transition portion ZJ21. Thus, the first transistor can be turned on or off in response to an electrical signal on the gate line GL. When the first transistor starts, the source and drain of the first transistor are turned on, and then a conductive path is formed between the data line DL and the first electrode D21.

[0175] In an embodiment of the present disclosure, the first electrode D21 and the first transition part ZJ21 are separated by the first insulating layer 240 and the second insulating layer 250, and the first floor space LK includes a plurality of vias formed on the first insulating layer 240 and the second insulating layer 250. The first transition part ZJ21 can contact the first electrode D21 through these vias, thereby realizing the connection between the two.

[0176] For example, the first electrode D21 includes a first connection portion D211, which may be a portion of the first electrode D21 for connecting to the first adapter ZJ21. Optionally, the subpixel PX10 includes an active display area for transmitting light and an inactive display area that at least partially surrounds the active display area. The first connection portion D211 is located in the inactive display area. For example, after the display substrate and the color filter substrate are assembled to form a display panel, the black matrix on the color filter substrate can shield the inactive display area, thereby preventing light reflection from components in the inactive display area and affecting the display effect.

[0177] The sub-pixel PX further includes a first hollow portion LK, which includes a first via hole V21 provided in the first insulating layer 240. Referring to FIG8A, the first via hole V21 exposes the first connection portion D211. Optionally, the first hollow portion LK is located in the ineffective display area.

[0178] The first hollow portion LK also includes: a second via V22 provided in the second insulating layer 250, the second via V22 being connected to the first via V21. Referring to FIG8A , the orthographic projection of the second via V22 on the first substrate 210 overlaps with the orthographic projection of the first via V21 on the first substrate 210, and in the overlapping area, the second via V22 is connected to the first via V21. Thus, the second via V22 can also expose the first connection portion D211. The first transition portion ZJ21 can be connected to the exposed first connection portion D211 at the bottom of the first via V21, and the first transition portion ZJ21 can also climb upward and connect to the second transition portion ZJ22, and then connect to the first transistor through the second transition portion ZJ22.

[0179] Specifically, the first hollow portion LK further includes: a first insulating portion 241 provided in the first insulating layer 240 and a filling portion TC provided on a side of the first insulating portion 241 away from the first substrate 210 .

[0180] The first insulating portion 241 may be a portion on the first insulating layer 240 for forming the first via hole V21. Referring to FIG8B , the first via hole V21 passes through the first insulating portion 241, and the sidewall of the first insulating portion 241 forms the first inner wall NB10 of the first via hole V21. In an embodiment of the present disclosure, the first via hole V21, the second via hole V22, and the filling portion TC may be formed simultaneously. For example, the first via hole V21, the second via hole V22, and the filling portion TC are formed based on the same mask and in the same patterning process. The patterning process includes an etching step, and the etching step may adopt a dry etching process, but this does not constitute a limitation to the embodiment of the present disclosure. The embodiment of the present disclosure may adopt any suitable etching process, such as a wet etching process. For clarity, unless otherwise specified, the etching step will be described below using the dry etching process as an example.

[0181] For example, the filling portion TC can be disposed in any film layer located on the side of the first insulating layer 240 facing away from the first substrate 210. For example, the filling portion TC can be located in the second insulating layer 250, or in the semiconductor layer. The semiconductor layer will be described in detail below and is not discussed here. For clarity, the following description assumes that the filling portion TC is located in the second insulating layer 250, unless otherwise specified.

[0182] FIG9 schematically shows a schematic diagram of preparing a filling portion in an embodiment of the present disclosure.

[0183] 8A to 9 , before the etching step, a first insulating material 310 and a second insulating material 320 are first formed on the first substrate 210. The first insulating material 310 is used to form the first insulating layer 240, and the second insulating material 320 is used to form the second insulating layer 250. Thereafter, a photoresist is formed on the first insulating material 310 and the second insulating material 320 using a mask. The photoresist exposes a location on the second insulating material 320 for forming the second via hole V22, and covers a location on the second insulating material 320 for forming the filling portion TC.

[0184] Afterwards, the first insulating material 310 and the second insulating material 320 are etched. During this process, the portions of the first insulating material 310 and the second insulating material 320 exposed by the photoresist will be removed. Since the portion of the second insulating material 320 used to form the filling portion TC is covered by the photoresist, the photoresist protects this position. Therefore, the etching force of the dry etching gas flow on this position will be weakened. As a result, the second insulating material 320 at this position can be retained while forming the first via hole V21 and the second via hole V22, thereby forming the filling portion TC.

[0185] Accordingly, the retained second insulating material 320 can also protect the first insulating material 310 below it, reducing the etching force of the dry etching gas flow on this part of the first insulating material 310, thereby reducing the drilling phenomenon here. Moreover, as long as it is ensured that the filling portion TC can be formed, the portion of the first insulating material 310 used to form the first via V21 will not be over-etched, and the undercut phenomenon DQ10 shown in Figure 5 will not occur, thereby forming the expected first insulating portion 241. In this way, in the first via V21 and the second via V22 that are finally formed, a more continuous and gentle climbing path can be formed for the first transition portion ZJ21, which is conducive to reducing the risk of fracture of the first transition portion ZJ21.

[0186] The first adapter portion ZJ21 includes a first adapter sub-portion ZJ211 and a second adapter sub-portion ZJ212 connected to the first adapter sub-portion ZJ211. The first adapter sub-portion ZJ211 is connected to the first connection portion D211 in the first via V21. For example, the first adapter sub-portion ZJ211 is connected to the first connection portion D211 at the bottom of the first via V21. The second adapter sub-portion ZJ212 extends continuously from the first inner wall NB10 through the filling portion TC to the second via V22. For example, one end of the second adapter sub-portion ZJ212 is connected to the first adapter sub-portion ZJ211, and the other end climbs upward along the first inner wall NB10 until it climbs to the filling portion TC. Then, the second adapter sub-portion ZJ212 continues to climb along the surface of the filling portion TC until it climbs to the second via V22. During this process, there is no longer the undercut phenomenon DQ10 shown in Figure 5 on the climbing path of the second adapter sub-section ZJ212. Compared with the scheme shown in Figure 5, the climbing path of the second adapter sub-section ZJ212 in the embodiment of the present disclosure is continuous and smooth, thereby greatly reducing the risk of breakage of the second adapter sub-section ZJ212, and further improving the problems such as poor overlap caused thereby.

[0187] In the embodiment of the present disclosure, the first hollow portion LK includes at least two configuration modes. One configuration mode of the first hollow portion LK in the embodiment of the present disclosure will be described below with reference to FIG. 7A to FIG. 12 .

[0188] In some specific embodiments, the display substrate further includes a metal conductive layer 260 disposed between the first insulating layer 240 and the second insulating layer 250, and a first signal line electrically connected to the sub-pixel PX10. Sub-pixel PX10 further includes a second transition portion ZJ22 located in the metal conductive layer 260. The second transition portion ZJ22 is electrically connected to the first signal line.

[0189] In an embodiment of the present disclosure, the second adapter ZJ22 is also connected to the first adapter ZJ21, thereby forming a conductive path between the first electrode D21 and the first signal line. The first signal line can be, for example, a data line DL or a common signal line. For example, when the first electrode D21 is a pixel electrode, the first signal line is the data line DL. In this example, the first signal line can be connected to the second adapter ZJ22 through a first transistor. For example, the source of the first transistor is connected to the first signal line, and the drain of the first transistor is connected to the second adapter ZJ22. When the first transistor is turned on, the first signal line is connected to the second adapter ZJ22, and the signal on the first signal line can be transmitted to the first electrode D21. When the first transistor is turned off, the first signal line is disconnected from the second adapter ZJ22, and the signal on the first signal line will not be transmitted to the first electrode D21. The first electrode D21 can maintain the last received electrical signal. When the first electrode D21 is a common electrode, the first signal line is also a common signal line. In this example, the first signal line can be directly connected to the second transition portion ZJ22, and no switching device such as a transistor is required to be provided between the two.

[0190] The second via hole V22 comprises a first half hole V221 and a second half hole V222, arranged opposite each other along the first direction X. The first half hole V221 communicates with the first via hole V21, while the second half hole V222 exposes the second transition portion ZJ22. The second transition sub-portion ZJ212 extends continuously through the filling portion TC into the second half hole V222 and connects to the exposed second transition portion ZJ22.

[0191] The first direction X may refer to the horizontal direction in FIG7A , the first half hole V221 may refer to the half hole on the left side in FIG7A , and the second half hole V222 may refer to the half hole on the right side in FIG7A . The shapes of the first half hole V221 and the second half hole V222 may include a semicircle, but this does not constitute a limitation to the embodiments of the present disclosure, and the shapes of the first half hole V221 and the second half hole V222 may include any suitable shape. The orthographic projection of the first half hole V221 on the first substrate 210 overlaps with the orthographic projection of the first via hole V21 on the first substrate 210, and, in the overlapping area, the first half hole V221 is connected to the first via hole V21, thereby forming a deeper (relative to the second half hole V222) via hole, which will hereinafter be referred to as a first deep hole. The second transition portion ZJ22 is located between the first insulating layer 240 and the second insulating layer 250. The second half hole V222 exposes the second transition portion ZJ22, thereby forming a shallower via hole (compared to the first deep hole). This via hole is also referred to as the first shallow hole. The first half hole V221 is connected to the second half hole V222, thereby connecting the first deep hole to the first shallow hole.

[0192] 8A to 8C , the second adapter sub-section ZJ212 extends from the bottom of the first deep hole on the left, along the surface of the first inner wall NB10 and the filling section TC, until it climbs into the first shallow hole on the right. The filling section TC is located between the first deep hole and the first shallow hole, thereby improving the undercut phenomenon at the junction of the first deep hole and the first shallow hole, allowing the second adapter sub-section ZJ212 to continuously climb from the bottom of the first deep hole on the left to the first shallow hole on the right, preventing breakage along the way. In addition, the filling section TC can also serve as a transition structure at the junction of the first deep hole and the first shallow hole, thereby further reducing the risk of breakage of the second adapter sub-section ZJ212.

[0193] The second half hole V222 exposes at least the surface of the second transition portion ZJ22 facing away from the first substrate 210 . The second transition sub-portion ZJ212 extends through the filling portion TC to the exposed surface of the second transition portion ZJ22 , thereby connecting to the second transition portion ZJ22 .

[0194] In some specific embodiments, the orthographic projection of the connection area LJ between the first half hole V221 and the second half hole V222 on the first substrate 210 defines a first pattern. The orthographic projection of the filling portion TC on the first substrate 210 is located within the orthographic projection of the second via hole V22 on the first substrate 210, and the filling portion TC overlaps with the first pattern. In other words, in the embodiments of the present disclosure, the filling portion TC is located within the area enclosed by the second via hole V22 and at least at the junction of the first half hole V221 and the second half hole V222.

[0195] For example, the orthographic projections of the first half hole V221 and the second half hole V222 on the first substrate 210 are respectively two semicircles. The shapes of the orthographic projections of the first half hole V221 and the second half hole V222 on the first substrate 210 can be the same. When the orthographic projections are the same, the straight edges of the two semicircles can be arranged to overlap. When the orthographic projections are different, the straight edges of the two semicircles can be arranged to partially overlap, for example, one straight edge covers the other straight edge. The connection area LJ can refer to the straight edges of the two semicircles and a portion of the area on the left and right sides of the straight edges.

[0196] Optionally, the extending direction of the filling portion TC may include an arc or a straight line. Exemplarily, the extending direction of the filling portion TC includes a straight line. For example, the filling portion TC extends along the second direction Y, and the second direction Y intersects the first direction X. Exemplarily, the first direction X may include the horizontal direction in FIG. 7A , and the second direction Y may include the vertical direction in FIG. 7A , that is, the first direction X and the second direction Y intersect.

[0197] In some specific embodiments, the first insulating portion 241 includes a first sub-portion 2411 , which extends along a second direction Y that intersects the first direction X. The connection region LJ between the first half hole V221 and the second half hole V222 exposes the first sub-portion 2411 , the second transition portion ZJ22 covers a portion of the first sub-portion 2411 , and the filling portion TC at least partially covers the portion of the first sub-portion 2411 not covered by the second transition portion ZJ22 .

[0198] In an embodiment of the present disclosure, the first insulating portion 241 further includes a second sub-portion 2412. The orthographic projection of the first insulating portion 241 on the first substrate 210 may include a semicircle. The orthographic projection of the first sub-portion 2411 on the first substrate 210 may be a straight edge of the semicircle, and the orthographic projection of the second sub-portion 2412 on the first substrate 210 may be an arc of the semicircle. For example, the orthographic projection of the first sub-portion 2411 on the first substrate 210 may include a strip-shaped structure extending along the second direction Y. With reference to Figures 8A to 8C, the right half of the first sub-portion 2411 is covered by the second transition portion ZJ22, and the left half of the first sub-portion 2411 is covered by the filling portion TC. In this way, the filling portion TC can cover as much of the first sub-portion 2411 as possible, thereby facilitating the formation of a continuous climbing path.

[0199] In some specific embodiments, the sidewall of the first sub-portion 2411 , the sidewall of the filling portion TC, and the sidewall of the second transition portion ZJ22 form a first step surface.

[0200] For example, the filling portion TC is slightly lower than the second transition portion ZJ22, thereby forming a step. For another example, the filling portion TC can be retracted toward the second transition portion ZJ22, thereby exposing a portion of the first sub-portion 2411 below to form another step. The second transition sub-portion ZJ212 at least partially covers the first step surface, for example, the second transition sub-portion ZJ212 covers the entire first step surface. The first step surface can reduce the steepness of the climbing path of the second transition sub-portion ZJ212, thereby further reducing the risk of breakage of the second transition sub-portion ZJ212.

[0201] In some specific embodiments, the filling portion TC is located in the second insulating layer 250. Referring to FIG. 7B , the filling portion TC includes a first end TC1 and a second end TC2 that are oppositely disposed along the second direction Y. The first end TC1 and the second end TC2 are respectively in contact with the inner wall NB60 of the second via hole V22. In this way, the filling portion TC and the second via hole V22 can form a closed shape, so that the filling portion TC spans the climbing path of the second adapter sub-section ZJ212, thereby preventing the undercut phenomenon shown in FIG. 5 from occurring at any position along the climbing path.

[0202] Figure 10 schematically shows one of the flow charts of the method for preparing a display substrate in an embodiment of the present disclosure, and Figure 11 schematically shows a schematic diagram of a first mask in an embodiment of the present disclosure. Below, in combination with Figures 7A to 11, the display substrate in an embodiment of the present disclosure is further explained through the preparation process.

[0203] In an embodiment of the present disclosure, the preparation method includes steps S110 to S140.

[0204] In step S110 , a first substrate 210 is provided.

[0205] In step S120 , a first insulating material 310 is formed on the first substrate 210 .

[0206] In step S130 , a second insulating material 320 is formed on a side of the first insulating material 310 facing away from the first substrate 210 .

[0207] In step S140 , the first insulating material 310 and the second insulating material 320 are patterned to form a first insulating layer 240 having a first via hole V21 , a second insulating layer 250 having a second via hole V22 , and a filling portion TC.

[0208] The filling portion TC is prepared through steps S141 and S142 .

[0209] In step S141 , a first sacrificial material 330 is formed on a side of the second insulating material 320 facing away from the first substrate 210 . The first sacrificial material 330 includes a first sacrificial portion XS1 . The first sacrificial portion XS1 covers a portion of the second insulating material 320 .

[0210] In an embodiment of the present disclosure, the first sacrificial material 330 may include photoresist. For example, the photoresist may be formed on the side of the second insulating material 320 facing away from the first substrate 210. The photoresist is then exposed and developed using a first mask to form a patterned photoresist, thereby obtaining the first sacrificial material 330. For example, the first mask includes two opposing half-apertures, namely a third half-aperture V23 and a fourth half-aperture V24. Furthermore, the mask also includes a first light shielding portion ZG1 disposed between the third and fourth half-apertures V23 and V24. Taking positive photoresist as an example, during exposure and development, the portion of the photoresist exposed by the third half-aperture V23 is removed, thereby forming a fifth half-aperture V25. The portion of the photoresist exposed by the fourth half-aperture V24 is removed, thereby forming a sixth half-aperture V26. The portion of the photoresist covered by the first light shielding portion ZG1 remains, thereby forming a first sacrificial portion XS1. The first sacrificial portion XS1 covers the portion of the second insulating material 320 that will form the filler portion TC.

[0211] In step S142, the second insulating material 320 and the first sacrificial material 330 are etched, and the first sacrificial portion XS1 is configured such that, during etching, the second insulating material 320 covered by the first sacrificial portion XS1 is etched first, so that after etching is completed, a portion of the second insulating material 320 can be retained to form a filling portion TC.

[0212] In an embodiment of the present disclosure, the first insulating material 310 and the second insulating material 320 can be etched simultaneously using the first sacrificial material 330 as a mask. During the etching process, the portion of the second insulating material 320 exposed by the fifth half-hole V25 is removed to form the first half-hole V221. The portion of the second insulating material 320 exposed by the sixth half-hole V26 is removed to form the second half-hole V222. The portion of the first insulating material 310 exposed by the fifth half-hole V25 is removed to form the first via V21. The first sacrificial portion XS1 protects the second insulating material 320 it covers, thereby reducing the etching intensity of the second insulating material 320 at that location. The first sacrificial portion XS1 and the second insulating material 320 at that location also protect the first insulating material 310 below, thereby reducing the etching intensity of the first insulating material 310 at that location. Thus, after etching to form the first via hole V21, the first half-hole V221, and the second half-hole V222, a portion of the second insulating material 320 can be retained at the junction of the first half-hole V221 and the second half-hole V222 to form a filling portion TC. Accordingly, since the etching intensity of the first insulating material 310 covered by the filling portion TC is also weakened, drilling at this location can be reduced, thereby preventing the formation of undercuts at this location.

[0213] Optionally, during the aforementioned etching process, the first sacrificial portion XS1, made of a photoresist material, can be removed simultaneously. Drilling occurs at the location of the first sacrificial portion XS1, ensuring complete removal of the first sacrificial portion XS1 and preventing any residue. Thus, the first via hole V21, the first half via hole V221, the second half via hole V222, and the filling portion TC are simultaneously fabricated. This results in a first insulating layer 240 having the first via hole V21 and a second insulating layer 250 having the first half via hole V221, the second half via hole V222, and the filling portion TC. Furthermore, no undercut occurs at the bottom of the first via hole V21.

[0214] After step S140, a second electrode material is formed on the side of the second insulating layer 250 away from the first substrate 210, and the second electrode material is subjected to a corresponding patterning process to form a first connection portion D211. Since there is no undercut phenomenon at the bottom of the first via hole V21, the first connection portion D211 can extend continuously from the bottom of the first via hole V21 through the filling portion TC to the second half hole V222.

[0215] Optionally, before forming the second insulating material 320, a metal conductive material is first formed on the side of the first insulating material 310 facing away from the first substrate 210, and the metal conductive material is patterned to form the second transition portion ZJ22. When forming the first sacrificial material 330, the sixth half hole V26 is positioned above the second transition portion ZJ22. This allows the second insulating material 320 exposed by the sixth half hole V26 to be removed during etching, exposing the second transition portion ZJ22 below. When forming the first transition portion ZJ21, the first transition portion ZJ21 is positioned to overlie the second transition portion ZJ22, thereby completing the connection between the two.

[0216] Optionally, the first light shielding portion ZG1 includes a strip structure, and a width K1 of the first light shielding portion ZG1 is greater than or equal to an average of the first etching offset M1 and the second etching offset M2. For example, the width K1 of the first light shielding portion ZG1 can be set to: K1 = (M1 + M2) / 2.

[0217] The first etching offset M1 comprises the deviation between the expected aperture diameter and the actual aperture diameter when forming the first via hole V21 and the first half hole V221. The second etching offset M2 comprises the deviation between the expected aperture diameter and the actual aperture diameter when forming the second half hole V222. For example, if the first via hole V21 and the first half hole V221 are formed simultaneously to form the first deep hole, the first etching offset M1 represents the deviation between the expected aperture diameter and the actual aperture diameter when forming the first deep hole.

[0218] In the embodiment of the present disclosure, the sizes of the third half hole V23 and the fourth half hole V24 can be the same or different, and can be determined according to actual needs. The inventors found in their research that the depths of the first deep hole formed by the first via hole V21 and the first half hole V221 are different from the depths of the first shallow hole formed by the second half hole V222. When the sizes of the third half hole V23 and the fourth half hole V24 are the same, the degree of outward expansion of the first half hole V221 will be different from that of the second half hole V222, which is specifically reflected in the outer diameter of the first half hole V221 being smaller than the outer diameter of the second half hole V222. When the outer diameter difference between the first half hole V221 and the second half hole V222 is large, the inner wall at the junction of the first half hole V221 and the second half hole V222 is prone to breakage, that is, the inner wall that should have extended continuously between the first half hole V221 and the second half hole V222 is broken. The breakage phenomenon can also cause the first adapter ZJ21 to break.

[0219] FIG12 schematically shows a schematic diagram of a second via hole in an embodiment of the present disclosure.

[0220] Referring to Figure 12, in some specific embodiments, the first half hole V221 includes a second inner wall NB20, and the second half hole V222 includes a third inner wall NB30. In the connection region LJ between the first half hole V221 and the second half hole V222, the second inner wall NB20 is located on a side of the third inner wall NB30 that is closer to a first reference line CL1, and has a first spacing J1. The first reference line CL1 includes a straight line passing through the center of the first half hole V221 and the center of the second half hole V222.

[0221] Referring to Figure 12 , the first reference line CL1 extends along the first direction X. In the connection area LJ between the first half hole V221 and the second half hole V222, the second inner wall NB20 is located inward of the third inner wall NB30, with a first spacing J1 between the two in the second direction Y. This first spacing J1 is less than or equal to the maximum thickness of the first transition portion ZJ21. This minimizes the difference in the outer diameters of the first half hole V221 and the second half hole V222, thereby preventing the inner wall from breaking at the junction of the first half hole V221 and the second half hole V222 and improving the potential for breakage of the first transition portion ZJ21.

[0222] In the embodiment of the present disclosure, the third half hole V23 and the fourth half hole V24 are designed to have different sizes. Specifically, the third half hole V23 is larger than the fourth half hole V24. Referring to Figure 11, the third half hole V23 includes a fourth inner wall NB40, and the fourth half hole V24 includes a fifth inner wall NB50. In the connection area between the third half hole V23 and the fourth half hole V24, the fifth inner wall NB50 is located on the side of the fourth inner wall NB40 that is closer to the second reference line CL2 and has a second spacing J2. The second reference line CL2 is a straight line passing through the center of the third half hole V23 and the center of the fourth half hole V24.

[0223] The second spacing J2 is configured as: J2 = (M2-M1) / 2.

[0224] In this way, the first spacing J1 can be made smaller than or equal to the maximum thickness of the first transition portion ZJ21 , thereby preventing a large difference in size between the outer diameters of the first half hole V221 and the second half hole V222 .

[0225] In some specific embodiments, the shape of the first light shielding portion ZG1 includes a quadrilateral. For example, the shape of the first light shielding portion ZG1 may include a rectangle or an isosceles trapezoid. When the shape of the first light shielding portion ZG1 is an isosceles trapezoid, the formed filling portion TC may also be an isosceles trapezoid. The isosceles trapezoid filling portion TC can serve as a transition between the first half hole V221 and the second via hole V222, thereby ensuring a continuous and smooth transition in aperture from the first half hole V221 to the second via hole V222, thereby improving the inner wall from being cut.

[0226] Another configuration method of the first hollow portion LK in the embodiment of the present disclosure will be described below with reference to FIG. 13 to FIG. 20E .

[0227] In some specific embodiments, the display substrate further includes a metal conductive layer 260 disposed between the first insulating layer 240 and the second insulating layer 250, and a first signal line electrically connected to the sub-pixel PX10. Sub-pixel PX10 further includes a second transition portion ZJ22 located in the metal conductive layer 260, electrically connected to the first signal line. The first hollow portion LK further includes a third via V30 disposed in the second insulating layer 250, exposing the second transition portion ZJ22.

[0228] In an embodiment of the present disclosure, the first via hole V21 is connected to the second via hole V22, and the first via hole V21 and the second via hole V22 expose the first connection portion D211, thereby forming a deeper via hole (relative to the third via hole V30), which will be referred to as a second deep hole hereinafter.

[0229] The second transition portion ZJ22 is located between the first insulating layer 240 and the second insulating layer 250. The third via hole V30 exposes the second transition portion ZJ22, thereby forming a shallower via hole (compared to the second deep hole). This via hole is hereinafter referred to as the second shallow hole. The third via hole V30 is spaced apart from the second via hole V22. For example, the third via hole V30 surrounds the outer periphery of the second via hole V22.

[0230] Referring to Figure 14C , the first transition portion ZJ21 also includes a third transition sub-portion ZJ213 and a fourth transition sub-portion ZJ214 connected to the third transition sub-portion ZJ213. The third transition sub-portion ZJ213 is located on the side of the second insulating layer 250 facing away from the first substrate 210. The fourth transition sub-portion ZJ214 is connected to the exposed second transition portion ZJ22 at the bottom of the third via V30. The second transition sub-portion ZJ212 extends continuously through the filling portion TC to the inner wall of the second via V22 and connects to the third transition sub-portion ZJ213.

[0231] That is, in the embodiment of the present disclosure, the first transition portion ZJ21 climbs along the inner wall of the first via hole V21, the sidewall of the filling portion TC, and the inner wall of the second via hole V22 to the side of the second insulating layer 250 facing away from the first substrate 210. Furthermore, the first transition portion ZJ21 extends toward the third via hole V30 on the side of the second insulating layer 250 facing away from the first substrate 210, and contacts the second transition portion ZJ22 in the third via hole V30, thereby connecting with the second transition portion ZJ22.

[0232] In the disclosed embodiment, the filling portion TC can be disposed around the first via hole V21, thereby protecting all locations on the first inner wall NB10 and preventing overcutting. Furthermore, in the disclosed embodiment, none of the first via hole V21, the second via hole V22, or the third via hole V30 is a half-hole, thus avoiding the drawbacks associated with the half-hole design.

[0233] In some specific embodiments, the orthographic projection of the first via V21 on the first substrate 210 defines a third pattern, the orthographic projection of the second via V22 on the first substrate 210 defines a fourth pattern, the orthographic projection of the third via V30 on the first substrate 210 defines a fifth pattern, and the orthographic projection of the filling portion TC on the first substrate 210 defines a sixth pattern. The sixth pattern at least partially surrounds the third pattern, the fourth pattern covers the sixth pattern, and the fifth pattern at least partially surrounds the fourth pattern.

[0234] Alternatively, at least one of the third pattern and the fourth pattern may include a circle, an ellipse, or a shape approximately circular or elliptical.

[0235] Optionally, at least one of the fifth pattern and the sixth pattern comprises a continuous annular pattern.

[0236] For example, the fifth pattern is a continuous annular pattern, meaning the third via V30 is a continuous annular hole, with the second connecting portion ZJ22 exposed at each location within the third via V30. This increases the contact area between the first connecting portion ZJ21 and the second connecting portion ZJ22. Furthermore, the annular third via V30 disperses the connection points between the first connecting portion ZJ21 and the second connecting portion ZJ22 around the second via V22, thereby preventing the connection points between the first connecting portion ZJ21 and the second connecting portion ZJ22 from being concentrated on the same side of the second via V22. This, in turn, prevents the second and third vias V22 and V30 from encroaching on the effective display area of ​​the sub-pixel PX10.

[0237] 14A to 14C , in some specific embodiments, the sidewalls of the second transition portion ZJ22 are covered by the second insulating layer 250. The sidewalls of the first insulating portion 241, the sidewalls of the filling portion TC, and the sidewalls of the second insulating layer 250 form a continuous first inclined surface. The slopes of the sidewalls of the first insulating portion 241, the sidewalls of the filling portion TC, and the sidewalls of the second insulating portion can be the same or different. When the slopes of the three are different, a first inclined surface with gentle ends and steep middle can be formed, thereby facilitating the continuous climbing of the second transition sub-portion ZJ212. The second transition sub-portion ZJ212 at least partially covers the first inclined surface, for example, the second transition sub-portion ZJ212 covers the entire first inclined surface.

[0238] Alternatively, the first insulating portion 241, the filling portion TC, and the second insulating portion form a second step surface. For example, the second insulating layer exposes a portion of the filling portion TC, thereby forming a step. In another example, the filling portion TC exposes some of the first insulating portion 241, thereby forming another step. The second transition sub-portion ZJ212 at least partially covers the second step surface, for example, the second transition sub-portion ZJ212 covers the entire second step surface.

[0239] In some specific embodiments, the display substrate further includes: a first semiconductor layer 270 arranged between the metal conductive layer 260 and the second electrode layer 230, the filling portion TC is located in the first semiconductor layer 270, a portion of the filling portion TC is connected to the second transition sub-portion ZJ212, and the other portion is connected to the second transition portion ZJ22.

[0240] In an embodiment of the present disclosure, the filling portion TC is conductive. For example, the filling portion TC may include a semiconductor material and a metal-doped material, so that the filling portion TC is conductive. Exemplarily, a portion of the filling portion TC is in contact with the second transfer sub-portion ZJ212, thereby achieving electrical connection between the two. Another portion of the filling portion TC is located on the side of the second transfer portion ZJ22 close to the first substrate 210, and is in contact therewith, thereby achieving connection between the two. In this way, two parallel conductive paths are formed between the second transfer portion ZJ22 and the first connection portion D211, wherein the first conductive path is: "second transfer portion ZJ22-fourth transfer sub-portion ZJ214-third transfer sub-portion ZJ213-second transfer sub-portion ZJ212-first transfer sub-portion ZJ211-first connection portion D211", and this conductive path can serve as the main conductive path. The second conductive path, "second transfer portion ZJ22 - filling portion TC - second transfer sub-portion ZJ212 - first transfer sub-portion ZJ211 - first connection portion D211," serves as a backup path. This ensures that if either conductive path fails, the other path remains as a backup, ensuring proper conduction between the first connection portion D211 and the second transfer portion ZJ22, ensuring proper operation of the sub-pixel PX10.

[0241] Optionally, the inner edge of the sixth pattern is a continuous ring-shaped pattern. For example, the portion of the filling portion TC exposed by the second via V22 is a continuous square ring or circular ring. In the embodiment of the present disclosure, the portion of the filling portion TC exposed by the second via V22 is a continuous circular ring. Compared to a square ring, a circular ring shape increases the contact area between the filling portion TC and the second adapter sub-unit ZJ212, thereby improving the conductive effect.

[0242] In some specific embodiments, FIG16 schematically shows one of the schematic diagrams of the third transition portion in the embodiment of the present disclosure.

[0243] Referring to Figure 16 , the display substrate further includes a gate metal layer 280 disposed between the first electrode layer 220 and the first insulating layer 240. Subpixel PX10 further includes a third transition portion ZJ23 disposed in the gate metal layer 280. The third transition portion ZJ23 is located in the first via hole V21 and covers the first connection portion D211. The first transition portion ZJ211 is connected to the first connection portion D211 via the third transition portion ZJ23.

[0244] The third adapter part ZJ23 covers the first connecting part D211, and the first adapter sub-part ZJ211 covers the third adapter part ZJ23. The third adapter part ZJ23 can reduce the climbing height of the second adapter sub-part ZJ212, and then further reduce the risk of breakage of the second adapter sub-part ZJ212.

[0245] Optionally, the third transition portion ZJ23 can be formed synchronously with the first connection portion D211. For example, in an embodiment of the present disclosure, the third transition portion ZJ23 and the first connection portion D211 can be formed simultaneously in one composition process through a mask plate integrating a semi-transparent area and a non-transparent area. Specifically, it will be introduced in detail below, so it will not be repeated here.

[0246] In some embodiments, the fifth pattern includes a continuous circular ring pattern or a square ring pattern.

[0247] Figure 15 schematically illustrates a third via in an embodiment of the present disclosure. Referring to Figure 15 , the fifth pattern is a continuous square ring pattern, meaning the third via V30 is square-ring-shaped. Compared to a circular ring, each position of the square-ring-shaped third via V30 is further away from the second via V22 (or the third transition portion ZJ23), thereby leaving ample space between the third via V30 and the second via V22 (or the third transition portion ZJ23) to prevent short circuits in the conductive device due to process fluctuations.

[0248] In some specific embodiments, the orthographic projection of the first insulating portion 241 on the first substrate 210 overlaps with the orthographic projection of the third transition portion ZJ23 on the first substrate 210, and in this overlapping area, the orthographic projection of the filling portion TC on the first substrate 210 overlaps with the orthographic projection of the third transition portion ZJ23 on the first substrate 210.

[0249] The third transition portion ZJ23 includes a first middle region and a first peripheral region surrounding the first middle region, the first middle region being exposed by the first via V21, and the first peripheral region being covered by the first insulating portion 241. For example, with reference to FIG14B and FIG16 , the side surfaces and upper surfaces of the left and right ends of the third transition portion ZJ23 are covered by the first insulating portion 241. The first peripheral region includes a first peripheral sub-region surrounding the first middle region and a second peripheral sub-region surrounding the first peripheral sub-region. The orthographic projection of the filling portion TC on the first substrate 210 does not overlap with the orthographic projection of the first peripheral sub-region on the first substrate 210, and the orthographic projection of the filling portion TC on the first substrate 210 overlaps with the orthographic projection of the second peripheral sub-region on the first substrate 210. The first transition sub-portion ZJ211 contacts the surface of the third transition portion ZJ23 on the side facing away from the first substrate 210, thereby achieving electrical connection between the two.

[0250] FIG17 schematically shows a second schematic diagram of the third adapter portion in an embodiment of the present disclosure.

[0251] 17 , in some specific embodiments, the orthographic projection of the first insulating portion 241 on the first substrate 210 overlaps with the orthographic projection of the third transition portion ZJ23 on the first substrate 210 , and the orthographic projection of the filling portion TC on the first substrate 210 does not overlap with the orthographic projection of the third transition portion ZJ23 on the first substrate 210 .

[0252] The third transition portion ZJ23 includes a first central region and a first peripheral region surrounding the first central region. The first central region is exposed by the first via V21, and the first peripheral region is covered by the first insulating portion 241. For example, only the side surfaces of the third transition portion ZJ23 are covered by the first insulating portion 241. In this embodiment, the size of the first via V21 is larger than that of the first via V21 in the embodiment shown in FIG. 16 . The first transition sub-portion ZJ211 can contact not only the surface of the third transition portion ZJ23 facing away from the first substrate 210, but also the side surfaces of the third transition portion ZJ23, thereby increasing the contact area between the two.

[0253] In some specific embodiments, the orthographic projection of the second transition portion ZJ22 on the first substrate 210 defines a seventh pattern, wherein the seventh pattern has a first dimension in the first direction X and a second dimension in the second direction Y, and the first direction X and the second direction Y intersect. For example, the ratio of the first dimension to the second dimension is greater than or equal to 1:2.5. For example, the ratio of the first dimension to the second dimension is 1:1.

[0254] In some specific embodiments, the etching rate of the filling portion TC is lower than the etching rate of the first insulating portion 241. For example, the material of the filling portion TC includes a semiconductor material, and the material of the first insulating portion 241 includes an inorganic insulating material. The etching rate of the semiconductor material is lower than the etching rate of the inorganic insulating material. In this way, during the etching process, the semiconductor material is removed relatively slowly, so that while the first via hole V21 is formed, the semiconductor material on the first insulating portion 241 can be retained, thereby forming the filling portion TC.

[0255] Figure 18 schematically illustrates a second flow chart of a method for preparing a display substrate according to an embodiment of the present disclosure. Figures 19A to 19C schematically illustrate a schematic diagram of the process for preparing a display substrate according to an embodiment of the present disclosure. Figures 20A to 20E schematically illustrate a schematic diagram of a mask according to an embodiment of the present disclosure, wherein Figures 20A and 20B schematically illustrate a second mask, Figures 20C and 20D schematically illustrate a third mask, and Figure 20E schematically illustrates a fifth mask. The display substrate according to an embodiment of the present disclosure will be further described below using a preparation method in conjunction with Figures 13 to 20E.

[0256] In an embodiment of the present disclosure, the preparation method includes steps S210 to S250.

[0257] In step S210 , a first substrate 210 is provided.

[0258] In step S220 , a first insulating material 310 is formed on the first substrate 210 .

[0259] In step S230 , a second mask is used to form a first semiconductor material 410 on a side of the first insulating material 310 facing away from the first substrate 210 . The first semiconductor material 410 includes a first covering portion 411 that covers a portion of the first insulating material 310 .

[0260] In step S230 , a second semiconductor material is first formed on a side of the first insulating material 310 facing away from the first substrate 210 , and then a metal conductive material is formed on a side of the second semiconductor material facing away from the first substrate 210 .

[0261] Next, a second mask is used to pattern the second semiconductor material and the metal conductive material. The second mask includes a first region Q1 and a second region Q2 surrounding the first region Q1. The first region Q1 is configured such that, when patterning the second semiconductor material and the metal conductive material, the metal conductive material directly opposite the first region Q1 is removed, while the second semiconductor material directly opposite the first region Q1 is retained to form the first covering portion 411. The second region Q2 is configured such that, when patterning the second semiconductor material and the metal conductive material, the metal conductive material directly opposite the second region Q2 is retained to form the second transition portion ZJ22, while the second semiconductor material directly opposite the second region Q2 is retained.

[0262] In an embodiment of the present disclosure, a second mask can be used to simultaneously etch the second semiconductor material and the metal conductive material. Specifically, in the second mask, the first region Q1 includes a first semi-transparent region, and the second region Q2 includes a first non-transparent region. During patterning, the metal conductive material can be removed through the first semi-transparent region, retaining the second semiconductor material, and the metal conductive material and the second semiconductor material can be retained through the first non-transparent region. Referring to Figure 19A, after the patterning is completed, an entire layer of the second semiconductor material is retained, and the metal conductive material in the middle is removed. Subsequently, the retained second semiconductor material is formed into the first semiconductor material 410, and the retained metal conductive material is formed into the second transition portion ZJ22.

[0263] 20A and 20B , the first region Q1 may optionally be circular or square. In the embodiment of the present disclosure, the first region Q1 is circular, thereby forming a large contact area between the filling portion TC and the second transfer sub-portion ZJ112, which is beneficial for enhancing the conductive effect of the backup conductive path.

[0264] In step S240 , a second insulating material 320 is formed on a side of the first semiconductor material 410 facing away from the first substrate 210 .

[0265] In step S250 , the first insulating material 310 , the second insulating material 320 and the first semiconductor material 410 are patterned to form a first insulating layer 240 having a first via hole V21 , a second insulating layer 250 having a second via hole V22 and a filling portion TC.

[0266] The filling portion TC is prepared through steps S251 and S252.

[0267] In step S251 , a first barrier material 510 is formed on a side of the second insulating material 320 facing away from the first substrate 210 using a third mask. The first barrier material 510 exposes a portion of the second insulating material 320 .

[0268] In an embodiment of the present disclosure, the first barrier material 510 may include photoresist. The third mask includes a third region Q3 and a fourth region Q4 surrounding the third region Q3. The third region Q3 is configured such that a fourth via hole V40 is formed on the first barrier material 510, exposing a first portion of the second insulating material 320. The fourth region Q4 is configured such that a fifth via hole V50 is formed on the first barrier material 510, at least partially surrounding the fourth via hole V40 and exposing a second portion of the second insulating material 320.

[0269] For example, first, a photoresist material is formed on the side of the second insulating material 320 facing away from the first substrate 210. In an embodiment of the present disclosure, the third region Q3 may include a circular hole, and the fourth region Q4 may include an annular hole surrounding the circular hole. The photoresist material is exposed and developed using a third mask, wherein the portion of the photoresist material facing the third region Q3 is removed to form a fourth via V40, and the portion of the photoresist material facing the fourth region Q4 is removed to form a fifth via V50. The first portion may refer to the portion of the second insulating material 320 used to form the second via V22, and the second portion may refer to the portion of the second insulating material 320 used to form the third via V30.

[0270] In step S252, the first insulating material 310, the first semiconductor material 410 and the second insulating material 320 are etched using the first barrier material 510 as a fourth mask. The first barrier material 510 is configured so that the portions of the first insulating material 310, the first semiconductor material 410 and the second insulating material 320 exposed by the first barrier material 510 are removed.

[0271] When etching the first insulating material 310, the first semiconductor material 410, and the second insulating material 320, the first portion is removed to form the second via hole V22, and the second portion is removed to form the third via hole V30. The third via hole V30 exposes the second transition portion ZJ22. In the first semiconductor material 410, the first covering portion 411 is configured such that when etching the first insulating material 310, the first semiconductor material 410, and the second insulating material 320, the first insulating material 310 covered by the first covering portion 411 is etched first.

[0272] After etching is complete, the portion of the first covering portion 411 exposed by the first barrier material 510 is removed, thereby removing the portion of the first insulating material 310 exposed by the fourth via V40, thereby forming the first via V21, which is connected to the second via V22. Because the etching rate of the first semiconductor material 410 is lower than that of the first insulating material 310, after the first via V21, the second via V22, and the third via V30 are formed, a portion of the first covering portion 411 remains between the first via V21 and the second via V22, and this portion covers the first insulating portion 241, thereby forming the filling portion TC. The remaining portion of the first covering portion 411 also protects the first insulating material 310 below, reducing the etching intensity of the first insulating material 310 in this area, thereby preventing the undercut phenomenon DQ10 shown in Figure 5.

[0273] At this point, the first via hole V21, the second via hole V22, the third via hole V30, and the filling portion TC are simultaneously fabricated. This means that the first insulating layer 240 having the first via hole V21, the second insulating layer 250 having the second and third via holes V22 and V30, and the first semiconductor layer 270 having the filling portion TC are obtained. Furthermore, the undercut phenomenon DQ10 shown in FIG. 5 does not exist at the bottom of the first via hole V21.

[0274] Optionally, the fourth region Q4 includes a circular ring or a square ring. In the embodiment of the present disclosure, the fourth region Q4 is a square ring. In this way, the third via V30 formed is a continuous square ring, which is conducive to leaving sufficient space between the third via V30 and the second via V22 (or the third transition portion ZJ23) to avoid short circuits in the conductive device due to process fluctuations.

[0275] In some specific embodiments, the preparation method further comprises:

[0276] Before forming the first insulating material 310 , a first electrode material is formed on the first substrate 210 .

[0277] A gate metal material is formed on a side of the first electrode material facing away from the first substrate 210 .

[0278] The first electrode material and the gate metal material are patterned using a fifth mask, wherein the fifth mask includes a fifth region Q5 and a sixth region Q6 surrounding the fifth region Q5.

[0279] The fifth region Q5 is configured as follows: when the first electrode material and the gate metal material are composed, the first electrode material opposite to the fifth region Q5 is retained to form a first connection portion D211, and the gate metal material opposite to the fifth region Q5 is retained to form a third transfer portion ZJ23 on the first connection portion D211.

[0280] The sixth region Q6 is configured such that when the first electrode material and the gate metal material are patterned, the first electrode material facing the sixth region Q6 is retained and the gate metal material facing the sixth region Q6 is removed.

[0281] In the embodiments of the present disclosure, a fifth mask can be used to simultaneously etch the first electrode material and the gate metal material. Specifically, in the fifth mask, the fifth region Q5 includes a second non-transparent region, and the sixth region Q6 includes a second semi-transparent region. During patterning, the second non-transparent region can be used to retain the first electrode material and the gate metal material, while the second semi-transparent region can be used to remove the gate metal material, leaving the first electrode material. Referring to FIG. 19B , an entire layer of the first electrode material is retained, while the intermediate gate metal material is retained. Subsequently, the retained first electrode material forms the first electrode layer 220, and the retained gate metal material forms the third transition portion ZJ23.

[0282] At least some embodiments of the present disclosure further provide a display device, which may include any device or product having a display function. For example, the display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0283] It should be understood that the above-mentioned display device has all the characteristics and advantages of the above-mentioned display substrate. For details, please refer to the above description, which will not be repeated here.

[0284] At least some embodiments of the present disclosure further provide a method for preparing a display substrate, wherein the display substrate includes the display substrate described above. Referring to FIG. 7A to FIG. 11 , in an embodiment of the present disclosure, the preparation method includes steps S110 to S140.

[0285] In step S110 , a first substrate 210 is provided.

[0286] In step S120 , a first insulating material 310 is formed on the first substrate 210 .

[0287] In step S130 , a second insulating material 320 is formed on a side of the first insulating material 310 facing away from the first substrate 210 .

[0288] In step S140 , the first insulating material 310 and the second insulating material 320 are patterned to form a first insulating layer 240 having a first via hole V21 , a second insulating layer 250 having a second via hole V22 , and a filling portion TC.

[0289] The filling portion TC is prepared through steps S141 and S142 .

[0290] In step S141 , a first sacrificial material 330 is formed on a side of the second insulating material 320 facing away from the first substrate 210 . The first sacrificial material 330 includes a first sacrificial portion XS1 . The first sacrificial portion XS1 covers a portion of the second insulating material 320 .

[0291] In an embodiment of the present disclosure, the first sacrificial material 330 may include photoresist. For example, the photoresist may be formed on the side of the second insulating material 320 facing away from the first substrate 210. The photoresist is then exposed and developed using a first mask to form a patterned photoresist, thereby obtaining the first sacrificial material 330. For example, the first mask includes two opposing half-apertures, namely a third half-aperture V23 and a fourth half-aperture V24. Furthermore, the mask also includes a first light shielding portion ZG1 disposed between the third and fourth half-apertures V23 and V24. Taking positive photoresist as an example, during exposure and development, the portion of the photoresist exposed by the third half-aperture V23 is removed, thereby forming a fifth half-aperture V25. The portion of the photoresist exposed by the fourth half-aperture V24 is removed, thereby forming a sixth half-aperture V26. The portion of the photoresist covered by the first light shielding portion ZG1 remains, thereby forming a first sacrificial portion XS1. The first sacrificial portion XS1 covers the portion of the second insulating material 320 that will form the filler portion TC.

[0292] In step S142, the second insulating material 320 and the first sacrificial material 330 are etched, and the first sacrificial portion XS1 is configured such that, during etching, the second insulating material 320 covered by the first sacrificial portion XS1 is etched first, so that after etching is completed, a portion of the second insulating material 320 can be retained to form a filling portion TC.

[0293] In an embodiment of the present disclosure, the first insulating material 310 and the second insulating material 320 can be etched simultaneously using the first sacrificial material 330 as a mask. During the etching process, the portion of the second insulating material 320 exposed by the fifth half-hole V25 is removed to form the first half-hole V221. The portion of the second insulating material 320 exposed by the sixth half-hole V26 is removed to form the second half-hole V222. The portion of the first insulating material 310 exposed by the fifth half-hole V25 is removed to form the first via V21. The first sacrificial portion XS1 protects the second insulating material 320 it covers, thereby reducing the etching intensity of the second insulating material 320 at that location. The first sacrificial portion XS1 and the second insulating material 320 at that location also protect the first insulating material 310 below, thereby reducing the etching intensity of the first insulating material 310 at that location. Thus, after etching to form the first via hole V21, the first half-hole V221, and the second half-hole V222, a portion of the second insulating material 320 can be retained at the junction of the first half-hole V221 and the second half-hole V222 to form a filling portion TC. Accordingly, since the etching intensity of the first insulating material 310 covered by the filling portion TC is also weakened, drilling at this location can be reduced, thereby preventing the formation of undercuts at this location.

[0294] Optionally, during the aforementioned etching process, the first sacrificial portion XS1, made of a photoresist material, can be removed simultaneously. Drilling occurs at the location of the first sacrificial portion XS1, ensuring complete removal of the first sacrificial portion XS1 and preventing any residue. Thus, the first via hole V21, the first half via hole V221, the second half via hole V222, and the filling portion TC are simultaneously fabricated. This results in a first insulating layer 240 having the first via hole V21 and a second insulating layer 250 having the first half via hole V221, the second half via hole V222, and the filling portion TC. Furthermore, no undercut occurs at the bottom of the first via hole V21.

[0295] After step S140, a second electrode material is formed on the side of the second insulating layer 250 away from the first substrate 210, and the second electrode material is subjected to a corresponding patterning process to form a first connection portion D211. Since there is no undercut phenomenon at the bottom of the first via hole V21, the first connection portion D211 can extend continuously from the bottom of the first via hole V21 through the filling portion TC to the second half hole V222.

[0296] Optionally, before forming the second insulating material 320, a metal conductive material is first formed on the side of the first insulating material 310 facing away from the first substrate 210, and the metal conductive material is patterned to form the second transition portion ZJ22. When forming the first sacrificial material 330, the sixth half hole V26 is positioned above the second transition portion ZJ22. This allows the second insulating material 320 exposed by the sixth half hole V26 to be removed during etching, exposing the second transition portion ZJ22 below. When forming the first transition portion ZJ21, the first transition portion ZJ21 is positioned to overlie the second transition portion ZJ22, thereby completing the connection between the two.

[0297] Optionally, the first light shielding portion ZG1 includes a strip structure, and a width K1 of the first light shielding portion ZG1 is greater than or equal to an average of the first etching offset M1 and the second etching offset M2. For example, the width K1 of the first light shielding portion ZG1 can be set to: K1 = (M1 + M2) / 2.

[0298] The first etching offset M1 comprises the deviation between the expected aperture diameter and the actual aperture diameter when forming the first via hole V21 and the first half hole V221. The second etching offset M2 comprises the deviation between the expected aperture diameter and the actual aperture diameter when forming the second half hole V222. For example, if the first via hole V21 and the first half hole V221 are formed simultaneously to form the first deep hole, the first etching offset M1 represents the deviation between the expected aperture diameter and the actual aperture diameter when forming the first deep hole.

[0299] In the embodiment of the present disclosure, the sizes of the third half hole V23 and the fourth half hole V24 can be the same or different, and can be determined according to actual needs. The inventors found in their research that the depths of the first deep hole formed by the first via hole V21 and the first half hole V221 are different from the depths of the first shallow hole formed by the second half hole V222. When the sizes of the third half hole V23 and the fourth half hole V24 are the same, the degree of outward expansion of the first half hole V221 will be different from that of the second half hole V222, which is specifically reflected in the outer diameter of the first half hole V221 being smaller than the outer diameter of the second half hole V222. When the outer diameter difference between the first half hole V221 and the second half hole V222 is large, the inner wall at the junction of the first half hole V221 and the second half hole V222 is prone to breakage, that is, the inner wall that should have extended continuously between the first half hole V221 and the second half hole V222 is broken. The breakage phenomenon can also cause the first adapter ZJ21 to break.

[0300] FIG12 schematically shows a schematic diagram of a second via hole in an embodiment of the present disclosure.

[0301] Referring to Figure 12, in some specific embodiments, the first half hole V221 includes a second inner wall NB20, and the second half hole V222 includes a third inner wall NB30. In the connection region LJ between the first half hole V221 and the second half hole V222, the second inner wall NB20 is located on a side of the third inner wall NB30 that is closer to a first reference line CL1, and has a first spacing J1. The first reference line CL1 includes a straight line passing through the center of the first half hole V221 and the center of the second half hole V222.

[0302] The first reference line CL1 extends along the first direction X. In the connection area LJ between the first half hole V221 and the second half hole V222, the second inner wall NB20 is located inward of the third inner wall NB30, and a first spacing J1 is defined between the second half hole V221 and the third half hole NB30 in the second direction Y. This first spacing J1 is less than or equal to the maximum thickness of the first transition portion ZJ21. This minimizes the difference in the outer diameters of the first half hole V221 and the second half hole V222, thereby preventing the inner wall from breaking at the junction of the first half hole V221 and the second half hole V222 and reducing the potential for breakage of the first transition portion ZJ21.

[0303] In the embodiment of the present disclosure, the third half hole V23 and the fourth half hole V24 are designed to have different sizes. Specifically, the third half hole V23 is larger than the fourth half hole V24. The third half hole V23 includes a fourth inner wall NB40, and the fourth half hole V24 includes a fifth inner wall NB50. In the connection area between the third half hole V23 and the fourth half hole V24, the fifth inner wall NB50 is located on the side of the fourth inner wall NB40 that is closer to the second reference line CL2 and has a second spacing. The second reference line CL2 includes a straight line passing through the center of the third half hole V23 and the center of the fourth half hole V24.

[0304] The second spacing J2 is configured as: J2 = (M2-M1) / 2.

[0305] In this way, the first spacing J1 can be made smaller than or equal to the maximum thickness of the first transition portion ZJ21 , thereby preventing a large difference in size between the outer diameters of the first half hole V221 and the second half hole V222 .

[0306] In some specific embodiments, the shape of the first light shielding portion ZG1 includes a quadrilateral. For example, the shape of the first light shielding portion ZG1 may include a rectangle or an isosceles trapezoid. When the shape of the first light shielding portion ZG1 is an isosceles trapezoid, the first insulating portion 241, the filling portion TC, and the second transition portion ZJ22 can be formed into two steps. These two steps can constitute the first step surface described above, thereby achieving a continuous and smooth transition from the aperture of the first half hole V221 to the second via hole V222, which helps to improve the internal wall breaking phenomenon.

[0307] At least some embodiments of the present disclosure further provide a method for preparing a display substrate, wherein the display substrate includes the display substrate described above. Referring to FIG. 13 to FIG. 20E , in an embodiment of the present disclosure, the preparation method includes steps S210 to S250 .

[0308] In step S210 , a first substrate 210 is provided.

[0309] In step S220 , a first insulating material 310 is formed on the first substrate 210 .

[0310] In step S230 , a second mask is used to form a first semiconductor material 410 on a side of the first insulating material 310 facing away from the first substrate 210 . The first semiconductor material 410 includes a first covering portion 411 that covers a portion of the first insulating material 310 .

[0311] In step S230 , a second semiconductor material is first formed on a side of the first insulating material 310 facing away from the first substrate 210 , and then a metal conductive material is formed on a side of the second semiconductor material facing away from the first substrate 210 .

[0312] Next, a second mask is used to pattern the second semiconductor material and the metal conductive material. The second mask includes a first region Q1 and a second region Q2 surrounding the first region Q1. The first region Q1 is configured such that, when patterning the second semiconductor material and the metal conductive material, the metal conductive material directly opposite the first region Q1 is removed, while the second semiconductor material directly opposite the first region Q1 is retained to form the first covering portion 411. The second region Q2 is configured such that, when patterning the second semiconductor material and the metal conductive material, the metal conductive material directly opposite the second region Q2 is retained to form the second transition portion ZJ22, while the second semiconductor material directly opposite the second region Q2 is retained.

[0313] In an embodiment of the present disclosure, a second mask can be used to simultaneously etch the second semiconductor material and the metal conductive material. Specifically, in the second mask, the first region Q1 includes a first semi-transparent region, and the second region Q2 includes a first non-transparent region. During patterning, the metal conductive material can be removed through the first semi-transparent region, retaining the second semiconductor material, and the metal conductive material and the second semiconductor material can be retained through the first non-transparent region. Referring to Figure 19A, after the patterning is completed, an entire layer of the second semiconductor material is retained, and the metal conductive material in the middle is removed. Subsequently, the retained second semiconductor material is formed into the first semiconductor material 410, and the retained metal conductive material is formed into the second transition portion ZJ22.

[0314] 20A and 20B , optionally, the first region Q1 includes a circle or a square. In the embodiment of the present disclosure, the first region Q1 is a circle.

[0315] In step S240 , a second insulating material 320 is formed on a side of the first semiconductor material 410 facing away from the first substrate 210 .

[0316] In step S250 , the first insulating material 310 , the second insulating material 320 and the first semiconductor material 410 are patterned to form a first insulating layer 240 having a first via hole V21 , a second insulating layer 250 having a second via hole V22 and a filling portion TC.

[0317] The filling portion TC is prepared through steps S251 and S252.

[0318] In step S251 , a first barrier material 510 is formed on a side of the second insulating material 320 facing away from the first substrate 210 using a third mask. The first barrier material 510 exposes a portion of the second insulating material 320 .

[0319] In an embodiment of the present disclosure, the first barrier material 510 may include photoresist. The third mask includes a third region Q3 and a fourth region Q4 surrounding the third region Q3. The third region Q3 is configured such that a fourth via hole V40 is formed on the first barrier material 510, exposing a first portion of the second insulating material 320. The fourth region Q4 is configured such that a fifth via hole V50 is formed on the first barrier material 510, at least partially surrounding the fourth via hole V40 and exposing a second portion of the second insulating material 320.

[0320] For example, first, a photoresist material is formed on the side of the second insulating material 320 facing away from the first substrate 210. In an embodiment of the present disclosure, the third region Q3 may include a circular hole, and the fourth region Q4 may include an annular hole surrounding the circular hole. The photoresist material is exposed and developed using a third mask, wherein the portion of the photoresist material facing the third region Q3 is removed to form a fourth via V40, and the portion of the photoresist material facing the fourth region Q4 is removed to form a fifth via V50. The first portion may refer to the portion of the second insulating material 320 used to form the second via V22, and the second portion may refer to the portion of the second insulating material 320 used to form the third via V30.

[0321] In step S252, the first insulating material 310, the first semiconductor material 410 and the second insulating material 320 are etched using the first barrier material 510 as a fourth mask. The first barrier material 510 is configured so that the portions of the first insulating material 310, the first semiconductor material 410 and the second insulating material 320 exposed by the first barrier material 510 are removed.

[0322] When etching the first insulating material 310, the first semiconductor material 410, and the second insulating material 320, the first portion is removed to form the second via hole V22, and the second portion is removed to form the third via hole V30. The third via hole V30 exposes the second transition portion ZJ22. In the first semiconductor material 410, the first covering portion 411 is configured such that when etching the first insulating material 310, the first semiconductor material 410, and the second insulating material 320, the first insulating material 310 covered by the first covering portion 411 is etched first.

[0323] After etching is complete, the portion of the first covering portion 411 exposed by the first barrier material 510 is removed, thereby removing the portion of the first insulating material 310 exposed by the fourth via V40, thereby forming the first via V21, which is connected to the second via V22. Because the etching rate of the first semiconductor material 410 is lower than that of the first insulating material 310, after the first via V21, the second via V22, and the third via V30 are formed, a portion of the first covering portion 411 remains between the first via V21 and the second via V22, and this portion covers the first insulating portion 241, thereby forming the filling portion TC. The remaining portion of the first covering portion 411 also protects the first insulating material 310 below, reducing the etching intensity of the first insulating material 310 in this area, thereby preventing the undercut phenomenon DQ10 shown in Figure 5.

[0324] At this point, the first via hole V21, the second via hole V22, the third via hole V30, and the filling portion TC are simultaneously fabricated. This means that the first insulating layer 240 having the first via hole V21, the second insulating layer 250 having the second and third via holes V22 and V30, and the first semiconductor layer 270 having the filling portion TC are obtained. Furthermore, the undercut phenomenon DQ10 shown in FIG. 5 does not exist at the bottom of the first via hole V21.

[0325] Optionally, the fourth region Q4 includes a circular ring or a square ring. In the embodiment of the present disclosure, the fourth region Q4 is a square ring.

[0326] In some specific embodiments, the preparation method further comprises:

[0327] Before forming the first insulating material 310 , a first electrode material is formed on the first substrate 210 .

[0328] A gate metal material is formed on a side of the first electrode material facing away from the first substrate 210 .

[0329] The first electrode material and the gate metal material are patterned using a fifth mask, wherein the fifth mask includes a fifth region Q5 and a sixth region Q6 surrounding the fifth region Q5.

[0330] The fifth region Q5 is configured as follows: when the first electrode material and the gate metal material are composed, the first electrode material opposite to the fifth region Q5 is retained to form a first connection portion D211, and the gate metal material opposite to the fifth region Q5 is retained to form a third transfer portion ZJ23 on the first connection portion D211.

[0331] The sixth region Q6 is configured such that when the first electrode material and the gate metal material are patterned, the first electrode material facing the sixth region Q6 is retained and the gate metal material facing the sixth region Q6 is removed.

[0332] In an embodiment of the present disclosure, a fifth mask can be used to simultaneously etch the first electrode material and the gate metal material. Specifically, in the fifth mask, the fifth region Q5 includes a second non-transparent region, and the sixth region Q6 includes a second semi-transparent region. During patterning, the first electrode material and the gate metal material can be retained through the second non-transparent region, and the gate metal material can be removed through the second semi-transparent region, retaining the first electrode material. After patterning is completed, an entire layer of the first electrode material is retained, and the gate metal material in the middle is retained. Subsequently, the retained first electrode material is formed into the first electrode layer 220, and the retained gate metal material is formed into the third transition portion ZJ23.

[0333] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.

[0334] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A display substrate, wherein, Comprising: A first substrate; A first electrode layer disposed on the first substrate; A second electrode layer disposed on a side of the first electrode layer facing away from the first substrate; A first insulating layer and a second insulating layer disposed between the first electrode layer and the second electrode layer, the second insulating layer being located on a side of the first insulating layer facing away from the first substrate; And Sub-pixels disposed on the first substrate, wherein the sub-pixels include: A first electrode disposed in the first electrode layer, the first electrode including a first connection portion; A first transfer portion disposed in the second electrode layer; and A first hollow portion, wherein the first hollow portion includes: A first via hole disposed in the first insulating layer, the first via hole exposing the first connection portion; A second via hole disposed in the second insulating layer, the second via hole communicating with the first via hole; A first insulating portion disposed in the first insulating layer, a side wall of the first insulating portion forming a first inner wall of the first via hole; and A filling portion disposed on a side of the first insulating portion facing away from the first substrate; Wherein the first transfer portion includes a first transfer sub-portion and a second transfer sub-portion connected to the first transfer sub-portion, the first transfer sub-portion being connected to the first connection portion in the first via hole, and the second transfer sub-portion continuously extending from the first inner wall, through the filling portion, into the second via hole.

2. The display substrate according to claim 1, wherein, The display substrate further includes: A metal conductive layer disposed between the first insulating layer and the second insulating layer; and A first signal line electrically connected to the sub-pixels; The sub-pixels further include: A second transfer portion located in the metal conductive layer, the second transfer portion being electrically connected to the first signal line; The second via hole includes a first half hole and a second half hole arranged along a first direction and oppositely disposed, the first half hole communicating with the first via hole, and the second half hole exposing the second transfer portion; The second transfer sub-portion continuously extends through the filling portion into the second half hole and is connected to the exposed second transfer portion.

3. The display substrate according to claim 2, wherein, A positive projection of a connection region between the first half hole and the second half hole on the first substrate defines a first pattern, a positive projection of the filling portion on the first substrate is located within a positive projection of the second via hole on the first substrate and overlaps with the first pattern.

4. The display substrate according to claim 2, wherein The first insulating portion includes a first sub-portion, the first sub-portion extending along a second direction, the second direction intersecting with the first direction; The connection region between the first half hole and the second half hole exposes the first sub-portion, the second transfer portion covers a part of the first sub-portion, and the filling portion at least partially covers a part of the first sub-portion not covered by the second transfer portion.

5. The display substrate according to claim 4, wherein, Side walls of the first sub-portion, side walls of the filling portion, and side walls of the second transfer portion form a first stepped surface.

6. The display substrate according to claim 2, wherein, The first half hole includes a second inner wall, and the second half hole includes a third inner wall; In the connection area between the first half hole and the second half hole, the second inner wall is located on a side of the third inner wall close to a first reference line and has a first spacing, wherein the first reference line includes: a straight line passing through the center of the first half hole and the center of the second half hole; The first spacing is less than or equal to a maximum thickness of the first transition portion.

7. The display substrate according to any one of claims 1 to 6, wherein, The filling portion is located in the second insulating layer, and includes a first end and a second end that are oppositely disposed along a second direction, wherein the first end and the second end are in contact with an inner wall of the second via hole, respectively.

8. The display substrate according to claim 1, wherein, The display substrate further comprises: a metal conductive layer disposed between the first insulating layer and the second insulating layer; and a first signal line electrically connected to the sub-pixel; The sub-pixel further includes: a second transfer portion located in the metal conductive layer, the second transfer portion being electrically connected to the first signal line; The first floor also includes: a third via hole penetrating the second insulating layer, the third via hole being spaced apart from the second via hole, and the third via hole exposing the second transfer portion; The first transfer portion further includes a third transfer sub-portion and a fourth transfer sub-portion connected to the third transfer sub-portion, the third transfer sub-portion is located on a side of the second insulating layer away from the first substrate, and the fourth transfer sub-portion is connected to the exposed second transfer portion at the bottom of the third via hole; The second transfer sub-portion extends continuously to the inner wall of the second via hole through the filling portion, and is connected to the third transfer sub-portion.

9. The display substrate according to claim 8, wherein, The orthographic projection of the first via hole on the first substrate defines a third pattern, the orthographic projection of the second via hole on the first substrate defines a fourth pattern, the orthographic projection of the third via hole on the first substrate defines a fifth pattern, and the orthographic projection of the filling portion on the first substrate defines a sixth pattern; The sixth pattern at least partially surrounds the third pattern, the fourth pattern covers the sixth pattern, and the fifth pattern at least partially surrounds the fourth pattern.

10. The display substrate according to claim 9, wherein, The fifth pattern includes a continuous square ring pattern.

11. The display substrate according to claim 8, wherein, The side wall of the second transition portion is covered by the second insulating layer; The side wall of the first insulating portion, the side wall of the filling portion and the side wall of the second insulating portion form a continuous first inclined surface, and the second transfer sub-portion at least partially covers the first inclined surface; or, The first insulating portion, the filling portion, and the second insulating portion form a second step surface, and the second transfer sub-portion at least partially covers the second step surface.

12. The display substrate according to claim 8, wherein, The display substrate further comprises: The first semiconductor layer is disposed between the metal conductive layer and the second electrode layer, and the filling portion is located at In the first semiconductor layer, a portion of the filling portion is connected to the second transition portion, and another portion is connected to the second transition portion.

13. The display substrate according to claim 8, wherein, The display substrate further includes a gate metal layer disposed between the first electrode layer and the first insulating layer; The sub-pixel further includes: A third transfer portion disposed in the gate metal layer, the third transfer portion being located in the first via hole and covering the first connection portion; The first adapter sub-portion is connected to the first connecting portion through the third adapter portion.

14. The display substrate according to claim 13, wherein, The orthographic projection of the first insulating portion on the first substrate overlaps with the orthographic projection of the third transition portion on the first substrate. In the overlapping area, the orthographic projection of the filling portion on the first substrate overlaps with the orthographic projection of the third transition portion on the first substrate.

15. The display substrate according to claim 13, wherein, The orthographic projection of the first insulating portion on the first substrate overlaps with the orthographic projection of the third transition portion on the first substrate, and the orthographic projection of the filling portion on the first substrate does not overlap with the orthographic projection of the third transition portion on the first substrate.

16. The display substrate according to claim 8, wherein, The orthographic projection of the second transition portion on the first substrate defines a seventh pattern, the seventh pattern has a first size in the first direction, the seventh pattern has a second size in the second direction, and the first direction intersects the second direction; The ratio of the first dimension to the second dimension is greater than or equal to 1 ∶ 2.5 17. The display substrate according to any one of claims 1 to 16, wherein, An etching rate of the filling portion is lower than an etching rate of the first insulating portion.

18. A display device, wherein, The invention comprises the display substrate as claimed in any one of claims 1 to 17.

19. A method for preparing a display substrate, wherein, The display substrate comprises the display substrate according to any one of claims 1 to 7 and 17, and the preparation method comprises: providing a first substrate; forming a first insulating material on the first substrate; forming a second insulating material on a side of the first insulating material facing away from the first substrate; Patterning the first insulating material and the second insulating material to form a first insulating layer having the first via hole, a second insulating layer having the second via hole, and the filling portion; Wherein, the filling part is prepared by the following steps: forming a first sacrificial material on a side of the second insulating material facing away from the first substrate, wherein the first sacrificial material comprises a first sacrificial portion, and the first sacrificial portion covers a portion of the second insulating material; The second insulating material and the first sacrificial material are etched, and the first sacrificial part is configured such that during etching, the second insulating material covered by the first sacrificial part is etched first, so that after etching, a portion of the second insulating material can be retained to form the filling part.

20. The preparation method according to claim 19, wherein, The preparation method further comprises: Before forming the second insulating material, forming a metal conductive material on a side of the first insulating material facing away from the first substrate; Patterning the metal conductive material to form a second transfer portion; The forming of a first sacrificial material on a side of the second insulating material facing away from the first substrate comprises: Using a first mask plate to pattern the first sacrificial material, wherein the first mask plate includes a third half hole and a fourth half hole arranged opposite to each other along a first direction, and a first light shielding portion located between the third half hole and the fourth half hole; The third half hole is configured as follows: the first sacrificial material directly opposite to the third half hole is removed to form a fifth half hole, the first sacrificial material directly opposite to the fourth half hole is removed to form a sixth half hole, and the first sacrificial material directly opposite to the first light shielding portion is retained to form the first sacrificial portion; The fifth half hole is configured such that: when etching the second insulating material, the second insulating material directly opposite to the fifth half hole is removed to form a first half hole, and the first insulating material directly opposite to the fifth half hole is removed to form a first via hole; The sixth half hole is configured such that when the second insulating material is etched, the sixth half hole is The second insulating material opposite to the hole is removed to form a second half hole, and the second half hole exposes the second transition portion.

21. The preparation method according to claim 20, wherein The third half hole and the fourth half hole have the same size; or, The third half hole includes a fourth inner wall, and the fourth half hole includes a fifth inner wall. In the connection area between the third half hole and the fourth half hole, the fifth inner wall is located on a side of the fourth inner wall close to a second reference line and has a second spacing, wherein the second reference line includes: a straight line passing through the center of the third half hole and the center of the fourth half hole.

22. The preparation method according to claim 20, wherein, The first light shielding portion comprises a strip structure, and a width of the first light shielding portion is greater than or equal to an average value of the first etching offset and the second etching offset; The first etching offset includes: when forming the first via hole and the first half hole, the deviation between the expected aperture and the actual aperture; the second etching offset includes: when forming the second half hole, the deviation between the expected aperture and the actual aperture.

23. A method for preparing a display substrate, wherein, The display substrate comprises the display substrate according to any one of claims 1 and 8 to 17, and the preparation method comprises: providing a first substrate; forming a first insulating material on the first substrate; Using a second mask, forming a first semiconductor material on a side of the first insulating material away from the first substrate, wherein the first semiconductor material includes a first covering portion, and the first covering portion covers a portion of the first insulating material; forming a second insulating material on a side of the first semiconductor material facing away from the first substrate; Patterning the first insulating material, the second insulating material, and the first semiconductor material to form a first insulating layer having the first via hole, a second insulating layer having the second via hole, and the filling portion; Wherein, the filling part is prepared by the following steps: A third mask is used to form a first barrier on a side of the second insulating material facing away from the first substrate. a barrier material, wherein the first barrier material exposes a portion of the second insulating material; Using the first barrier material as a fourth mask, etching the first insulating material, the first semiconductor material and the second insulating material, wherein the first barrier material is configured to remove portions of the first insulating material, the first semiconductor material and the second insulating material that are exposed by the first barrier material; The first covering portion is configured such that when the first insulating material, the first semiconductor material and the second insulating material are etched, the first insulating material covered by the first covering portion is etched first, and after the etching is completed, the portion of the first covering portion not exposed by the first barrier material is retained to form the filling portion.

24. The preparation method according to claim 23, wherein, Forming a first semiconductor material on a side of the first insulating material facing away from the first substrate by using a second mask includes: Forming a second semiconductor material on a side of the first insulating material facing away from the first substrate; Forming a metal conductive material on a side of the second semiconductor material facing away from the first substrate; Using the second mask to pattern the second semiconductor material and the metal conductive material, wherein the second mask includes a first region and a second region surrounding the first region; The first region is configured to: when patterning the second semiconductor material and the metal conductive material, remove the metal conductive material facing the first region and retain the second semiconductor material facing the first region to form the first covering portion; The second region is configured to: when patterning the second semiconductor material and the metal conductive material, retain the metal conductive material facing the second region to form a second connection portion, and retain the second semiconductor material facing the second region to electrically connect the second connection portion to the first covering portion.

25. The preparation method according to claim 24, wherein, The first region includes a circle or a square.

26. The preparation method according to claim 24, wherein The third mask includes a third region and a fourth region surrounding the third region; The third region is configured to: form a fourth via hole in the first barrier material, and the fourth via hole Exposes a first portion on the second insulating material; The fourth region is configured to: form a fifth via hole in the first barrier material, the fifth via hole at least partially surrounds the fourth via hole, and the fifth via hole exposes a second portion on the second insulating material; Etching the first insulating material, the first semiconductor material, and the second insulating material by using the first barrier material as a fourth mask includes: Removing the first portion to form the second via hole, removing the second portion to form the third via hole, and the third via hole exposes the second connection portion.

27. The preparation method according to claim 26, wherein, The fourth region includes a circular ring or a square ring.

28. The preparation method according to claim 23, wherein The manufacturing method further includes: Forming a first electrode material on the first substrate before forming the first insulating material; Forming a gate metal material on a side of the first electrode material facing away from the first substrate; Using a fifth mask to pattern the first electrode material and the gate metal material, wherein the fifth mask includes a fifth region and a sixth region surrounding the fifth region; The fifth region is configured to: when patterning the first electrode material and the gate metal material, retain the first electrode material facing the fifth region to form a first connection portion, and retain the gate metal material facing the fifth region to form a third connection portion on the first connection portion; The sixth region is configured to: when patterning the first electrode material and the gate metal material, retain the first electrode material facing the sixth region and remove the gate metal material facing the sixth region.

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