Array substrate, display panel, and display device

Abstract

An array substrate (10), a display panel (100), and a display device (1000). The array substrate (10) has a display area (AA) and a peripheral area (BB) provided at the periphery of the display area (AA). The array substrate (10) comprises a plurality of sub-pixels (PX) located in the display area (AA), and each sub-pixel (PX) comprises a first transistor (T1) and a pixel electrode (1051); the array substrate (10) comprises: a base substrate (101), and a first gate metal layer (102), a first source-drain metal layer (103), a planarization layer (104), and a pixel electrode layer (105) which are sequentially provided on one side of the base substrate (101); the first source-drain metal layer (103) comprises a drain pattern (T11) of the first transistor (T1); a first via hole (1041) is provided in the planarization layer (104); the pixel electrode layer (105) comprises a plurality of pixel electrodes (1051), and the pixel electrode (1051) and the drain pattern (T11) of the first transistor (T1) belonging to the same sub-pixel (PX) are connected by means of the first via hole (1041); the array substrate further comprises a first light-shielding pattern (11); the first light-shielding pattern (11) is located on the side of the first gate metal layer (102) distant from the base substrate (101); and the orthographic projection of the first via hole (1041) on the base substrate (101) is located within the orthographic projection of the first light-shielding pattern (11) on the base substrate (101).

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are widely used in the display field due to their small size, low power consumption, thinness, and radiation-free nature. With the development of display technology, their display quality has also been continuously improved along with advancements in manufacturing processes.

[0003] Summary of the Invention

[0004] On the one hand, an array substrate is provided. The array substrate has a display area and a peripheral area arranged outside the display area, the array substrate includes a plurality of sub-pixels located in the display area, and each of the plurality of sub-pixels includes a first transistor and a pixel electrode. The array substrate includes: a base substrate, a first gate metal layer, a first source-drain metal layer, a planar layer, and a pixel electrode layer. The first gate metal layer is arranged on one side of the base substrate; the first source-drain metal layer is arranged on the side of the first gate metal layer away from the base substrate; the first source-drain metal layer includes a drain pattern of the first transistor; the planar layer is arranged on the side of the first source-drain metal layer away from the base substrate; and the planar layer has a first via. The pixel electrode layer is arranged on the side of the planar layer away from the base substrate; the pixel electrode layer includes a plurality of pixel electrodes, and the pixel electrodes belonging to the same sub-pixel are connected to the drain pattern of the first transistor through the first via.

[0005] The array substrate further includes a first shading pattern; the first shading pattern is located on a side of the first gate metal layer away from the base substrate; the orthographic projection of the first via on the base substrate is located within the orthographic projection of the first shading pattern on the base substrate.

[0006] In some embodiments, the sub-pixels further include color resist blocks; the array substrate further includes: a color resist layer disposed between the first source / drain metal layer and the planar layer; the color resist layer includes multiple color resist blocks, wherein the color resist blocks belonging to the same sub-pixel overlap with the pixel electrode; a spacing region is defined between the color resist blocks of two adjacent sub-pixels in a first direction; the first via is located within the spacing region; and the first direction is a column direction of the array arrangement of the multiple sub-pixels. The dimension of the first light-shielding pattern in the first direction is greater than or equal to the dimension of the spacing region in the first direction.

[0007] In some embodiments, the array substrate further includes a first active film layer located between the first gate metal layer and the first source / drain metal layer; the first active film layer includes an active pattern of the first transistor. The first gate metal layer includes a first gate line, the first gate line overlapping the active pattern of the first transistor of a row of sub-pixels. The dimension of the first gate line in the first direction is smaller than the dimension of the first light-shielding pattern in the first direction.

[0008] In some embodiments, the array substrate further includes: a passivation layer, a common signal line layer, and a common electrode layer sequentially arranged on a side of the pixel electrode layer away from the base substrate, and the first light-shielding pattern is located in the common signal line layer.

[0009] In some embodiments, the common signal line layer includes a plurality of first shading lines, and the plurality of first shading lines extend along a second direction; the second direction is the row direction of the arrangement of the plurality of sub-pixel arrays; the orthographic projection of the first via holes of a row of sub-pixels on the substrate is located within the orthographic projection of a first shading line on the substrate; the first shading line includes a plurality of the first shading patterns.

[0010] In some embodiments, the first gate metal layer includes a first gate line; and an orthographic projection of a channel region of an active pattern of the first transistor on the base substrate is located within an orthographic projection of the first gate line on the base substrate.

[0011] In some embodiments, the array substrate further includes a second gate metal layer disposed between the first active film layer and the first source / drain metal layer, and the first light-shielding pattern is located in the second gate metal layer.

[0012] In some embodiments, the second gate metal layer includes a second gate line, which overlaps with the active pattern of the first transistor of a row of sub-pixels; in the sub-pixels, the active pattern of the first transistor overlaps with the first via, and the first light-shielding pattern is the portion of the second gate line that overlaps with the active pattern of the first transistor.

[0013] In some embodiments, the first gate metal layer includes a first gate line; and a portion of the first gate line overlapping with the active layer of the first transistor serves as a gate pattern of the first transistor.

[0014] In some embodiments, the second gate line is electrically connected to the first gate line in the peripheral region, and a portion of the second gate line that overlaps with the active layer of the first transistor serves as a top gate pattern of the first transistor.

[0015] In some embodiments, the second gate metal layer includes a second gate line, which overlaps with the active pattern of the first transistor of a row of sub-pixels; the second gate line includes a first shading structure and a second gate pattern connected thereto, the second gate pattern overlaps with the active pattern of the first transistor, and the second gate pattern serves as the gate pattern of the first transistor; the first shading pattern does not overlap with the active pattern of the first transistor.

[0016] In some embodiments, a second source-drain metal layer is further included between the first source-drain metal layer and the second gate metal layer, the second source-drain metal layer includes a data line, the data line extends along a first direction, and the orthographic projection of the data line on the substrate overlaps with the second gate pattern; wherein the first direction is the column direction in which the multiple sub-pixels are arranged.

[0017] In some embodiments, the array substrate further includes a second transistor disposed in the peripheral region; the gate pattern of the second transistor is located in the first gate metal layer. The array substrate further includes: a second active film layer disposed between the base substrate and the first gate metal layer, and a second source-drain metal layer disposed on a side of the first source-drain metal layer closer to the base substrate; the second active film layer includes an active pattern for the second transistor, and the second source-drain metal layer includes a source pattern and a drain pattern for the second transistor, as well as a source pattern for the first transistor.

[0018] On the other hand, a display panel is provided, comprising the array substrate described above, an opposing substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposing substrate.

[0019] In some embodiments, the display panel also includes a first boss and a second boss arranged between the array substrate and the opposing substrate, wherein the first boss is closer to the side of the array substrate relative to the second boss, and the first boss and the second boss are arranged opposite to each other; the orthographic projection of the first boss on the base substrate is located within the orthographic projection of the first shading pattern on the base substrate.

[0020] In some embodiments, the counter substrate further includes a black matrix light-shielding pattern, and an orthographic projection of the first light-shielding pattern on the base substrate is located within the orthographic projection of the light-shielding pattern on the base substrate.

[0021] In another aspect, a display device is provided, comprising: the display panel as described above, and a backlight module stacked with the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0023] FIG1A is a cross-sectional structural diagram of a display panel according to some embodiments;

[0024] FIG1B is a diagram showing the relationship between the sizes of the first via hole and the first gate pattern in some embodiments;

[0025] FIG2A is a cross-sectional structural diagram of a display panel according to some embodiments of the present disclosure;

[0026] FIG2B is a diagram illustrating the size relationship between the first via hole and the first light shielding pattern according to some embodiments of the present disclosure;

[0027] FIG3A is a film layer structure diagram of a first gate metal layer of an array substrate provided by some embodiments of the present disclosure;

[0028] FIG3B is a diagram showing a film layer stacking structure of a first active film layer of an array substrate provided in some embodiments of the present disclosure;

[0029] FIG3C is a diagram showing a film layer stacking structure of a second gate metal layer of an array substrate provided by some embodiments of the present disclosure;

[0030] FIG3D is a diagram showing a film layer stacking structure of a second interlayer dielectric layer of an array substrate provided by some embodiments of the present disclosure;

[0031] 3E is a diagram showing a film layer stacking structure of a second source / drain metal layer of an array substrate provided by some embodiments of the present disclosure;

[0032] 3F is a diagram illustrating a film layer stacking structure of a first source / drain metal layer of an array substrate provided by some embodiments of the present disclosure;

[0033] FIG3G is a diagram showing a film layer stacking structure of a color resist layer of an array substrate provided by some embodiments of the present disclosure;

[0034] FIG3H is a diagram showing a film layer stacking structure of a planar layer of an array substrate provided in some embodiments of the present disclosure;

[0035] FIG3I is a diagram showing a film layer stacking structure of a pixel electrode layer of an array substrate provided by some embodiments of the present disclosure;

[0036] FIG3J is a diagram showing a film layer stacking structure of a common signal line layer of an array substrate provided by some embodiments of the present disclosure;

[0037] FIG4A is another cross-sectional structural diagram of a display panel provided according to some embodiments of the present disclosure;

[0038] FIG4B is a diagram showing a film layer stacking structure of an array substrate provided according to some embodiments of the present disclosure;

[0039] FIG4C is a film layer structure diagram of a common signal line layer of an array substrate provided according to some embodiments of the present disclosure;

[0040] FIG5A is another cross-sectional structural diagram of a display panel provided by some embodiments of the present disclosure;

[0041] FIG5B is another cross-sectional structural diagram of a display panel provided by some embodiments of the present disclosure;

[0042] 6A is a diagram illustrating a film layer stacking structure of a first gate metal layer and a first active film layer of an array substrate provided in some embodiments of the present disclosure;

[0043] 6B is a diagram illustrating a film layer stacking structure of a first active film layer and a second gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0044] 6C is a diagram illustrating a film layer stacking structure of a first active film layer, a first gate metal layer, and a second gate metal layer of an array substrate provided in some embodiments of the present disclosure;

[0045] FIG6D is a diagram showing another film layer stacking structure of an array substrate provided in some embodiments of the present disclosure;

[0046] FIG6E is a diagram showing another film layer stacking structure of an array substrate provided in some embodiments of the present disclosure;

[0047] FIG7 is a planar structural diagram of an array substrate according to some embodiments of the present disclosure;

[0048] FIG8 is a structural diagram of a display panel provided by some embodiments of the present disclosure;

[0049] FIG9 is another cross-sectional structural diagram of a display panel provided by some embodiments of the present disclosure;

[0050] FIG10 is another cross-sectional structural diagram of a display device provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0058] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0059] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0060] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0061] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0062] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0063] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0064] At present, in order to achieve high PPI (Pixels Per Inch, pixel density), display panels generally use LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide) process to prepare thin film transistors, that is, oxide (Oxide) thin film transistors are used in the pixel area, and low temperature polycrystalline silicon (Low Temperature Poly-Silicon, referred to as LTPS) thin film transistors are used in the peripheral area. As shown in Figure 1A, in some embodiments, an array substrate is provided, the array substrate 10 having a display area AA and a peripheral area BB arranged outside the display area, the array substrate 10 includes a first transistor T1 located in the display area AA and a second transistor T2 located in the peripheral area BB. The first transistor T1 is, for example, an oxide thin film transistor, and the second transistor T2 is, for example, a low temperature polycrystalline silicon thin film transistor. The patterns of the first transistor T1 and the second transistor T2 located in the same film layer can be formed simultaneously.

[0065] In which, the display panel includes a first gate metal layer 102, the first gate metal layer 102 includes a gate pattern T24 of a second transistor T2 arranged in a peripheral area of ​​the display panel, and a first gate pattern 12 arranged in the display area. The first gate pattern 12 overlaps with the first transistor T1. In Figure 1A, the first gate pattern 12 serves as a light shielding bar 1021, which is used to shield light to prevent the characteristics of the oxide thin film transistor from being affected by light, while also avoiding other light leakage problems.

[0066] In some examples, during the preparation of the first gate metal layer, a photoresist is used as a mask to pattern the initial first gate metal layer to obtain a light shielding strip 1021. To meet the above-mentioned light shielding requirements, the width of the light shielding strip needs to be set to be relatively wide. For example, the dimension of the light shielding strip 1021 (first gate pattern 12) in the first direction X is L4', so that the coverage of the photoresist becomes higher. When preparing the second transistor in the peripheral area, in order to save preparation steps, the photoresist mask pattern PR used when preparing the first gate metal layer is used to perform a doping process on the active film layer of the second transistor, such as an N+ Doping process. Due to the high coverage of the photoresist, during the doping process, particles will bombard the surface of the photoresist and react with the photoresist to produce a carbonization reaction, and a large amount of gas will be produced as a by-product. The high coverage will cause a large amount of gas to overflow from the photoresist, affecting the vacuum level in the chamber and easily causing a vacuum alarm.

[0067] Based on this, in some embodiments of the present application, by arranging the film layers in the array substrate in layers and reasonably setting the position of the shading strips, it is possible to reduce the width of the shading strips while ensuring the above-mentioned shading requirements, so as to prevent equipment alarms from occurring during the preparation process and improve the reliability of the display panel.

[0068] The array substrate, display panel, and display device provided by the present disclosure are respectively introduced below.

[0069] As shown in Figures 1A, 2A, 4A, 5A, 5B and 9, the present disclosure provides multiple embodiments of an array substrate. To clearly describe the film layer structure of the array substrate, the film layers included in the array substrate are listed below. The array substrate 10 includes a base substrate 101, and a buffer layer 116, a second active film layer 112, a first gate insulation layer 117, a first gate metal layer 102, a first interlayer dielectric layer 113, a first active film layer 107, a second gate insulation layer 115, a second gate metal layer 110, a second interlayer dielectric layer 114, a second source-drain metal layer 111, an interlayer insulating layer 118, a first source-drain metal layer 103, a color resist layer 106, a planarization layer 104, a pixel electrode layer 105, a passivation layer 108, a common signal line layer 119 and a common electrode layer 109 stacked in sequence on the base substrate 101.

[0070] 3J , 4B , and 6E , the first gate metal layer 102 includes a plurality of first gate lines S1, the first active film layer 107 includes a plurality of active patterns T13 of first transistors, the second gate metal layer 110 includes a plurality of second gate lines S2, the second source / drain metal layer 111 includes a plurality of data lines Dt, and a source pattern T12 of the first transistor (see FIG1A ), the color resist layer 106 includes a plurality of color resist blocks 106 a, the planar layer 104 includes a plurality of first vias 1041, the pixel electrode layer 105 includes a plurality of pixel electrodes 1051, and the common signal line layer 119 includes a plurality of common signal lines 1191 (refer to FIG2A , FIG4A , FIG5A , FIG5B , and FIG9 ). 3J , 4B , and 6E , and in combination with FIG. 3D and 6C , T12′ is a source connection pillar connecting the active pattern T13 of the first transistor and the source pattern T12, and the source connection pillar T12′ passes through the second gate insulating layer 115 and the second interlayer dielectric layer 114 , and T11′ is a drain connection pillar connecting the active pattern T13 of the first transistor and the drain pattern T11, and the drain connection pillar T11′ passes through the second gate insulating layer 115 , the second interlayer dielectric layer 114 , and the interlayer insulating layer 118 .

[0071] The array substrates mentioned in the following embodiments all conform to the above film layer arrangement, and the structure of each film layer is described in detail below.

[0072] In some embodiments, as shown in Figures 2A, 4A, 5A, and 5B, the array substrate includes a plurality of sub-pixels PX, each of which includes a first transistor T1 and a pixel electrode 1051. The first transistor T1 is electrically connected to the pixel electrode 1051. The pixel electrode 1051 forms a capacitor Cst with an opposing common electrode, and a drain pattern T11 of the first transistor T1 is connected to the pixel electrode.

[0073] The array substrate 10 includes a base substrate 101, a first gate metal layer 102, a first source / drain metal layer 103, a planarization layer 104, and a pixel electrode layer 105. The first gate metal layer 102 is disposed on one side of the base substrate 101, and the first source / drain metal layer 103 is disposed on a side of the first gate metal layer 102 away from the base substrate 101. The first source / drain metal layer 103 includes a drain pattern T11 of the first transistor T1. The planarization layer 104 is disposed on a side of the first source / drain metal layer 103 away from the base substrate 101. The planarization layer 104 includes a first via 1041. Exemplarily, the material of the planarization layer 104 is an organic material, such as a resin. The pixel electrode layer 105 is arranged on the side of the flat layer 104 away from the base substrate 101. The pixel electrode layer 105 includes multiple pixel electrodes 1051. The pixel electrodes belonging to the same sub-pixel are connected to the drain pattern of the first transistor through the first via hole; that is, a sub-pixel PX includes the first transistor T1, the pixel electrode 1051 and the first via hole 1041.

[0074] The array substrate 10 further includes a first light-shielding pattern 11. As shown in FIG2A , the first light-shielding pattern 11 is located in the common signal line layer 119. As shown in FIG4A , the first light-shielding pattern 11 is located in the second gate metal layer 110. As shown in FIG5A and FIG5B , the first light-shielding pattern 11 is located in the second gate metal layer 110. The first light-shielding pattern 11 is located on the side of the first gate metal layer 102 away from the base substrate 101; the orthographic projection of the first via 1041 on the base substrate 101 is located within the orthographic projection of the first light-shielding pattern 11 on the base substrate 101.

[0075] As shown in Figures 2A, 4A, and 5A, the first transistor T1 is located on the side of the first gate metal layer 102 away from the substrate. The first transistor T1 includes an active pattern T13, a gate pattern T14, a drain pattern T11, and a source pattern T12. The planar layer 104 and the pixel electrode layer 105 are sequentially arranged on the side of the first transistor T1 away from the substrate. The pixel electrode 1051 is connected to the drain pattern T11 of the first transistor T1 through a first via 1041. At the location of the first via 1041, liquid crystal arrangement is easily disrupted, resulting in poor light leakage. Therefore, a light shielding structure is required to shield the first via to prevent poor light leakage.

[0076] In the array substrate shown in Figure 1A, the first gate metal layer 102 includes a first gate pattern 12 located in the display area. The first gate pattern 12 serves as a light-shielding bar 1021. The light-shielding bar needs to block the first via 1041. Therefore, the size of the light-shielding bar 1021 needs to be larger than the size of the first via. At the same time, the light-shielding bar needs to shield the first transistor. The size of the light-shielding bar also needs to be larger than the size of the active pattern T13 of the first transistor T1. This causes the size L4' of the light-shielding bar (first gate pattern) to increase, the coverage rate of the photoresist to increase, and triggers a vacuum alarm phenomenon in the subsequent doping process.

[0077] For example, as shown in Figure 1B, Figure 1B is a dimensional relationship diagram of the first via 1041 of the flat layer and the shading strip 1021. In order to meet the shading requirements, the width of the shading strip 1021 is e+2*y+2f, e is the bottom size of the first via 1041, e can be 2.0um, e+2*y is the top size of the first via 1041, e+2*y can be 4.0um, f is the process fluctuation between the shading strip and the flat layer (including the fluctuation of the overlay and the fluctuation of the size), f can be 0.5um, that is, the size L4' of the shading strip is 5.0um, which can be seen that the size is relatively large.

[0078] 2A , 4A , and 5A , in some embodiments of the present disclosure, the orthographic projection of the first via hole 1041 on the base substrate 101 is arranged to be within the orthographic projection of the first shading pattern 11 on the base substrate 101 . That is, the first shading pattern 11 can completely block the first via hole 1041 , and at the same time avoid the problem of light leakage at the position of the first via hole 1041 due to liquid crystal disorder, thereby improving the liquid crystal display light efficiency of the display panel. It is understood that the first light-shielding pattern 11 is located on the side of the first gate metal layer 102 away from the base substrate 101. That is, the first light-shielding pattern 11 is not provided on the first gate metal layer 102. The first light-shielding pattern 11 can be distributed on other film layers of the array substrate 10 other than the first gate metal layer, which is equivalent to arranging the structure that performs the light-shielding function on other film layers other than the first gate metal layer 102. That is, the first gate pattern 12 does not need to block the first via hole. Compared with the solution of FIG1A, the size of the first gate pattern 12 can be reduced, and the coverage of the photoresist used in preparing the first gate metal layer is reduced. In this way, when the second transistor is prepared and the photoresist mask pattern used in preparing the first gate metal layer is used for the doping process, it is possible to avoid affecting the vacuum level of the chamber, thereby avoiding the vacuum level alarm phenomenon during the doping process. Therefore, in the array substrate provided by some embodiments of the present disclosure, while ensuring that the first via hole is blocked and the light leakage problem is avoided, the photoresist coverage can be reduced, thereby solving the vacuum level alarm problem during the doping process.

[0079] Exemplarily, the first gate pattern 12 is located on the side of the first transistor T1 close to the substrate. The first gate pattern 12 can shield the first transistor from light, preventing the characteristics of the first transistor from being altered by light. Exemplarily, the first transistor can be a non-photosensitive oxide transistor. That is, when light irradiates the surface of the non-photosensitive oxide transistor, the characteristics of the non-photosensitive oxide transistor will not be altered. In this case, there is no need to provide a light shielding strip on the first gate metal layer 102. That is, the first gate pattern does not need to serve as a light shield. As a result, the size of the first gate pattern can be further reduced, or even removed, to further reduce the coverage of the photoresist and further avoid vacuum alarm issues during the doping process.

[0080] For example, as shown in Figures 3B and 6A, the first gate metal layer 102 includes a first gate line S1, which overlaps with the active pattern T13 of the first transistor of a row of sub-pixels; the overlapping portion of the first gate line S1 and the active pattern T13 of the first transistor is the first gate pattern 12, that is, the first gate line S1 includes multiple first gate patterns.

[0081] It should be noted that the first gate line S1 may transmit a gate scanning signal or may not transmit an electrical signal. When the first gate line S1 transmits a gate scanning signal, the first gate pattern 12 may serve as a bottom gate pattern of the first transistor.

[0082] If the first transistor T1 is a non-photosensitive oxide transistor and the first gate line S1 does not transmit an electrical signal, the first gate line S1 may be eliminated.

[0083] It should be noted that the first transistor disclosed in the present invention is an oxide thin film transistor, which has a small off-state current, a strong charge retention capability, and good stability.

[0084] In some embodiments, referring to Figures 1A, 2A, 4A, 5A, and 5B, a subpixel includes a first transistor T1, a pixel electrode 1051, a first via 1041, and a color resist block 106a. The array substrate 10 includes a color resist layer 106 disposed between the first source / drain metal layer 103 and the planar layer 104. The color resist layer 106 includes a plurality of color resist blocks 106a. Referring also to Figures 3H, 4B, and 6D, the color resist blocks 106a belonging to the same subpixel PX overlap with the pixel electrode 1051. A gap region G is defined between the color resist blocks 106a of two adjacent subpixels in a first direction X. The first via 1041 is located within the gap region G. The first direction is the column direction of the array arrangement of the plurality of subpixels.

[0085] Exemplarily, the color resist layer 106 includes a first color resist block 1061 and a second color resist block 1062. The first color resist block 1061 overlaps with the pixel electrode 1051 and belongs to the same sub-pixel PX. The first color resist block 1061 and the second color resist block 1062 are adjacent to each other along the first direction X. Along the first direction X, a gap region G is defined between the first color resist block 1061 and the second color resist block 1062, and the first via 1041 is located within the gap region G. As shown in Figures 2A and 2B, and Figures 7 and 8, a dimension L1 of the first light-shielding pattern 11 in the first direction X is greater than or equal to a dimension L2 of the gap region G in the first direction X, i.e., L1>L2.

[0086] For example, the color resist layer 106 may include red color resist blocks, green color resist blocks, and blue color resist blocks. The first color resist blocks 1061 may be any one of these, and the second color resist blocks 1062 may be any one of these. Along the first direction X, the first color resist blocks 1061 and the second color resist blocks 1062 may be color resist blocks of the same color or of different colors.

[0087] It should be noted that Figures 3A to 3J are plan views of the various film layers in the array substrate shown in Figure 2A, Figures 4B and 4C are plan views of the various film layers in the array substrate shown in Figure 4A, and Figures 6A to 6E are plan views of the various film layers in the array substrate shown in Figure 5A. Referring to Figures 3H and 3I, and Figures 4B and 6D, first via 1041 is located within spacing region G. In other words, dimension L2 of spacing region G between first color resist block 1061 and second color resist block 1062 in the first direction X is greater than dimension L3 of first via 1041 in the first direction X.

[0088] For example, referring to Figures 3H and 3I, Figures 4B and 6D, the size L1 of the first light-shielding pattern 11 in the first direction X is larger than the size L2 of the spacing area G in the first direction X. It can be seen from the above that the first via 1041 is located in the spacing area G. It can be understood that the size L1 of the first light-shielding pattern 11 in the first direction X is also larger than the size L3 of the first via 1041 in the first direction X. At this time, the first light-shielding pattern 11 can block the spacing area G between the first color block 1061 and the second color block 1062 while also blocking the first via 1041 to prevent poor display problems caused by light leakage.

[0089] For example, referring to FIG3I , the dimension L1 of the first light-shielding pattern 11 in the first direction X is equal to the dimension L2 of the spacing region G in the first direction X. As can be seen from the above, the first via 1041 is located within the spacing region G. It can be understood that the dimension L1 of the first light-shielding pattern 11 in the first direction X is greater than the dimension L3 of the first via 1041 in the first direction X. In this case, the first light-shielding pattern 11 can block the spacing region G between the first color resist block 1061 and the second color resist block 1062 while also blocking the first via 1041, thereby preventing poor display caused by light leakage. Therefore, in the array substrate provided in some embodiments of the present disclosure, while ensuring that the first via is blocked and the gaps between adjacent color resist blocks are blocked to avoid light leakage, the photoresist coverage can be reduced, thereby resolving the vacuum alarm issue during the doping process.

[0090] In some embodiments, referring to Figures 2A, 4A, 5A, and 5B, the array substrate 10 further includes a first active film layer 107 located between the first gate metal layer 102 and the first source / drain metal layer 103. The first active film layer 107 includes an active pattern T13 of the first transistor T1. The first gate metal layer 102 includes a first gate line S1, which overlaps with the active pattern T13 of the first transistor of a row of sub-pixels. The overlapping portion of the first gate line S1 and the active pattern T13 of the first transistor is a first gate pattern 12. The first gate metal layer 102 includes the first gate pattern 12, which overlaps with the active pattern T13 of the first transistor T1. Referring to Figures 2A and 2B, a dimension L4 of the first gate pattern 12 in the first direction X is smaller than a dimension L1 of the first light-shielding pattern 11 in the first direction X. In other words, the dimension of the first gate line S1 in the first direction is smaller than the dimension of the first light-shielding pattern in the first direction.

[0091] It can be understood that, referring to FIG3B , the active pattern of the first transistor T1 includes the channel region Sg of the first transistor T1. The first gate pattern 12 overlaps with the active pattern of the first transistor T1. This can be achieved by overlapping the orthographic projection of the first gate pattern 12 on the substrate 101 with the channel region Sg of the active pattern of the first transistor T1. Alternatively, the orthographic projection of the channel region Sg of the active pattern of the first transistor T1 on the substrate 101 is located within the orthographic projection of the first gate pattern 12 on the substrate 101. In other words, the first gate pattern 12 can completely block the channel region Sg of the active pattern of the first transistor T1 to prevent light leakage.

[0092] It should be noted that the first gate pattern 12 is arranged on the first gate metal layer 102. At this time, the first gate pattern 12 is only used to shield the channel region Sg of the first transistor T1. For example, the size of the channel region Sg of the first transistor T1 in the first direction X is 2 μm. Taking into account process fluctuations, the size L4 of the first gate pattern 12 in the first direction X is 3 μm to meet the light shielding requirements. Therefore, as shown in Figures 2A and 2B, the size L4 of the first gate pattern 12 in the first direction X is smaller than the size L1 of the first light shielding pattern 11 in the first direction X.

[0093] In the case where the first light-shielding pattern 11 is provided and the first gate pattern 12 is provided at the same time, the first transistor T1 can be a photosensitive oxide transistor, and the first gate pattern 12 can shield the channel region of the photosensitive oxide transistor to prevent the characteristics of the photosensitive oxide transistor from being changed by light. Furthermore, the first light-shielding pattern 11 and the first gate pattern 12 are provided at different film layers. Compared with the method in the related art in which the first gate pattern provided in the first gate metal layer simultaneously shields the channel region of the first transistor, shields the first via, and shields the gap between adjacent color resist blocks, in this embodiment, the first light-shielding layer is used to shield the first via and shield the gap between adjacent color resist blocks, and the first gate pattern 12 is only used to shield the channel region of the first transistor. The size of the first gate pattern 12 located in the first gate metal layer 102 in the first direction X can be reduced, and thus, the coverage rate of the photoresist can be reduced during the preparation process, thereby avoiding the phenomenon of equipment alarm during the doping process.

[0094] Some embodiments regarding the location of the first light-shielding pattern are described below.

[0095] In some embodiments, the setting position of the first light-shielding layer is: referring to Figures 4A to 4C, the array substrate 10 also includes a passivation layer 108, a common signal line layer 119 and a common electrode layer 109, which are sequentially arranged on the side of the pixel electrode layer 105 away from the base substrate 101, and the first light-shielding pattern 11 is located in the common signal line layer 119.

[0096] For example, as shown in Figure 2A, the first light-shielding pattern 11 is located on the side of the passivation layer 108 close to the common electrode layer 109. The first light-shielding pattern 11 is located in the common signal line layer 119, which can meet the requirements of blocking the first via 1041 and the spacing area G. Thus, the size of the first gate pattern is reduced, thereby avoiding the occurrence of equipment alarms in subsequent doping processes.

[0097] As shown in FIG. 4B to FIG. 4C , the common signal line layer 119 includes a plurality of first light-shielding lines 1192 , and the plurality of first light-shielding lines 1192 extend along a second direction Y; the second direction Y is a row direction in which the plurality of sub-pixel arrays are arranged.

[0098] The orthographic projection of the first via holes 1041 of a row of sub-pixels on the base substrate is located within the orthographic projection of a first light-shielding line 1192 on the base substrate; the first light-shielding line includes a plurality of first light-shielding patterns 11 .

[0099] The common signal line layer 119 includes a plurality of common signal lines 1191, which extend along the first direction X. The second source-drain metal layer 111 includes a plurality of data lines Dt, which extend along the first direction X. One data line Dt is connected to the source pattern of the first transistor of a column of sub-pixels. One data line Dt overlaps with one common signal line 1191, and the orthographic projection of the boundary line of two columns of color resist blocks adjacent to the common signal line 1192 is located on the common signal line 1191.

[0100] The common signal line 1192 is used to transmit a common voltage signal. The common signal line 1192 is connected to the common electrode layer and is used to transmit signals to the common electrode layer. The material of the common electrode layer is metal, which has lower resistance than the material of the common electrode layer (indium tin oxide). Using the common signal line 1192 to transmit a common voltage signal is beneficial to improving the voltage uniformity of the common electrode layer, improving the signal transmission effect, reducing losses, and thereby improving the uniformity of light within the plane. The common signal line is located between two adjacent columns of color resist blocks, and can block the edges of the color resist blocks to avoid color deviation at a wide viewing angle.

[0101] For example, the orthographic projection of a first shielding line 1192 on the substrate lies between the orthographic projections of two adjacent rows of color-resistance blocks on the substrate. This allows the first shielding line to block both the spacing between the two adjacent rows of color-resistance blocks and the first vias of a row of sub-pixels. For a given sub-pixel, the first shielding line 1192 includes multiple first shielding patterns 11. These first shielding patterns 11 can block the spacing G between the first color-resistance block 1061 (the color-resistance block of the given sub-pixel) and the second color-resistance block 1062 (the resistance block of the sub-pixel adjacent to the given sub-pixel), while also blocking the first vias 1041 of the given sub-pixel, thereby preventing display defects caused by light leakage.

[0102] Multiple common signal lines 1192 extend along the first direction X. One common signal line 1192 is connected to multiple first light-shielding lines 1192, and one first light-shielding line 1192 is connected to multiple common signal lines 1192. The multiple common signal lines and the multiple first light-shielding lines can be integrally formed. It can be understood that the width of the common signal lines located within the spacing region G is increased and connected to form the first light-shielding lines 1192, while the width of the remaining portions remains unchanged.

[0103] It should be noted that, in the stacking diagram of the film layers of the array substrate shown in Figure 4C, the difference between the array substrate shown in Figures 4A to 4C and the array substrate shown in Figures 2A to 3J is that the width of the second gate line S2 in the second gate metal layer 110 of the array substrate shown in Figures 4A to 4C is smaller than the width of the second gate line S2 in the second gate metal layer 110 of the array substrate shown in Figures 2A to 3J, and the pattern of the common signal line layer of the array substrate shown in Figures 4A to 4C has been changed compared to the common signal line layer of the array substrate shown in Figures 2A to 3J, and the remaining film layers can be referenced to each other.

[0104] It should be noted that in addition to preventing light leakage, the above-mentioned first shading pattern 11 also has the function of ensuring the uniformity of light within the surface of the array substrate 10 because it is connected to the common signal line 1191 and also transmits a common voltage signal, which can reduce production costs to a certain extent.

[0105] Exemplarily, the material of the first light-shielding pattern is metal.

[0106] The size of the first light-shielding pattern 11 in the first direction X may be set with reference to the size setting of the light-shielding strip 1021 (first gate pattern 12 ) in FIG. 1B . For example, the size of the first light-shielding pattern 11 in the first direction X is 5 μm.

[0107] When the first light-shielding pattern 11 is located on the side of the passivation layer 108 close to the common electrode layer 109, in some embodiments, the orthographic projection of the active pattern of the first transistor T1 on the base substrate 101 is located within the orthographic projection of the first gate pattern 12 on the base substrate 101. In other words, the orthographic projection of the channel region of the active pattern of the first transistor on the base substrate is located within the orthographic projection of the first gate line on the base substrate.

[0108] It can be understood that the first gate pattern 12 can completely block the active pattern of the first transistor T1, that is, the first gate pattern 12 can block the channel region Sg of the first transistor T1, thereby preventing the characteristics of the first transistor T1 from being affected by light and changing. Moreover, since the first gate pattern 12 at this time is only used to block the channel region Sg of the first transistor T1, the size of the first gate pattern 12 can be greatly reduced, for example, from 5 μm in the embodiment of FIG1A to 3 μm in this embodiment. Therefore, the coverage of the photoresist can be reduced during the preparation process, thereby avoiding the phenomenon of equipment alarm during the doping process.

[0109] 4A , the gate pattern T14 of the first transistor T1 is located on the second gate metal layer 110. The first gate pattern 12 is used to shield the active layer pattern of the first transistor, and the first gate pattern 12 does not transmit electrical signals.

[0110] The first light shielding pattern 11 is provided to shield the first via hole 1041 and the spacer region G, and the first gate pattern 12 is provided to shield the channel region Sg of the first transistor T1 , thereby meeting the light shielding requirement and reducing the size of the first gate pattern.

[0111] In other embodiments, the first transistor adopts a non-photosensitive oxide transistor, and there is no limitation on the size relationship between the first gate pattern 12 and the active pattern of the first transistor T1. The first gate pattern does not need to play a light shielding role, the size of the first gate pattern can be further reduced, and the first gate pattern 12 can even be removed.

[0112] In other embodiments, the first light-shielding layer is disposed as follows: Referring to FIG. 2A and FIG. 3A to FIG. 3J , the array substrate 10 further includes a second gate metal layer 110 disposed between the first active film layer 107 and the first source / drain metal layer 103, and the first light-shielding pattern 11 is located in the second gate metal layer 110. The following describes an embodiment in which the first light-shielding pattern 11 is located in the second gate metal layer 110.

[0113] For example, referring to FIG2B , the first light-shielding pattern 11 is located on the second gate metal layer 110 and on the side of the active pattern T13 of the first transistor T1 away from the substrate. The first light-shielding pattern 11 can meet the requirements of shielding the first via 1041 and the spacing region G, thereby reducing the size of the first gate pattern 12. Furthermore, the second gate metal layer 110 is located on the side of the pixel electrode layer 105 close to the substrate 101. Therefore, the electric field generated by the second gate metal layer 110 is shielded by the electric field of the pixel electrode layer 105. Accordingly, the electric field generated by the second gate metal layer 110 does not affect the electric field distribution between the pixel electrode layer 105 and the common electrode layer 109, thereby not affecting the liquid crystal light efficiency of the display panel, thereby improving the display effect.

[0114] Referring to FIG. 2B , FIG. 2B illustrates the relationship between the dimensions of the first via 1041 in the planar layer 104 and the first light-shielding pattern located in the second gate metal layer 110. For example, the bottom dimension e of the first via 1041 is, for example, 2 μm, and the top dimension g = e + 2*y is, for example, 4 μm. In this case, the dimension L1 of the first light-shielding pattern 11 in the first direction X is L1 = e + 2*y + 2f, where f represents process fluctuation. This means that L1 is at least 5 μm to meet light-shielding requirements. The first light-shielding pattern 11 shown in FIG. 2B serves only as a diagram illustrating the relationship between the dimensions of the first via 1041 in the first direction X and does not represent its specific location.

[0115] In some embodiments, referring to Figures 2A and 3G , the second gate metal layer 110 includes a second gate line S2, which overlaps with the active pattern T13 of the first transistor T1 of a row of sub-pixels. In the sub-pixels, the active pattern T13 of the first transistor overlaps with the first via 1041, and the first light-shielding pattern 11 is the portion of the second gate line S2 that overlaps with the active pattern T13 of the first transistor.

[0116] The first gate metal layer 102 includes a first gate line S1; the portion of the first gate line S1 that overlaps with the active pattern T13 of the first transistor (a first gate pattern 12) serves as the gate pattern of the first transistor. The first gate pattern 12 serves as the gate pattern T14 of the first transistor T1. The orthographic projection of the first gate pattern 12 on the substrate 101 is located within the orthographic projection of the active pattern of the first transistor T1 on the substrate 101. In this case, the first transistor T1 is a bottom-gate transistor.

[0117] For example, as shown in Figures 2A and 3B, the first gate pattern 12 serves only as the gate pattern of the first transistor T1 and is not used to shield the active pattern T13 of the first transistor T1. In this case, for example, the dimension of the channel region Sg of the first transistor T1 in the first direction X is 2 μm. Since the gate of the first transistor T1 overlaps with the channel region Sg, the dimension of the first gate pattern 12 in the first direction X only needs to be 2 μm. The provision of the first gate pattern 12 can further reduce the coverage of the photoresist used in the fabrication process, thereby avoiding equipment alarms during the doping process.

[0118] It should be noted that when the first gate pattern 12 is used as the gate pattern of the first transistor T1 , the first transistor T1 may be a non-photosensitive oxide transistor to prevent light from affecting its characteristics and thus causing adverse effects on the display of the display panel.

[0119] In some embodiments, as shown in Figures 3C to 3I, Figures 3C to 3I are planar stacking views corresponding to Figure 2B. That is, the first light-shielding patterns 11 shown in Figures 3C to 3I are all located in the second gate metal layer 110. Referring to Figures 3B, 3D, and 3F, the array substrate 10 further includes a first interlayer dielectric layer 113 and a second interlayer dielectric layer 114. The first interlayer dielectric layer 113 is disposed between the first gate metal layer 102 and the first active film layer 107, and the second interlayer dielectric layer 114 is disposed between the second gate metal layer 110 and the first source / drain metal layer 103. Exemplarily, the material of the first interlayer dielectric layer 113 and the second interlayer dielectric layer 114 can be any one of silicon nitride, silicon oxide, or silicon oxynitride, or a combination of any two of these materials.

[0120] In some embodiments, referring to Figures 2A and 3C, the second gate line S2 is electrically connected to the first gate line S1 in the peripheral area BB. For example, the second gate line S2 is connected through a via hole penetrating the first interlayer dielectric layer 113 and the second gate insulation layer 115. The portion of the second gate line S2 that overlaps with the active pattern T13 of the first transistor serves as the top gate pattern of the first transistor.

[0121] That is, the first light-shielding pattern 11 overlaps with the active pattern of the first transistor, and the first light-shielding pattern 11 is electrically connected to the first gate pattern 12 in the peripheral region BB.

[0122] Exemplarily, the first light-shielding pattern 11 is electrically connected to the first gate pattern 12 in the peripheral region BB via a through-hole. For example, a first interlayer dielectric layer 113 and a second gate insulating layer 115 are sequentially disposed between the first gate metal layer 102 and the second gate metal layer 110. The first interlayer dielectric layer 113 is located near the side of the first gate metal layer 102, and the via is a via in the first interlayer dielectric layer 113 and the second gate insulating layer 115. Through this electrical connection, the second gate line S2 and the first gate line S1 transmit scan signals synchronously. In other words, the first light-shielding pattern 11 and the first gate pattern transmit scan signals synchronously. The first light-shielding pattern 11 is located on the side of the active pattern of the first transistor T1 away from the substrate and overlaps with the active pattern of the first transistor T1. The first light-shielding pattern can serve as the top gate pattern of the first transistor, and the first gate pattern can serve as the bottom gate pattern of the first transistor. This changes the bottom-gate structure of the first transistor T1 to a top-bottom gate structure, thereby improving transmission stability and enhancing the reliability of the display panel.

[0123] The following describes another embodiment in which the first light-shielding pattern 11 is located in the second gate metal layer 110. As shown in Figures 5A and 5B, Figures 5A and 5B are cross-sectional views of the same array substrate at different locations. As shown in Figures 6A to 6E, Figures 6A to 6E are plan views of the various film layers of the array substrate shown in Figures 5A and 5B. Figure 5A is a cross-sectional view taken at position AA in Figure 6C, and Figure 5B is a cross-sectional view taken at position BB in Figure 6C.

[0124] In some embodiments, referring to Figures 6A to 6E , the second gate metal layer 110 includes a second gate line S2, which overlaps with the active pattern T13 of the first transistor of a row of sub-pixels. The second gate line S2 includes a first light-shielding pattern 11 and a second gate pattern 13 connected thereto. The second gate pattern 13 overlaps with the active pattern of the first transistor, and the second gate pattern 13 serves as the gate pattern of the first transistor; the first light-shielding pattern 11 does not overlap with the active pattern of the first transistor.

[0125] The first light-shielding pattern 11 is located in the second gate metal layer 110, and the first light-shielding pattern 11 does not overlap with the active pattern T13 of the first transistor. The second gate metal layer 110 also includes a second gate pattern 13, and the second gate pattern overlaps with the active pattern T13 of the first transistor. The second gate pattern 13 serves as the gate pattern of the first transistor T1, and the second gate pattern 13 is connected to the first light-shielding pattern 11.

[0126] It can be understood that the second gate pattern 13 only serves as the gate of the first transistor T1 and is not used to shield the channel region Sg of the first transistor T1. At this time, the size of the channel region Sg of the first transistor T1 in the first direction X is, for example, 2 μm. Since the gate of the first transistor T1 overlaps with the channel region Sg, the size L5 of the second gate pattern 13 in the first direction X only needs to meet 2 μm.

[0127] Exemplarily, referring to Figure 6B, the second gate pattern 13 is connected to the first shading pattern 11 along the second direction Y, wherein the second direction Y is perpendicular to the first direction X, and the dimension L1 of the first shading pattern 11 in the first direction X is the width described above. It can be seen from Figure 10 that the dimension L1 of the first shading pattern 11 in the first direction X is greater than the dimension L5 of the second gate pattern 13 in the first direction X.

[0128] In some examples, as shown in FIG. 6B , the first light-shielding pattern 11 and the second gate pattern 13 are arranged along the second direction Y and are sequentially connected. On a surface parallel to the base substrate 101 , the first direction X is perpendicular to the second direction Y.

[0129] As shown in Figures 6A to 6C, the first gate metal layer 102 includes a plurality of first gate lines S1, and a plurality of second gate lines S2 are arranged on the second gate metal layer 110. The plurality of second gate lines S2 all extend along the second direction Y. A first gate line passes through the active pattern T13 of a row of first transistors, and a second gate line passes through the active pattern T13 of a row of first transistors. A first gate line overlaps with a second gate line, and the second gate line S2 includes a plurality of first light-shielding patterns 11 and a plurality of second gate patterns 13 that are alternately arranged.

[0130] It should be noted that when the first transistor T1 is a photosensitive oxide transistor, in addition to the first light-shielding pattern 11 and the second gate pattern 13, the array substrate 10 also includes a first gate pattern 12 disposed in the first gate metal layer 102. In this case, the first gate pattern 12 can shield the channel region of the first transistor T1. The provision of the first gate pattern 12 can prevent the first transistor T1 from being affected by light and causing changes in its characteristics, which in turn can affect signal transmission on the display panel. As can be seen from the foregoing, the first gate pattern 12 can be 3μm in diameter. Compared to the related art method of disposing the entire light-shielding structure in the first gate metal layer 102, the dimension L4 of the first gate pattern 12 in the first gate metal layer 102 in the first direction X can be significantly reduced, further reducing the coverage of the photoresist used in the manufacturing process and avoiding equipment alarms during the doping process. When the first transistor T1 is a non-photosensitive oxide transistor, the second gate pattern 13 may not be provided in the array substrate 10 . The non-photosensitive oxide transistor has no effect on its characteristics when exposed to light, and the device alarm phenomenon during the doping process can be avoided.

[0131] In some embodiments, referring to FIG. 5B and FIG. 6C , an orthographic projection of the active pattern of the first transistor T1 on the base substrate 101 is located within an orthographic projection of the first gate pattern 12 on the base substrate 101 .

[0132] By way of example, referring to Figures 5B and 6C , the orthographic projection of the active pattern of the first transistor T1 on the substrate 101 is located within the orthographic projection of the first gate pattern 12 on the substrate 101. In other words, the first gate pattern 12 serves to shield the channel region of the first transistor T1. In this case, the first transistor T1 is a photosensitive oxide transistor, and a dimension L4 of the first gate pattern 12 in the first direction X is greater than a dimension L6 of the active pattern T13 of the first transistor T1 in the first direction X. As shown in Figure 7 , the active pattern of the first transistor T1 is located in the first active film layer 107, and the orthographic projection of the active pattern of the first transistor T1 on the substrate 101 is located within the orthographic projection of the first gate pattern 12 on the substrate 101.

[0133] In some embodiments, as shown in Figure 6D, the array substrate 10 further includes a second source-drain metal layer 111 disposed between the first source-drain metal layer 103 and the second gate metal layer 110, and the second source-drain metal layer 111 includes a data line Dt, which extends along a first direction X, and the orthographic projection of the data line Dt on the base substrate 101 overlaps with the second gate pattern 13; wherein the first direction X is perpendicular to the direction in which the second gate pattern 13 and the first light-shielding pattern 11 are arranged.

[0134] For example, referring to FIG6D , the data line Dt is located in the second source-drain metal layer 111 and extends along the first direction X. According to FIG6D , the orthographic projection of the spacing region G between the first color resist block 1061 and the second color resist block 1062 on the base substrate 101 partially overlaps with the orthographic projection of the second gate pattern 13 on the base substrate 101. The second gate pattern 13 has the function of shielding the spacing region G to prevent light leakage. Among them, the size L5 of the second gate pattern 13 in the first direction X is less than or equal to the size L2 of the spacing area G in the first direction X. Referring to Figure 6D, when the size L5 of the second gate pattern 13 in the first direction X is equal to the size L2 of the spacing area G in the first direction X, the second gate pattern 13 can be used to block the edge position of the spacing area G to prevent light leakage; referring to Figure 6E, when the size L5 of the second gate pattern 13 in the first direction X is less than the size L2 of the spacing area G in the first direction X, since the orthographic projection of the data line Dt on the base substrate 101 overlaps with the second gate pattern 13, the data line Dt can make up for the area in the spacing area G that is not blocked by the second gate pattern 13, thereby achieving secondary blocking and further preventing the occurrence of light leakage.

[0135] In some embodiments, referring to Figures 1A, 2A, 4A, 5A, and 5B, the array substrate 10 further includes a second transistor T2 disposed in the peripheral area BB; the gate pattern of the second transistor T2 is located in the first gate metal layer 102; the second active film layer 112 includes an active pattern T23 of the second transistor T2; the first gate metal layer 102 includes a gate pattern T24 of the second transistor T2; the second source-drain metal layer 111 includes a source pattern T21 and a drain pattern T22 of the second transistor T2, and a source pattern T12 of the first transistor T1. The second transistor T2 is a top-gate transistor.

[0136] For example, referring to Figures 2A, 2B and 7, the second transistor T2 is arranged in the peripheral area BB of the array substrate 10. The second transistor T2 is a low-temperature polysilicon transistor, and the corresponding material of the second active film layer 112 arranged between the base substrate 101 and the first gate metal layer 102 is a low-temperature polysilicon material.

[0137] In some embodiments, referring to FIG7 , the array substrate 10 includes a plurality of pixel areas P, each pixel area P including at least a red sub-pixel area P1, a green sub-pixel area P2, and a blue sub-pixel area P3. For example, the three sub-pixels may be arranged in a stripe, a triangle, or a diagonal arrangement. The arrangement in FIG7 is illustrated using a stripe arrangement as an example. Along the second direction Y, the red sub-pixel area P1, the green sub-pixel area P2, and the blue sub-pixel area P3 are arranged periodically. In the first direction X, the red sub-pixel area P1, the green sub-pixel area P2, and the blue sub-pixel area P3 are arranged in columns. A first transistor T1, a color group block, and a common electrode are provided in each pixel area.

[0138] Exemplarily, with reference to FIG6E , along the first direction X, in two adjacent red sub-pixel regions P1, respectively, the orthographic projections of the first color resist block 1061 and the second color resist block 1062 on the substrate 101 overlap with the orthographic projection of the same data line Dt extending along the first direction X on the substrate 101. That is, the sub-pixels in a column of sub-pixel regions are connected to one data line Dt, and the active patterns of the multiple first transistors T1 included in the multiple pixel regions P are arranged in an array. With reference to FIG6B , the orthographic projections of the active patterns of the first transistors T1 on the substrate 101 overlap with the orthographic projections of the data line Dt on the substrate 101. Therefore, the active patterns of the first transistors T1 are all connected to the data line Dt through their source patterns.

[0139] 8 , an embodiment of the present disclosure further provides a display panel 100, comprising the array substrate 10 provided in any of the above embodiments, an opposing substrate 20 disposed opposite the array substrate 10, and a liquid crystal layer 30 located between the array substrate 10 and the opposing substrate 20. Therefore, the display panel 100 provided by the present invention has all the beneficial effects of the array substrate 10 provided in any of the above embodiments, and a detailed description thereof will not be repeated here.

[0140] For example, as shown in FIG. 8 , the array substrate 10 and the counter substrate 20 may be adhered together by a sealant 40 , thereby confining the liquid crystal layer 30 within the area enclosed by the sealant 40 .

[0141] In some embodiments, as shown in Figures 1A, 2A, 4A, 5A, 5B, and 9, the display panel 100 further includes a first boss 50 and a second boss 60 arranged between the array substrate 10 and the opposing substrate 20, wherein the first boss 50 is closer to the side of the array substrate 10 relative to the second boss 60, and the first boss 50 and the second boss 60 are arranged opposite to each other; the orthographic projection of the first boss 50 on the base substrate 101 is located within the orthographic projection of the first shading pattern 11 on the base substrate 101.

[0142] For example, to ensure that the display panel 100 maintains a certain cell gap when pressed by external force, a first boss 50 and a second boss 60, also known as photo spacers (PS), are provided between the array substrate 10 and the counter substrate 20. The first boss 50 and the second boss 60 provide a certain support function. Because the liquid crystal arrangement is disordered at the location of the first boss 50, light leakage is prone to occur. The above-mentioned configuration arranges the orthographic projection of the first boss 50 on the base substrate 101 within the orthographic projection of the first light-shielding pattern 11 on the base substrate 101. The first light-shielding pattern 11 has a light-shielding effect, which can prevent light leakage from occurring at the location of the first boss 50 and affect the display of the display panel.

[0143] In some embodiments, as shown in FIG. 9 , the counter substrate 20 further includes a light-shielding pattern 201 , and the orthographic projection of the first light-shielding pattern 11 on the base substrate 101 is located within the orthographic projection of the light-shielding pattern 201 on the base substrate 101 .

[0144] Exemplarily, referring to Figure 10, the above-mentioned shading pattern 201 is mainly set to block the spacing area G between the first via 1041, the first color block 1061 and the second color block 1062, to avoid light interference and light leakage, and to ensure the in-plane uniformity of the array substrate 10. According to the above part, the size L1 of the first shading pattern 11 in the first direction X is, for example, 5μm. If the first shading pattern 11 is not set, the shading pattern 201 is used to replace the first shading pattern 11. Since the shading pattern 201 is located on the opposing substrate 20, the alignment accuracy between the array substrate 10 and the opposing substrate 20 needs to be considered, and the alignment accuracy is, for example, 1.5μm. That is to say, the size of the shading pattern 201 in the first direction X can be 7μm to meet the above-mentioned shading requirements. Therefore, the orthographic projection of the first shading pattern 11 on the base substrate 101 is located within the orthographic projection of the shading pattern 201 on the base substrate 101.

[0145] Some embodiments of the present disclosure provide a display device 1000, as shown in FIG10 , which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, a wearable display device, etc. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the above-mentioned display device. As shown in FIG10 , the display device 1000 includes the display panel 100 provided in any of the above embodiments. Therefore, the display device 1000 provided by the present invention has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be described in detail here.

[0146] For example, as shown in Figure 10, the display device 1000 in the embodiments of the present disclosure is exemplified by a liquid crystal display device. Referring to Figure 10, in some embodiments, the main structure of the liquid crystal display device 1000 includes a frame 200, a cover plate 300, a display panel 100, a backlight module 400, a circuit board 500, and other electronic components.

[0147] The frame 200 defines a housing space within which the display panel 100, backlight module 400, circuit board 500, and other electronic components are disposed. The cover plate 300 is disposed on the open side of the frame 200. The display panel 100 is positioned closer to the cover plate 300 relative to the backlight module 400 and circuit board 500. The circuit board 500 is positioned further away from the cover plate 300 relative to the display panel 100 and backlight module 400. The backlight module 400 is disposed between the display panel 100 and circuit board 500.

[0148] As shown in Figure 10, some embodiments of the present disclosure provide a display device. The display device provided by the embodiments of the present disclosure can be any device that displays whether it is moving (e.g., video) or fixed (e.g., still image) and whether it is text or image. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0149] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate having a display area and a peripheral area disposed around the display area. The array substrate includes a plurality of sub-pixels located in the display area, and each sub-pixel of the plurality of sub-pixels includes a first transistor and a pixel electrode; The array substrate includes: A substrate; A first gate metal layer disposed on one side of the substrate; A first source-drain metal layer disposed on the side of the first gate metal layer away from the substrate; the first source-drain metal layer includes a drain pattern of the first transistor; A planarization layer disposed on the side of the first source-drain metal layer away from the substrate; A first via hole is formed in the planarization layer; A pixel electrode layer disposed on the side of the planarization layer away from the substrate; the pixel electrode layer includes a plurality of pixel electrodes, and the pixel electrodes belonging to the same sub-pixel are connected to the drain pattern of the first transistor through the first via hole; The array substrate further includes a first light-shielding pattern; the first light-shielding pattern is located on the side of the first gate metal layer away from the substrate; The orthographic projection of the first via hole on the substrate is located within the orthographic projection of the first light-shielding pattern on the substrate.

2. The array substrate according to claim 1, wherein, The sub-pixel further includes a color resist block; the array substrate further includes: A color resist layer disposed between the first source-drain metal layer and the planarization layer; the color resist layer includes a plurality of color resist blocks, and the color resist blocks belonging to the same sub-pixel overlap with the pixel electrode; there is a spacing region between the color resist blocks of two adjacent sub-pixels in a first direction; the first via hole is located within the spacing region; the first direction is the column direction in which the plurality of sub-pixels are arranged in an array; Wherein, the size of the first light-shielding pattern in the first direction is greater than or equal to the size of the spacing region in the first direction.

3. The array substrate according to claim 2, wherein, The array substrate further includes a first active film layer located between the first gate metal layer and the first source-drain metal layer; the first active film layer includes an active pattern of the first transistor; The first gate metal layer includes a first gate line, and the first gate line overlaps with the active patterns of the first transistors of one row of sub-pixels; The size of the first gate line in the first direction is smaller than the size of the first light-shielding pattern in the first direction.

4. The array substrate according to any one of claims 1 to 3, wherein The array substrate further includes: a passivation layer, a common signal line layer, and a common electrode layer sequentially disposed on the side of the pixel electrode layer away from the substrate, and the first light-shielding pattern is located in the common signal line layer.

5. The array substrate according to claim 4, wherein, The common signal line layer includes a plurality of first light-shielding lines extending along a second direction; the second direction is the row direction in which the plurality of sub-pixels are arranged in an array; The orthographic projection of the first via holes of one row of sub-pixels on the substrate is located within the orthographic projection of one of the first light-shielding lines on the substrate; The first light-shielding line includes a plurality of the first light-shielding patterns.

6. The array substrate according to claim 4, wherein, The first gate metal layer includes a first gate line; the orthographic projection of the channel region of the active pattern of the first transistor on the substrate is located within the orthographic projection of the first gate line on the substrate.

7. The array substrate according to any one of claims 1 to 3, wherein The array substrate further includes a second gate metal layer disposed between the first active film layer and the first source-drain metal layer, and the first light-shielding pattern is located on the second gate metal layer.

8. The array substrate according to claim 7, wherein, The second gate metal layer includes second gate lines, and the second gate lines overlap with the active patterns of the first transistors of one row of sub-pixels; In the sub-pixels, the active patterns of the first transistors overlap with the first vias, and the first light-shielding pattern is the part of the second gate lines that overlaps with the active patterns of the first transistors.

9. The array substrate according to claim 8, wherein, The first gate metal layer includes first gate lines; the part of the first gate lines that overlaps with the active patterns of the first transistors serves as the gate patterns of the first transistors.

10. The array substrate according to claim 9, wherein, The second gate lines are electrically connected to the first gate lines in the peripheral area, and the part of the second gate lines that overlaps with the active layers of the first transistors serves as the top gate patterns of the first transistors.

11. The array substrate according to claim 7, wherein, The second gate metal layer includes second gate lines, and the second gate lines overlap with the active patterns of the first transistors of one row of sub-pixels; The second gate lines include a connected first light-shielding structure and second gate patterns, the second gate patterns overlap with the active patterns of the first transistors, and the second gate patterns serve as the gate patterns of the first transistors; The first light-shielding pattern does not overlap with the active patterns of the first transistors.

12. The array substrate according to claim 11, wherein, It further includes a second source-drain metal layer disposed between the first source-drain metal layer and the second gate metal layer, the second source-drain metal layer includes data lines, the data lines extend along a first direction, and the orthographic projection of the data lines on the substrate overlaps with the second gate patterns; Wherein, the first direction is the column direction in which the multiple sub-pixels are arranged.

13. The array substrate according to any one of claims 1 to 12, wherein, It further includes a second transistor disposed in the peripheral area; the gate pattern of the second transistor is located on the first gate metal layer; The array substrate further includes: A second active film layer disposed between the substrate and the first gate metal layer, and the second active film layer includes the active patterns of the second transistors; A second source-drain metal layer disposed on the side of the first source-drain metal layer close to the substrate, the second source-drain metal layer includes the source patterns and drain patterns of the second transistors, and the source patterns of the first transistors.

14. A display panel, comprising: The array substrate according to any one of claims 1 to 13 above; An opposed substrate disposed opposite to the array substrate; A liquid crystal layer located between the array substrate and the opposed substrate.

15. The display panel according to claim 14, wherein, It further includes a first boss and a second boss disposed between the array substrate and the opposed substrate, wherein the first boss is closer to the side of the array substrate than the second boss, and the first boss and the second boss are disposed opposite to each other; The orthographic projection of the first boss on the substrate is located within the orthographic projection of the first light-shielding pattern on the substrate.

16. The display panel according to claim 14 or 15, wherein, The opposed substrate further includes a black matrix light-shielding pattern, and the orthographic projection of the first light-shielding pattern on the substrate is located within the orthographic projection of the light-shielding pattern on the substrate.

17. A display device, comprising: The display panel according to any one of claims 14 to 16 above; A backlight module stacked with the display panel.

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