Memristor array structure having NAND structure and preparation method therefor

Abstract

The present application relates to the technical field of non-volatile storage, in particular to a memristor array structure having a NAND-structure and a preparation method therefor. The memristor array structure comprises: a plurality of 1T1R cell structures, the plurality of 1T1R cell structures being arranged into rows and columns and forming the memristor array structure having a NAND-structure; a plurality of 1T1R cell structures located in the same column are connected in series, and 1T1R cell structures at two ends are connected to a second transistor and a third transistor, respectively, a drain of the second transistor being connected to a bit line, and a source of the third transistor being connected to a source line; gates of first transistors of all 1T1R cell structures in the same row are connected to a same word line (WL), gates of second transistors in the same row are connected to a same drain gating line, and gates of third transistors in the same row are connected to a same source gating line. Thus, problems such as existing memristor array structures not being able to be reduced to the theoretical minimum feature area 4F2 of a memristor are solved.

Description

NAND structure memristor array structure and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number "202311778006.7" filed by Tsinghua University on December 21, 2023, with the invention name "NAND structure memristor array structure and its preparation method". Technical Field

[0003] The present application relates to the field of non-volatile storage technology, and in particular to a NAND structure memristor array structure and a preparation method thereof. Background Art

[0004] As shown in Figure 1, a memristor is a new type of non-volatile memory. Its structure typically consists of a stacked bottom electrode, a resistive material layer, and a top electrode. Memristors offer advantages such as high speed, low power consumption, simple processing, and amenability to downstream integration, making them a promising new type of semiconductor memory. Memristors store information by switching between conductive (or resistive) states. In practice, applying a voltage pulse of a specific amplitude and width to a memristor changes its resistance, enabling data writing. Data reading can be achieved by measuring the resistance of the memristor.

[0005] As shown in Figure 2-4, in practical applications, memristors are composed of transistors connected in series to form a 1-transistor-1-memristor structure (1T1R structure), which is then formed into a memristor array in the form of a crossbar switch matrix. A crossbar 1T1R memristor array typically has multiple intersecting word lines (WLs) and bit lines (BLs), as well as a connected source line (SL). When a memristor is selected, a high voltage Vpass is applied to the corresponding WL to turn on the transistor, while the voltages of the other WLs are 0V to turn off the transistors. An operating voltage Vopr is applied to the corresponding BL, and the voltages of the other BLs and SL are 0V. This ensures that only the voltage across the selected memristor reaches the operating voltage Vopr.

[0006] Among them, the unit area of ​​the Crossbar structure 1T1R memristor array is determined by the size of the series transistor. Since the Crossbar structure transistor device has independent drain and gate, the unit characteristic area is limited by the characteristic area of ​​the transistor and can only reach 6-8F. 2 , it is impossible to further reduce the theoretical minimum characteristic area of ​​4F for memristors. 2 , thus limiting the improvement of storage density.

[0007] Summary of the Invention

[0008] This application provides a NAND structure memristor array structure and its preparation method to solve the problem that the existing memristor array structure cannot be reduced to the theoretical minimum characteristic area of ​​4F 2 , which in turn limits the further improvement of storage density and other issues.

[0009] A first aspect of the present application provides a 1T1R cell structure, comprising: a memristor and a first transistor, wherein one end of the memristor is connected to the source of the first transistor, and the other end of the memristor is connected to the drain of the transistor.

[0010] Optionally, the resistive switching layer of the memristor is made of a multi-metal oxide, a metal-nonmetal mixed oxide and / or a perovskite oxide material composed of any one or more of HfOx, TaOx, TiOx, ZrOx, AlOx, and SiOx.

[0011] Optionally, the electrodes of the memristor are selected from one or more of Pt, Pd, Ir, Ta, Hf, Ti, Zr, W, Ru, Al, TiN, TaN, and Poly-Si.

[0012] Optionally, the first transistor is any one of a silicon-based transistor, a compound semiconductor transistor, a thin film oxide transistor, and a two-dimensional material transistor.

[0013] A second aspect of the present application provides a NAND structure memristor array structure, comprising: a plurality of 1T1R unit structures, wherein the plurality of 1T1R unit structures are arranged in rows and columns to form a NAND structure memristor array structure, wherein:

[0014] The multiple 1T1R unit structures located in the same column are connected in series, and the 1T1R unit structures located at both ends are respectively connected to a second transistor and a third transistor, the drain of the second transistor is connected to a bit line, and the source of the third transistor is connected to a source line;

[0015] The gates of the first transistors of each 1T1R unit structure in the same row are connected to the same WL word line, the gates of the second transistors in the same row are connected to the same drain gate line, and the gates of the third transistors are connected to the same source gate line.

[0016] Optionally, the first transistor, the second transistor and the third transistor are of different models and sizes.

[0017] Optionally, the second transistor is selected from any one of a silicon-based transistor, a compound semiconductor transistor, a thin film oxide transistor, and a two-dimensional material transistor; the third transistor is selected from any one of a silicon-based transistor, a compound semiconductor transistor, a thin film oxide transistor, and a two-dimensional material transistor.

[0018] A third embodiment of the present application provides a method for preparing a NAND structure memristor array, comprising:

[0019] The initial NAND array transistors are obtained by connecting multiple 1T1R unit structure transistors in series through the semiconductor front-end process;

[0020] Growing a layer of memristor bottom electrode material on the initial NAND array transistor and performing a first photolithography to define a memristor bottom electrode pattern;

[0021] Performing a first etching on the memristor lower electrode pattern to form a memristor lower electrode;

[0022] Growing a resistive switching layer material on the lower electrode of the memristor and performing a second photolithography to define a resistive switching layer pattern of the memristor;

[0023] Performing a second etching on the memristor resistive switching layer pattern to form a memristor resistive switching layer;

[0024] Growing a memristor top electrode material on the memristor resistive switching layer, and performing a third photolithography process to define a memristor top electrode pattern;

[0025] The electrode pattern on the memristor is etched for a third time to form a memristor, thereby completing the preparation of a NAND structure memristor array.

[0026] A fourth aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for preparing a NAND structure memristor array as described in the above embodiment.

[0027] A fourth aspect of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, which, when executed by a processor, implements the above-mentioned method for preparing a NAND structure memristor array.

[0028] The NAND structure memristor array structure and its preparation method proposed in the embodiment of the present application realizes the reduction of the area of ​​1T1R storage unit by connecting the transistors of the 1T1R unit of the NAND structure memristor array in series and sharing the source and drain active area, achieving the theoretical minimum characteristic area of ​​4F for memristors. 2 , which improves the storage density of the memristor.

[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic diagram of the memristor structure;

[0032] Figure 2 is a schematic diagram of a conventional 1T1R structure;

[0033] Figure 3 is a schematic diagram of the structure of a Crossbar structure 1T1R memristor array;

[0034] FIG4 is a schematic diagram of the operation of a Crossbar structure 1T1R memristor array device;

[0035] FIG5 is a schematic structural diagram of a NAND structure 1T1R memristor array according to an embodiment of the present application;

[0036] FIG6 is a schematic diagram of a 1T1R structure according to an embodiment of the present application;

[0037] FIG7 is a schematic diagram of the operation of a NAND structure 1T1R memristor array device according to an embodiment of the present application;

[0038] FIG8 is a flow chart of a method for preparing a NAND structure memristor array according to an embodiment of the present application;

[0039] FIG9 is a schematic diagram of a series transistor fabricated by a front-end process according to an embodiment of the present application;

[0040] FIG10 is a schematic diagram of a lower electrode material of a growing memristor according to an embodiment of the present application;

[0041] FIG11 is a schematic diagram of a first photolithography definition of a lower electrode according to an embodiment of the present application;

[0042] FIG12 is a schematic diagram of forming a lower electrode by etching for the first time according to an embodiment of the present application;

[0043] FIG13 is a schematic diagram of a growing resistive switching layer material according to an embodiment of the present application;

[0044] FIG14 is a schematic diagram of a second photolithography process for defining a resistive switching layer according to an embodiment of the present application;

[0045] FIG15 is a schematic diagram of forming a resistive switching layer by a second etching according to an embodiment of the present application;

[0046] FIG16 is a schematic diagram of growing an upper electrode material according to an embodiment of the present application;

[0047] FIG17 is a schematic diagram of a third photolithography definition of an upper electrode according to an embodiment of the present application;

[0048] FIG18 is a schematic diagram of a 1T1R structure formed by a third etching according to an embodiment of the present application;

[0049] FIG19 is a schematic diagram of a crossbar structure memristor array in which transistors do not share source and drain active regions according to an embodiment of the present application, wherein (a) is a side view and (b) is a top view;

[0050] FIG20 is a schematic diagram of a crossbar structure memristor array in which adjacent transistors share a source active region according to an embodiment of the present application, wherein (a) is a side view and (b) is a top view;

[0051] FIG21 is a schematic diagram of a NAND structure memristor array according to an embodiment of the present application, wherein (a) is a side view and (b) is a top view;

[0052] FIG22 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

[0053] Description of reference numerals:

[0054] 50 - NAND structure memristor array structure, 51 - 1T1R cell structure, 511 - memristor, 512 - first transistor, 513 - second transistor and 514 - third transistor. DETAILED DESCRIPTION

[0055] The NAND structure memristor array structure and its manufacturing method according to the embodiment of the present application are described below with reference to the accompanying drawings.

[0056] FIG5 is a schematic structural diagram of a NAND structure 1T1R memristor array according to an embodiment of the present application.

[0057] As shown in FIG. 5 , the NAND structure memristor array structure 50 includes: a plurality of 1T1R unit structures 51 , each of which includes a memristor 511 and a first transistor 512 .

[0058] As shown in FIG6 , one end of the memristor 511 is connected to the source of the first transistor 512, and the other end of the memristor is connected to the drain of the transistor to form a single 1T1R unit structure 51. Multiple 1T1R unit structures 51 are connected in series in rows and columns through multiple source lines SL and word lines WL, multiple source strobe lines SGS and drain strobe lines SGD, and the connected source line SL to form a NAND structure memristor array structure. Multiple 1T1R unit structures located in the same column are connected in series, and the 1T1R unit structures located at both ends are respectively connected to the second transistor 513 and the third transistor 514. The drain of the second transistor 513 is connected to the bit line BL, and the source of the third transistor 514 is connected to the source line SL. The gate of the first transistor 512 of each 1T1R unit structure located in the same row is connected to the same word line WL, the gate of the second transistor 513 located in the same row is connected to the same drain strobe line SGD, and the gate of the third transistor 514 is connected to the same source strobe line SGS.

[0059] In some embodiments, the first transistor, the second transistor, and the third transistor are selected based on transistors of different materials, and the selected materials include but are not limited to silicon-based transistors, compound semiconductor transistors, thin-film oxide transistors, two-dimensional material transistors, etc., but the first transistor, the second transistor, and the third transistor are different in model and size.

[0060] In some embodiments, the first transistor, the second transistor, and the third transistor are selected according to conductivity type, and the selected conductivity types include P-type and N-type transistors, but the first transistor, the second transistor, and the third transistor are different in type and size.

[0061] In some embodiments, the resistive switching layer materials that can be used in the memristor include but are not limited to non-metal oxides such as HfOx, TaOx, TiOx, ZrOx, AlOx, SiOx, as well as multi-metal oxides, metal-nonmetal mixed oxides and / or perovskite oxide materials composed of the foregoing.

[0062] In some embodiments, the electrodes of the memristor may be selected from one or more combinations including but not limited to inert metal materials and alloys such as Pt, Pd, Ir, or metal materials and alloys such as Ta, Hf, Ti, Zr, W, Ru, Al, or TiN, TaN, Poly-Si, or metallic compound materials.

[0063] As shown in Figure 7, when operating a selected memristor, an operating voltage, Vopr, is applied to the selected bitline BL, while the voltage on the remaining bitlines BL is 0V. A high voltage, Vpass, is applied to the selected SGS and SGD lines, turning on their transistors. The voltages on the unselected source gate lines SGS and drain gate lines SGD are 0V, turning off the transistors and splitting the voltage, resulting in almost no voltage splitting across the memristors on the same unselected bitlines BL. The voltage on the selected wordline WL is 0V, turning off the transistors and splitting the voltage, resulting in a voltage splitting across the selected memristor equal to the operating voltage, Vopr. A high voltage, Vpass, is applied to the unselected wordlines WL, turning on the transistors and leaving the unselected memristors without any voltage splitting, resulting in a voltage of 0V. This way, only the selected memristor is operated, while the remaining memristors are unaffected.

[0064] According to the NAND structure memristor array proposed in the embodiment of the present application, the transistors of the 1T1R unit of the NAND structure memristor array are connected in series and share the source and drain active areas, thereby reducing the area of ​​the 1T1R storage unit and achieving the theoretical minimum characteristic area of ​​the memristor of 4F. 2 , which improves the storage density of the memristor.

[0065] Next, a method for preparing a NAND structure memristor array according to an embodiment of the present application will be described with reference to the accompanying drawings.

[0066] FIG8 is a flow chart of a method for preparing a NAND structure memristor array according to an embodiment of the present application.

[0067] As shown in FIG8 , the method for preparing the NAND structure memristor array includes the following steps:

[0068] In step S801 , a plurality of 1T1R unit structure transistors are connected in series through a semiconductor front-end process to obtain an initial NAND array transistor.

[0069] Specifically, as shown in FIG9 , transistors of a NAND array are manufactured through a semiconductor front-end process, and transistors of 1T1R units connected in series share a source and a drain to obtain initial NAND array transistors.

[0070] In step S802 , as shown in FIG. 10-11 , a layer of memristor bottom electrode material is grown on the initial NAND array transistors, and a first photolithography step is performed to define a memristor bottom electrode pattern.

[0071] In step S803 , as shown in FIG12 , the memristor lower electrode pattern is etched for the first time to form the memristor lower electrode.

[0072] In step S804 , as shown in FIG. 13-14 , a resistive switching layer material is grown on the lower electrode of the memristor, and a second photolithography process is performed to define the resistive switching layer pattern of the memristor.

[0073] In step S805 , as shown in FIG15 , the memristor resistive switching layer pattern is etched a second time to form a memristor resistive switching layer.

[0074] In step S806 , as shown in FIG16 , a memristor top electrode material is grown on the memristor resistive switching layer, and a third photolithography step is performed to define a memristor top electrode pattern.

[0075] In step S807 , as shown in FIG. 17-18 , the electrode pattern on the memristor is etched for the third time to form a memristor, thereby completing the preparation of the NAND structure memristor array.

[0076] Furthermore, as shown in Figures 19-21, the transistors of the traditional Crossbar structure memristor array 1T1R unit do not share the source and drain active regions, so the characteristic area of ​​the 1T1R unit is 8F. 2 If two adjacent transistors share the same source active area, the characteristic area of ​​the 1T1R unit is 6F. 2 , and the NAND type 1T1R memristor array prepared by deposition, etching, photolithography and other processes proposed in this application can share the source and drain active regions with each other in series transistors, so the feature size can be reduced to 4F 2 , achieving the theoretical minimum area of ​​the memristor storage unit, thereby effectively improving the storage density of the memristor array.

[0077] FIG22 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0078] Memory 2201 , processor 2202 , and computer programs stored in the memory 2201 and executable on the processor 2202 .

[0079] When the processor 2202 executes the program, the method for preparing the NAND structure memristor array provided in the above embodiment is implemented.

[0080] Furthermore, the electronic device further includes:

[0081] The communication interface 2203 is used for communication between the memory 2201 and the processor 2202 .

[0082] The memory 2201 is used to store computer programs that can be run on the processor 2202.

[0083] The memory 2201 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0084] If the memory 2201, processor 2202, and communication interface 2203 are implemented independently, the communication interface 2203, memory 2201, and processor 2202 can be interconnected via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of illustration, FIG22 shows only one thick line, but this does not mean that there is only one bus or only one type of bus.

[0085] Optionally, in a specific implementation, if the memory 2201, the processor 2202 and the communication interface 2203 are integrated on a chip, the memory 2201, the processor 2202 and the communication interface 2203 can communicate with each other through an internal interface.

[0086] The processor 2202 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0087] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned method for preparing a NAND structure memristor array.

[0088] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0089] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0090] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing a custom logical function or process step, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed in a different order than shown or discussed, including performing functions in a substantially simultaneous manner or in a reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0091] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or N wires (electronic devices), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program can be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing it in other suitable ways as necessary, and then storing it in a computer memory.

[0092] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0093] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0094] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0095] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A 1T1R cell structure, characterized in that Comprising: A memristor and a first transistor, wherein one end of the memristor is connected to the source electrode of the first transistor, and the other end of the memristor is connected to the drain electrode of the transistor.

2. The 1T1R cell structure according to claim 1, wherein The resistive switching layer of the memristor is selected from any one or more of HfOx, TaOx, TiOx, ZrOx, AlOx, SiOx, which are composed of multi-metal oxides, metal-nonmetal mixed oxides, and / or perovskite oxide materials.

3. The 1T1R cell structure according to claim 1, wherein The electrodes of the memristor are selected from one or more of Pt, Pd, Ir, Ta, Hf, Ti, Zr, W, Ru, Al, TiN, TaN, Poly-Si.

4. The 1T1R cell structure according to claim 1, characterized in that, The first transistor is selected from any one of a silicon-based transistor, a compound semiconductor transistor, a thin-film oxide transistor, and a two-dimensional material transistor.

5. A NAND structure memristor array structure, characterized in that, Adopting the 1T1R cell structure described in any one of claims 1-4, comprising: A plurality of 1T1R cell structures, which are arranged in rows and columns to form a NAND structure memristor array structure, wherein The plurality of 1T1R cell structures in the same column are connected in series, and the 1T1R cell structures at both ends are respectively connected to a second transistor and a third transistor. The drain electrode of the second transistor is connected to the bit line, and the source electrode of the third transistor is connected to the source line; The gate electrodes of the first transistors of each 1T1R cell structure in the same row are all connected to the same WL word line, the gate electrodes of the second transistors in the same row are all connected to the same drain select line, and the gate electrodes of the third transistors are all connected to the same source select line.

6. The NAND structure memristor array structure according to claim 5, characterized in that, The models and sizes of the first transistor, the second transistor, and the third transistor are all different.

7. The NAND-structured memristor array structure according to claim 6, characterized in that, The second transistor is selected from any one of a silicon-based transistor, a compound semiconductor transistor, a thin-film oxide transistor, and a two-dimensional material transistor; The third transistor is selected from any one of a silicon-based transistor, a compound semiconductor transistor, a thin-film oxide transistor, and a two-dimensional material transistor.

8. A method for fabricating a NAND-structured memristor array, characterized in that, Including the following steps: Connecting the transistors of a plurality of 1T1R cell structures in series through a semiconductor front-end process to obtain an initial NAND array transistor; Growing a layer of memristor bottom electrode material on the initial NAND array transistor and performing a first photolithography to define the memristor bottom electrode pattern; Performing a first etching on the memristor bottom electrode pattern to form a memristor bottom electrode; Growing a resistive switching layer material on the memristor bottom electrode and performing a second photolithography to define the memristor resistive switching layer pattern; Performing a second etching on the memristor resistive switching layer pattern to form a memristor resistive switching layer; Growing a memristor top electrode material on the memristor resistive switching layer and performing a third photolithography to define the memristor top electrode pattern; Performing a third etching on the memristor top electrode pattern to form a memristor, completing the preparation of the NAND structure memristor array.

9. An electronic device, characterized in that, Including: A memory, a processor, and a computer program stored on the memory and executable on the processor. The processor executes the program to implement the method for preparing a NAND structure memristor array as described in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by a processor to implement the method for fabricating a NAND-structured memristor array as described in claim 8.

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