Low dropout regulator capable of suppressing ripples

Abstract

Embodiments of the present disclosure provide a low dropout regulator (LDO) capable of suppressing ripples. The LDO capable of suppressing ripples comprises: an LDO main circuit, a ripple introduction capacitor, and a first resistor. The LDO main circuit is configured to form a control loop on the basis of an error amplifier and a power transistor and to control the output voltage of the LDO. The ripple introduction capacitor is configured to introduce ripples at an input end of the LDO into the control loop by means of the error amplifier. The first resistor is configured to isolate the ripples at the input end of the LDO from an output end of the LDO. The present invention solves the problems of complex circuit structures and impacts on circuit stability and transient response when FFRC is used to cancel LDO output ripples.

Description

Low-dropout linear regulator with ripple suppression

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese invention patent application with application number 202311737810.0, entitled “Low-voltage-dropout linear regulator with ripple suppression,” filed with the National Intellectual Property Administration of China on December 18, 2023. All disclosed contents are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to the field of power management technology, and in particular, to a low-dropout linear regulator capable of suppressing ripple. Background Art

[0004] The low-dropout linear regulator (LDO) is a new generation of integrated circuit voltage regulators. A miniature, low-power system-on-chip (SoC), it can be used for main current channel control and features overcurrent protection, overtemperature protection, a precision reference source, a differential amplifier, and a delay circuit. Under normal circumstances, the LDO's output voltage does not change with changes in the input voltage. Large fluctuations in the input result in small fluctuations in the output. To suppress output ripple and improve power supply rejection (PSR), ripple suppression circuits have been proposed in the prior art. Feed-Forward Ripple Cancellation (FFRC) is a commonly used ripple suppression method. The FFRC principle involves introducing power supply (input voltage) ripple into the output stage of the LDO's error amplifier and adding a summing circuit to suppress the output ripple through the power transistor.

[0005] As shown in Figure 1, this is a relatively common example circuit diagram of applying FFRC to suppress LDO output ripple. Among them, the Feedforward Amplifier is a feedforward op amp unit, and the Summing Amplifier is a summing unit. The working principle of the circuit in Figure 1 is: the ripple of Vin is collected by the Feedforward Amplifier, and then summed with the output of the error amplifier EA through the Summing Amplifier, generating ripple at the output of the Summing Amplifier. This output ripple and the ripple of the Vin input are offset at the power tube MP, thereby eliminating the ripple on the output VOUT.

[0006] Combined with the circuit structure diagram in Figure 1, it can be seen that the implementation of the feedforward ripple elimination method requires two operational amplifiers, as well as other electronic components such as resistors and capacitors. The structure is very complex and has an impact on circuit stability and transient response.

[0007] Summary of the Invention

[0008] The embodiments described herein provide a ripple-suppressing low-dropout linear regulator (LDO) to address the problem that using FFRC to eliminate LDO output ripple has a complex circuit structure and affects circuit stability and transient response.

[0009] According to a first aspect of the present disclosure, a ripple-suppressing low-dropout linear regulator is provided. The ripple-suppressing low-dropout linear regulator includes: an LDO main circuit, a ripple introduction capacitor, and a first resistor. The LDO main circuit is configured to control the output voltage of the low-dropout linear regulator based on a control loop composed of an error amplifier and a power tube; the ripple introduction capacitor is configured to introduce ripple at the input end of the low-dropout linear regulator into the control loop through the error amplifier; and the first resistor is configured to isolate the ripple at the input end of the low-dropout linear regulator from the output end of the low-dropout linear regulator.

[0010] Optionally, one end of the ripple introduction capacitor is coupled to the input end of the low-voltage difference linear regulator, and the other end of the ripple introduction capacitor is coupled to the positive input end of the error amplifier and one end of the first resistor respectively; the other end of the first resistor is coupled to the output end of the low-voltage difference linear regulator.

[0011] Optionally, the first resistor is a variable resistor, wherein the variable resistor is configured so that a resistance value of the variable resistor is negatively correlated with an impedance from an input terminal to an output terminal of the low voltage difference linear regulator.

[0012] Optionally, the LDO main circuit includes: the error amplifier, a first power tube, and an output capacitor, wherein the negative input terminal of the error amplifier is coupled to a reference voltage, and the output terminal of the error amplifier is coupled to the control terminal of the first power tube; the first terminal of the first power tube is coupled to the input terminal of the low-voltage difference linear regulator, the second terminal of the first power tube is respectively coupled to one end of the output capacitor, the load current, and the output terminal of the low-voltage difference linear regulator, and the other end of the output capacitor is coupled to the ground terminal.

[0013] Optionally, the LDO main circuit also includes: a second power tube and a current compensation module, wherein the current compensation module is configured to control the current of the second power tube to flow into the current compensation module according to the current mirror principle, and prevent the current of the second power tube from flowing into the first resistor; the control electrode of the second power tube is coupled to the control electrode of the first power tube, the first electrode of the second power tube is coupled to the input end of the low voltage difference linear regulator, and the second electrode of the second power tube is coupled to one end of the current compensation module and the first resistor respectively.

[0014] Optionally, the current compensation module includes: a third transistor, a fourth transistor, and a fifth transistor, wherein the control electrode of the third transistor is coupled to the control electrode of the second power tube, the first electrode of the third transistor is coupled to the input end of the low-voltage difference linear regulator, and the second electrode of the third transistor is respectively coupled to the second electrode of the fourth transistor, the control electrode of the fourth transistor, and the control electrode of the fifth transistor; the first electrode of the fourth transistor and the first electrode of the fifth transistor are both coupled to the ground end, and the second electrode of the fifth transistor is coupled to the second electrode of the second power tube.

[0015] Optionally, the resistance of the variable resistor is negatively correlated with the impedance from the input end to the output end of the low-voltage difference linear regulator, including: the resistance of the variable resistor decreases as the voltage difference between the input end and the output end of the low-voltage difference linear regulator increases; or the resistance of the variable resistor increases as the load current increases.

[0016] Optionally, a current mirror ratio between the third transistor and the second power transistor is equal to a current mirror ratio between the fourth transistor and the fifth transistor.

[0017] Optionally, the first power tube and the second power tube are P-type transistors.

[0018] Optionally, the LDO main loop further includes: a second resistor, wherein one end of the second resistor is coupled to the input voltage, and the other end of the second resistor is coupled to the first electrode of the second power tube and the first electrode of the third transistor respectively.

[0019] The ripple-suppressing low-voltage dropout (LDO) linear regulator in the embodiment of the present disclosure includes: an LDO main circuit, a ripple introduction capacitor, and a first resistor, wherein the LDO main circuit is configured to control the output voltage of the LDO linear regulator based on a control loop formed by an error amplifier and a power tube; the ripple introduction capacitor is configured to introduce ripple at the input end of the LDO linear regulator into the control loop through the error amplifier; and the first resistor is configured to isolate the ripple at the input end of the LDO linear regulator from the output end of the LDO linear regulator. Based on the above structure, the ripple-suppressing LDO linear regulator in the embodiment of the present disclosure introduces the ripple at the input end into the input end of the error amplifier through the ripple introduction capacitor, thereby generating ripple at the output end of the error amplifier. The ripple is in the same direction as the ripple at the input end of the power tube. Therefore, the ripple at the output end can be suppressed by common-mode cancellation of the power tube, thereby improving the PSR. Compared with the existing feedforward ripple elimination method, the ripple suppression structure in the embodiment of the present disclosure can be realized by only adding capacitors and resistors. The structure is very simple and has little impact on the stability and transient response of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0021] FIG1 shows an example circuit diagram of a conventional method of applying FFRC to suppress ripple of LDO output;

[0022] FIG2 shows an exemplary circuit diagram of a ripple-suppressing low-dropout linear regulator according to an embodiment of the present disclosure;

[0023] FIG3 shows an exemplary circuit diagram of another ripple-suppressing low-dropout linear regulator according to an embodiment of the present disclosure;

[0024] FIG4 shows an exemplary block diagram of yet another ripple-suppressing low-dropout linear regulator according to an embodiment of the present disclosure;

[0025] FIG5 shows an exemplary circuit diagram of another ripple-suppressing low-dropout linear regulator according to an embodiment of the present disclosure;

[0026] 6-7 show two exemplary circuit diagrams of low-dropout linear regulators with ripple suppression according to embodiments of the present disclosure;

[0027] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0030] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the directions of the conduction current between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0031] In order to solve the problem that the circuit structure of using FFRC to eliminate LDO output ripple is complex and affects circuit stability and transient response, a new ripple elimination technology is proposed. The low-voltage difference linear regulator with ripple suppression in the embodiment of the present disclosure introduces the ripple of the power supply (input end) into the input end of the error amplifier through a capacitor, generating ripple at the output end of the error amplifier. The ripple is offset by the input end on the power tube, thereby suppressing the ripple at the output end and improving the PSR. The low-voltage difference linear regulator with ripple suppression disclosed in the present disclosure is described in detail below.

[0032] FIG2 shows a schematic block diagram of a ripple-suppressing low-voltage dropout linear regulator 200 according to an embodiment of the present disclosure. As shown in FIG2 , the ripple-suppressing low-voltage dropout linear regulator 200 includes: an LDO main circuit 210, a ripple-introducing capacitor C1, a first resistor R1,

[0033] The LDO main circuit 210 is configured to control the output voltage of the low-dropout linear regulator 200 by forming a control loop based on an error amplifier and a power transistor. The LDO main circuit 210 is the basic structural circuit of a low-dropout linear regulator. Its primary operation is to compare the output voltage with a reference voltage and output the gate voltage of the power transistor through the output of the error amplifier. When a load change causes the output voltage to drop, the error amplifier output decreases after comparing the output voltage with the reference voltage, causing the gate voltage of the power transistor to drop. This, in turn, increases the voltage difference between the gate and source of the power transistor, increasing the output current. This increase in output current causes the output voltage to rise, returning the output voltage to a normal value.

[0034] The ripple-introducing capacitor C1 is configured to introduce ripple at the input terminal Vcc of the low-dropout linear regulator 200 into the control loop (the control loop of the LDO main circuit) via the error amplifier. Specifically, one end of the ripple-introducing capacitor C1 is coupled to the input terminal Vcc of the low-dropout linear regulator 200, and the other end is coupled to the positive input terminal of the error amplifier. A first resistor R1 is coupled to the ripple-introducing capacitor C1 and the output terminal Vout of the low-dropout linear regulator 200, respectively, and is configured to isolate the ripple at the input terminal Vcc of the low-dropout linear regulator 200 from the output terminal Vout of the low-dropout linear regulator 200.

[0035] Furthermore, as shown in FIG2 , the LDO main circuit 210 includes an output capacitor Co in addition to an error amplifier EA and a power transistor (the first power transistor MP1 in FIG2 ). The negative input terminal of the error amplifier EA is coupled to a reference voltage Vref, and the output terminal of the error amplifier EA is coupled to the control terminal of the first power transistor MP1. The first terminal of the first power transistor MP1 is coupled to the input terminal Vcc of the low-dropout linear regulator 200, and the second terminal of the first power transistor MP1 is coupled to one terminal of the output capacitor Co, the load current Io, and the output terminal Vout of the low-dropout linear regulator 200. The other terminal of the output capacitor Co is coupled to ground. One terminal of the ripple-introducing capacitor C1 is coupled to the input terminal Vcc of the low-dropout linear regulator 200, and the other terminal of the ripple-introducing capacitor C1 is coupled to the positive input terminal of the error amplifier EA and one terminal of the first resistor R1. The other terminal of the first resistor R1 is coupled to the output terminal Vout of the low-dropout linear regulator 200. The LDO main circuit 210 in Figure 2 is an exemplary circuit diagram. A series voltage divider resistor can also be added to the output terminal Vout, as in Figure 1. Alternatively, an LDO circuit structure with other functions (besides ripple suppression) can be employed. This embodiment does not limit the circuit structure of the LDO main circuit 210. The main emphasis is on the structure of the ripple introduction capacitor C1 and the first resistor R1.

[0036] The ripple suppression principle of the ripple-suppressing low-dropout linear regulator 200 in the embodiment of the present disclosure is illustrated with reference to FIG2 : The ripple-introducing capacitor C1 is coupled between the input terminal Vcc and the positive input terminal of the error amplifier EA. Therefore, the ripple of the input terminal Vcc can be introduced into the control loop of the LDO main circuit 210 via the positive input terminal, generating a ripple at the output terminal of the error amplifier EA in the same direction as the input terminal Vcc of the low-dropout linear regulator 200. This ripple is in the same direction as the ripple of the input terminal Vcc on the first power transistor MP1. Therefore, the common-mode cancellation of the first power transistor MP1 can suppress the ripple at the output terminal Vout, thereby improving the PSR. Furthermore, the first resistor R1 is used to isolate the output terminal Vout from the ripple-introducing capacitor C1. Without the first resistor R1, the ripple-introducing capacitor C1 would be directly coupled to the output terminal Vout. The low-resistance characteristic of the low-dropout linear regulator 200 would result in the output terminal Vout directly absorbing the ripple of the input terminal Vcc, failing to achieve the ripple suppression function.

[0037] As can be seen from the above description, in the ripple-suppressing low-dropout linear regulator 200 of the present embodiment, the ripple at the input terminal Vcc is introduced into the positive input terminal of the error amplifier EA via the ripple introduction capacitor C1. This generates a ripple at the output terminal of the error amplifier EA. This ripple is in the same direction as the ripple at the input terminal Vcc of the first power transistor MP1. Therefore, the common-mode cancellation of the first power transistor MP1 can suppress the ripple at the output terminal Vout, thereby improving the PSR. Compared with existing feedforward ripple elimination methods, the ripple suppression structure of the present embodiment only requires the addition of capacitors and resistors. The structure is very simple and has minimal impact on the stability and transient response of the circuit.

[0038] Furthermore, as shown in FIG3 , an embodiment of the present disclosure also provides an exemplary circuit diagram of another low-voltage dropout linear regulator 200 for suppressing ripple. Unlike FIG2 , FIG3 sets the first resistor R1 in FIG2 as a variable resistor to achieve dynamic ripple suppression. Specifically, the resistance of the variable resistor is negatively correlated with the impedance from the input terminal Vcc to the output terminal Vout of the low-voltage dropout linear regulator 200. In practical applications, the resistance of the variable resistor can be adjusted according to the following rules: the resistance of the variable resistor decreases as the voltage difference between the input terminal Vcc and the output terminal Vout increases; under the premise that the voltage difference between the input terminal Vcc and the output terminal Vout remains unchanged, the resistance of the variable resistor increases as the load current Io increases. The principle of dynamic ripple suppression is analyzed in conjunction with Figure 3: when the voltage difference between the input terminal Vcc and the output terminal Vout becomes larger, the amplitude of the ripple that needs to be coupled to the positive input terminal of the error amplifier EA needs to be smaller (that is, the intensity of the ripple coupled to the positive input terminal of the error amplifier EA is more attenuated), so the resistance of the variable resistor can be adjusted to be smaller, so that part of the amplitude is absorbed by the output terminal Vout; when the voltage difference between the input terminal Vcc and the output terminal Vout becomes smaller, the amplitude of the ripple that needs to be coupled to the positive input terminal of the error amplifier EA needs to be larger (that is, the intensity of the ripple coupled to the positive input terminal of the error amplifier EA is less attenuated), so the resistance of the variable resistor can be adjusted to be larger, increasing the amplitude absorbed by the output terminal Vout. When the voltage difference between the input terminal Vcc and the output terminal Vout remains unchanged, when the load current Io increases, the impedance from the input terminal Vcc to the output terminal Vout decreases, and the amplitude of the ripple that needs to be coupled to the positive input terminal of the error amplifier EA becomes larger, so the resistance value of the variable resistor can be adjusted to be larger; conversely, when the load current Io decreases, the impedance from the input terminal Vcc to the output terminal Vout increases, and the amplitude of the ripple that needs to be coupled to the positive input terminal of the error amplifier EA becomes smaller, so the resistance value of the variable resistor can be adjusted to be smaller.

[0039] Furthermore, as shown in FIG4 , an embodiment of the present disclosure also provides an exemplary circuit diagram of another ripple-suppressing low-dropout linear regulator 200. FIG4 differs from FIG2 in the structure of the LDO main circuit 210; otherwise, the LDO main circuit 210 is the same. In FIG4 , in addition to the error amplifier EA, the first power transistor MP1, and the output capacitor Co shown in FIG2 , the LDO main circuit 210 also includes a second power transistor MP2 and a current compensation module 211. The current compensation module 211 is configured to control the current of the second power transistor MP2 to flow into the current compensation module 211 based on the current mirror principle, thereby preventing the current of the second power transistor MP2 from flowing into the first resistor R1. The control electrode of the second power transistor MP2 is coupled to the control electrode of the first power transistor MP1, the first electrode of the second power transistor MP2 is coupled to the input terminal Vcc of the low-dropout linear regulator 200, and the second electrode of the second power transistor MP2 is coupled to the current compensation module 211 and one end of the first resistor R1, respectively. The first power transistor MP1 and the second power transistor MP2 are P-type transistors, such as P-type MOS transistors.

[0040] Furthermore, as shown in FIG4 , the current compensation module 211 includes a third transistor MP3, a fourth transistor MN4, and a fifth transistor MN5. The control electrode of the third transistor MP3 is coupled to the control electrode of the second power transistor MP2. The first electrode of the third transistor MP3 is coupled to the input terminal Vcc of the low-dropout linear regulator 200. The second electrode of the third transistor MP3 is coupled to the second electrode of the fourth transistor MN4, the control electrode of the fourth transistor MN4, and the control electrode of the fifth transistor MN5, respectively. The first electrode of the fourth transistor MN4 and the first electrode of the fifth transistor MN5 are both coupled to ground, and the second electrode of the fifth transistor MN5 is coupled to the second electrode of the second power transistor MP2. The third transistor MP3 is a P-type transistor, specifically a P-type MOS transistor. The fourth transistor MN4 and the fifth transistor MN5 are N-type transistors, specifically N-type MOS transistors. The current mirror ratio between the third transistor MP3 and the second power transistor MP2 is equal to the current mirror ratio between the fourth transistor MN4 and the fifth transistor MN5.

[0041] Figure 4 shares the same ripple suppression principle as Figure 2: Both utilize C1 to introduce the ripple at the input Vcc into the positive input of EA, generating a ripple at the output of EA in the same direction as the input Vcc. This ripple is in the same direction as the ripple at the input Vcc of the first power transistor MP1. Therefore, common-mode cancellation by the first power transistor MP1 suppresses the ripple at the output Vout, thereby improving the PSR. In the example circuit of Figure 4, the addition of a second power transistor MP2 and current compensation module 211 isolates the first power transistor MP1 and the output capacitor Co outside the LDO small loop (in Figure 4, the second power transistor MP2 is a mirror image of the first power transistor MP1, and MP2 is a very small power transistor; the EA and the second power transistor MP2 form the LDO small loop). This reduces the impact of the output capacitor Co's capacitance on circuit stability, particularly when the input capacitor is large. Specifically, in FIG4 , when the load current Io increases, the current flowing through the first power transistor MP1 increases. The second power transistor MP2, which is a mirror transistor of the first power transistor MP1, causes the gate-source voltage Vgs of the second power transistor MP2 to increase. Simultaneously, the current of the third transistor MP3, which is the mirror transistor of the second power transistor MP2, also increases. The third transistor MP3 and the fourth transistor MN4 are on the same current path. Therefore, the current flowing through the fourth transistor MN4 is equal to the current flowing through the third transistor MP3. Furthermore, because the current mirror ratio between the third transistor MP3 and the second power transistor MP2 is equal to the current mirror ratio between the fourth transistor MN4 and the fifth transistor MN5, the current flowing through the fifth transistor MN5 is equal to the current flowing through the second power transistor MP2. That is, MN5 provides the same current as MP2 requires, thereby reducing the current flowing to the load through the first resistor R1. Ideally (MP2 and MP3, MN4 and MN5 are well matched), the current flowing through R1 is zero, ensuring that the voltage at point A is also equal to Vout. It can be seen that the first resistor R1 in FIG4 can also play a role in isolating the output capacitor Co and the first power transistor MP1 from the outside of the LDO loop, thereby reducing the impact of the output capacitor Co on the circuit stability.

[0042] Furthermore, as shown in FIG5 , another embodiment of the present disclosure provides an exemplary circuit diagram of another low-dropout linear regulator 200 for ripple suppression. Unlike FIG4 , FIG5 utilizes the first resistor R1 in FIG4 as a variable resistor to achieve dynamic ripple suppression. The principle of dynamic ripple suppression is the same as that in the embodiment of FIG3 and will not be further described here.

[0043] Furthermore, as shown in Figures 6 and 7, the present disclosure also provides two other circuit diagrams of a low-dropout linear regulator 200 for ripple suppression. Compared to Figures 4 and 5, Figure 6 adds a second resistor R2 to Figure 4, and Figure 7 adds a second resistor R2 to Figure 5. One end of the second resistor R2 is coupled to the input voltage Vcc, and the other end of the second resistor R2 is coupled to the second power transistor Mp2 and the first electrode of the third transistor Mp3. The addition of the second resistor R2 is intended to reduce power consumption, especially when the load current Io is large. The second resistor R2 can ensure that the ratio of the current flowing through the second power transistor Mp2 to the current flowing through the first power transistor Mp1 is not consistent with the size ratio of the second power transistor Mp2 to the first power transistor Mp1 (which is consistent in Figures 4 and 5). That is, when the current of the first power tube Mp1 is large, the current flowing through the second power tube Mp2 can be made smaller than that in Figures 4 and 5 through the second resistor R2, thereby reducing the power consumption of (Mp2, Mp3, Mn4, Mn5).

[0044] The present disclosure also provides an electronic device including the ripple-suppressing low-dropout linear regulator 200 of the aforementioned embodiment. The electronic device may be a mobile terminal (such as a mobile phone, tablet, or wearable smart device), a camera (such as an in-vehicle camera), or other electronic device with high power requirements.

[0045] In summary, the ripple-suppressing low-voltage dropout linear regulator in the embodiment of the present disclosure can introduce the ripple of the power supply into the input end of the error amplifier through a capacitor, and at the same time add a resistor or a variable resistor between the capacitor and the output end for isolation, thereby achieving output ripple suppression. The structure is very simple, and the impact on the stability and transient response of the circuit is very small.

[0046] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0047] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0048] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A ripple-suppressing low-dropout linear regulator, characterized in that: The low voltage drop linear regulator comprises: an LDO main circuit, a ripple introduction capacitor, a first resistor, Wherein, the LDO main circuit is configured to control the output voltage of the low-dropout linear regulator by forming a control loop based on an error amplifier and a power tube; The ripple introduction capacitor is configured to introduce the ripple at the input end of the low-dropout linear regulator into the control loop through the error amplifier; The first resistor is configured to isolate the ripple at the input end of the low-dropout linear regulator from the output end of the low-dropout linear regulator.

2. The ripple-suppressing low-dropout linear regulator according to claim 1, characterized in that: One end of the ripple introduction capacitor is coupled to the input end of the low voltage dropout linear regulator, and the other end of the ripple introduction capacitor is respectively coupled to the positive input end of the error amplifier and one end of the first resistor; the other end of the first resistor is coupled to the output end of the low voltage dropout linear regulator.

3. The ripple-suppressing low-dropout linear regulator according to claim 2, characterized in that: The first resistor is a variable resistor, The variable resistor is configured so that the resistance of the variable resistor is negatively correlated with the impedance from the input end to the output end of the low voltage difference linear regulator.

4. The ripple-suppressing low-dropout linear regulator according to claim 3, characterized in that: The LDO main circuit includes: the error amplifier, the first power tube, and an output capacitor. Wherein, the negative input terminal of the error amplifier is coupled to a reference voltage, and the output terminal of the error amplifier is coupled to a control electrode of the first power tube; The first pole of the first power tube is coupled to the input end of the low voltage difference linear regulator, the second pole of the first power tube is respectively coupled to one end of the output capacitor, the load current, and the output end of the low voltage difference linear regulator, and the other end of the output capacitor is coupled to the ground end.

5. The ripple-suppressing low-dropout linear regulator according to claim 4, characterized in that: The LDO main circuit also includes: a second power tube, a current compensation module, The current compensation module is configured to control the second power The current of the second power tube flows into the current compensation module, preventing the current of the second power tube from flowing into the first resistor; The control electrode of the second power tube is coupled to the control electrode of the first power tube, the first electrode of the second power tube is coupled to the input end of the low voltage difference linear regulator, and the second electrode of the second power tube is respectively coupled to the current compensation module and one end of the first resistor.

6. The ripple-suppressing low-dropout linear regulator according to claim 5, characterized in that: The current compensation module includes: a third transistor, a fourth transistor, and a fifth transistor. Wherein, the control electrode of the third transistor is coupled to the control electrode of the second power transistor, the first electrode of the third transistor is coupled to the input end of the low voltage difference linear regulator, and the second electrode of the third transistor is respectively coupled to the second electrode of the fourth transistor, the control electrode of the fourth transistor, and the control electrode of the fifth transistor; The first electrode of the fourth transistor and the first electrode of the fifth transistor are both coupled to the ground terminal, and the second electrode of the fifth transistor is coupled to the second electrode of the second power tube.

7. The ripple-suppressing low-dropout linear regulator according to claim 4, characterized in that: The resistance value of the variable resistor is negatively correlated with the impedance from the input end to the output end of the low voltage difference linear regulator, including: The resistance of the variable resistor decreases as the voltage difference between the input terminal and the output terminal of the low voltage dropout linear regulator increases; or, The resistance of the variable resistor increases as the load current increases.

8. The ripple-suppressing low-dropout linear regulator according to claim 6, characterized in that: The current mirror ratio of the third transistor to the second power tube is equal to the current mirror ratio of the fourth transistor to the fifth transistor.

9. The ripple-suppressing low-dropout linear regulator according to claim 5, characterized in that: The first power tube and the second power tube are P-type transistors.

10. The ripple-suppressing low-dropout linear regulator according to claim 6, characterized in that: The LDO main loop further includes: a second resistor, One end of the second resistor is coupled to the input voltage, and the other end of the second resistor is respectively The first electrode of the second power tube is coupled to the first electrode of the third transistor.

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