Back contact cell and manufacturing method therefor

Abstract

A back contact cell and a manufacturing method therefor, which relate to the technical field of photovoltaics, and are used for increasing the light utilization rate of the side of a shaded surface in the back contact cell and facilitating an improvement in the photoelectric conversion efficiency of the back contact cell. The back contact cell comprises a silicon substrate, and first doped semiconductor layers formed in some regions on the side of a shaded surface of the silicon substrate, wherein in the shaded surface of the silicon substrate, regions corresponding to the first doped semiconductor layers are first regions, and the remaining regions are second regions; the first regions and the second regions are alternately distributed; a recess structure recessed into the silicon substrate relative to a surface of each first region is formed in each second region; and the end portion of each first doped semiconductor layer adjacent to each second region is suspended. The manufacturing method for a back contact cell is used for manufacturing the back contact cell.

Description

Back contact battery and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 26, 2024, with application number 202410111962.8 and titled “A Back Contact Battery and Its Manufacturing Method,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for manufacturing the same. Background Art

[0004] A back-contact cell refers to a solar cell in which the light-facing side of the cell has no electrode, and both the positive and negative electrodes are arranged on the backlight side of the cell. This can reduce the shading of the electrode on the cell, increase the short-circuit current of the cell, and improve the energy conversion efficiency of the cell.

[0005] However, the light utilization rate on the backlight side of the back contact cell in the related art is reduced, which is not conducive to improving the photoelectric conversion efficiency of the back contact cell.

[0006] Summary of the Invention

[0007] The purpose of this application is to provide a back-contact cell and a method for manufacturing the same, which are used to increase the light utilization rate on the backlight side of the back-contact cell, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0008] To achieve the above objectives, in a first aspect, the present application provides a back-contact cell, comprising: a silicon substrate, and a first doped semiconductor layer formed on a portion of a backlit side of the silicon substrate. The region of the backlit side of the silicon substrate corresponding to the first doped semiconductor layer is a first region, and the remaining region is a second region. The first and second regions are arranged alternately. A groove structure is formed in the second region, recessed into the silicon substrate relative to the surface of the first region. The end of the first doped semiconductor layer adjacent to the second region is suspended.

[0009] When the back-contact cell provided herein is in operation, light is refracted from the light-facing side into the silicon substrate along the direction from the light-facing side to the back-facing side. After absorbing the photon energy, the silicon substrate generates electrons and holes. The electrons and holes move toward the first doped semiconductor layer and a portion of the second region, respectively, and are ultimately conducted away by the corresponding electrodes, forming a photocurrent. However, the light that enters the silicon substrate is not completely absorbed and utilized by the silicon substrate; some of it is refracted away from the back-facing side of the silicon substrate. In this case, the end of the first doped semiconductor layer adjacent to the second region on the back-facing side of the silicon substrate is suspended. In this case, some of the light refracted away from the back-facing side of the silicon substrate can be reflected by the suspended end of the first doped semiconductor layer adjacent to the second region and returned to the silicon substrate for absorption and utilization. This increases the light utilization efficiency of the back-contact cell and improves the photoelectric conversion efficiency of the back-contact cell.

[0010] In addition, in the back-contact battery provided in the present application, a groove structure is formed on the second area of ​​the backlight surface of the silicon substrate, which is concave into the silicon substrate relative to the surface of the first area, so that the surface of the first area and the surface of the second area can be staggered along the thickness of the silicon substrate, which is beneficial for at least partially staggering the first doped semiconductor layer and the corresponding doped area located in the second area (or the second doped semiconductor layer formed on the second area), both of which are located on the backlight side of the silicon substrate and have opposite conductivity types, along the thickness direction of the silicon substrate, thereby reducing the risk of leakage on the backlight side and improving the electrical reliability of the back-contact battery.

[0011] As a possible implementation solution, the depth of the groove structure is greater than or equal to 200 nm and less than or equal to 2500 nm.

[0012] When the above technical solution is adopted, in the actual manufacturing process, after forming a groove structure on the second region on the backlight side of the silicon substrate that is recessed into the silicon substrate relative to the surface of the first region, the end of the first doped semiconductor layer adjacent to the second region can be suspended. Based on this, the depth of the groove structure is within the above range. This can prevent the end of the first doped semiconductor layer adjacent to the second region from having a smaller suspended height due to the smaller depth, resulting in a weaker reflection of light at the end. This is conducive to allowing more light to return to the silicon substrate due to the reflection of the end of the first doped semiconductor layer adjacent to the second region, ensuring a higher light utilization rate for the back-contact cell. It can also prevent the first doped semiconductor layer and the corresponding doped region located in the second region (or the second doped semiconductor layer formed on the second region), both located on the backlight side of the silicon substrate and of opposite conductivity types, from being offset to a smaller extent along the thickness direction of the silicon substrate due to the smaller groove, further reducing the risk of leakage on the backlight side. In addition, it can also prevent the end of the first doped semiconductor layer from being affected by the etching liquid for etching the silicon substrate due to the large depth of the groove structure, resulting in the end length suspended on the second area becoming shorter, ensuring that more light can be reflected back into the silicon substrate by the end of the first doped semiconductor layer adjacent to the second area and with a relatively large length; it can also prevent the need to use a thicker silicon substrate due to the large depth of the above-mentioned groove structure, thereby reducing the manufacturing cost of the back contact battery and facilitating the thin-film production of the back contact battery.

[0013] As a possible implementation solution, along the arrangement direction of the first region and the second region, the length of the suspended end portion of the first doped semiconductor layer is greater than 0 and less than or equal to 3000 nm.

[0014] When the above technical solution is adopted, it can be understood that the longer the suspended end portion of the first doped semiconductor layer is, the longer its coverage length on the second region is. Two doping regions of opposite conductivity types are provided on the backlight side of the back contact battery. Therefore, along the arrangement direction of the first region and the second region, the length of the suspended end portion of the first doped semiconductor layer is within the above range, which can prevent leakage caused by the large length of the suspended end portion of the first doped semiconductor layer, resulting in a small distance between the first doped semiconductor layer and the corresponding doping region located in the second region (or the second doped semiconductor layer formed on the second region), thereby ensuring that the back contact battery has high electrical reliability. In addition, when the length of the suspended end portion of the first doped semiconductor layer is greater than 0 and less than or equal to 3000 nm, the length of the suspended end portion has a larger optional range, which is conducive to reducing the difficulty of manufacturing a first doped semiconductor layer with a fixed length value, and at the same time can also improve the applicability of the back contact battery provided by the present application in different application scenarios.

[0015] As a possible implementation scheme, at least part of the surface of the sidewall of the above-mentioned groove structure is tilted relative to the horizontal plane, so that the cross-sectional area of ​​at least part of the region of the groove structure gradually increases from the light-facing side to the backlight side. In this case, the groove bottom area of ​​the groove structure is smaller than the groove mouth area, which is conducive to increasing the spacing between the first doped semiconductor layer and the corresponding doped region with a conductivity type opposite to that of the first doped semiconductor layer and located in the second region (or the second doped semiconductor layer formed on the second region) along the arrangement direction of the first region and the second region, reducing the leakage risk on the backlight side of the back contact battery, and ensuring that the back contact battery has high electrical reliability. In addition, the portion of the sidewall of the groove structure that is tilted relative to the horizontal plane is also conducive to reflecting light, further reducing the probability of light being refracted from the backlight side of the back contact battery, thereby helping to improve the photoelectric conversion efficiency of the back contact battery.

[0016] As a possible implementation, the surface of the sidewall of the groove structure near the notch is perpendicular to the horizontal plane. In this case, the morphology of the groove structure in the back-contact battery provided by the present application provides another possible implementation solution, which is conducive to improving the applicability of the back-contact battery provided by the present application in different application scenarios.

[0017] As a possible implementation solution, the angle between the portion of the sidewall of the groove structure that is tilted relative to the horizontal plane and the horizontal plane is greater than or equal to 52° and less than or equal to 58°.

[0018] When the above technical solution is adopted, the angle between the portion of the side wall of the groove structure that is inclined relative to the horizontal plane and the horizontal plane is within the above range, which can prevent the angle from being larger or smaller, resulting in the portion of the side wall of the groove structure that is inclined relative to the horizontal plane having a weaker effect of reflecting light back into the silicon substrate, ensuring that more light can return to the silicon substrate and be reused by the silicon substrate under the greater reflection effect of the portion of the side wall of the groove structure that is inclined relative to the horizontal plane, thereby further improving the utilization rate of light by the back contact battery.

[0019] As a possible implementation, a plane parallel to the horizontal plane is provided between a portion of the surface near the groove opening and a portion of the surface near the groove bottom in the sidewall of the groove structure. In this case, the sidewall of the groove structure can have at least two surfaces disposed at different angles relative to the horizontal plane. This facilitates different portions of the sidewall of the groove structure reflecting light at different angles, thereby allowing more light to be reflected back into the silicon substrate by the sidewall of the groove structure and reused by the silicon substrate.

[0020] As a possible implementation solution, along the arrangement direction of the first region and the second region, the length of a plane parallel to the horizontal plane in the sidewall of the groove structure is greater than 0 and less than 2 μm.

[0021] When the above technical solution is adopted, within a certain range, along the arrangement direction of the first region and the second region, the length of the plane of the sidewall of the groove structure parallel to the horizontal plane is proportional to the etching time corresponding to the groove structure. Based on this, if the length of the plane of the sidewall of the groove structure parallel to the horizontal plane is within the above range, it can prevent the length from being too large and causing the etching time corresponding to the groove structure to be long, and ensure that after the groove structure is formed, the end portion of the first doped semiconductor layer adjacent to the second region and disposed in the air has a certain length.

[0022] As a possible implementation, along the arrangement direction of the first and second regions, the minimum distance between a plane parallel to the horizontal plane in the sidewall of the groove structure and the notch of the groove structure is greater than 0 and less than 1 μm. In this case, a large distance between the plane parallel to the horizontal plane in the sidewall of the groove structure and the notch of the groove structure along the arrangement direction of the first and second regions can be avoided, thereby preventing the plane from having a poor reflection coordination effect with the suspended end portion of the first doped semiconductor layer. This ensures that more light is reflected back into the silicon substrate by the combined action of the plane and the suspended end portion, further improving the light efficiency of the back-contact cell.

[0023] As a possible implementation scheme, at least part of the surface of the bottom of the groove structure is a velvet surface. In this case, because the velvet surface has an uneven surface feature, when the entire surface of the bottom of the groove structure is a velvet surface, the surface area of ​​the corresponding doped region (or the second doped semiconductor layer) formed at the bottom of the groove structure can be increased, thereby increasing the contact area between the corresponding doped region (or the second doped semiconductor layer) and the electrode, reducing the contact resistance, and helping to improve the photoelectric conversion efficiency of the back contact battery. In addition, when the part of the surface of the bottom of the groove structure exposed outside the stacked second passivation layer and the second doped semiconductor layer is a velvet surface, this part of the surface can have a certain light trapping effect, so that more light is transmitted from the bottom of the groove structure into the silicon substrate. At the same time, the second passivation layer is formed on the planar part of the groove bottom, which can improve the passivation effect of the second passivation layer on this part of the surface, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0024] As a possible implementation solution, the above-mentioned back-contact cell further includes a first passivation layer located between the first region and the first doped semiconductor layer.

[0025] When adopting the above-mentioned technical solution, the first passivation layer and the first doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the corresponding area on the backlight surface of the silicon substrate, and to achieve selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, and facilitating the improvement of the photoelectric conversion efficiency of the back-contact battery.

[0026] As a possible implementation solution, the above-mentioned back-contact battery further includes a second doped semiconductor layer formed on the bottom of the groove structure, and the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer.

[0027] As a possible implementation solution, when the back contact cell includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the first doped semiconductor layer is a doped polysilicon layer.

[0028] As a possible implementation solution, in the case where the back-contact cell includes a second doped semiconductor layer, the back-contact cell further includes a second passivation layer located between the silicon substrate and the second doped semiconductor layer.

[0029] As a possible implementation, when the back contact cell includes a second doped semiconductor layer, along the arrangement direction of the first region and the second region, the spacing between the first doped semiconductor layer and the second doped semiconductor layer is greater than or equal to 20 μm and less than or equal to 110 μm.

[0030] When using the above technical solution, the spacing between the first and second doped semiconductor layers of opposite conductivity types is within the above range. This can prevent leakage between the first and second doped semiconductor layers due to a smaller spacing, ensuring high electrical reliability of the back-contact cell. Furthermore, it can prevent carriers on the backlight side from being collected by the first and second doped semiconductor layers and conducted away by the corresponding electrodes in a timely manner due to a larger spacing, further reducing the carrier recombination rate on the backlight side.

[0031] As a possible implementation solution, the second passivation layer is a tunneling passivation layer, and the second doped semiconductor layer is a doped polysilicon layer.

[0032] In the second aspect, the present application also provides a method for manufacturing a back-contact battery, which includes the following steps: first, providing a silicon substrate; next, forming a whole layer of doped semiconductor material layer and a mask layer located on a portion of the doped semiconductor material layer on the backlight surface of the silicon substrate; then, under the masking action of the mask layer, selectively etching the doped semiconductor material layer to form a first doped semiconductor layer as the remaining part of the doped semiconductor material layer, wherein the area corresponding to the first doped semiconductor layer in the backlight surface of the silicon substrate is the first area, and the remaining area is the second area, and the first area and the second area are alternately distributed; next, under the masking action of the mask layer, a groove structure is formed on the second area that is concave into the silicon substrate relative to the surface of the first area, and the end of the first doped semiconductor layer adjacent to the second area is suspended.

[0033] As a possible implementation, the material of the first doped semiconductor layer includes silicon. Furthermore, the step of forming a fully layered doped semiconductor material layer and a mask layer located on a portion of the doped semiconductor material layer on the backlight surface of the silicon substrate includes the following steps: forming a fully layered intrinsic semiconductor material layer on the backlight surface of the silicon substrate; then, doping the intrinsic semiconductor material layer to form a doped semiconductor material layer, and forming a fully layered doped silicon glass layer on the doped semiconductor material layer; then, heat-treating a portion of the doped silicon glass layer using a laser etching process to form a mask layer on the unheat-treated portion of the doped silicon glass layer; and then, removing the heat-treated portion of the doped silicon glass layer.

[0034] In the case of adopting the above technical solution, when the material of the first doped semiconductor layer includes silicon, the material of the intrinsic semiconductor material layer used to manufacture the doped semiconductor material layer also includes silicon. Based on this, after the intrinsic semiconductor material layer is doped, not only can a doped semiconductor material layer be obtained, but also a doped silicon glass layer can be formed on the doped semiconductor material layer. Then, a laser etching process is used to heat-treat part of the doped silicon glass layer. At this time, the density of the laser-treated part of the doped silicon glass layer becomes worse, and it is easy to remove. The density of the unlaser-treated part of the doped silicon glass layer is higher, and it is not easy to remove, so that after the heat treatment, different parts of the doped silicon glass layer have different etching selectivities, thereby obtaining a mask layer for patterning the doped semiconductor material layer, without the need to additionally form other mask materials and other mask deposition processes in order to obtain the above-mentioned mask layer, which is beneficial to reducing the manufacturing cost of the back contact battery and simplifying the manufacturing process of the back contact battery.

[0035] As one possible implementation, a wet chemical process is used, and under the masking action of a mask layer, a groove structure is formed on the second region, the groove structure being recessed into the silicon substrate relative to the surface of the first region. The process temperature of the wet chemical process is greater than or equal to 65°C and less than or equal to 85°C, and / or the process time of the wet chemical process is greater than or equal to 50 seconds and less than or equal to 500 seconds.

[0036] When the above technical solution is adopted, the process temperature and process time of the wet chemical process will affect the specifications of the groove structure formed by the wet chemical process and the specifications of the end portion suspended in the first doped semiconductor layer. Based on this, the process temperature of the wet chemical process is within the above range, which can prevent the depth of the groove structure, the height and length of the suspended end portion in the first doped semiconductor layer from being small due to the low process temperature. In addition, it can also prevent the depth of the groove structure from being large due to the high process temperature. Among them, the beneficial effects of preventing the depth of the groove structure, the height and length of the suspended end portion in the first doped semiconductor layer from being small, and preventing the depth of the groove structure from being large can be referred to the above. In addition, the beneficial effects of the process time within the above range are similar to the beneficial effects of the process temperature being greater than or equal to 65°C and less than or equal to 85°C, and will not be repeated here.

[0037] As a possible implementation, after providing a silicon substrate and before forming a doped semiconductor material layer disposed entirely on the backlight surface of the silicon substrate and a mask layer located partially on the doped semiconductor material layer, the method for manufacturing a back-contact cell further includes forming a first passivation material layer disposed entirely on the backlight surface of the silicon substrate. Furthermore, after selectively etching the doped semiconductor material layer under the masking action of the mask layer and before forming a recessed structure recessed into the silicon substrate relative to the surface of the first region on the second region under the masking action of the mask layer, the method for manufacturing a back-contact cell further includes selectively etching the first passivation material layer under the masking action of the mask layer, so that the remaining portion of the first passivation material layer forms the first passivation layer.

[0038] As a possible implementation scheme, while forming a groove structure recessed into the silicon substrate relative to the surface of the first region on the second region under the masking action of the mask layer, the bottom of the groove structure is subjected to a texturing treatment to form a velvet surface on the bottom of the groove structure.

[0039] As a possible implementation scheme, after the step of forming a groove structure recessed into the silicon substrate relative to the surface of the first region on the second region under the masking action of the mask layer, the manufacturing method of the back-contact battery also includes the step of forming a second doped semiconductor layer at the bottom of the groove structure.

[0040] As a possible implementation scheme, after the step of forming a groove structure recessed into the silicon substrate relative to the surface of the first region on the second region under the masking action of the mask layer, and before the step of forming a second doped semiconductor layer at the bottom of the groove structure, the manufacturing method of the back contact battery also includes the step of: forming a second passivation layer at the bottom of the groove structure.

[0041] As a possible implementation, under the masking effect of the mask layer, the bottom of the groove structure formed in the second region is flat. Furthermore, after forming the second doped semiconductor layer at the bottom of the groove structure, a texturing process is performed on the portion of the groove bottom exposed outside the second doped semiconductor layer.

[0042] The beneficial effects of the second aspect and its various implementations in this application can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0044] FIG1 is a schematic longitudinal cross-sectional view of a first structure of a back-contact battery provided in an embodiment of the present application;

[0045] FIG2 is a schematic longitudinal cross-sectional view of a second structure of a back-contact battery provided in an embodiment of the present application;

[0046] FIG3 is a schematic longitudinal cross-sectional view of a third structure of a back-contact battery provided in an embodiment of the present application;

[0047] FIG4 is a first SEM image of the structure of a back-contact cell provided in an embodiment of the present application at an end portion of the first doped semiconductor layer adjacent to the second region;

[0048] FIG5 is a second SEM image of the structure of a back-contact cell provided in an embodiment of the present application at an end portion of the first doped semiconductor layer adjacent to the second region;

[0049] FIG6 is a third SEM image of the structure of a back-contact cell provided in an embodiment of the present application at an end portion of the first doped semiconductor layer adjacent to the second region;

[0050] FIG7 is a fourth SEM image of the structure of a back-contact cell provided in an embodiment of the present application at an end portion of the first doped semiconductor layer adjacent to the second region;

[0051] FIG8 is a fifth SEM image of the structure of a back-contact cell provided in an embodiment of the present application at an end portion of the first doped semiconductor layer adjacent to the second region;

[0052] FIG9 is an enlarged schematic diagram of the structure of a back-contact cell provided in an embodiment of the present application at an end portion of the first doped semiconductor layer adjacent to the second region;

[0053] FIG10 is a schematic longitudinal cross-sectional view of a fourth structure of a back-contact battery provided in an embodiment of the present application;

[0054] FIG11 is a schematic longitudinal cross-sectional view of a fifth structure of a back-contact battery provided in an embodiment of the present application;

[0055] FIG12 is a first SEM image of a partial structure of a back-contact cell provided in an embodiment of the present application further including a second doped semiconductor layer;

[0056] FIG13 is a second SEM image of a partial structure of a back-contact cell provided in an embodiment of the present application further including a second doped semiconductor layer;

[0057] FIG14 is a third SEM diagram of a partial structure of a back-contact cell provided in an embodiment of the present application further including a second doped semiconductor layer;

[0058] FIG15 is a first SEM image of the structure of a back-contact cell provided in an embodiment of the present application at a sidewall of the second doped semiconductor layer opposite to the first doped semiconductor layer;

[0059] FIG16 is a second SEM image of the structure of the back-contact cell provided in an embodiment of the present application at the sidewall of the second doped semiconductor layer opposite to the first doped semiconductor layer;

[0060] FIG17 is a third SEM image of the structure of the back-contact cell provided in an embodiment of the present application at the sidewall of the second doped semiconductor layer opposite to the first doped semiconductor layer;

[0061] FIG18 is a fourth SEM image of the structure of the back-contact cell provided in an embodiment of the present application at the sidewall of the second doped semiconductor layer opposite to the first doped semiconductor layer;

[0062] FIG19 is a schematic longitudinal cross-sectional view of a sixth structure of a back-contact battery provided in an embodiment of the present application;

[0063] FIG20 is a first structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0064] FIG21 is a second structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0065] FIG22 is a third structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0066] FIG23 is a fourth structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0067] FIG24 is a fifth structural diagram of the back-contact battery during the manufacturing process provided in an embodiment of the present application.

[0068] Figure numerals: 11 is a silicon substrate, 12 is a first doped semiconductor layer, 13 is a first region, 14 is a second region, 15 is a groove structure, 16 is a first passivation layer, 17 is a second doped semiconductor layer, 18 is a second passivation layer, 19 is a doped semiconductor material layer, 20 is a mask layer, 21 is an intrinsic semiconductor material layer, 22 is a doped silicon glass layer, and 23 is a first passivation material layer. DETAILED DESCRIPTION

[0069] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0070] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0071] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application more clearly understood, the application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain this application and are not intended to limit this application.

[0072] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0073] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0074] Currently, solar cells are being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight energy into electrical energy. Specifically, solar cells use the principle of photovoltaics to generate carriers, and then use electrodes to lead out the carriers, thereby facilitating the effective use of electrical energy. Among them, when the positive and negative electrodes included in the solar cell are both located on the back of the solar cell, the solar cell is called a back-contact cell. Because the front of the back-contact cell does not have the problem of being blocked by a metal electrode, it has a higher short-circuit current Isc, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0075] Specifically, the back-contact cell of the related art includes at least a silicon substrate and a first doped semiconductor layer formed on a portion of the backlight side of the silicon substrate. The first doped semiconductor layer can have a conductivity type opposite to that of the silicon substrate; alternatively, the first doped semiconductor layer can have the same conductivity type as the silicon substrate. In this case, the back-contact cell also includes a second doped semiconductor layer formed on a portion of the backlight side of the silicon substrate, and the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer. Furthermore, regardless of which of the above structures the back-contact cell has, the backlight side of the back-contact cell has two doped regions of opposite conductivity types, and the two doped regions of opposite conductivity types are spaced apart to prevent short circuits.

[0076] In the actual manufacturing process of the above-mentioned back-contact cell, it is necessary to first form a layer of doped semiconductor material on the backlight side of the silicon substrate, and then selectively remove the doped semiconductor material layer located in a portion of the backlight side to obtain the above-mentioned first doped semiconductor layer. However, all portions of the first doped semiconductor layer obtained using the manufacturing method of the related art are in contact with the silicon substrate. In this case, after light is refracted into the silicon substrate from the light-facing side, a small portion of the unused light that strikes the space between the two doped regions of opposite conductivity types can be reflected by the backlight side of the silicon substrate and reused, while the majority of the unused light that strikes the space between the two doped regions of opposite conductivity types will transmit out of the silicon substrate. In other words, most of the light cannot be reflected once by the backlight side of the silicon substrate and return to the silicon substrate. This results in a lower reflectivity of the backlight side of the back-contact cell in the related art, which in turn reduces the light utilization efficiency of the back-contact cell, which is not conducive to improving the photoelectric conversion efficiency of the back-contact cell. In addition, the manufacturing method of the related technology usually adopts a laser etching process to achieve selective etching of the above-mentioned doped semiconductor material layer. In order to completely remove the corresponding part of the doped semiconductor material layer, the high-temperature laser used may cause damage to the silicon substrate, which is not conducive to improving the yield of the back-contact battery.

[0077] In order to solve the above technical problems, in the first aspect, an embodiment of the present application provides a back-contact battery. As shown in Figure 1, the back-contact battery provided by the embodiment of the present application includes: a silicon substrate 11, and a first doped semiconductor layer 12 formed on a partial area on the backlight side of the silicon substrate 11. Among them, the area on the backlight side of the silicon substrate 11 corresponding to the first doped semiconductor layer 12 is the first area 13, and the remaining area is the second area 14. The first area 13 and the second area 14 are distributed alternately. A groove structure 15 is formed on the second area 14, which is concave into the silicon substrate 11 relative to the surface of the first area 13. The end of the first doped semiconductor layer 12 adjacent to the second area 14 is suspended.

[0078] When the back-contact cell provided in the embodiments of the present application is in operation, light is refracted from the light-facing side into the silicon substrate along the direction from the light-facing side to the back-facing side. After absorbing the photon energy, the silicon substrate generates electrons and holes. These electrons and holes move toward the first doped semiconductor layer and a portion of the second region, respectively, and are ultimately conducted away by the corresponding electrodes, forming a photocurrent. However, the light that enters the silicon substrate is not completely absorbed and utilized by the silicon substrate; some of it is refracted away from the back-facing side of the silicon substrate. In this case, as shown in FIG1 , the end of the first doped semiconductor layer 12 adjacent to the second region 14 on the back-facing side of the silicon substrate 11 is suspended. In this case, some of the light refracted away from the back-facing side of the silicon substrate 11 can be reflected by the suspended end of the first doped semiconductor layer 12 adjacent to the second region 14 and returned to the silicon substrate 11, where it is absorbed and utilized. This increases the light utilization efficiency of the back-contact cell and improves the photoelectric conversion efficiency of the back-contact cell. In addition, as shown in Figures 1 and 2, in the back-contact battery provided in the embodiment of the present application, a groove structure 15 is formed on the second region 14 of the backlight surface of the silicon substrate 11, which is concave into the silicon substrate 11 relative to the surface of the first region 13, so that the surface of the first region 13 and the surface of the second region 14 can be staggered along the thickness direction of the silicon substrate 11, which is beneficial for at least partially staggering the first doped semiconductor layer 12 and the corresponding doped region located in the second region 14 (or the second doped semiconductor layer 17 formed on the second region 14), both of which are located on the backlight side of the silicon substrate 11 and have opposite conductivity types, along the thickness direction of the silicon substrate 11, thereby reducing the leakage risk on the backlight side and improving the electrical reliability of the back-contact battery.

[0079] Herein, the end portion of the first doped semiconductor layer adjacent to the second region and suspended can also be referred to as the end portion of the first doped semiconductor layer suspended, or the end portion of the first doped semiconductor layer adjacent to the second region, or the end portion of the first doped semiconductor layer adjacent to the groove structure, etc.

[0080] In actual applications, as shown in Figures 1 and 2, the light-facing surface of the silicon substrate 11 can be flat; or, as shown in Figure 3, the light-facing surface of the silicon substrate 11 can be a velvet surface. Because the velvet surface has a light-trapping effect, when the light-facing surface of the silicon substrate 11 is a velvet surface, the reflectivity of the light-facing surface can be reduced, allowing more light to be refracted from the light-facing surface into the silicon substrate 11 and absorbed and utilized by the silicon substrate 11, thereby improving the photoelectric conversion efficiency of the back-contact solar cell.

[0081] In addition, the boundary between the first region and the second region on the backlight side of the silicon substrate is a virtual boundary. As shown in Figures 1 and 2, since the first doped semiconductor layer 12, except for the end portion adjacent to the second region 14 and suspended, is entirely located on the first region 13, and the corresponding doped region (or second doped semiconductor layer 17) having a conductivity type opposite to that of the first doped semiconductor layer 12 and used to collect carriers is formed in the second region 14 (or on the second region 14), the range of the first region 13 and the second region 14 on the backlight side of the silicon substrate 11 can be determined based on the requirements for the formation range of the first doped semiconductor layer 12, the length of the suspended end portion of the first doped semiconductor layer 12, the formation range of the corresponding doped region (or second doped semiconductor layer 17), and the anti-leakage spacing between the first doped semiconductor layer 12 and the corresponding doped region (or second doped semiconductor layer 17) in the actual application scenario, and is not specifically limited here.

[0082] In the actual manufacturing process, a recessed groove structure is formed in the second region on the backlight side of the silicon substrate, recessed into the silicon substrate relative to the surface of the first region. This allows the end portion of the first doped semiconductor layer adjacent to the second region to be suspended. Therefore, the shape of the recessed groove structure formed in the second region can be determined based on the actual manufacturing process, and any shape of the recessed groove structure can be used as long as the end portion of the first doped semiconductor layer adjacent to the second region is suspended by the recessed groove structure.

[0083] Exemplarily, the depth of the groove structure can be greater than or equal to 200 nm and less than or equal to 2500 nm. For example, the depth of the groove structure can be 200 nm, 500 nm, 1000 nm, 1500 nm, 2000 nm, or 2500 nm. In this case, if the depth of the groove structure is within the above range, it can prevent the end of the first doped semiconductor layer adjacent to the second region from having a smaller suspended height due to the smaller depth, resulting in a weaker reflection of light from the end, thereby allowing more light to be reflected back into the silicon substrate by the end of the first doped semiconductor layer adjacent to the second region, ensuring a higher light utilization rate for the back-contact cell. As shown in Figures 1 and 2, it can also prevent the first doped semiconductor layer 12 and the corresponding doped region in the second region 14 (or the second doped semiconductor layer 17 formed on the second region 14), both located on the backlight side of the silicon substrate 11 and of opposite conductivity types, from being offset to a smaller extent along the thickness direction of the silicon substrate 11 due to the smaller groove, further reducing the risk of leakage on the backlight side. In addition, it can also prevent the end of the first doped semiconductor layer 12 from being affected by the etching solution for etching the silicon substrate 11 due to the large depth of the groove structure 15, resulting in the end being suspended on the second area 14. The length of the end is reduced, ensuring that more light can be reflected back into the silicon substrate 11 by the end of the first doped semiconductor layer 12 which is adjacent to the second area 14 and has a relatively large length; it can also prevent the need to use a thicker silicon substrate 11 to manufacture the back contact battery provided in the embodiment of the present application due to the large depth of the above-mentioned groove structure 15, thereby reducing the manufacturing cost of the back contact battery while facilitating the thin-film production of the back contact battery.

[0084] In addition, as shown in Figures 1 and 2, the bottom of the groove structure 15 can be a plane. Alternatively, as shown in Figure 3, at least part of the surface of the bottom of the groove of the groove structure 15 can also be a velvet surface. Specifically, as shown in Figure 3, the entire surface of the bottom of the groove of the groove structure 15 can be a velvet surface. In this case, because the velvet surface has an uneven surface feature, when the bottom of the groove of the groove structure 15 is a velvet surface, the surface area of ​​the corresponding doped region (or the second doped semiconductor layer) formed at the bottom of the groove structure 15 can be increased, thereby increasing the contact area between the corresponding doped region (or the second doped semiconductor layer) and the electrode (not shown in the figure), reducing the contact resistance, and helping to improve the photoelectric conversion efficiency of the back contact battery. Alternatively, as shown in Figures 12 to 14, the surface of the groove structure 15 that is exposed outside the stacked second passivation layer 18 and second doped semiconductor layer 17 (the stacked structure and second passivation layer 18 will be described in detail below and can be seen in Figure 19) can be suede. In this way, this surface can have a certain light-trapping effect, allowing more light to be transmitted from the bottom of the groove structure 15 into the silicon substrate 11. At the same time, the second passivation layer 18 is formed on the flat portion of the groove bottom, which can enhance the passivation effect of the second passivation layer 18 on this surface, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0085] As for the morphology of the sidewall of the groove structure, each portion of the surface of the sidewall of the groove structure can be arranged perpendicular to the horizontal plane, in which case the cross-sectional area of ​​each portion of the groove structure along its own depth direction is the same. Alternatively, as shown in Figures 1 to 4, at least a portion of the surface of the sidewall of the groove structure 15 is arranged obliquely relative to the horizontal plane, so that the cross-sectional area of ​​at least a portion of the region of the groove structure 15 gradually increases from the light-facing side to the backlight side. In this case, the bottom area of ​​the groove structure 15 is smaller than the groove opening area, which is conducive to increasing the spacing between the first doped semiconductor layer 12 and the corresponding doped region of the opposite conductivity type to the first doped semiconductor layer 12 and located in the second region 14 (or the second doped semiconductor layer 17 formed on the second region 14) along the arrangement direction of the first region 13 and the second region 14, reducing the leakage risk on the backlight side of the back contact battery, and ensuring that the back contact battery has high electrical reliability. In addition, the portion of the sidewall of the groove structure 15 that is inclined to the horizontal plane is also conducive to reflecting light, further reducing the probability of light being refracted out from the backlight side of the back contact cell, thereby helping to improve the photoelectric conversion efficiency of the back contact cell.

[0086] In the above case, the angle between the portion of the side wall of the groove structure that is inclined relative to the horizontal plane and the horizontal plane can be determined according to the actual manufacturing process and the requirements for the reflection of light by the side wall of the groove structure, and is not specifically limited here.

[0087] Illustratively, the angle between the portion of the sidewall of the groove structure that is tilted relative to the horizontal plane and the horizontal plane can be greater than or equal to 52° and less than or equal to 58°. For example, the angle between the portion of the sidewall of the groove structure that is tilted relative to the horizontal plane and the horizontal plane can be 52°, 53°, 54°, 55°, 56°, 57° or 58°, etc. In this case, the angle between the portion of the sidewall of the groove structure that is tilted relative to the horizontal plane and the horizontal plane is within the above range, which can prevent the portion of the sidewall of the groove structure that is tilted relative to the horizontal plane from reflecting light back into the silicon substrate weakly due to the angle being too large or too small, thereby ensuring that more light can return to the silicon substrate under the greater reflection effect of the portion of the sidewall of the groove structure that is tilted relative to the horizontal plane and be reused by the silicon substrate, further improving the utilization rate of light by the back contact cell.

[0088] In addition, in the above case, as shown in FIG. 4 to FIG. 6 , all surfaces of the sidewalls of the groove structure 15 may be inclined relative to the horizontal plane.

[0089] Alternatively, as shown in Figures 7 to 9, only a portion of the sidewall of the groove structure 15 is inclined relative to the horizontal plane; while at least a portion of the remaining surface may be perpendicular to the horizontal plane, or at least a portion may be parallel to the horizontal plane. In this case, the sidewall morphology of the groove structure 15 can be divided into at least the following three types:

[0090] The first type: as shown in FIG7 , in the side wall of the groove structure 15 , part of the surface close to the notch is perpendicular to the horizontal plane, and the rest of the surface is inclined to the horizontal plane.

[0091] The second type: As shown in Figure 8, in the side wall of the groove structure 15, the partial surface close to the groove mouth is arranged perpendicular to the horizontal plane, the partial surface close to the groove bottom is arranged inclined to the horizontal plane, and there is a plane parallel to the horizontal plane between the partial surface close to the groove mouth and the partial surface close to the groove bottom.

[0092] The third type: As shown in Figure 9, in the side wall of the groove structure 15, part of the surface close to the groove mouth is inclined to the horizontal plane, part of the surface close to the groove bottom is inclined to the horizontal plane, and there is a plane parallel to the horizontal plane between the part of the surface close to the groove mouth and the part of the surface close to the groove bottom.

[0093] Among them, the height of the surface perpendicular to the horizontal plane in the side wall of the above-mentioned groove structure, the length of the plane parallel to the horizontal plane in the side wall of the groove structure along the arrangement direction of the first area and the second area, and the size of the spacing between the plane parallel to the horizontal plane in the side wall of the groove structure and the notch of the groove structure along the arrangement direction of the first area and the second area can be determined according to the actual manufacturing process and are not specifically limited here.

[0094] For example, as shown in FIG9 , along the arrangement direction of the first region and the second region, the length L2 of the plane arranged parallel to the horizontal plane in the sidewall of the groove structure can be greater than 0 and less than 2 μm. For example, the length L2 of the plane arranged parallel to the horizontal plane in the sidewall of the groove structure can be 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm or 2 μm, etc. In this case, within a certain range, along the arrangement direction of the first region and the second region, the length of the plane arranged parallel to the horizontal plane in the sidewall of the groove structure is proportional to the etching time corresponding to the groove structure. Based on this, the length of the plane arranged parallel to the horizontal plane in the sidewall of the groove structure is within the above range, which can prevent the length from being too large and causing the etching time corresponding to the groove structure to be long, and ensure that after the groove structure is formed, the end of the first doped semiconductor layer 12 adjacent to the second region and suspended has a certain length.

[0095] For example, as shown in FIG9 , along the arrangement direction of the first region and the second region, the minimum distance L1 between the plane parallel to the horizontal plane in the sidewall of the groove structure and the notch of the groove structure can be greater than 0 and less than 1 μm. For example, the minimum distance L1 between the plane parallel to the horizontal plane in the sidewall of the groove structure and the notch of the groove structure can be 0.1 μm, 0.3 μm, 0.6 μm, 0.9 μm, or 1 μm. In this case, it is possible to prevent the plane parallel to the horizontal plane in the sidewall of the groove structure and the notch of the groove structure from being too large along the arrangement direction of the first region and the second region, thereby preventing the plane from having a poor reflection coordination effect with the suspended end portion of the first doped semiconductor layer 12. This ensures that more light can be reflected back into the silicon substrate 11 under the combined action of the plane and the suspended end portion, further improving the light efficiency of the back-contact cell.

[0096] It is worth noting that, as shown in Figures 4 to 9, in the back-contact cell provided by the embodiment of the present application, the groove structure 15 located on the second region 14 has a variety of possible morphologies, which is conducive to improving the applicability of the back-contact cell provided by the embodiment of the present application in different application scenarios. In addition, when a plane parallel to the horizontal plane is provided between the surface of the portion of the sidewall of the groove structure 15 near the groove opening and the surface of the portion of the sidewall near the groove bottom, the sidewall of the groove structure 15 can have at least two surfaces with different angles relative to the horizontal plane, which is conducive to different parts of the sidewall of the groove structure 15 reflecting light at different angles, thereby facilitating more light to return to the silicon substrate 11 under the reflection effect of the sidewall of the groove structure 15 and be reused by the silicon substrate 11.

[0097] Regarding the first doped semiconductor layer, the material of the first doped semiconductor layer may be a semiconductor material such as silicon, silicon germanium, germanium, or gallium arsenide. Regarding the arrangement of the material, the crystalline phase of the first doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline.

[0098] The thickness of the first doped semiconductor layer can be set according to actual needs and is not specifically limited here. For example, the thickness of the first doped semiconductor layer can be greater than or equal to 100 nm and less than or equal to 500 nm.

[0099] In addition, as can be seen from the above, the end portion of the first doped semiconductor layer adjacent to the second region and suspended has a reflective effect on light, so that part of the light refracted from the backlight side of the silicon substrate can be reflected back into the silicon substrate under the action of the above end portion and reused by the silicon substrate. In addition, it can be understood that the longer the suspended end portion of the first doped semiconductor layer is, the greater its coverage length on the second region. The backlight side of the back contact battery is provided with two doping regions of opposite conductivity types. Therefore, the longer the length of the suspended end portion of the first doped semiconductor layer adjacent to the second region is, the more likely it is to cause leakage. Based on this, the length of the suspended end portion of the first doped semiconductor layer can be determined according to the light utilization and leakage requirements of the back contact battery in the actual application scenario.

[0100] For example, along the arrangement direction of the first region and the second region, the length of the suspended end portion of the first doped semiconductor layer can be greater than 0 and less than or equal to 3000 nm. For example, the length of the suspended end portion of the first doped semiconductor layer can be 1 nm, 50 nm, 100 nm, 500 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, or 3000 nm. In this case, if the length of the suspended end portion of the first doped semiconductor layer is within the above range, it can prevent leakage caused by the large length of the suspended end portion of the first doped semiconductor layer, which leads to a small distance between the first doped semiconductor layer and the corresponding doped region located in the second region (or the second doped semiconductor layer formed on the second region), thereby ensuring that the back contact battery has high electrical reliability. In addition, when the length of the suspended end portion of the first doped semiconductor layer is greater than 0 and less than or equal to 3000 nm, the length of the suspended end portion has a large optional range, which helps reduce the difficulty of manufacturing a first doped semiconductor layer with a fixed length value, and can also improve the applicability of the back contact battery provided by the embodiment of the present application in different application scenarios.

[0101] In actual applications, as shown in Figures 1 to 3, part of the first doped semiconductor layer 12 can be formed directly on the first region 13 of the silicon substrate 11. Alternatively, as shown in Figure 10, the back-contact cell further includes a first passivation layer 16 located between the first region 13 and the first doped semiconductor layer 12. In this case, the first passivation layer 16 and the first doped semiconductor layer 12 can form a selective contact structure to chemically passivate the corresponding region on the backlight surface of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0102] Specifically, the material of the first passivation layer can be determined according to the material of the first doped semiconductor layer and the type of the selective contact structure composed of the first passivation layer and the first doped semiconductor layer in actual application scenarios, and is not specifically limited here.

[0103] For example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure, the first doped semiconductor layer is a doped polysilicon layer, and the first passivation layer is a tunneling passivation layer. The tunneling passivation layer may be made of materials such as silicon oxide, aluminum oxide, or titanium oxide, and may also be referred to as a tunneling oxide layer.

[0104] For another example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a heterogeneous contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0105] The thickness of the first passivation layer can be set according to actual needs and is not specifically limited here. For example, the thickness of the first passivation layer can be greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0106] As for the conductivity type of the above-mentioned first doped semiconductor layer, as mentioned above, the conductivity type of the first doped semiconductor layer can be opposite to the conductivity type of the silicon substrate; or, the conductivity type of the first doped semiconductor layer can also be the same as the conductivity type of the silicon substrate. In this case, the back-contact battery provided in the embodiment of the present application also includes a second doped semiconductor layer formed on the bottom of the groove structure, and the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the silicon substrate.

[0107] It should be noted that, as shown in Figures 2 and 11, regardless of whether the conductivity type of the first doped semiconductor layer 12 is opposite to or the same as that of the silicon substrate 11, the back-contact cell provided in the embodiments of the present application may include a second doped semiconductor layer 17 formed on the bottom of the groove structure 15. Moreover, the conductivity type of the second doped semiconductor layer 17 is opposite to that of the first doped semiconductor layer 12. The second doped semiconductor layer 17 is formed only on the bottom of the groove structure 15, and the sidewalls of the groove structure 15 are exposed outside the second doped semiconductor layer 17. At the same time, the first doped semiconductor layer 12 and the second doped semiconductor layer 17 are spaced apart and do not contact each other to prevent leakage.

[0108] Specifically, the material of the second doped semiconductor layer can be a semiconductor material such as silicon, silicon-germanium, germanium, or gallium arsenide. The crystalline phase of the second doped semiconductor layer can be amorphous, nanocrystalline, microcrystalline, single crystal, or polycrystalline. Furthermore, the present embodiment does not impose any specific restrictions on the thickness of the second doped semiconductor layer; any thickness can be used as long as it can be applied to the back-contact battery provided in the present embodiment.

[0109] As for the spacing between the first doped semiconductor layer and the second doped semiconductor layer along the arrangement direction of the first region and the second region, it can be determined according to the anti-leakage requirements for the back contact battery in the actual application scenario, and is not specifically limited here.

[0110] For example, along the arrangement direction of the first region and the second region, the spacing between the first doped semiconductor layer and the second doped semiconductor layer can be greater than or equal to 20μm and less than or equal to 110μm. For example, the spacing between the first doped semiconductor layer and the second doped semiconductor layer can be 20μm, 40μm, 60μm, 80μm, 100μm or 110μm, etc. In this case, the spacing between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity type is within the above range, which can prevent leakage between the first doped semiconductor layer and the second doped semiconductor layer due to the small spacing, thereby ensuring that the back contact battery has high electrical reliability. In addition, it can also prevent the carriers on the backlight side from being collected by the first doped semiconductor layer and the second doped semiconductor layer in time and being led out by the corresponding electrodes due to the large spacing, thereby further reducing the carrier recombination rate on the backlight side.

[0111] In addition, the sidewall of the second doped semiconductor layer opposite to the first doped semiconductor layer can be arranged perpendicular to the horizontal plane. Alternatively, as shown in Figures 12 to 18, the sidewall of the second doped semiconductor layer 17 opposite to the first doped semiconductor layer 12 can also be arranged at an angle to the horizontal plane. In this case, the risk of lateral leakage between the first doped semiconductor layer 12 and the second doped semiconductor layer 17 can be reduced, ensuring that the back contact battery has high electrical reliability. As for the angle at which the sidewall of the second doped semiconductor layer 17 opposite to the first doped semiconductor layer 12 is inclined relative to the horizontal plane, it can be determined according to the actual application scenario and is not specifically limited here.

[0112] In some cases, as shown in FIG19 , the back-contact cell provided in the embodiment of the present application may further include a second passivation layer 18 located between the silicon substrate 11 and the second doped semiconductor layer 17. In this case, the second passivation layer 18 and the second doped semiconductor layer 17 may constitute a selective contact structure to chemically passivate the corresponding area on the backlight surface of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0113] Specifically, the material of the second passivation layer can be determined according to the material of the second doped semiconductor layer and the type of the selective contact structure composed of the second passivation layer and the second doped semiconductor layer in actual application scenarios, and is not specifically limited here.

[0114] For example, when the selective contact structure formed by the second passivation layer and the second doped semiconductor layer is a tunneling passivation contact structure, the second doped semiconductor layer is a doped polysilicon layer, and the second passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include silicon oxide, aluminum oxide, or titanium oxide.

[0115] For another example, when the selective contact structure formed by the second passivation layer and the second doped semiconductor layer is a heterogeneous contact structure, the second doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the second passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0116] In a second aspect, embodiments of the present application provide a method for manufacturing a back-contact battery. The manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 20 to 24. Specifically, the method for manufacturing a back-contact battery includes the following steps:

[0117] First, a silicon substrate is provided. The specific structure of the silicon substrate can be found in the previous section and will not be described in detail here.

[0118] Next, as shown in FIG23 , a doped semiconductor material layer 19 is formed entirely on the backlight surface of the silicon substrate 11 , and a mask layer 20 is partially formed on the doped semiconductor material layer 19 .

[0119] In actual manufacturing, the doped semiconductor material layer is used to manufacture the first doped semiconductor layer of the back-contact cell described above. Therefore, the material and thickness of the doped semiconductor material layer can be determined based on the material and thickness of the first doped semiconductor layer described above. Furthermore, the specific material of the doped semiconductor material layer can determine the specific process for forming the doped semiconductor material layer and the specific process for forming the mask layer.

[0120] Illustratively, in the case where the material of the above-mentioned first doped semiconductor layer includes silicon, the above-mentioned steps of forming a doped semiconductor material layer on the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer may include the following steps: as shown in Figure 20, a whole layer of intrinsic semiconductor material layer 21 is formed on the backlight surface of the silicon substrate 11; then, as shown in Figure 21, the intrinsic semiconductor material layer is doped to form a doped semiconductor material layer 19 in the intrinsic semiconductor material layer, and a whole layer of doped silicon glass layer 22 is formed on the doped semiconductor material layer 19; then, as shown in Figure 22, a laser etching process is used to heat-treat a portion of the doped silicon glass layer so that the unheat-treated portion of the doped silicon glass layer forms a mask layer 20; then, as shown in Figure 23, the heat-treated portion of the doped silicon glass layer is removed.

[0121] Specifically, the material of the first doped semiconductor layer includes silicon, which may mean that the material of the first doped semiconductor layer only includes silicon; or it may also mean that the material of the first doped semiconductor layer includes both silicon and other semiconductor materials such as germanium silicon. Secondly, in the actual manufacturing process, chemical vapor deposition and other processes can be used to form a layer of intrinsic semiconductor material layer arranged on the backlight side. Next, the intrinsic semiconductor material layer can be doped using processes such as diffusion. After the above-mentioned doping treatment, not only a doped semiconductor material layer can be obtained, but also a doped silicon glass layer arranged as a whole layer can be formed on the doped semiconductor material layer. Then, a laser etching process is used to heat-treat part of the doped silicon glass layer. At this time, as shown in Figure 22, the density of the laser-treated portion of the doped silicon glass layer becomes poor, and it is easy to be removed. The untreated portions of the doped silica glass layer are denser and less easily removed, resulting in different etching selectivities for different portions of the doped silica glass layer after heat treatment. This allows for a mask layer 20 for patterning the doped semiconductor material layer 19, eliminating the need for additional mask material and mask deposition steps to obtain the mask layer 20. This reduces the manufacturing cost of back-contact cells and simplifies the manufacturing process for back-contact cells. The specific conditions for the laser etching process can be set based on the actual application scenario and are not specifically limited here.

[0122] For example, the laser used in the laser etching process may be a nanosecond laser, a picosecond laser, or a femtosecond laser, etc. The processing power used in the laser etching process may be greater than or equal to 10W and less than or equal to 100W, and the diameter of the laser spot may be greater than or equal to 50μm and less than or equal to 300μm.

[0123] Of course, when the material of the first doped semiconductor layer includes silicon, or when the material of the first doped semiconductor layer does not include silicon, chemical vapor deposition and doping processes can also be used to form a layer of doped semiconductor material disposed on the backlight side. Then, chemical vapor deposition and etching processes can be used to form a mask layer made of other materials such as silicon nitride that have a masking function.

[0124] It should be noted that when the manufactured back-contact battery also includes a first passivation layer located between the first region and the first doped semiconductor layer, after the step of providing a silicon substrate and before the step of forming a whole layer of doped semiconductor material layer on the backlight surface of the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer, the manufacturing method of the back-contact battery also includes the step of: as shown in Figure 20, forming a whole layer of first passivation material layer 23 on the backlight surface of the silicon substrate 11.

[0125] Specifically, the first passivation material layer can be formed by chemical vapor deposition or other processes. The first passivation material layer is used to manufacture the first passivation layer, so the material and thickness of the first passivation material layer can be determined according to the material and thickness of the first passivation layer.

[0126] Next, as shown in FIG24 , under the masking action of mask layer 20, the doped semiconductor material layer is selectively etched, so that the remaining portion of the doped semiconductor material layer forms first doped semiconductor layer 12. The area of ​​the backlight surface of silicon substrate 11 corresponding to first doped semiconductor layer 12 is first region 13, and the remaining area is second region 14. First regions 13 and second regions 14 are arranged alternately. Next, under the masking action of mask layer 20, recess structures 15 are formed in second regions 14, recessed into silicon substrate 11 relative to the surface of first regions 13, and the ends of first doped semiconductor layer 12 adjacent to second regions 14 are suspended.

[0127] In actual manufacturing, a wet chemical process or other process can be employed. Under the masking action of a mask layer, a groove structure can be formed in the second region, recessed into the silicon substrate relative to the surface of the first region. This prevents damage to the silicon substrate caused by the high-temperature laser, thereby improving the yield of back-contact cells. Furthermore, when forming the groove structure using a wet chemical process, the wet chemical solution etches the silicon substrate in a generally isotropic manner, which helps increase the length of the suspended end portion of the first doped semiconductor layer.

[0128] Specifically, the process conditions for selectively etching the doped semiconductor material layer can be determined according to the adopted etching process, the material of the doped semiconductor material layer, and the specifications of the formed groove structure, etc., and are not specifically limited here.

[0129] For example, when a wet chemical process is used, and under the masking action of a mask layer, to form a recessed structure in the second region that is recessed into the silicon substrate relative to the surface of the first region, the process temperature of the wet chemical process can be greater than or equal to 65°C and less than or equal to 85°C. Furthermore, the process time of the wet chemical process can be greater than or equal to 50 seconds and less than or equal to 500 seconds. For example, the process temperature of the wet chemical process can be 65°C, 70°C, 75°C, 80°C, or 85°C. The process time of the wet chemical process can be 50 seconds, 100 seconds, 200 seconds, 300 seconds, 400 seconds, or 500 seconds. In this case, both the process temperature and process time of the wet chemical process affect the specifications of the recessed structure formed by the wet chemical process and the specifications of the suspended end portion of the first doped semiconductor layer. Therefore, keeping the process temperature of the wet chemical process within the above range can prevent the depth of the recessed structure, the height of the suspended end portion of the first doped semiconductor layer, and the length of the suspended end portion of the first doped semiconductor layer from being reduced due to a lower process temperature. Furthermore, it can prevent the depth of the recessed structure from being increased due to a higher process temperature. The beneficial effects of preventing the depth of the groove structure, the height and length of the suspended end portion of the first doped semiconductor layer from being small, and preventing the depth of the groove structure from being large can be referenced above. Furthermore, the beneficial effects of maintaining the process time within the above range are similar to those of maintaining the process temperature at a temperature greater than or equal to 65°C and less than or equal to 85°C, and are not further elaborated here.

[0130] It should be noted that if the above-mentioned first passivation material layer is formed on the backlight side before the doped semiconductor layer is formed, then after the step of selectively etching the doped semiconductor material layer under the masking action of the mask layer, and before the step of forming a groove structure recessed into the silicon substrate relative to the surface of the first region on the second region under the masking action of the mask layer, the above-mentioned back-contact battery manufacturing method also includes the following steps: wet chemical processes can be used, and under the masking action of the mask layer, the first passivation material layer is selectively etched to form the first passivation layer with the remaining part of the first passivation material layer.

[0131] In addition, when the bottom of the groove structure in the manufactured back-contact battery is a velvet surface, while the step of forming a groove structure that is recessed into the silicon substrate relative to the surface of the first area on the second area under the masking action of the mask layer is carried out, the bottom of the groove structure can also be textured to form a velvet surface on the bottom of the groove structure.

[0132] Specifically, the formation of a groove structure with a velvet bottom can be achieved by adding a texturing additive to a wet chemical solution used to etch a portion of the silicon substrate. Specifically, the type of texturing additive and the proportion of the additive in the wet chemical solution can be determined based on the actual application scenario.

[0133] For example, the texturing auxiliary additives may include sodium benzoate, defoaming agent, surfactant, etc. The proportion of the texturing auxiliary additives in the wet chemical solution may be greater than or equal to 0.5% and less than or equal to 5%.

[0134] In some cases, if the manufactured back-contact cell also includes the aforementioned second doped semiconductor layer, after forming a recessed structure in the second region, recessed into the silicon substrate relative to the surface of the first region, using the mask layer, the back-contact cell manufacturing method may further include forming the second doped semiconductor layer at the bottom of the recessed structure. Specifically, the second doped semiconductor layer may be formed using processes such as chemical vapor deposition and selective etching. The material and thickness of the second doped semiconductor layer can be found in the previous section and are not further described here.

[0135] In some cases, if the manufactured back-contact cell further includes a second passivation layer located between the silicon substrate and the second doped semiconductor layer, then after forming a recessed structure on the second region, recessed into the silicon substrate relative to the surface of the first region, under the masking action of the mask layer, and before forming the second doped semiconductor layer at the bottom of the recessed structure, the above-mentioned back-contact cell manufacturing method further includes the step of forming a second passivation layer at the bottom of the recessed structure. The material and thickness of this second passivation layer can be referred to above.

[0136] Specifically, after forming the groove structure and before forming the second doped semiconductor layer, a second passivation layer can be formed on the groove bottom of the groove substrate by using processes such as chemical vapor deposition and selective etching.

[0137] Alternatively, a process such as chemical vapor deposition can be used to sequentially form a second passivation material layer and a second doped semiconductor material layer disposed entirely on the backlight side. Subsequently, a process such as laser etching can be used to selectively remove portions of the second passivation material layer and the second doped semiconductor material layer, thereby obtaining a second passivation layer and a second doped semiconductor layer located only at the bottom of the groove structure.

[0138] It should be noted that, when the manufactured back-contact battery also includes a second passivation layer and a second doped semiconductor layer, the bottom of the groove structure formed on the second region under the masking action of the mask layer can be a plane. In this case, when the second passivation layer is formed at the bottom of the groove structure in the above manner, the second passivation layer can be formed on a relatively flat surface, which is beneficial to improving the passivation effect of the second passivation layer on the corresponding part of the surface of the silicon substrate. In addition, after the step of forming the second doped semiconductor layer at the bottom of the groove structure, the part of the groove bottom of the groove structure exposed outside the second doped semiconductor layer can be textured, so that the surface of the groove bottom of the groove structure exposed outside the second doped semiconductor layer has a certain light trapping effect, so that more light is transmitted from the surface of the groove bottom of the groove structure exposed outside the second doped semiconductor layer to the silicon substrate, thereby improving the photoelectric conversion efficiency of the back-contact battery.

[0139] Specifically, during the actual manufacturing process, if a wet chemical process is used to pattern the second doped semiconductor material layer for forming the second doped semiconductor layer, a texturing additive may be added to the etching solution used in the wet chemical process to simultaneously achieve the formation of the second doped semiconductor layer and the textured surface. The specific composition and proportion of the texturing additive can be found in the previous section and will not be further described here.

[0140] The beneficial effects of the second aspect and its various implementations in the embodiments of the present application can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0141] In addition, the present invention also provides a comparative example and an example to illustrate the manufacturing process and working performance of the back-contact battery provided in the present invention. Table 1 shows the test results of the back-contact battery corresponding to Example 1 and Comparative Example 1.

[0142] Example 1

[0143] In the first step, the single crystal silicon wafer is subjected to alkaline polishing treatment using an alkaline solution having a concentration of 15% to form a smooth and clean silicon surface.

[0144] In the second step, a tunnel oxide layer and an intrinsic polysilicon layer are sequentially deposited on the surface of the single crystal silicon wafer, wherein the thickness of the tunnel oxide layer is 1.8 nm and the thickness of the intrinsic polysilicon layer is 350 nm.

[0145] The third step is to perform boron doping on the deposited intrinsic polysilicon layer to form a doped polysilicon layer; and to form a borosilicate glass layer on the doped polysilicon layer. The boron doping concentration is 8×10 19 / cm 3 .

[0146] The fourth step is to heat-treat the borosilicate glass layer using a laser etching process to prepare a mask layer with a specific pattern. The laser can be a picosecond laser with a processing power of 40W and a spot diameter of 200μm.

[0147] In the fifth step, under the masking effect of the mask layer, a portion of the doped polysilicon layer is selectively removed. The surface of the single-crystalline silicon wafer is then etched to form a groove structure, while the end of the doped polysilicon layer adjacent to the groove structure is left suspended. The main components of the etching solution used include alkali and texturing auxiliary additives. The alkali concentration in the etching solution is 5%, the etching temperature is 82°C, the process time is 300 seconds, the proportion of the texturing auxiliary additive is 2%, and the main components of the texturing auxiliary additive include sodium benzoate, defoaming agent, and surfactant.

[0148] Step 6: Form a tunnel oxide layer and an N-type doped polysilicon layer stacked in sequence at the bottom of the groove structure. The N-type doped polysilicon layer has a thickness greater than or equal to 150 nm and less than or equal to 180 nm. The tunnel oxide layer has a thickness greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0149] Comparative Example 1

[0150] The manufacturing method corresponding to Comparative Example 1 is identical to the manufacturing process of Example 1, except for steps 4 and 5. In the manufacturing method provided in Comparative Example 1, after the deposited intrinsic polysilicon layer is subjected to boron doping and before forming a tunneling oxide layer and an N-type doped polysilicon layer stacked in sequence at the bottom of the groove structure, the borosilicate glass layer is removed, and the formed tunneling oxide layer and doped polysilicon layer are selectively etched directly using a laser etching process, thereby forming a groove structure in the silicon substrate with sidewalls perpendicular to the horizontal plane.

[0151] Table 1 Test results of back contact cells corresponding to Example 1 and Comparative Example 1

[0152] It can be seen from the data shown in Table 1 that in the back-contact battery formed by the manufacturing method provided in Example 1, more light can be reflected back into the silicon substrate and reused by the silicon substrate because the end of the first doped semiconductor layer adjacent to the groove structure is suspended. Therefore, the working efficiency, open-circuit voltage, short-circuit current and fill factor of the back-contact battery obtained by the corresponding manufacturing method of Comparative Example 1 are higher, that is, the back-contact battery provided by the embodiment of the present application has higher working performance.

[0153] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0154] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A back contact battery, comprising: A silicon substrate, and a first doped semiconductor layer formed on a partial area of ​​a backlight side of the silicon substrate; wherein The area on the backlight surface of the silicon substrate corresponding to the first doped semiconductor layer is the first area, and the remaining area is the second area; the first area and the second area are alternately distributed; a groove structure is formed on the second area and is recessed into the silicon substrate relative to the surface of the first area; the end of the first doped semiconductor layer adjacent to the second area is suspended.

2. The back contact battery according to claim 1, wherein the depth of the groove structure is greater than or equal to 200 nm and less than or equal to 2500 nm; and / or, Along the arrangement direction of the first region and the second region, the length of the suspended end portion of the first doped semiconductor layer is greater than 0 and less than or equal to 3000 nm.

3. The back contact battery according to claim 1, wherein at least a portion of the surface of the sidewall of the groove structure is inclined relative to the horizontal plane, so that the cross-sectional area of ​​at least a portion of the groove structure gradually increases from the light-facing surface to the backlight surface; and / or, In the side wall of the groove structure, a surface portion close to the notch is arranged perpendicular to the horizontal plane. 4 . The back contact battery according to claim 3 , wherein an angle between a portion of the side wall of the groove structure that is inclined relative to the horizontal plane and the horizontal plane is greater than or equal to 52° and less than or equal to 58°. 5 . The back contact battery according to claim 3 , wherein in the side wall of the groove structure, a plane parallel to the horizontal plane is provided between a partial surface close to the groove opening and a partial surface close to the groove bottom.

6. The back contact battery according to claim 5, wherein along the arrangement direction of the first region and the second region, the length of the plane parallel to the horizontal plane in the side wall of the groove structure is greater than 0 and less than 2 μm; and / or, Along the arrangement direction of the first region and the second region, a minimum distance between a plane in the sidewall of the groove structure that is arranged parallel to the horizontal plane and a notch of the groove structure is greater than 0 and less than 1 μm. 7 . The back contact battery according to claim 1 , wherein at least a portion of the surface of the bottom of the groove structure is a velvet surface.

8. The back-contact cell according to claim 1, further comprising a first passivation layer located between the first region and the first doped semiconductor layer; and / or, The back contact cell further includes a second doped semiconductor layer formed on a groove bottom of the groove structure, wherein the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer.

9. The back contact cell according to claim 8, wherein when the back contact cell comprises the first passivation layer, and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polysilicon layer; and / or In the case where the back contact cell comprises a second doped semiconductor layer, the back contact cell further comprises a second passivation layer located between the silicon substrate and the second doped semiconductor layer; and / or, In the case where the back contact cell includes a second doped semiconductor layer, along the arrangement direction of the first region and the second region, a distance between the first doped semiconductor layer and the second doped semiconductor layer is greater than or equal to 20 μm and less than or equal to 110 μm. 10 . The back contact cell according to claim 9 , wherein the second passivation layer is a tunnel passivation layer, and the second doped semiconductor layer is a doped polysilicon layer.

11. A method for manufacturing a back contact battery, comprising the steps of: Providing a silicon substrate; forming a doped semiconductor material layer disposed entirely on the backlight surface of the silicon substrate, and a mask layer located on a portion of the doped semiconductor material layer; Under the masking action of the mask layer, the doped semiconductor material layer is selectively etched so that the remaining part of the doped semiconductor material layer forms a first doped semiconductor layer; wherein the area corresponding to the first doped semiconductor layer in the backlight surface of the silicon substrate is the first area, and the remaining area is the second area; the first area and the second area are alternately distributed; Under the masking action of the mask layer, a groove structure is formed on the second region, which is recessed into the silicon substrate relative to the surface of the first region, and the end of the first doped semiconductor layer adjacent to the second region is suspended.

12. The method for manufacturing a back contact cell according to claim 11, wherein the material of the first doped semiconductor layer comprises silicon; in, The step of forming a doped semiconductor material layer disposed entirely on the backlight surface of the silicon substrate and a mask layer located on part of the doped semiconductor material layer comprises the following steps: Forming a whole layer of intrinsic semiconductor material layer on the backlight surface of the silicon substrate; Performing a doping treatment on the intrinsic semiconductor material layer, so that the intrinsic semiconductor material layer forms the doped semiconductor material layer, and a doped silicon glass layer is formed on the doped semiconductor material layer; Using a laser etching process, heat-treating a portion of the doped silicon glass layer, so that the portion of the doped silicon glass layer that has not been heat-treated forms the mask layer; The heat-treated portion of the doped silicon glass layer is removed.

13. The method for manufacturing a back contact battery according to claim 11, wherein a wet chemical process is used, and under the masking action of the mask layer, the groove structure is formed on the second region and is recessed into the silicon substrate relative to the surface of the first region; wherein: The process temperature of the wet chemical process is greater than or equal to 65° C. and less than or equal to 85° C., and / or the process time of the wet chemical process is greater than or equal to 50 s and less than or equal to 500 s.

14. The method for manufacturing a back-contact cell according to any one of claims 11 to 13, after the step of providing a silicon substrate and before the step of forming a doped semiconductor material layer disposed entirely on the backlight surface of the silicon substrate and a mask layer located on a portion of the doped semiconductor material layer, the method for manufacturing a back-contact cell further comprises the steps of: forming a first passivation material layer disposed entirely on the backlight surface of the silicon substrate; After the step of selectively etching the doped semiconductor material layer under the masking action of the mask layer, and before the step of forming a groove structure on the second region that is recessed into the silicon substrate relative to the surface of the first region under the masking action of the mask layer, the method for manufacturing a back-contact battery also includes the step of: selectively etching the first passivation material layer under the masking action of the mask layer so that the remaining part of the first passivation material layer forms a first passivation layer.

15. According to the method for manufacturing a back-contact battery according to any one of claims 11 to 13, while performing the step of forming a groove structure on the second region that is recessed into the silicon substrate relative to the surface of the first region under the masking action of the mask layer, the bottom of the groove structure is subjected to a texturing treatment so that a velvet surface is formed on the bottom of the groove structure.

16. The method for manufacturing a back-contact battery according to any one of claims 11 to 13, after the step of forming a groove structure on the second region that is recessed into the silicon substrate relative to the surface of the first region under the masking action of the mask layer, the method for manufacturing a back-contact battery further comprises the steps of: A second doped semiconductor layer is formed at the bottom of the groove structure.

17. The method for manufacturing a back-contact battery according to claim 16, after the step of forming a groove structure on the second region that is recessed into the silicon substrate relative to the surface of the first region under the masking action of the mask layer, and before the step of forming a second doped semiconductor layer at the bottom of the groove structure, the method for manufacturing a back-contact battery further comprises the steps of: A second passivation layer is formed at the bottom of the groove structure.

18. The method for manufacturing a back contact battery according to claim 16, wherein under the masking effect of the mask layer, the bottom of the groove structure formed on the second area is a plane; After the step of forming the second doped semiconductor layer at the bottom of the groove structure, a texturing process is performed on a portion of the groove bottom of the groove structure that is exposed outside the second doped semiconductor layer.

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