Super-junction IGBT device and manufacturing method therefor

Abstract

Disclosed in embodiments of the present invention are a super-junction IGBT device and a manufacturing method therefor. The device comprises a first conductive type epitaxial layer; a plurality of trenches are formed at intervals in one side of the first conductive type epitaxial layer; a first conductive type well region, a second conductive type well region, and a first conductive type heavily-doped region are sequentially arranged between adjacent trenches in the extension direction of the first conductive type epitaxial layer; an emitter metal layer connected to the first conductive type heavily-doped region is arranged in the direction of the trenches distant from the first conductive type epitaxial layer; an insulating dielectric layer is arranged between the emitter metal layer and the trenches; a buffer layer, a second conductive type layer, and a collector metal layer are sequentially arranged on the other side of the first conductive type epitaxial layer; and a plurality of second conductive type super-junction structures are arranged in a body region of the first conductive type epitaxial layer, and the concentration of the second conductive type super-junction structures gradually changes in the extension direction of the first conductive type epitaxial layer. In this way, the embodiments of the present invention can achieve a PN pillar structure close to an ideal regular rectangle, so as to maximize the withstand voltage of the super-junction structures.

Description

Super junction IGBT device and manufacturing method thereof Technical Field

[0001] The embodiments of the present invention relate to the technical field of semiconductor devices, and in particular to a super junction IGBT device and a method for manufacturing the same. Background Art

[0002] With the development of insulated-gate bipolar transistor (IGBT) technology, the current mainstream field-stop structure is getting closer and closer to its theoretical limit. Superjunction is hailed as a milestone in power MOS. At the same time, its introduction into IGBT can also further improve device performance. However, the P-pillar shape formed by the superjunction IGBT power device in the existing technology is a "gourd"-shaped distribution that increases from bottom to top. This "gourd"-shaped distribution causes the electric field distribution in the body region to change from a rectangular distribution to a trapezoidal distribution, which to some extent weakens the voltage resistance of the superjunction structure.

[0003] Therefore, a new high-voltage device structure and a superjunction semiconductor device structure and manufacturing method that are compatible with existing manufacturing processes are very necessary.

[0004] Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide a super junction IGBT device and a method for manufacturing the same, which overcome the above problems or at least partially solve the above problems.

[0006] According to one aspect of an embodiment of the present invention, a super junction IGBT device is provided, comprising: a first conductive type epitaxial layer, a plurality of trenches arranged at intervals on one side of the first conductive type epitaxial layer, a first conductive type well region, a second conductive type well region and a first conductive type heavily doped region arranged in sequence between adjacent trenches along the extension direction of the first conductive type epitaxial layer, polysilicon and an oxide layer surrounding the polysilicon are arranged in the trenches, an emitter metal layer is arranged in a direction away from the first conductive type epitaxial layer, the emitter metal layer is connected to the first conductive type heavily doped region, an insulating dielectric layer is arranged between the emitter metal layer and the trenches, a buffer layer, a second conductive type layer and a collector metal layer are arranged in sequence on the other side of the first conductive type epitaxial layer along the direction away from the first conductive type epitaxial layer; a plurality of second conductive type super junction structures are arranged in the body region of the first conductive type epitaxial layer along the extension direction of the first conductive type epitaxial layer, and the second conductive type super junction structures have a concentration gradient along the extension direction of the first conductive type epitaxial layer.

[0007] Optionally, along the extension direction of the first conductive type epitaxial layer, the concentration of the second conductive type super junction structure decreases successively.

[0008] Optionally, a second conductivity type super junction structure is provided in the body region of the first conductivity type epitaxial layer directly below any of the trenches, and the second conductivity type super junction structure is in contact with the oxide layer below the trench.

[0009] Optionally, a second conductive type super junction structure is provided in the body region of the first conductive type epitaxial layer directly below any of the trenches, and the second conductive type super junction structure is spaced a first preset distance from the bottom of the trench.

[0010] Optionally, a second conductive type super junction structure is provided in the body region of the first conductive type epitaxial layer directly below any adjacent trenches, and an end of the second conductive type super junction structure close to the trench is flush with the bottom of the trench.

[0011] Optionally, a second conductive type super junction structure is provided in the body region of the first conductive type epitaxial layer directly below any adjacent trenches, and an end of the second conductive type super junction structure close to the trench is spaced a second preset distance from the bottom of the trench in the extension direction of the first conductive type epitaxial layer.

[0012] Based on the same inventive concept, a method for manufacturing a super junction IGBT device is provided, comprising:

[0013] A first conductive type epitaxial layer is generated on a first conductive type substrate, and a second conductive type is gradually injected, and annealing is performed to form a second conductive type super junction structure; a second conductive type well region is injected on the first conductive type epitaxial layer, and then trench etching and oxide layer growth are performed; polysilicon is filled in the trench, and the first conductive type well region is injected; an insulating dielectric layer is generated and a first conductive type heavily doped region is injected, and then contact holes on the first conductive type heavily doped region are etched and metallized to generate an emitter metal layer; the first conductive type substrate is thinned to generate a buffer layer, and a second conductive type layer and a collector metal layer are sequentially generated on the side of the buffer layer away from the first conductive type epitaxial layer.

[0014] Optionally, the step of generating a first conductive type epitaxial layer on a first conductive type substrate and gradually performing a second conductive type injection comprises: generating a first conductive type epitaxial layer on a first conductive type substrate; starting from a first distance from the first conductive type epitaxial layer on a side away from the first conductive type substrate, injecting a second conductive type into the first conductive type epitaxial layer at intervals of a second distance, and successively decreasing the injection dose, wherein the second distance is equal to 1 / n of the first distance, and n is a positive integer; and continuing to generate a new first conductive type epitaxial layer on the first conductive type epitaxial layer.

[0015] Optionally, the step of generating a first conductive type epitaxial layer on a first conductive type substrate and gradually performing a second conductive type injection comprises: generating a first conductive type epitaxial layer on a first conductive type substrate; epitaxially growing a new first conductive type epitaxial layer on the first conductive type epitaxial layer n times, and injecting a second conductive type into each new first conductive type epitaxial layer grown, with the injection dose decreasing successively, and n being a positive integer; and continuing to generate a new first conductive type epitaxial layer on the first conductive type epitaxial layer.

[0016] Optionally, the first conductive type substrate and the first conductive type epitaxial layer are heavily doped with the first conductive type, and the doping concentration of the first conductive type substrate is higher than the doping concentration of the first conductive type epitaxial layer.

[0017] The super junction IGBT device of an embodiment of the present invention includes a first conductive type epitaxial layer, a plurality of trenches arranged at intervals on one side of the first conductive type epitaxial layer, a first conductive type well region, a second conductive type well region and a first conductive type heavily doped region are arranged in sequence between adjacent trenches along the extension direction of the first conductive type epitaxial layer, polysilicon and an oxide layer surrounding the polysilicon are arranged in the trench, an emitter metal layer is arranged in the direction away from the first conductive type epitaxial layer of the trench, the emitter metal layer is connected to the first conductive type heavily doped region, an insulating dielectric layer is arranged between the emitter metal layer and the trench, a buffer layer, a second conductive type layer and a collector metal layer are arranged in sequence on the other side of the first conductive type epitaxial layer along the direction away from the first conductive type epitaxial layer; a plurality of second conductive type super junction structures are arranged in the body region of the first conductive type epitaxial layer along the extension direction of the first conductive type epitaxial layer, the second conductive type super junction structure has a concentration gradient along the extension direction of the first conductive type epitaxial layer, and can achieve a PN column structure close to an ideal regular rectangle to maximize the withstand voltage of the super junction structure.

[0018] The above description is only an overview of the technical solutions of the embodiments of the present invention. In order to more clearly understand the technical means of the embodiments of the present invention, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0020] FIG1 shows a schematic structural diagram of a super junction IGBT device provided by an embodiment of the present invention;

[0021] FIG2 shows a schematic structural diagram of another super junction IGBT device provided by an embodiment of the present invention;

[0022] FIG3 shows a schematic structural diagram of another super junction IGBT device provided by an embodiment of the present invention;

[0023] FIG4 shows a schematic structural diagram of a third super junction IGBT device provided by an embodiment of the present invention;

[0024] FIG5 shows a schematic structural diagram of a fourth super junction IGBT device provided by an embodiment of the present invention;

[0025] FIG6 is a schematic flow chart showing a method for manufacturing the super junction IGBT device in FIG5 ;

[0026] FIG7 shows a first schematic diagram of generating a second conductivity type super junction structure of the super junction IGBT device in FIG5 ;

[0027] FIG8 shows a second schematic diagram of generating a second conductivity type super junction structure of the super junction IGBT device in FIG5 ;

[0028] FIG9 shows a schematic diagram of generating a first conductivity type epitaxial layer for trench etching of the super junction IGBT device in FIG5 ;

[0029] FIG10 shows a schematic diagram of annealing of the super junction IGBT device in FIG5 ;

[0030] FIG11 is a schematic diagram showing the second conductivity type well region implantation and trench etching of the super junction IGBT device in FIG5 ;

[0031] FIG12 shows a schematic diagram of trench oxide layer formation in the super junction IGBT device in FIG5 ;

[0032] FIG13 is a schematic diagram showing trench filling and first conductivity type well region implantation of the super junction IGBT device in FIG5 ;

[0033] FIG14 shows a schematic diagram of the implantation and metallization surface of the first conductivity type heavily doped region of the super junction IGBT device in FIG5 . DETAILED DESCRIPTION

[0034] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0035] FIG1 shows a schematic diagram of the structure of a super junction IGBT device provided by an embodiment of the present invention. As shown in FIG1 , the super junction IGBT device comprises: a first conductive type epitaxial layer 1, a plurality of trenches 2 spaced apart on one side of the first conductive type epitaxial layer 1, a first conductive type well region 3, a second conductive type well region 4 and a first conductive type heavily doped region 5 sequentially arranged between adjacent trenches 2 along the extension direction of the first conductive type epitaxial layer 1, polysilicon 6 and an oxide layer 7 surrounding the polysilicon 6 are arranged in the trenches 2, an emitter metal layer 8 is arranged in the direction away from the first conductive type epitaxial layer 1, and the emitter metal layer 8 is connected to the first conductive type epitaxial layer 1. The first conductive type heavily doped region 5 is connected, an insulating dielectric layer 9 is arranged between the emitter metal layer 8 and the trench 2, and a buffer layer 10, a second conductive type layer 11 and a collector metal layer 12 are arranged in sequence on the other side of the first conductive type epitaxial layer 1 along the direction away from the first conductive type epitaxial layer 1; a plurality of second conductive type super junction structures 13 are arranged along the extension direction of the first conductive type epitaxial layer 1 in the body region of the first conductive type epitaxial layer 1, and the concentration of the second conductive type super junction structure 13 changes gradually along the extension direction of the first conductive type epitaxial layer 1.

[0036] In an embodiment of the present invention, the concentration of the second conductive type super junction structure 13 decreases gradually along the extension direction of the first conductive type epitaxial layer 1. In the first conductive type epitaxial layer 1, a first conductive type super junction structure 14 is formed between two adjacent second conductive type super junction structures 13. The second conductive type super junction structure 13 and the first conductive type super junction structure 14 are both columnar structures. The second conductive type super junction structure 13 is a gourd-shaped columnar structure. The figures of the embodiments of the present invention are illustrated using an N-type IGBT device as an example. If it is an N-type IGBT device, the first conductive type is N-type and the second conductive type is P-type. If it is a P-type IGBT device, the opposite is true. The embodiment of the present invention uses the second conductive type super junction structure 13 with a gradually varying concentration, which is more conducive to forming a regular PN column alternating distribution structure to achieve a regular rectangular electric field distribution in the body region and maximize the device withstand voltage.

[0037] In an embodiment of the present invention, the layout design between the front trench and the superjunction structure is optimized. For conventional IGBT devices, in the blocking state, the highest electric field within the chip typically occurs at the silicon surface at the bottom of the trench and in the gate oxide dielectric layer above the silicon surface at that location. If the second-conductivity-type superjunction structure 13 in the body region is connected to the bottom of the trench, the second-conductivity-type superjunction structure 13 can weaken the electric field at the bottom of the trench, thereby improving device reliability. Furthermore, staggering the second-conductivity-type superjunction structure 13 from the first-conductivity-type well region 3 of the front cell can prevent the second-conductivity-type doping at the top of the second-conductivity-type superjunction structure 13 from affecting the first-conductivity-type doping of the first-conductivity-type well region 3, thereby affecting the carrier storage effect of the first-conductivity-type well region 3 and increasing the collector-emitter turn-on voltage Vceon of the IGBT device. Referring to Figure 2, a second-conductivity-type superjunction structure 13 can be disposed in the body region of the first-conductivity-type epitaxial layer 1 directly below any trench 2, and the second-conductivity-type superjunction structure 13 can be in contact with the oxide layer 7 below the trench 2. Alternatively, referring to FIG3 , a second conductive type super junction structure 13 may be provided in the body region of the first conductive type epitaxial layer 1 directly below any of the trenches 2 , and the second conductive type super junction structure 13 may be spaced from the bottom of the trench 2 by a first preset distance h.

[0038] Referring to Figure 4, the second conductive type super junction structure 13 and the first conductive type super junction structure 14 in Figure 2 are swapped left and right. A second conductive type super junction structure 13 is set in the body region of the first conductive type epitaxial layer 1 directly below any adjacent grooves 2, and the end of the second conductive type super junction structure 13 close to the groove 2 is flush with the bottom of the groove 2. The first conductive type super junction structure 14 is at the bottom of the groove 2. When the second conductive type super junction structure 13 is below the table, it has certain advantages for the dynamic performance of the device. During the tailing stage of the device turn-off current, there are still holes injected into the collector on the back of the chip. At this time, the second conductive type super junction structure 13 can collect holes faster, providing a hole extraction path, so that the tailing time and current of the turn-off process are reduced, thereby reducing losses. Referring to Figure 5 , a second conductivity type superjunction structure 13 is disposed in the body region of the first conductivity type epitaxial layer 1 directly below any adjacent trenches 2. The end of the second conductivity type superjunction structure 13 proximal to the trench 2 is spaced a second predetermined distance from the bottom of the trench 2 in the extension direction of the first conductivity type epitaxial layer 1. The second predetermined distance can be equal to the first predetermined distance h, but can also be different in other embodiments of the present invention, and this is not specifically limited herein. The first and second predetermined distances are preferably 4-10 μm.

[0039] Based on the same concept, an embodiment of the present invention further provides a method for manufacturing a super junction IGBT device. As shown in FIG6 , the method for manufacturing a super junction IGBT device includes:

[0040] Step S11: growing a first conductivity type epitaxial layer on a first conductivity type substrate, gradually performing second conductivity type implantation, and annealing to form a second conductivity type super junction structure.

[0041] The embodiment of the present invention is specifically described using an N-type superjunction IGBT device. Two main methods can be used to manufacture the second conductivity type superjunction structure. Referring to FIG7 , a first conductivity type epitaxial layer epi1 is generated on a first conductivity type substrate N++sub. This first conductivity type epitaxial layer epi1 is relatively thick, and its thickness is not less than the sum of the thickness used to prepare the second conductivity type superjunction structure and the distance between the bottom of the second conductivity type superjunction structure 13 and the first conductivity type substrate N++sub. The first conductivity type substrate N++sub and the first conductivity type epitaxial layer epi1 are heavily doped with the first conductivity type, and the doping concentration of the first conductivity type substrate N++sub is higher than the doping concentration of the first conductivity type epitaxial layer epi1. After the second conductivity type superjunction structure is prepared, a new first conductivity type epitaxial layer is continuously generated on the first conductivity type substrate to be used for the front IGBT trench etching structure. Then, starting from a first distance away from the first conductive type epitaxial layer epi1 on the side away from the first conductive type substrate N++sub, a second conductive type is injected into the first conductive type epitaxial layer epi1 at intervals of a second distance, and the injection dose is successively reduced, wherein the second distance is equal to 1 / n of the first distance, and n is a positive integer. For example, after photolithography on the epitaxial layer epi1, the injection is performed, such as "e++++" is the highest injection energy, and the P-type impurities are injected into the position d required by the design, and the "e+++" energy is the second highest, and the P-type impurities are injected into the position required by the design "e++" is to inject P-type impurities into the desired position of the design "e+" is to inject P-type impurities into the desired position of the design And so on. To keep the total dose p of P-type injected in the current step unchanged, the dose injected each time is The larger the n value, the more uniform the doping distribution in the superjunction region and the more uniform the electric field distribution at the PN column interface, maximizing the withstand voltage.

[0042] The second preparation method of the second conductive type super junction structure is shown in Figure 8. A first conductive type epitaxial layer epi1 is generated on the first conductive type epitaxial layer 1. The thickness of the first conductive type epitaxial layer epi1 only needs to be no less than the spacing between the bottom of the second conductive type super junction structure and the first conductive type substrate N++sub. Then, a new first conductive type epitaxial layer epi2-epi5 is epitaxially grown on the first conductive type epitaxial layer epi1 for n times, and a second conductive type injection is performed in each new first conductive type epitaxial layer epi2-epi5 grown, and the injection dose is successively reduced, and n is a positive integer. In the embodiment of the present invention, by increasing the P-type injection of the first conductive type epitaxial layer, each subsequent injection step gradually increases to ensure that a "gourd"-shaped distribution of uniform size is formed after all thermal budgets, so as to achieve a regular rectangular electric field distribution and maximize the device withstand voltage.

[0043] After the second conductivity type super junction structure is prepared, as shown in FIG9 , a new first conductivity type epitaxial layer epi6 is generated on the first conductivity type substrate for use in the trench etching structure on the front side of the super junction IGBT device.

[0044] After the gradient second conductivity type implantation is complete, annealing is performed to form a second conductivity type superjunction structure, as shown in Figure 10. This utilizes the concentration difference between the highly doped first conductivity type substrate and the first conductivity type epitaxial layer, creating a concentration gradient after thermal budgeting. Subsequent thinning of the first conductivity type substrate is all that is needed to form the buffer layer.

[0045] Step S12: implanting a second conductivity type well region on the first conductivity type epitaxial layer, and then performing trench etching and oxide layer growth.

[0046] Referring to Figure 11 , a second conductivity type well region is implanted in the first conductivity type epitaxial layer. Specifically, P-type impurities are implanted in the epitaxial layer N+epi1 to form a P-type well region PW. Trench etching is then performed to form trenches AT and DT, where trench AT serves as the emitter trench and trench DT as the gate trench. After trench etching, an oxide layer is grown on the device surface. The resulting structure is shown in Figure 12 .

[0047] Step S13: filling the trench with polysilicon and implanting a first conductivity type well region.

[0048] 13 , polysilicon is filled in the etched trenches. After the polysilicon filling is completed, a first conductivity type well region is implanted on a side of the second conductivity type well region close to the second conductivity type super junction structure to form a first conductivity type well region.

[0049] Step S14: forming an insulating dielectric layer and implanting a first conductive type heavily doped region, then etching contact holes on the first conductive type heavily doped region and performing metallization to form an emitter metal layer.

[0050] Referring to Figure 14 , an insulating dielectric layer is first grown on the surface of the superjunction IGBT device. Then, a heavily doped region of the first conductivity type is implanted to form the heavily doped region 5. Contact holes are then etched above the insulating dielectric layer 9, and finally, surface metallization is performed to form the emitter metal layer 8. The emitter metal layer 8 is connected to the heavily doped region 5 of the first conductivity type through the contact hole.

[0051] Step S15: thinning the first conductive type substrate to form a buffer layer, and sequentially forming a second conductive type layer and a collector metal layer on a side of the buffer layer away from the first conductive type epitaxial layer.

[0052] After the annealing treatment in step S11, a concentration gradient difference has been formed between the first conductive type substrate and the first conductive type epitaxial layer. In this way, in step S15, the first conductive type substrate needs to be precisely thinned to the position of the required concentration to form a shallow buffer layer structure on the back side, forming a gradually changing "soft" buffer layer (shallow buffer) structure design. Compared with the traditional process, it reduces specific injection and thermal diffusion processes, further reducing the difficulty and cost of the process. In this way, this method can replace the conventional buffer layer obtained by back injection, further reducing the back process flow and reducing process costs. The super junction IGBT device shown in Figure 5 is obtained.

[0053] The super-junction IGBT device of the embodiment of the present invention adopts a P-column structure formed by a "gradient P" injection method, which is more conducive to forming a regular PN-column alternating distribution structure to achieve a regular rectangular electric field distribution in the body region and maximize the device's withstand voltage; the integrated chip back buffer layer structure design optimizes the back injection process flow, which not only improves the chip's sophistication, but also further improves the chip's performance.

[0054] In summary, the super junction IGBT device of the embodiment of the present invention includes: a first conductive type epitaxial layer, a plurality of trenches spaced apart on one side of the first conductive type epitaxial layer, a first conductive type well region, a second conductive type well region and a first conductive type heavily doped region are sequentially arranged between adjacent trenches along the extension direction of the first conductive type epitaxial layer, polysilicon and an oxide layer surrounding the polysilicon are arranged in the trenches, an emitter metal layer is arranged in the direction away from the first conductive type epitaxial layer, the emitter metal layer is connected to the first conductive type heavily doped region, and an insulating layer is arranged between the emitter metal layer and the trenches. A buffer layer, a second conductive type layer and a collector metal layer are sequentially arranged on the other side of the first conductive type epitaxial layer along a direction away from the first conductive type epitaxial layer; a plurality of second conductive type super junction structures are arranged in the body region of the first conductive type epitaxial layer along the extension direction of the first conductive type epitaxial layer, and the concentration of the second conductive type super junction structure changes gradually along the extension direction of the first conductive type epitaxial layer; the design requirements of the refined cell are met, the current density of the trench gate IGBT device is improved, and the introduction of the super junction structure accelerates the switching speed of the device, maximizes the withstand voltage of the device, reduces the switching loss of the device, and has strong practicality.

[0055] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present invention as described above, which are not provided in detail for the sake of simplicity.

[0056] This application is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of all embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of this disclosure.

Claims

1. A super junction IGBT device, characterized in that: The super junction IGBT device includes: a first conductive type epitaxial layer, a plurality of grooves arranged at intervals on one side of the first conductive type epitaxial layer, a first conductive type well region, a second conductive type well region and a first conductive type heavily doped region are arranged in sequence between adjacent grooves along the extension direction of the first conductive type epitaxial layer, polysilicon and an oxide layer surrounding the polysilicon are arranged in the grooves, an emitter metal layer is arranged in the direction away from the first conductive type epitaxial layer of the groove, the emitter metal layer is connected to the first conductive type heavily doped region, an insulating dielectric layer is arranged between the emitter metal layer and the grooves, a buffer layer, a second conductive type layer and a collector metal layer are arranged in sequence on the other side of the first conductive type epitaxial layer along the direction away from the first conductive type epitaxial layer; a plurality of second conductive type super junction structures are arranged in the body region of the first conductive type epitaxial layer along the extension direction of the first conductive type epitaxial layer, and the second conductive type super junction structure has a concentration gradient along the extension direction of the first conductive type epitaxial layer.

2. The super junction IGBT device according to claim 1, characterized in that: Along the extension direction of the first conductive type epitaxial layer, the concentration of the second conductive type super junction structure decreases successively.

3. The super junction IGBT device according to claim 1, characterized in that A second conductivity type super junction structure is disposed in the body region of the first conductivity type epitaxial layer directly below any of the trenches, and the second conductivity type super junction structure is in contact with the oxide layer below the trenches.

4. The super junction IGBT device according to claim 1, characterized in that: A second conductive type super junction structure is disposed in the body region of the first conductive type epitaxial layer directly below any of the trenches, and the second conductive type super junction structure is spaced a first preset distance from the bottom of the trench.

5. The super junction IGBT device according to claim 1, characterized in that: A second conductive type super junction structure is disposed in the body region of the first conductive type epitaxial layer directly below any adjacent trenches, and an end of the second conductive type super junction structure close to the trench is flush with the bottom of the trench.

6. The super junction IGBT device according to claim 1, characterized in that: A second conductive type super junction structure is arranged in the body region of the first conductive type epitaxial layer directly below any adjacent trenches, and an end of the second conductive type super junction structure close to the trench is spaced a second preset distance from the bottom of the trench in the extension direction of the first conductive type epitaxial layer.

7. A method for manufacturing a super junction IGBT device, characterized in that: The manufacturing method comprises: Generating a first conductivity type epitaxial layer on a first conductivity type substrate, and gradually performing second conductivity type implantation, and annealing to form a second conductivity type super junction structure; The second conductive type well region is implanted on the first conductive type epitaxial layer, and then the trench is etched and the oxidation layer is formed. Growth; Filling the trench with polysilicon and implanting a first conductivity type well region; Generating an insulating dielectric layer and implanting a first conductive type heavily doped region, then etching contact holes on the first conductive type heavily doped region and performing metallization to generate an emitter metal layer; The first conductive type substrate is thinned to generate a buffer layer, and a second conductive type layer and a collector metal layer are sequentially generated on a side of the buffer layer away from the first conductive type epitaxial layer.

8. The manufacturing method according to claim 7, characterized in that: The step of generating a first conductivity type epitaxial layer on a first conductivity type substrate and gradually performing second conductivity type implantation comprises: Generating a first conductivity type epitaxial layer on a first conductivity type substrate; Starting from a first distance from the first conductive type epitaxial layer on a side away from the first conductive type substrate, a second conductive type is implanted into the first conductive type epitaxial layer at intervals of a second distance, and the implantation dose is successively reduced, wherein the second distance is equal to 1 / n of the first distance, and n is a positive integer; A new first conductivity type epitaxial layer is continuously generated on the first conductivity type epitaxial layer.

9. The manufacturing method according to claim 7, characterized in that: The step of generating a first conductivity type epitaxial layer on a first conductivity type substrate and gradually performing second conductivity type implantation comprises: Generating a first conductivity type epitaxial layer on a first conductivity type substrate; Epitaxially grow a new first conductivity type epitaxial layer on the first conductivity type epitaxial layer n times, and perform second conductivity type implantation in each newly grown first conductivity type epitaxial layer, and the implantation dose decreases successively, and n is a positive integer; A new first conductivity type epitaxial layer is continuously generated on the first conductivity type epitaxial layer.

10. The manufacturing method according to claim 7, characterized in that: The first conductive type substrate and the first conductive type epitaxial layer are heavily doped with the first conductive type, and the doping concentration of the first conductive type substrate is higher than the doping concentration of the first conductive type epitaxial layer.

Images