Circuit model simulation method and device, and computer-readable storage medium

Abstract

Disclosed in the present disclosure are a circuit model simulation method and device, and a computer-readable storage medium. The simulation method comprises: acquiring a template circuit file of a target circuit model; pre-simulating the template circuit file to obtain a pre-simulation time; determining a netlist assembly mode of a simulation task of the template circuit file on the basis of the pre-simulation time; using the corresponding netlist assembly mode to assemble the simulation task; and simulating a netlist file obtained by means of assembly. By means of the circuit model simulation method and device, and the computer-readable storage medium provided above, an improvement in the simulation speed and simulation efficiency of the target circuit model is facilitated.

Description

Circuit model simulation method, device and computer-readable storage medium CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to the Chinese patent application filed on December 22, 2023, with application number 202311787324.X and titled “Simulation method, device and computer-readable storage medium for circuit model”. Technical Field

[0002] The present disclosure generally relates to the field of circuit simulation technology. More specifically, the present disclosure relates to a circuit model simulation method, a circuit model simulation device, and a computer-readable storage medium. Background Art

[0003] During the parameter extraction process for semiconductor device models, the diversity of template circuits and the inconsistency of simulation speeds impact the efficiency of parameter extraction. Traditional simulation methods typically assemble a netlist file for each template circuit simulation task, then simulate each netlist file to extract the semiconductor device model parameters. However, this approach suffers from low simulation speed and efficiency.

[0004] In view of this, there is an urgent need to provide a circuit model simulation solution to improve the simulation speed of the circuit model of the semiconductor device. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems mentioned above, the present disclosure proposes a circuit model simulation method, a device for circuit model simulation, and a computer-readable storage medium solution in multiple aspects.

[0006] In a first aspect, the present disclosure provides a simulation method for a circuit model, comprising: obtaining a template circuit file of a target circuit model; pre-simulating the template circuit file to obtain a pre-simulation time; determining a netlist assembly method for a simulation task of the template circuit file based on the pre-simulation time; assembling the simulation task using a corresponding netlist assembly method; and simulating the assembled netlist file.

[0007] In some embodiments, determining the netlist assembly method of the simulation task of the template circuit file based on the pre-simulation time includes: in response to the pre-simulation time being greater than a preset threshold, determining that the netlist assembly method of the simulation task of the template circuit file is a first assembly method; in response to the pre-simulation time being less than or equal to a preset threshold, determining that the netlist assembly method of the simulation task of the template circuit file is a second assembly method.

[0008] In other embodiments, the first assembling method includes assembling a simulation task into a netlist file; the second assembling method includes assembling at least two simulation tasks of the same template circuit file into a netlist file.

[0009] In some further embodiments, assembling the simulation task using a corresponding netlist assembly method includes: in response to determining that the netlist assembly method is a first assembly method, replacing the circuit variables in the corresponding template circuit file with the simulation task variables of the simulation task; in response to determining that the netlist assembly method is a second assembly method, assembling the at least two simulation tasks into a netlist file based on the simulation task variables in the at least two simulation tasks of the same template circuit file.

[0010] In some embodiments, assembling the at least two simulation tasks into one netlist file includes: assembling the at least two simulation tasks into one netlist file using an Alter language.

[0011] In other embodiments, the preset threshold includes 200ms.

[0012] In some further embodiments, assembling the simulation tasks using the corresponding netlist assembly method further includes: determining the number of netlist files corresponding to the same template circuit file in the second assembly method based on the number of simulation processes used to perform the simulation; and determining the number of simulation tasks for the same template circuit file used to assemble into a netlist file based on the number of netlist files.

[0013] In some embodiments, the number of simulation processes is less than or equal to the number of processors in the device used to perform the simulation, and the sum of the number of netlist files assembled using the first assembly method and the number of netlist files assembled using the second assembly method is less than or equal to the number of simulation processes, and one netlist file calls a corresponding simulation process to perform simulation.

[0014] In other embodiments, the target circuit model includes a circuit model of at least one of a static random access memory, an inverter, a ring oscillator, an inverter ring oscillator, an amplifier, an inverter, a delay chain, and a phase-locked loop.

[0015] In a second aspect, the present disclosure provides a device for circuit model simulation, comprising: a processor for executing program instructions; and a memory storing the program instructions, wherein when the program instructions are loaded and executed by the processor, the processor executes the simulation method according to any one of the first aspects of the present disclosure.

[0016] In a third aspect, the present disclosure provides a computer-readable storage medium having computer-readable instructions stored thereon. When the computer-readable instructions are executed by one or more processors, the simulation method as described in any one of the first aspects of the present disclosure is implemented.

[0017] Through the circuit model simulation method, device, and computer-readable storage medium provided above, the disclosed embodiments pre-simulate a template circuit file and determine a netlist assembly method based on the pre-simulation time, thereby assembling a netlist for the simulation task using the corresponding netlist assembly method. Simulating the netlist file assembled in this manner can take into account the inconsistencies in the simulation speeds of various template circuit files and adopt a targeted netlist assembly method, thereby improving the simulation speed and efficiency of the circuit model of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an illustrative and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0019] FIG1 shows a flow chart of a simulation method of a circuit model according to an embodiment of the present disclosure;

[0020] FIG2 shows a flow chart of a simulation method according to another embodiment of the present disclosure;

[0021] FIG3 is a schematic block diagram illustrating a system for circuit model simulation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of this disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this disclosure, not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this disclosure.

[0023] It should be understood that the terms “include” and “comprising” used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0024] It should also be understood that the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0025] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0026] The inventors have found that when a circuit model includes multiple template circuits to be simulated, and / or the template circuits correspond to multiple simulation tasks, assembling each simulation task into a netlist file for simulation will take up many simulation processes. In particular, when the number of simulation tasks is greater than the number of simulation processes, the simulation process needs to be simulated in a loop to complete a round of simulation operations, resulting in a long simulation time, affecting the simulation speed and simulation efficiency. The inventors have also found that, if all simulation tasks of each template circuit are assembled into a netlist file, although the number of netlist files can be reduced to reduce the number of occupied simulation processes, the amount of simulation data for each netlist file will be large, thereby increasing the simulation time of each simulation process that performs simulation, and at the same time causing other simulation processes to idle, resulting in a waste of computing resources.

[0027] Based on this, the present disclosure provides a new solution that pre-simulates a template circuit file and, based on the pre-simulation time, uses a targeted netlist assembly method to assemble the netlist file, thereby improving the simulation speed and efficiency of the circuit model of the semiconductor device. The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0028] FIG1 shows a flow chart of a simulation method for a circuit model according to an embodiment of the present disclosure. As shown in FIG1 , the simulation method 100 may include: in step 101, a template circuit file of a target circuit model may be obtained. The target circuit model may be a circuit model of a circuit device to be simulated. In some embodiments, the target circuit model may include a circuit model of a semiconductor device. In other embodiments, the target circuit model may include a circuit model of at least one device of a static random access memory (SRAM), an inverter, a ring oscillator, an inverter ring oscillator (a ring oscillator made of an inverter), an amplifier, an inverter, a delay chain, a phase-locked loop, etc.

[0029] In step 101, one or more template circuit files of the target circuit model may be obtained. In some embodiments, the template circuit file may be a circuit file including the target circuit model. The template circuit file provides a peripheral circuit for the target circuit model, which may be used to simulate the parameters of the target circuit model. Different template circuit files may provide different peripheral circuits for the target circuit model, for simulating different parameters of the target circuit model. For example, assuming that multiple output parameters of the target circuit model need to be simulated, a corresponding plurality of template circuit files may be obtained for the multiple output parameters, each template circuit file may provide a peripheral circuit in which the target circuit model can output the corresponding output parameters, and the target circuit model may be placed in the circuit environment of the plurality of template circuit files to simulate the output conditions of the target circuit model in a variety of circuit environments, thereby being used to simulate multiple output parameters of the target circuit model.

[0030] Next, in step 102, the template circuit file may be pre-simulated to obtain a pre-simulation time. In some embodiments, a simulation tool may be used to pre-simulate the template circuit file. In other embodiments, the pre-simulation may be performed by performing a round of simulation operations, and the pre-simulation time may be the time required to perform the round of simulation operations. In still other embodiments, the simulation tool may include a Spice simulator, etc. In some embodiments, in response to the existence of multiple template circuit files to be simulated, the multiple template circuit files may be pre-simulated separately to obtain a pre-simulation time for each template circuit file.

[0031] Then, the process can proceed to step 103, and the netlist assembly method of the simulation task of the template circuit file can be determined based on the pre-simulation time. Each template circuit file can have one or more simulation tasks. For example, assuming that the simulation task to be simulated includes the parameters of the target circuit template obtained by simulating the template circuit file at multiple temperatures, that is, the same template circuit file can have simulation tasks simulated at multiple temperatures. In other embodiments, the simulation tasks of the same template circuit file can adopt the same netlist assembly method. In some embodiments, the netlist assembly method can include assembling one netlist file for one simulation task, assembling one netlist file for multiple simulation tasks, etc.

[0032] The inventors have found that the factors affecting the simulation speed mainly include two stages: database establishment and simulation calculation. Generally, for template circuit files with faster simulation speeds, the simulation calculation speed is faster, while the database establishment speed is relatively slow; for template circuit files with slower simulation speeds, the simulation calculation speed is slower, while the database establishment speed is relatively fast.

[0033] Based on this, for template circuit files with faster simulation speeds, assembling a netlist file for one simulation task requires multiple database builds, resulting in slower simulation speeds. However, assembling multiple simulation tasks into one netlist file reduces the number of database builds, which can help improve the model's simulation speed. For template circuit files with slower simulation speeds, assembling multiple simulation tasks into one netlist file increases the simulation computational load, thereby reducing the model's simulation speed. In comparison, assembling one netlist file per simulation task leverages the faster database build speed, which is more conducive to ensuring the model's simulation speed.

[0034] Therefore, the pre-simulation speed of the template circuit file can be determined based on the length of the pre-simulation time, so that the simulation speed of each netlist file used to perform the simulation can be optimized by determining an appropriate netlist assembly method, so as to improve the simulation speed and simulation efficiency of the model. For example, the netlist assembly method of the simulation task of the template circuit file with a short pre-simulation time can be determined as a method of assembling one netlist file from multiple simulation tasks; or the netlist assembly method of the simulation task of the template circuit file with a long pre-simulation time can be determined as a method of assembling one netlist file from a single simulation task. For example, in other embodiments, in response to the existence of multiple template circuit files to be simulated, the multiple template circuit files can be grouped according to the length of the pre-simulation time, and it can be determined that the simulation tasks of the template circuit files in the same group adopt the same netlist assembly method.

[0035] After determining the netlist assembly method for the simulation task of the template circuit file, the process can proceed to step 104, and the corresponding netlist assembly method can be used to assemble the simulation task. Corresponding here refers to the netlist assembly method corresponding to the template circuit file determined in step 103. In some embodiments, in response to the existence of multiple template circuit files, the simulation task of each template circuit file can be assembled using the netlist assembly method corresponding to each template circuit file. In other embodiments, in response to the existence of multiple simulation tasks for the same template circuit file, the netlist assembly method corresponding to the template circuit file can be used to assemble one or more simulation tasks of the template circuit file.

[0036] Further, in step 105, the assembled netlist file can be simulated. In some embodiments, the netlist file can be a description of the circuit structure involved in the simulation task. In some embodiments, the template circuit file can be pre-simulated using a simulation tool. In other embodiments, the simulation tool can include a Spice simulator, etc. In some other embodiments, in response to the simulation result of the current round of simulation not reaching the simulation target, the simulation is repeated until the simulation result reaches the simulation target. In some embodiments, the simulation target can be determined based on the actual measured values ​​of the electrical parameters of the target circuit model. In other embodiments, each simulation task can have a corresponding simulation target. For example, assuming that the simulation task of the target circuit model to be simulated is the simulation of the output current, and its actual measured value is 5A, the simulation target can be determined as 5A; in response to the output current in the simulation result not being 5A, the simulation can be repeated until the output current in the simulation result is 5A, thereby completing the simulation and parameter extraction.

[0037] The above is an exemplary description of the simulation method of the circuit model according to the embodiment of the present disclosure in combination with Figure 1. It can be understood that the above description is exemplary rather than restrictive. In order to more easily understand the implementation method of the simulation method of the embodiment of the present disclosure, it will be further explained in combination with Figure 2 below.

[0038] FIG2 is a flowchart of a simulation method according to another embodiment of the present disclosure. As will be apparent from the following description, the simulation method 200 described below in conjunction with FIG2 may be a specific embodiment of the simulation method 100 described above in conjunction with FIG1 . Therefore, the description of the simulation method 100 in conjunction with FIG1 may also be applicable to the description of the simulation method 200 below.

[0039] As shown in FIG2 , simulation method 200 may include: in step 201, obtaining a template circuit file of a target circuit model. In step 202, pre-simulation may be performed on the template circuit file to obtain a pre-simulation time. Steps 201 and 202 have been described in detail above in conjunction with steps 101 and 102 shown in FIG1 , and will not be repeated here.

[0040] Then, in step 203, it can be determined whether the pre-simulation time is greater than a preset threshold. In some embodiments, the preset threshold may include, for example, 200ms. The preset threshold can be set based on actual application conditions or experience. The preset threshold is also related to the configuration and operating system of the device used to perform the simulation. The higher the configuration of the device and the faster the operating speed, the smaller the preset threshold can be set; the lower the configuration of the device and the slower the operating speed, the larger the preset threshold can be set. In other embodiments, the number of preset thresholds may not be limited to one, and multiple thresholds may be set, so that more netlist assembly methods can be divided according to the pre-simulation time.

[0041] In response to the pre-simulation time being greater than a preset threshold, the process may proceed to step 204, where the netlist assembly method for the simulation task of the template circuit file may be determined to be a first assembly method. In some embodiments, the first assembly method may include assembling one simulation task into one netlist file. That is, the simulation tasks of the template circuit file that meet the requirement that the pre-simulation time is greater than the threshold and their netlist files may correspond one to one, such that one simulation task corresponds to one netlist file. According to the first assembly method, the number of assembled netlist files may be the same as the number of simulation tasks.

[0042] Then, the process can proceed to step 205. In response to determining that the netlist assembly mode is the first assembly mode, the simulation task variables of the simulation task can be used to replace the circuit variables in the corresponding template circuit file to form a netlist file. Circuit variables refer to the changeable circuit parameters corresponding to the simulation task variables in the template circuit file. The simulation task variables can be simulation conditions or variable parameters required or set in the simulation task. For example, assuming that the simulation task variable of a certain simulation task is temperature, the circuit temperature in the template circuit file corresponding to the simulation task (i.e., the circuit variable corresponding to the simulation task variable) can be replaced with the temperature required for the simulation task. In other embodiments, in response to determining that the assembly mode of multiple simulation tasks is the first assembly mode, the circuit variables in the template circuit file corresponding to each simulation task can be replaced accordingly in turn to form multiple netlist files.

[0043] Further, as further shown in Figure 2, in response to the pre-simulation time being less than or equal to a preset threshold, the process can proceed to step 206, and the netlist assembly method of the simulation task of the template circuit file can be determined to be the second assembly method. In some embodiments, the second assembly method may include assembling at least two simulation tasks of the same template circuit file into one netlist file. In other embodiments, all simulation tasks of the same template circuit file can be assembled into one netlist file. In yet other embodiments, some simulation tasks of all simulation tasks of the same template circuit file can be assembled into one netlist file. For example, in some embodiments, one template circuit file corresponds to eight simulation tasks, and the eight simulation tasks can be assembled into one netlist file; or three simulation tasks of the eight simulation tasks can be assembled into one netlist file, and the remaining five simulation tasks can be assembled into another netlist file. According to the second assembly method, the number of assembled netlist files is less than the number of simulation tasks.

[0044] Then, the process can proceed to step 207. In response to determining that the netlist assembly mode is the second assembly mode, the at least two simulation tasks can be assembled into a netlist file based on at least two simulation task variables in at least two simulation tasks of the same template circuit file. In some embodiments, at least two simulation tasks can be assembled into a netlist file in a programming manner. In other embodiments, assembling at least two simulation tasks into a netlist file can include: assembling at least two simulation tasks into a netlist file using Alter language. Alter is a modification statement of SPICE standard syntax, and the simulation task variables can be modified by using Alter language so that the simulation task variables of at least two simulation tasks can be assembled into a netlist file.

[0045] In some other embodiments, step 207 may further include: determining the number of netlist files corresponding to the same template circuit file in the second assembly mode based on the number of simulation processes used to perform the simulation; and determining the number of simulation tasks for assembling the same template circuit file into one netlist file based on the number of netlist files. If the number of simulation tasks is greater than the number of simulation processes, the number of assembled netlist files may be controlled to be less than or equal to the number of simulation processes, which can help improve the simulation parallelism of each netlist file and thus help improve the simulation speed.

[0046] In some embodiments, in response to the existence of a netlist file assembled in the first assembly method, the number of netlist files in the second assembly method can be determined based on the difference between the number of simulation processes and the number of netlist files assembled in the first assembly method, and the number of netlist files corresponding to each template circuit file can be determined. In other embodiments, in response to the absence of a netlist file assembled in the first assembly method, the number of netlist files in the second assembly method can be determined based on the number of simulation processes, and the number of netlist files corresponding to each template circuit file can be determined.

[0047] For example, assuming that there are simulation tasks for two template circuit files in the second assembly method, and the number of simulation processes is three (in the absence of a netlist file assembled by the first assembly method, or the number of simulation processes after subtracting the number of netlist files assembled by the first assembly method), all simulation tasks of one template circuit file in the second assembly method can be assembled into one netlist file, and the simulation tasks of another template circuit file in the second assembly method can be assembled into two netlist files.

[0048] Furthermore, assuming that a template circuit file needs to be assembled into two netlist files, and the template circuit file corresponds to five simulation tasks, two of the five simulation tasks can be assembled into one netlist file, and the remaining three simulation tasks can be assembled into another netlist file.

[0049] In some further embodiments, when assembling simulation tasks for a template circuit file that conforms to the second assembly method, in response to the fact that there is only one simulation task to be assembled, the first assembly method may be used for assembly. For example, assuming that a template circuit file needs to be assembled into two netlist files, and the template circuit file corresponds to three simulation tasks, two of the three simulation tasks may be assembled into one netlist file, while the remaining simulation task may be assembled into another netlist file according to the first assembly method.

[0050] In other embodiments, the number of simulation processes can be set to be less than or equal to the number of processors in the device used to perform the simulation, and the sum of the number of netlist files assembled using the first assembly method and the number of netlist files assembled using the second assembly method can be less than or equal to the number of simulation processes, and one netlist file can call a corresponding simulation process to perform simulation.

[0051] According to such a setting, one processor can process one simulation process, so that all simulation processes can be executed in parallel. According to the number of simulation processes set in this way, the number of netlist files is determined, and by setting a netlist file to call a corresponding simulation process to perform simulation, all netlist files can be simulated in parallel, which is conducive to further improving the simulation speed and simulation efficiency. Furthermore, by determining the number of netlist files corresponding to the same template circuit file in the second assembly method according to the number of simulation processes, the amount of simulation tasks executed by each simulation process can be set more evenly, which is conducive to avoiding the waste of resources caused by the idle operation of the simulation process, and is conducive to improving the simulation speed and simulation efficiency.

[0052] As further shown in FIG. 2 , after the netlist files are assembled according to the various assembly methods, the process proceeds to step 208 , where the assembled netlist files are simulated. Multiple simulation processes can be used to execute the netlist files in parallel to further improve simulation speed and efficiency. Step 208 may be the same as or similar to step 105 described above in conjunction with FIG. 1 , and will not be further described here.

[0053] In summary, the simulation method of the disclosed embodiment pre-simulates the template circuit file and determines the appropriate netlist assembly method according to the pre-simulation time, so that when simulating the netlist file assembled using the corresponding netlist assembly method, it can help improve the simulation speed and efficiency.

[0054] The above-mentioned solutions of the embodiments of the present disclosure can be implemented with the aid of program instructions. Therefore, the present disclosure also provides a device for circuit model simulation, comprising: a processor configured to execute program instructions; and a memory storing program instructions, wherein when the program instructions are loaded and executed by the processor, the processor executes the simulation method described above in conjunction with any of the embodiments of FIG. 1 and FIG. 2 .

[0055] FIG3 is a schematic block diagram of a system for circuit model simulation according to an embodiment of the present disclosure. The system 300 may include a device 301 according to an embodiment of the present disclosure, as well as its peripheral devices and external networks, wherein the device 301 is used to perform simulation operations on a semiconductor device model to implement the technical solutions of the embodiments of the present disclosure described in any of FIG1-FIG2. As shown in FIG3, the device 301 may include a CPU (Central Processing Unit) 3011, which may be a general-purpose CPU, a dedicated CPU, or other information processing and program execution unit. Further, the device 301 may also include a large-capacity memory 3012 and a read-only memory ROM 3013, wherein the large-capacity memory 3012 may be configured to store various types of data, including target circuit models, template circuit files, etc., as well as various programs required for running simulations, and the ROM 3013 may be configured to store data required for power-on self-test of the device 301, initialization of various functional modules in the system, basic input / output drivers of the system, and booting the operating system. Furthermore, the device 300 also includes other hardware platforms or components, such as the TPU (Tensor Processing Unit) 3014, GPU (Graphics Processing Unit) 3015, FPGA (field-programmable gate array) 3016 and MLU (Machine Learning Unit) 3017 shown. It will be understood that although a variety of hardware platforms or components are shown in the device 300, this is merely exemplary and not restrictive, and those skilled in the art can add or remove corresponding hardware according to actual needs. For example, the device 301 may include only a CPU as a well-known hardware platform and another hardware platform as the test hardware platform of the present disclosure.

[0056] The device 301 of the present disclosure also includes a communication interface 3018, so that it can be connected to a local area network / wireless local area network (LAN / WLAN) 305 through the communication interface 3018, and then connected to a local server 306 or to the Internet ("Internet") 307 through the LAN / WLAN. Alternatively or additionally, the device 301 of the present disclosure can also be directly connected to the Internet or a cellular network based on wireless communication technology through the communication interface 3018, such as wireless communication technology based on the third generation ("3G"), fourth generation ("4G") or fifth generation ("5G") generation. In some application scenarios, the device 301 of the present disclosure can also access a server 308 of an external network and a possible database 309 as needed to obtain various known data, etc., and can remotely store various parameters or intermediate data.

[0057] The peripheral devices of device 301 may include display device 302, input device 303 and data transmission interface 304. In one embodiment, display device 302 may include, for example, one or more speakers and / or one or more visual displays, which are configured to perform voice prompts and / or image video display on the simulation process and simulation results of the disclosed device. Input device 303 may include, for example, a keyboard, a mouse, a microphone, a gesture capture camera, or other input buttons or controls, which are configured to receive input or user instructions from a processor. Data transmission interface 304 may include, for example, a serial interface, a parallel interface or a universal serial bus interface ("Universal Serial Bus, USB"), a small computer system interface ("Small Computer System Interface, SCSI"), a serial ATA (Advanced Technology Attachment, hard disk interface specification), FireWire ("FireWire"), PCI Express and a high-definition multimedia interface ("High Definition Multimedia Interface, HDMI"), etc., which are configured to transmit and interact with data of other devices or systems. According to the scheme disclosed herein, the data transmission interface 304 can receive template circuit files, simulation tasks, etc. of a target circuit model, and transmit various types of data and results to device 301.

[0058] The CPU 3011, mass storage 3012, read-only memory ROM 3013, TPU 3014, GPU 3015, FPGA 3016, MLU 3017, and communication interface 3018 of the device 301 of the present disclosure can be interconnected via a bus 3019 and can exchange data with peripheral devices via the bus. In one embodiment, the CPU 3011 can control other hardware components in the device 301 and its peripheral devices via the bus 3019.

[0059] During operation, the processor CPU 3011 of the device 301 disclosed herein can receive a netlist file of a target circuit model for simulation via the input device 303 or the data transmission interface 304, and retrieve computer program instructions or code (e.g., code related to simulation operations) stored in the memory 3012 to simulate the received netlist file to obtain simulation results. After the CPU 3011 determines the simulation results by executing the program instructions, the simulation results can be displayed on the display device 302 or output via voice prompts. In addition, the device 301 can also upload the simulation results to a network, such as a remote database 309, via the communication interface 3018.

[0060] It should also be understood that any module, unit, component, server, computer, terminal, or device that executes instructions of the disclosed examples may include or otherwise access computer-readable media, such as storage media, computer storage media, or data storage devices (removable and / or non-removable) such as magnetic disks, optical disks, or tapes. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data.

[0061] Based on the above, the present disclosure further provides a computer-readable storage medium having computer-readable instructions stored thereon. When the computer-readable instructions are executed by one or more processors, the simulation method described above in combination with any one of the embodiments in FIG. 1-FIG . 2 is implemented.

[0062] The computer-readable storage medium may be any suitable magnetic storage medium or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc., or any other medium that can be used to store the required information and can be accessed by the application, module, or both. Any such computer storage medium may be part of the device or accessible or connectable to the device. Any application or module described in this disclosure may be implemented using computer-readable / executable instructions that may be stored or otherwise maintained by such a computer-readable medium.

[0063] Although a plurality of embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may conceive of many modifications, changes, and alternatives without departing from the ideas and spirit of the present disclosure. It should be understood that in practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The appended claims are intended to define the scope of protection of the present disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A circuit model simulation method, comprising: Obtain a template circuit file of a target circuit model; Pre-simulating the template circuit file to obtain a pre-simulation time; Determining a netlist assembly mode of a simulation task of the template circuit file according to the pre-simulation time; Assembling the simulation task using a corresponding netlist assembly method; as well as Simulate the assembled netlist file.

2. The simulation method according to claim 1, wherein determining the netlist assembly mode of the simulation task of the template circuit file according to the pre-simulation time comprises: In response to the pre-simulation time being greater than a preset threshold, determining that the netlist assembly mode of the simulation task of the template circuit file is a first assembly mode; In response to the pre-simulation time being less than or equal to a preset threshold, determining that the netlist assembly mode of the simulation task of the template circuit file is a second assembly mode.

3. The simulation method according to claim 2, wherein The first assembling method includes assembling a simulation task into a netlist file; The second assembling method includes assembling at least two simulation tasks of the same template circuit file into one netlist file.

4. The simulation method according to claim 2 or 3, wherein assembling the simulation task using a corresponding netlist assembly method comprises: In response to determining that the netlist assembly mode is the first assembly mode, replacing the circuit variables in the corresponding template circuit file with the simulation task variables of the simulation task; In response to determining that the netlist assembly mode is the second assembly mode, the at least two simulation tasks are assembled into one netlist file according to simulation task variables in the at least two simulation tasks of the same template circuit file.

5. The simulation method according to claim 4, wherein assembling the at least two simulation tasks into a netlist file comprises: The at least two simulation tasks are assembled into a netlist file using the Alter language. The simulation method according to claim 2 , wherein the preset threshold comprises 200 ms.

7. The simulation method according to claim 2 or 3, wherein assembling the simulation task using a corresponding netlist assembly method further comprises: Determining the number of netlist files corresponding to the same template circuit file in the second assembly mode according to the number of simulation processes used to perform the simulation; as well as The number of simulation tasks for assembling a same template circuit file into one netlist file is determined according to the number of netlist files.

8. The simulation method according to claim 7, wherein the number of simulation processes is less than or equal to the number of processors in the device for performing the simulation, and The sum of the number of netlist files assembled using the first assembly method and the number of netlist files assembled using the second assembly method is less than or equal to the number of simulation processes, and one netlist file calls a corresponding simulation process to perform simulation.

9. The simulation method according to claim 1, wherein The target circuit model includes a circuit model of at least one device of a static random access memory, an inverter, a ring oscillator, an inverter ring oscillator, an amplifier, an inverter, a delay chain, and a phase-locked loop.

10. A device for circuit model simulation, comprising: a processor for executing program instructions; as well as A memory storing the program instructions, which, when loaded and executed by the processor, enables the processor to execute the simulation method according to any one of claims 1 to 9.

11. A computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by one or more processors, the simulation method according to any one of claims 1 to 9 is implemented.

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