An address decoder for an SRAM

Abstract

The present disclosure relates to an SRAM. The SRAM comprises an address decoder including a plurality of NAND gates and inverter gates. Each NAND gate is connected to a unique combination of address lines representing a plurality of addresses. Each inverter gate is e8xclusively connected to one of a plurality of sequentially numbered word associated with one of the plurality of addresses. The address decoder further comprises a set of first pass gates and a set of second pass gates. Each NAND gate is associated with a first pass gate to establish or break a connection of the NAND gate to an inverter gate connected to a word line having a particular number, and with a second pass gate to establish or break a connection of the NAND gate to an inverter gate connected to a word line having a number equal to the particular number plus one.

Description

[0001] AN ADDRESS DECODER FOR AN SRAM

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to a static random access memory (SRAM). In particular, the disclosure is concerned with the address decoder of the SRAM, which is configured to decode addresses that are associated with word lines of the SRAM.

[0004] BACKGROUND

[0005] When retrieving instructions from an SRAM array, there are instances where a read operation needs to be performed on a word line subsequent to the word line that is indicated by a current address, which is decoded by the address decoder of the SRAM. For example, this situation may arise, when data is to be accessed from different parts of the array simultaneously. In such cases, while certain sections of the array are accessed using the decoded current address, others may be accessed using an incremented address that points to the next word line. This approach allows for a more flexible and efficient data retrieval from the SRAM array.

[0006] A conventional solution to facilitate the reading from the next word line, as described above, involves the use of an adder and a multiplexer. The adder is configured to increment the current address by one, thereby generating the incremented address for the next word line. Following this, a 2: 1 multiplexer is employed for each output bit of the adder. These multiplexers are controlled by a common control signal. The common control signal determines whether the data access from the SRAM array should be based on the current address or the incremented address. By toggling the control signal, one can switch between accessing data from the current address or from the incremented address of the next word line.

[0007] However, incorporating such an adder, even for a simple operation like adding “plus one”, has drawbacks. Firstly, the adder operation consumes valuable time, which could impact the overall speed of the data retrieval. Secondly, the adder (and the multiplexers) requires additional chip area. Thirdly, the operation of the adder demands extra power. Moreover, in scenarios where multiple input sources are involved, this adder-based approach may need to be replicated multiple times.

[0008] SUMMARY

[0009] In view of the above, an objective of this disclosure is to provide an improved solution for reading based on the next word line with respect to the word the line pointed to by a current address, rather than reading based on the pointed to word line itself. Another objective is to perform the required “plus one” function without the need for an adder on the critical address path.

[0010] These and other objectives are achieved by the solutions of this disclosure as described in the independent claims. Advantageous implementations are further described in the dependent claims.

[0011] A first aspect of this disclosure provides an SRAM, comprising an address decoder for decoding a plurality of addresses, wherein the address decoder includes: a plurality of NAND gates, wherein each NAND gate is connected to a unique combination of address lines of a plurality of address lines, the plurality of address lines being configured to represent the plurality of addresses; a plurality of inverter gates, wherein each inverter gate is exclusively connected to one word line of a plurality of sequentially numbered word lines of the SRAM, each word line being associated with one of the plurality of addresses; and a plurality of pass gates comprising a set of first pass gates and a set of second pass gates; wherein each NAND gate is associated with a respective first pass gate, which is configured to establish or break a connection of the NAND gate to an inverter gate connected to a word line having a particular number; wherein each NAND gate is further associated with a respective second pass gate, which is configured to establish or break a connection of the NAND gate to an inverter gate connected to a word line having a number equal to the particular number plus one; wherein the plurality of pass gates are controlled by a common control line; and wherein the first pass gates are designed to establish the connection if a control signal is provided on the control line and to break the connection if the inverse of the control signal is provided on the control line, and the second pass gates are designed to establish the connection if the inverse of the control signal is provided on the control line and to break the connection if the control signal is provided on the control line.

[0012] Compared to a conventional address decoder of an SRAM, the pass gates are added between each of the NAND gates and the corresponding inverter gate, which is driving an associated word line of the array. In this way, the required “plus one” function can be performed, without the need for an adder on the critical address path. Accordingly, an improved solution for reading based on the next word line with respect to the word the line pointed to be the current address is provided. The solution may particular allow for a faster data retrieval, may require less chip area, and may demand lower power.

[0013] In an implementation of the first aspect, the address decoder is a line decoder and the addresses are row addresses.

[0014] The SRAM may comprise a memory array, wherein the word lines are arranged in and define rows, and wherein bit lines of the SRAM are arranged in and defined columns. This arrangement allows for the organization and addressability of individual memory cells of the array at the intersection of these lines.

[0015] In an implementation of the first aspect, the word lines are sequentially numbered from 0 to N, and the number N plus one is equal to the number 0.

[0016] In an exemplary implementation of the first aspect, N=255. However, the solutions of this disclosure are not limited to that number of N.

[0017] In an implementation of the first aspect, the first pass gates and the second pass gates each comprise a pair of an NMOS transistor and a PMOS transistor, wherein the pairs in the second pass gates are connected inversely compared to the pairs in the first pass gates.

[0018] In this way, the first pass gates and the second pass gates behave oppositely in response to the control signal or the inverse of the control signal, respectively, on the control line.

[0019] In an implementation of the first aspect, the control signal is a high or low signal on the control line, and the inverse of the control signal is respectively a low or high signal on the control line.

[0020] That is, if the control signal is a high signal, the inverse control signal is a low signal. If the control signal is a low signal, the inverse control signal is a high signal. High and low are relative and determine “1” and “0” of the digital signals.

[0021] In an implementation of the first aspect, each NAND gate is connected to a different combination of address lines and corresponding inverted address lines.

[0022] This facilitates precise address decoding. The configuration may ensure that each NAND gate responds to a specific combination of address inputs, thereby accurately selecting the corresponding word line (or next word line). A second aspect of this disclosure provides a method for operating an SRAM of the first aspect or any implementation form thereof, wherein the method comprises: providing the control signal on the control line, in order to select a word line associated with a particular address of the plurality of addresses; and / or providing the inverse of the control signal on the control line, in order to select a word line associated with an address equal to the particular address plus one.

[0023] In an implementation form of the second aspect, the method further comprises providing a distinct set of address signals on the plurality of address lines, in order to provide the particular address to the address decoder of the SRAM.

[0024] The method of the second aspect achieves the advantages described above with respect to the SRAM of the first aspect.

[0025] A third aspect of this disclosure provide a computer program comprising instructions which, when the program is executed by a processor, cause the processor to perform the method according to the second aspect or its implementation form.

[0026] A fourth aspect of this disclosure provides a non-transitory storage medium storing executable program code which, when executed by a processor, causes the method according to the second aspect or any of its implementation forms to be performed.

[0027] In summary of the above, the present disclosure implements a 2: 1 multiplexer as simple pass gates arranged inside the address decoder (particularly, a line decoder or x-decoder) of the SRAM. The addition of the first and second pass gates enables the shifting of the decoded current address by one (word line), just as functionally required. The second pass gates always add one, not more. The timing and area cost of this solution are minimal, the functional need is sufficiently met, and the need for adder and multiplexers on the critical address path, as described above, is eliminated.

[0028] It has to be noted that some entities, elements, units and means described in the present application could be implemented by software or hardware elements or any kind of combination thereof. All steps performed by the various entities described in the present application, as well as the functionalities described to be performed by the various entities, are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity, which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented by respective software or hardware elements, or any kind of combination thereof.

[0029] BRIEF DESCRIPTION OF DRAWINGS

[0030] The above described aspects and implementation forms are explained in the following description in relation to the enclosed drawings, in which:

[0031] FIG. 1 shows parts of an address decoder of an SRAM according to this disclosure.

[0032] FIG. 2 shows parts of an exemplary address decoder of an SRAM according to this disclosure.

[0033] FIG. 3 shows a method according to this disclosure for operating an SRAM according to this disclosure. DETAILED DESCRIPTION OF EMBODIMENTS

[0034] FIG. 1 shows parts of an SRAM according to this disclosure, in particular, it shows parts of an address decoder 100 of the SRAM. The address decoder 100 may be referred to a as line decoder, x-decoder, or row decoder. Besides the shown parts of the address decoder 100, the SRAM may be designed like a conventional SRAM, in particular, the address decoder 100 may be designed like an address decoder of a conventional SRAM apart from the new features described in the following.

[0035] As shown in FIG. 1, the address decoder 100 comprises a plurality of NAND gates 101. Each NAND gate 101 is connected to a unique combination of address lines 102a, 102b, 102c of a plurality of address lines 102, wherein the plurality of address lines 102 are configured to represent the plurality of addresses. In FIG. 1, a first shown NAND gate 101 is connected to a first address line combination 102a, a second NAND gate 101 is connected to a second address line combination 102b, and a third NAND gate 101 is connected to a third address line combination 102c. The address line combinations 102a, 102b, and 102c are different from each other. Of course, the address decoder 100 may comprise more such NAND gates 101.

[0036] For example, a specific address may be relayed to the address decoder 100 through a particular arrangement of high or low signals on the address lines 102. When the NAND gates 101 receive a specific pattern of such signals from their combination of address lines 102a, 102b, 102c, they output a low signal (logic 0) only when all their inputs are high (logic 1). This functionality allows the NAND gates 101 to act as part of a logic circuit that decodes binary address information.

[0037] The address decoder 100 further comprises a plurality of inverter gates 103. Each inverter gate 103 is exclusively connected to one-word line 104 of a plurality of sequentially numbered word lines 104 of the SRAM. Each word line 104 is associated with one of the plurality of addresses. The inverter gates 13 are also known as NOT gates, and may be used to select the word lines 104. They function by inverting their input signal, meaning a low input (logic 0, e.g., output by a NAND gate 101) becomes a high output (logic 1), and vice versa. This inversion capability may be used for generating the signals to select particular word lines 104.

[0038] The address decoder 100 further comprises a plurality of pass gates 105a, 105b, which comprise a set of first pass gates 105a (all shaded) and a set of second pass gates 105b. A pass gate 105 is an electronic component, for instance, at least one transistor, which may be used to allow an input signal to pass or to block the input signal, depending on a control signal. Each pass gate 105 may comprise an NMOS transistor and a PMOS transistor.

[0039] Each NAND gate 101 is associated with a respective first pass gate 105a, which is configured to establish or break a connection of the NAND gate 101 to an inverter gate 103 that is connected to a word line 104 having a particular number. That is, the respective first pass gate 105a may allow an output signal of the NAND gate 101 to pass to the inverter gate 103, or may block the output signal of the NAND gate 101. Each NAND gate 101 is further associated with a respective second pass gate 105b, which is configured to establish or break a connection of the NAND gate 101 to another inverter gate 103 connected to a word line 104 having a number equal to the particular number plus one. That is, the respective second pass gate 105b may allow an output signal of the NAND gate 101 to pass to the other inverter gate 103, or may block the output signal of the NAND gate 101. The pass gates 105a, 105b are controlled by a common control line 106, and may be controlled such that either the first or the second pass gate 105a, 105b associated with a NAND gate 101 allow the output signal of the NAND gate 101 to pass (while the other blocks it).

[0040] In particular, the first pass gates 105a are designed to establish the connection if a control signal is provided on the control line 106 and to break the connection if the inverse of the control signal is provided on the control line 106. The second pass gates 105b are designed to establish the connection if the inverse of the control signal is provided on the control line 106 and to break the connection if the control signal is provided on the control line 106. To this end, the second pass gates 105b may comprise a pair of an NMOS transistor and a PMOS transistor, wherein the pairs in the second pass gates 105b are connected inversely compared to the pairs in the first pass gates 105a.

[0041] FIG. 2 shows parts of an exemplary address decoder 100 of an SRAM according to this disclosure, which builds on what is shown in FIG. 1. Same element in FIG. 1 and FIG. 2 are labelled with the same reference signs, and may be implemented and function likewise. FIG. 2 shows particularly the final stage of a circuit of the address decoder 100 of the SRAM, which is used for selecting a word line 104 to perform a read operation (or write operation).

[0042] FIG. 2 shows a detailed wiring of the NAND gates 101 to the inverter gates 103 through the pass gates 105a, 105b, which are respectively arranged between them. FIG. 2 also shows that the word lines 104 are sequentially numbered from 0 to N, e.g. from 0 to 255, wherein the number N plus one is equal to the number 0. That is WL_255 = WL -l as shown in the figure.

[0043] The control signal on the control line 106 may be a high or low signal, and accordingly the inverse of the control signal may be a low or high signal on the control line 106. By setting and / or toggling this control signal, it may be decided to use the current address for accessing a word line 104, or to use the incremented address (plus one) for accessing the (next) word line. In the first case, the first pass gates 105a are set to “pass”, while the second pass gates 105b are set to “block”, while in the second case the first pass gates 105a are set to “block” and the second pass gates 105b are set to “pass”. It can be seen that the solution is limited to the function “plus one”, which is however sufficient in most scenarios. The solution is simple, consumes only little area, and has a low power consumption.

[0044] FIG. 3 shows a method 300 for operating an SRAM according to this disclosure, in particular, for selecting or switching between a particular word line 104 and the next word line 104. The method 300 comprises a step 301 of providing 301 the control signal on the control line 106, in order to select a word line 104 associated with a particular address of the plurality of addresses. Alternatively or additionally (before or after the step 301), the method 300 comprises a step 302 of providing the inverse of the control signal on the control line 106, in order to select a word line 104 associated with an address equal to the particular address plus one.

[0045] The method 300 may be performed or controlled by a processor, for instance, a CPU, or a controller. For instance, the SRAM may comprise processing circuitry (not shown) configured to perform, conduct or initiate the method 300. The processing circuitry may comprise hardware and / or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The SRAM may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processing circuitry, in particular under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the method 300 to be performed.

[0046] The solution of this disclosure, i.e., the SRAM comprising the address decoder 100 with pass gates 105a, 105b, may be incorporated in all products having a CPU, such as cellular chips and server chips.

[0047] The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. A static random access memory, SRAM, comprising an address decoder (100) for decoding a plurality of addresses, wherein the address decoder (100) includes: a plurality of NAND gates (101), wherein each NAND gate (101) is connected to a unique combination of address lines (102a, 102b, 102c) of aplurality of address lines (102), the plurality of address lines (102) being configured to represent the plurality of addresses; a plurality of inverter gates (103), wherein each inverter gate (103) is exclusively connected to one-word line (104) of a plurality of sequentially numbered word lines (104) of the SRAM, each word line (104) being associated with one of the plurality of addresses; and a plurality of pass gates (105a, 105b) comprising a set of first pass gates (105a) and a set of second pass gates (105b); wherein each NAND gate (101) is associated with a respective first pass gate (105a), which is configured to establish or break a connection of the NAND gate (101) to an inverter gate (103) connected to a word line (104) having a particular number; wherein each NAND gate (101) is further associated with a respective second pass gate (105b), which is configured to establish or break a connection of the NAND gate (101) to an inverter gate (103) connected to a word line (104) having a number equal to the particular number plus one; wherein the plurality of pass gates (105a, 105b) are controlled by a common control line (106); and wherein the first pass gates ( 105a) are designed to establish the connection if a control signal is provided on the control line (106) and to break the connection if the inverse of the control signal is provided on the control line (106), and the second pass gates (105b) are designed to establish the connection if the inverse of the control signal is provided on the control line (106) and to break the connection if the control signal is provided on the control line (106).

2. The SRAM of claim 1, wherein the address decoder (100) is a line decoder and the addresses are row addresses.

3. The SRAM of claim 1 or 2, wherein the word lines (104) are sequentially numbered from 0 to N, and the number N plus one is equal to the number 0.

4. The SRAM of one of the claims 1 to 3, wherein the first pass gates (105a) and the second pass gates (105b) each comprise a pair of an NMOS transistor and a PMOS transistor, wherein the pairs in the second pass gates (105b) are connected inversely compared to the pairs in the first pass gates (105a).

5. The SRAM one of the claims 1 to 4, wherein the control signal is a high or low signal on the control line (106), and the inverse of the control signal is respectively a low or high signal on the control line (106).

6. The SRAM of one of the claims 1 to 5, wherein each NAND gate (101) is connected to a different combination of address lines (102a, 102b, 102c) and corresponding inverted address lines.

7. A method (300) for operating an SRAM of one of the claims 1 to 6, wherein the method (300) comprises: providing (301) the control signal on the control line (106), in order to select a word line (104) associated with a particular address of the plurality of addresses; and / or providing the inverse of the control signal on the control line (106), in order to select a word line (104) associated with an address equal to the particular address plus one.

8. The method (300) of claim 7, wherein the method (300) further comprises providing a distinct set of address signals on the plurality of address lines (102), in order to provide the particular address to the address decoder (100) of the SRAM.

9. A computer program comprising instructions which, when the program is executed by a processor, cause the processor to perform the method (300) according to claim 7 or 8.

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