Sealing process

Abstract

Herein is provided a method for sealing a chip (100), the method comprising arranging holes (120) to respective gaps (105) in between a cap wafer (104) and a device wafer (101, 102, 103) bonded together for evacuating matter from the respective gaps (105), and sealing the holes (120) by solder material (110) Herein is further provided a sealed chip (100).

Description

[0001] SEALING PROCESS

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to the field of semiconductors and semiconductor chips. The disclosure relates particularly, though not exclusively, to a sealing process of semiconductor wafers.

[0004] BACKGROUND

[0005] This section illustrates useful background information without admission of any technique described herein representative of the state of the art.

[0006] Many chips comprising semiconductor devices are typically sensitive to impurities, contamination, and environmental distractions. Therefore, these devices are typically packaged within the chips such that they are protected from the outside environment. For example, there may be a need for hermetically seal the device within the chip. Many semiconductor devices are typically adapted to function in a vacuum.

[0007] SUMMARY

[0008] The appended claims define the scope of protection. Any examples and technical descriptions of apparatuses, products and / or methods in the description and / or drawings not covered by the claims are presented not as embodiments of the invention but as background art or examples useful for understanding the invention.

[0009] It is an object of certain embodiments of the present disclosure to provide a seal for the chip, or at least to provide an alternative to an existing technology. Accordingly, certain disclosed embodiments provide for an ingenious method for sealing a chip. According to a first example aspect of the present disclosure there is provided a method for sealing a chip, the method comprising arranging holes to respective gaps in between a cap wafer and a device wafer bonded together for evacuating matter from the respective gaps; and sealing the holes by solder material.

[0010] In certain embodiments, the method is a method for resealing a chip. In certain embodiments, the cap wafer is a wafer substrate. In certain embodiments, the device wafer is a wafer substrate. In certain embodiments, the cap wafer is a silicon wafer. In certain embodiments, the device wafer is a silicon wafer. In certain embodiments, the cap wafer is a whole wafer. In certain embodiments, the cap wafer is at least a part or a portion of a wafer. In certain embodiments, the device wafer is a whole wafer. In certain embodiments, the device wafer is at least a part or a portion of a wafer. In certain embodiments, the device wafer is a silicon on insulator, SOI, wafer.

[0011] In certain embodiments, the cap wafer and the device wafer are bonded together to form a chip. In certain embodiments, the bonding comprises thermocompression bonding. In certain embodiments, the bonding comprises eutectic bonding, or flip chip bonding. In certain alternative embodiments, the bonding comprises glass frit bonding, anodic bonding or adhesive bonding. In certain embodiments, the bonding of the wafers forms an encapsule. In certain embodiments, said sealing occurs after bonding.

[0012] In certain embodiments, a plurality of gap is formed in between the cap wafer and the device wafer bonded together. In certain embodiments, the device wafer comprises a plurality of gaps, each comprising a resonator device.

[0013] In certain embodiments, the method comprises providing a solder material onto the cap wafer. In certain embodiments, the method comprises providing a solder material onto the cap wafer prior to (before) arranging holes to respective gaps in between the cap wafer and the device wafer. In certain embodiments, the method comprises providing a solder material onto the cap wafer on the opposite side of the gaps.

[0014] In certain embodiments, the method comprises the steps of (in the following order):

[0015] - providing a solder material onto a cap wafer,

[0016] - arranging holes to respective gaps in between a cap wafer and a device wafer bonded together for evacuating matter from the respective gaps; and

[0017] - sealing the holes by solder material.

[0018] In certain embodiments, the solder material provided onto the cap wafer is (in a form of) a solder bump. In certain embodiments, the solder material provided onto the cap wafer is (in a form of) a solder material deposit. In certain embodiments, the solder material provided onto the cap wafer is (in a form of) a solder material structure.

[0019] In certain embodiments, the providing the solder material comprises depositing a solderable material on the cap wafer; depositing a non-solderable material on the solderable material; and depositing the solder material on the non-solderable material. In certain embodiments, each deposition step comprises patterning the material.

[0020] In certain embodiments, the method comprises providing solder material on top of a patterned layers of non-solderable material and solderable material. In certain embodiments, the method comprises elevating temperature, causing the solder material to retreat from the non-solderable material and to flow towards the solderable material. In certain embodiments, the method comprises arranging the non-solderable material and the solderable material such that the solder material is configured to cover the holes.

[0021] In certain embodiments, the method comprises depositing the solder material via electroplating (electro-chemical depositing). In certain embodiments, the method comprises depositing the solder material via sputtering. In certain embodiments, the method comprises depositing the solder material via solder pasted printing. In certain embodiments, the method comprises depositing the solder material via ink jet printing. Above identified deposition means for the solder material apply equally to the solderable material and to the non-solderable material as well.

[0022] In certain embodiments, said arranging the holes comprises etching the holes. In certain embodiments, said arranging the holes comprises etching the holes using deep reactive ion etching, DRIE. In certain embodiments, said arranging the holes comprises etching the holes using laser etching. In certain embodiments, said arranging the holes comprises providing the holes through the cap wafer. In certain embodiments, said arranging the holes comprises providing the holes through the cap wafer to respective gaps. In certain embodiments, said arranging the holes comprises drilling the holes.

[0023] In certain embodiments, said evacuating matter comprises removing impurities from the respective gaps in between the cap wafer and the device wafer. In certain embodiments, said evacuating matter comprises removing air from the respective gaps. In certain embodiments, said evacuating matter comprises pumping a vacuum to the respective gaps in between the cap wafer and the device wafer. In certain embodiments, the said evacuating matter comprises improving an existing vacuum within the respective gaps. In certain embodiments, said sealing the holes by solder material comprises causing the solder material to cover the holes. In certain embodiments, said sealing the holes occurs via reflow soldering.

[0024] In certain embodiments, said sealing the holes comprises elevating the temperature, causing the solder material to flow towards the holes. In certain embodiments, said sealing the holes comprises elevating the temperature, causing the solder material to flow onto the holes. In certain embodiments, said sealing the holes comprises elevating the temperature, causing the solder material to flow towards and onto the holes. In certain embodiments, said sealing the holes comprises elevating the temperature, causing the solder material to melt onto the holes. In certain embodiments, said sealing the holes comprises elevating the temperature, causing the solder material to cover the holes.

[0025] In certain embodiments, the method comprises lowering the temperature, causing the solder material to set onto the holes. In certain embodiments, the method comprises forming a bump (a dome, a ball) of the solder material during the sealing.

[0026] In certain alternative embodiments, the method comprises forming a bump (such as a micro bump or a flip chip bump) from the solder material (by depositing said solder material) onto the holes. In certain embodiments, the method comprises elevating the temperature, causing the bump to melt onto the holes. In certain embodiments, the method comprises lowering the temperature, causing the bump to set onto the holes after melting (thereby sealing the holes).

[0027] In certain embodiments, the solder material is Sn, or an alloy thereof. In certain embodiments, the solder material is In, or an alloy thereof. In certain embodiments, the solder material is Pd, or an alloy thereof. In certain embodiments, the solder material is Zn, or an alloy thereof. In certain embodiments, the solder material is Bi, or an alloy thereof. In certain embodiments, the solder material is Cd, or an alloy thereof. In certain embodiments, the solder material is selected from a group comprising Sn, In, Pd, Zn, Bi, Cd, and any combination or an alloy thereof.

[0028] In certain embodiments, the solder material comprises a plurality (such as two) of layers or materials. In certain embodiments, the solder material comprises a plurality of layers of materials forming a eutectic alloy (eutectic mixture). In certain embodiments, the solder material comprises a plurality of layers of materials forming a eutectic alloy upon heating. In certain embodiments, the solder material comprises layer(s) of Au and Si, forming a eutectic alloy of AuSi. In certain embodiments, the solder material is AuSi. In certain embodiments, the solder material comprises layer(s) of Al and Ge, forming a eutectic alloy of AIGe. In certain embodiments, the solder material is AIGe.

[0029] In certain embodiments, the method comprises sealing more than one hole at the same time. In certain embodiments, the method comprises sealing at least two holes at the same time. In certain embodiments, the method comprises sealing all the holes to respective gaps simultaneously (at the same time). In certain embodiments, the method comprises sealing all the holes on the cap wafer at the same time. In certain embodiments, the method comprises sealing all the holes on the cap wafer in the same processing step.

[0030] In certain embodiments, the method comprises arranging the holes in proximity of the solder material. In certain embodiments, the method comprises arranging the solder material at least partly surrounding the holes. In certain embodiments, the method comprises arranging the solder material next to the holes. In certain embodiments, the method comprises arranging the holes in proximity of the solder material, wherein the solder material is provided in a shape of a donut, a square or an equal sign. In certain embodiments, the method comprises arranging the holes in the middle of the solder material, wherein the solder material is provided in a shape of a donut, a square or an equal sign. In certain embodiments, patterning the solder material in a shape of a donut, a square or an equal sign in proximity of each hole.

[0031] In certain embodiments, the method comprises arranging the holes in proximity of the eutectic alloy (material(s) that are configured to form eutectic alloy when heated). In certain embodiments, the method comprises arranging the eutectic alloy at least partly surrounding the holes. In certain embodiments, the method comprises arranging the eutectic alloy next to the holes.

[0032] In certain embodiments, the method comprises arranging the solder material in proximity of the holes. In certain embodiments, the method comprises arranging the holes next to the solder material. In certain embodiments, the method comprises arranging the solder material in proximity of the holes, wherein the solder material is provided in a shape of a donut, a square or an equal sign.

[0033] In certain embodiments, the method comprises arranging the solder material (directly) onto the holes. In certain embodiments, the method comprises forming a pile of the solder material (depositing solder material on top of the hole). In certain embodiments, the method comprises forming a cylinder (a cylindrical pile) of the solder material (depositing solder material with a cylindrical shape on top of the hole). In certain embodiments, the pile (the cylinder) of the solder material comprises two materials, such as Cu and Sn. In certain embodiments, the pile (the cylinder) of solder material comprises two materials on top of each other.

[0034] In certain embodiments, the method comprises forming a pile of materials forming a eutectic alloy (upon heating) on top of the hole (depositing eutectic materials on top of the hole). In certain embodiments, the pile (or a cylinder) of materials forming the eutectic alloy comprises two materials on top of each other.

[0035] In certain embodiments, said sealing the holes provides a hermetical seal for the chip. In certain embodiments, said sealing the holes provides an airtight seal for the chip. In certain embodiments, the method comprises providing a hermetical seal for the chip.

[0036] In certain embodiments, the method comprises providing a hermetical seal for the chip by solder material. In certain embodiments, the method comprises providing a hermetical seal for the chip by reflow soldering. In certain embodiments, the method comprises providing a hermetical seal for the chip by allowing the solder material to flow onto the holes. In certain embodiments, the method comprises providing a hermetical seal for the chip by allowing the solder material to flow onto the holes upon elevating temperature.

[0037] In certain embodiments, the device wafer comprises resonator devices. In certain embodiments, the resonator devices are fabricated on a substrate. In certain embodiments, the resonator devices are fabricated on a SOI substrate. In certain embodiments, the substrate comprises a silicon body. In certain embodiments, the resonator devices are microelectromechanical systems, MEMS, resonator devices.

[0038] In certain embodiments, a plurality of gaps are formed in between the device wafer and the cap wafer, each comprising a resonator device. In certain embodiments, said arranging holes comprises providing at least one hole to each of the said plurality of gaps (respective gaps). In certain embodiments, said arranging holes comprises providing the holes through the cap wafer to each of the said plurality of gaps (respective gaps).

[0039] In certain embodiments, the resonator devices are located in the respective gaps. In certain embodiments, the resonator devices are facing the respective gaps. In certain embodiments, the device wafer comprises one resonator device for each respective gap. In certain embodiments, the gaps are separated from neighbouring gaps by sealing ring.

[0040] In certain embodiments, each resonator device is adapted to resonate in an in-plane resonance mode. In certain embodiments, each resonator device is adapted to resonate in a length extensional resonance mode. In certain embodiments, each resonator device is adapted to resonate in an in-plane length extensional resonance mode. In certain embodiments, each resonator device is adapted to resonate in a Lamb wave resonance mode. In certain embodiments, each resonator device is adapted to resonate in a contour resonance mode. In certain embodiments, each resonator device is a beam resonator. In certain embodiments, each resonator device is a stacked beam resonator.

[0041] According to a second example aspect of the invention there is provided a sealed chip manufactured using the method according to first example aspect.

[0042] In certain embodiments, the sealed chip is formed by bonding a cap wafer (portion) and a device wafer (portion) together. In certain embodiments, the sealed chip comprises a vacuum within. In certain embodiments, the sealed chip is a hermetically sealed chip. In certain embodiments, the sealed chip is sealed by solder material. In certain embodiments, the sealed chip is sealed by reflow soldering.

[0043] In certain embodiments, the sealed chip comprises a bump (a dome, a ball) formed of solder material. In certain embodiments, the bump of the solder material is formed during the sealing.

[0044] Different non-binding example aspects and embodiments have been illustrated in the foregoing. The embodiments in the foregoing are used merely to explain selected aspects or steps that may be utilized in different implementations. Some embodiments may be presented only with reference to certain example aspects. It should be appreciated that corresponding embodiments may apply to other example aspects as well. In particular, the embodiments described in the context of the first aspect are applicable to each further aspect. Any appropriate combinations of the embodiments may be formed.

[0045] BRIEF DESCRIPTION OF THE FIGURES

[0046] Some example embodiments will be described with reference to the accompanying figures, in which:

[0047] Fig. 1a schematically shows a bonded chip according to certain example embodiments;

[0048] Fig. 1 b schematically shows the chip comprising solder material according to certain example embodiments;

[0049] Fig. 1 c schematically shows the chip comprising solder material and drilled holes according to certain example embodiments; Fig. 1d schematically shows the chip comprising drilled holes sealed using solder material according to certain example embodiments;

[0050] Fig. 2 schematically shows an enlarged portion of the chip according to an example embodiment of Fig. 1 d;

[0051] Fig. 3a schematically shows a bonded chip according to certain example embodiments;

[0052] Fig. 3b schematically shows the chip sealed according to certain example embodiments; and

[0053] Fig. 4a-4d schematically show alternatives of shapes of solder material from a top view according to certain example embodiments.

[0054] DETAILED DESCRIPTION

[0055] In the following description, like reference signs denote like elements or steps.

[0056] As used herein, the term chip means an entity of wafers (substrates) bonded together comprising a resonator device. In the context of the present disclosure, the term chip is understood to mean the entity comprising a resonator device prior to dicing the entities as individual dies, or after dicing the entities to individual dies. In dicing, the dies are separated from each other using a special equipment. In the context of the instant disclosure, the term die forms a synonym to the term chip.

[0057] As used herein, the term solder material refers to a material that is configured to cover and seal a hole on a wafer (substrate), such as to cover and seal a hole drilled through a cap wafer, which cap wafer is bonded together with a device wafer to form a chip.

[0058] Figs. 1 a, 1 b, 1 c and 1 d schematically show steps of a method for sealing a chip according to certain example embodiments. Fig. 1a shows a starting situation. Fig. 1 a shows a chip 100. The chip 100 comprises a device wafer 101 , 102, 103 and a cap wafer 104. In this example embodiment, the device wafer comprises a silicon body 101 , an insulating layer 102 and a device layer 103. In certain embodiments, the insulating layer 102 is of silicon dioxide, SiC>2.

[0059] The device wafer 101 , 102, 103 and the cap wafer 104 are bonded together to form the chip 100. Respective gaps 105 are formed in between the device wafer 101 , 102, 103 and the cap wafer 104. The respective gaps 105 are separated from adjacent gaps by a sealing ring 106.

[0060] In certain embodiments, the device wafer (more specifically the device layer 103) comprises resonator devices (not shown). In certain embodiments, each respective gap houses one resonator device. In certain embodiments, the device wafer comprises one resonator device for each respective gap.

[0061] Fig. 1 b shows the chip 100 comprising solder material 110. The solder material 110 is provided on the cap wafer. In certain embodiments, the solder material 110 is deposited on the cap wafer. In certain embodiments, the solder material 110 is selected from a group comprising Sn, In, Pd, Zn, Bi, Cd, and any combination or an alloy thereof.

[0062] In certain embodiments, the solder material 110 comprises a plurality of layers of materials, such as two layers, forming a eutectic alloy upon heating. In certain embodiments, the solder material 110 comprises layer(s) of Au and Si, forming a eutectic alloy of AuSi when heated. In certain embodiments, the solder material 110 comprises layer(s) of Al and Ge, forming a eutectic alloy of AIGe when heated.

[0063] In certain embodiments, the solder material 110 is electroplated on the cap wafer (deposited via electro-chemical depositing). In certain alternative embodiments, the solder material 110 sputtered, solder pasted printed, or ink jet printed onto the cap wafer.

[0064] In this example embodiments, the solder material 110 is patterned. In certain embodiments, the solder material 110 is patterned to match the location, wherein holes to respective gaps 105 will be provided later.

[0065] Fig. 1c shows the chip 100 comprising holes 120. The holes 120 are arranged to respective gaps 105 in between the cap wafer and a device wafer bonded together for evacuating matter from the respective gaps 105. The holes 120 are arranged in proximity of the solder material 110. In this example embodiment, the holes 120 are arranged in the middle of the solder material 110 provided.

[0066] The holes 120 are used to evacuate matter from the respective gaps 105. In certain embodiments, said evacuating matter comprises removing air or impurities from the respective gaps 105. In certain embodiments, the said evacuating matter comprises pumping a vacuum within the respective gaps 105. In certain embodiments, the said evacuating matter comprises improving an existing vacuum within the respective gaps 105. Fig. 1 d shows the chip 100 sealed. The holes 120 are sealed by solder material 110. In this example embodiment, sealing the holes occurs via reflow soldering. In certain embodiments, said sealing the holes 120 comprises elevating the temperature, causing the solder material 110 to flow towards and onto the holes 120. In certain embodiments, the solder material 110 covers the holes 120. In this example embodiment, the two sections of solder material 110 move inwards towards the holes 120 and towards each other. In this example embodiment, the solder material 110 sections join together on top of the holes 120 and seal the holes 120.

[0067] In certain embodiments, said sealing the holes comprises lowering the temperature, causing the solder material 110 to set onto the holes 120. In this example embodiment, a bump of the solder material 110 is formed onto the respective holes 120 during the sealing. In certain embodiments, the chip shown in Fig. 1 d comprises a vacuum inside.

[0068] The method shown in Figs. 1 a-1d occurs throughout the wafer (substrate) simultaneously. This enables sealing all the holes 120 arranged on the substrate at the same time, after evacuating matter from said holes 120.

[0069] In certain alternative embodiments (not shown), a bump (such as a micro bump or a flip chip bump) is formed from the solder material by depositing said solder material directly onto the holes. In certain embodiments, the method comprises elevating the temperature, causing the bump to melt onto the holes. In certain embodiments, the method comprises lowering the temperature, causing the bump to set onto the holes after melting thereby sealing the holes.

[0070] Fig. 2 shows an enlarged portion of the chip 100 shown in Fig. 1d according to certain example embodiments. The enlarged portion is focused on the area of one respective gap 105. Fig. 2 illustrates the location of the resonator device in the chip 100.

[0071] The slashed area 210 marked to the enlarged portion denotes the locations of the resonator device in the chip 100. The resonator devices are located in the respective gaps 105. The slashed area 210 shows that in this example embodiment, the resonator device is fabricated on a device layer 103 of the device wafer 101 , 102, 103. In certain embodiments, the slashed area 210 of the device wafer 101 , 102, 103 comprises a cavity (not shown). The cavity is adapted to provide space for the resonating body of the resonator device to resonate in. In certain embodiments, the resonator device is adapted to resonate in an in-plane length extensional resonance mode. In certain embodiments, each resonator device is a stacked beam resonator. As used herein, the term stacked beam resonator refers to a ladder-like configuration of the resonator. In certain embodiments, the stacked beam resonator comprises a plurality of beams adjacent to each other (in a row). In certain embodiments, said plurality of beams are attached to each other via connection elements.

[0072] The slashed area 210 illustrates that a resonator device is provided for each respective gap 105. A plurality of gaps 105 are formed in between the device wafer 101 , 102, 103 and the cap wafer 104, each comprising a resonator device. In this example embodiment, the gaps 105 are separated from neighbouring gaps by a sealing ring 106. In certain embodiments, the sealing ring 106 is configured to encircle the resonator device.

[0073] According to the method of the first aspect shown in Figs. 1 a-1 d, holes 105 are arranged to respective gaps 105 in between the cap wafer 104 and the device wafer 101 , 102, 103 bonded together for evacuating matter from the respective gaps 105. This enables removal of impurities and air from said gaps 105, which enhances the performance of the resonator devices located within the said gaps (located at the slashed area 210 in Fig. 2).

[0074] Figs. 3a and 3b show steps to manufacture a sealed chip 100 according to certain example embodiments. Fig. 3a shows that the chip 100 comprises a device wafer 101 , 102, 103 and a cap wafer 104. In this example embodiment, the device wafer comprises a silicon body 101 , an insulating layer 102 and a device layer 103. In certain embodiments, the insulating layer 102 is of silicon dioxide, SiC>2.

[0075] The device wafer 101 , 102, 103 and the cap wafer 104 are bonded together to form the chip 100. The gap 105 is formed in between the device wafer 101 , 102, 103 and the cap wafer 104. The gap 105 is separated from adjacent gaps by a sealing ring 106.

[0076] Solderable material 111 is deposited on the cap wafer 104. The solderable material is deposited on the cap wafer on the opposite side than the gap 105. In certain embodiments, the solderable material is a solderable material layer 111. In certain embodiments, the solderable material layer 111 is patterned, e.g. using lithography. Non-solderable material 112 is deposited on the solderable material 111. In certain embodiments, the non- solderable material is a non-solderable material layer 112. In certain embodiments, the non- solderable material layer 112 is patterned. Finally, the solder material 110 is deposited on the non-solderable material 112. In certain embodiments, the solder material 110 is electroplated on the non-solderable material 112. In certain embodiments, the solder material 110 is patterned.

[0077] As used herein, the term solderable material refers to a material that is wettable by the solder material. As used herein, the term non-solderable material refers to a material that is not wettable by the solder material. In an example embodiment, the solder material is Sn. In this example embodiment, the solderable material is selected from a group comprising Cu, Au, Ni, Pd, and any combination or an alloy thereof. In this example embodiment, the non-solderable material is selected from a group comprising Al, W, Mo, and any combination or an alloy thereof.

[0078] In certain embodiments, the hole 120 is arranged to respective gap 105 in between the cap wafer and a device wafer bonded together for evacuating matter from the gap 105. In certain embodiments, the hole 120 is arranged through the solderable material layer 111 , the non- solderable material layer 112 and the solder material 110. In this example embodiments, the hole 120 is etched using deep reactive ion etching, DRIE, or laser etching.

[0079] In certain embodiments, the hole 120 is used to evacuate matterfrom the gap 105. In certain embodiments, the hole 120 is used to pump a vacuum or to improve an existing vacuum to the gap 105.

[0080] Fig. 3b shows the chip 100 sealed using solder material 110 according to certain example embodiments. As shown in Fig. 3a, the solder material 110 is provided on top of patterned layers of non-solderable material 112 and solderable material 111. In certain embodiments, upon elevating temperature, the solder material 110 to retreat from the non-solderable material layer 112 and flows towards the solderable material layer 111. The solder material 110 flows towards the hole 120.

[0081] In certain embodiments, the hole 120 is arranged in proximity of the solder material 110. In this example embodiment, the solder material at least partly surrounds the hole 120. This ensures that the solder material 110 moves to a correct direction, i.e. towards the hole 120 upon elevating the temperature.

[0082] The Figs. 3a and 3b show only the area of one gap 105. However, in certain embodiments, a plurality of gaps 105 is formed in between the cap wafer 104 and the device wafer 101 , 102, 103 bonded together. Thus, in certain embodiments, a plurality of chips 100 are formed. In certain embodiments, each gap 105 comprises a resonator device (not shown). In certain embodiments, each chip 100 comprises a resonator device (not shown). In certain embodiments, the steps shown in Figs. 3a and 3b (equally as in Figs. 1a-1d) are performed to all the chips 100 simultaneously, instead of individually operating one chip 100 comprising one gap 105 at a time. In certain embodiments, each step of arranging holes 120, evacuating matter from respective gaps 105 via the holes 120, and sealing the holes 120 by solder material is performed sequentially for all the chips 100 on the substrate at the same time. This enables a faster and cheaper sealing process. Furthermore, as many semiconductor processes are batch processes with capability to process several wafers at the same time, the method according to the first aspect allows processing a plurality of substrates at the same time too, enabling even faster sealing process.

[0083] Figs. 4a-4d show example alternatives of shapes of solder material from a top view according to certain example embodiments. Figs. 4a-4d present examples of possible manners to arrange the hole 120 in relation to the solder material 110. Figs. 4a-4d show simplifications. In all Figs. 4a-4d, the holes 120 are arranged in proximity of the solder material 110.

[0084] Fig. 4a shows that the solder material 110 is provided next to the hole 120 according to certain example embodiments. Fig. 4b shows that the solder material 110 is provided in the shape of a donut according to certain example embodiments. Fig. 4c shows that the solder material 110 is provided in the shape of a square according to certain example embodiments. In Figs. 4b and 4c, the hole 120 is arranged in the middle of the solder material 110 according to certain example embodiments. In certain embodiments, the solder material 110 surrounds the hole 120. Fig. 4d shows that the solder material 110 is provided is a shape of an equal sign according to certain example embodiments. In certain embodiments, the solder material 110 at least partly surrounds the hole 120.

[0085] Without limiting the scope and the interpretation of the patent claims, certain technical effects of one or more of the example embodiments disclosed herein are listed in the following. A technical effect of the invention is enabling sealing a hole on a substrate. A further technical effect is enabling sealing plurality of holes arranged through the cap wafer at the same time. A need for individually sealing each hole, for instance by using a laser beam, is avoided. Therefore, a further technical effect is providing a cheaper and faster sealing process.

[0086] A further technical effect is enabling hermetic sealing the chip after vacuum pumping. This enables creating the desired vacuum within the chip and maintaining the desired vacuum within the chip in use. A further technical effect is minimizing radial distribution in vacuum level. In conventional semiconductor manufacturing processes, the vacuum level within the chips on a substrate may have a radial distribution. This may result in undesired quality variation within the chips and may cause issues in meeting the chip specifications. The present disclosure enables improving and stabilizing the vacuum level of chips on the substrate. The present disclosure enables omitting getter materials from within the enclosure of the chips.

[0087] A further technical effect is enabling the provision of micro bumps in the same solder-based pump and resealing process. The need to separately fabricate micro bumps is avoided. A further technical effect is providing a wafer level resealing. A further technical effect is providing a relatively low temperature sealing process. A further technical effect is enabling omitting flags from bonding process during the wafer level packaging. Solder-based reseal process enables lowering the residual pressure inside the package.

[0088] Various embodiments have been presented. It should be appreciated that in this document, words comprise, include, and contain are each used as open-ended expressions with no intended exclusivity.

[0089] The foregoing description has provided by way of non-limiting examples of particular implementations and embodiments a full and informative description of the best mode presently contemplated by the inventors for carrying out the invention. It is however clear to a person skilled in the art that the invention is not restricted to details of the embodiments presented in the foregoing, but that it can be implemented in other embodiments using equivalent means or in different combinations of embodiments without deviating from the characteristics of the invention.

[0090] Furthermore, some of the features of the afore-disclosed example embodiments may be used to advantage without the corresponding use of other features. As such, the foregoing description shall be considered as merely illustrative of the principles of the present invention, and not in limitation thereof. Hence, the scope of the invention is only restricted by the appended patent claims.

Claims

CLAIMS1 . A method for sealing a chip (100), the method comprising: arranging holes (120) to respective gaps (105) in between a cap wafer (104) and a device wafer (101 , 102, 103) bonded together for evacuating matter from the respective gaps (105); and sealing the holes (120) by solder material (110).

2. The method of claim 1 , comprising providing the solder material (110) onto the cap wafer (104).

3. The method of claim 2, wherein the providing the solder material (110) comprises: depositing a solderable material (111 ) on the cap wafer (104); depositing a non-solderable material (112) on the solderable material (111 ); and depositing the solder material (110) on the non-solderable material (112).

4. The method of claim 3, wherein each deposition step comprises patterning the material.

5. The method of any preceding claim, wherein said evacuating matter comprises pumping a vacuum to the gaps (105) in between the cap wafer (104) and the device wafer (101 , 102, 103).

6. The method of any preceding claim, wherein said sealing the holes (120) by solder material (110) comprises causing the solder material (110) to cover the holes (120).

7. The method of any preceding claim, wherein said sealing the holes (120) occurs via reflow soldering.

8. The method of any preceding claim, wherein said sealing the holes (120) comprises elevating the temperature, causing the solder material (110) to flow towards and onto the holes (120).

9. The method of claim 8, comprising lowering the temperature, causing the solder material (110) to set onto the holes (120).

10. The method of any preceding claim, comprising sealing all the holes (120) to respective gaps (105) simultaneously.11 . The method of any preceding claim, comprising arranging the holes (120) in proximity of the solder material (110).

12. The method of any preceding claim, wherein the solder material (110) at least partly surrounds the holes (120).

13. The method of any preceding claim, wherein said sealing the holes (120) provides a hermetical seal for the chip 100.

14. The method of any preceding claim, wherein the device wafer (101 , 102, 103) comprises resonator devices.

15. The method of claim 14, wherein each resonator device is a microelectromechanical systems, MEMS, resonator device.

16. A sealed chip (100) manufactured using the method according to the method of any of claims 1-15.

17. The sealed chip (100) of claim 16, comprising a bump formed of solder material (110).

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